Project Report on

LCD Interfacing with SPARTAN-3 FPGA

ELECTRONICS AND COMMUNICATION ENGINEERING
By

Roll no. 97: Mr. Karansingh Bais

Roll no. 98: Mr. Priyesh K. Sinha
Roll no. 99: Mr. Ankit Zatte
Roll no. 100: Mr. Kunal Dekate

Submitted to

Prof. P. N. Thakre
Electronics & Communication Engineering
Shri Ramdeobaba College of Engineering & Management, Nagpur 440 013
(An Autonomous Institute affiliated to Rashtrasant Tukdoji Maharaj Nagpur University Nagpur)

2016-17

VHDL Assignment 2 97,98,99,100

DESCRIPTION:
VL-FPGA-B includes a LCD Module, which is a dot matrix liquid crystal display that displays alphanumeric,
Kana(Japanese) characters and symbols. Built in controller provides connectivity between LCD and FPGA.
This LCD has a built in Dot Matrix Controller, with font 5 X 7 or 5 X 10 dots, display data RAM for 80 characters (80 x 8
bit) and a character generator ROM which provides 160 characters with 5x7 font and 32 characters with font of 5x10.
All the functions required for LCD are provided internally. Internal refresh is provided by the controller.

DATA LINES CONNECTION:

LCD has 8 bit bidirectional to FPGA. When Enable signal is at low level, this data bus remains in high impedance state.
Interface details of the data lines with SPARTAN-3 FPGA are as shown in below table:
DATA BIT
LCD_D<0>
LCD_D<1>
LCD_D<2>
LCD_D<3>
LCD_D<4>
LCD_D<5>
LCD_D<6>
LCD_D<7>
VHDL Assignment 2 97,98,99,100

DATA Line Interface to SPARTAN-3 FPGA

FPGA Pin
P167
P166
P165
P162
P161
P156
P155
P154

CONTROL LINE INTERFACE:

The control lines of LCD comprise of RS, R/W# and E. The significance of above mentioned control signals is as follows:
RS: Register select signal is used to select data register or command/status register.
High on RS selects the data register
Low on RS selects the command/status register
R/W: Read/write select control lines.
High on R/W# selects the read operation
Low on R/W# selects the write operation
E: Enable signal is used to enable or disable data bus.
Low on the enable signal puts the data bus into a high impedance state.
High on enable signal selects the data bus.
The control line interface of LCD with FPGA is shown in the below table:
Control Bit
LCD_E
LCD_RS
LCD_RW_bar

Control Line interface to SPARTAN-3 FPGA

FPGA Pin
P168
P171
P169

----------------------------------------------------------------------------------------------------------------------------------------------------------------

#Program Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test_lcd_mod is
port( CLK_4M
: in STD_LOGIC; -- 4 Mhz
RESET
: in STD_LOGIC;
LCD_D
: out STD_LOGIC_VECTOR (7 downto 0);
LCD_RW
: out STD_LOGIC;
LCD_RS
: out STD_LOGIC;
LCD_E
: out STD_LOGIC
--posedge_clk
: out std_logic_vector(7 downto 0)
);
end test_lcd_mod;
architecture Behavioral of test_lcd_mod is
-**************************************************************************************************
**************
-- signal
VHDL Assignment 2 97,98,99,100

signal data_s,data_s1 : std_logic_vector(9 downto 0);

signal edge1 : std_logic_vector(1 downto 0);
signal refresh,refresh_d,refresh_s : std_logic;
signal en1,en2 : std_logic;
signal lcd_clk : std_logic;--152 Hz
signal lcd_posedge_s : std_logic;-- pose edge of 152 Hz
signal Div : std_logic_vector(10 downto 0);
type state is
(wait_state1,func_set0,func_set0_t,func_set0_t1,func_set0_t2,func_set1,func_set1_t,func_set2,func_set2_t,func_set3,
func_set3_t,disp_ctrl,disp_ctrl_t,clear_disp,clear_disp_t,mode_set,mode_set_t,cur_set,cur_set_t,ddram_add,ddram_ad
d_t );
signal ps_1, ns_1 : state;
type state1 is (wait_state2,idle1,idle,A,B,C,D,E,F);
signal prst, nxt : state1;
begin
-- Note this design works with a clock of 4M for any other clock plaese modify suitably
-----------LCD CLOCK GENERATION(152 HZ)-------------------------------process(RESET, CLK_4M,Div)
begin
if( RESET = '1' )then
Div <= (others=>'0');
elsif(CLK_4M'event and CLK_4M = '1')then
Div <= Div + 1;
end if;
end process;
lcd_clk <= Div(10);
en2 <= Div(10);
-- ** Generate a pulse of 4M width on postive edge of LCD_Clock. starts here
process(RESET,CLK_4M,lcd_clk)
begin
if RESET = '1' then
edge1 <= "00";
elsif (CLK_4M'event and CLK_4M = '0') then
edge1(0)<= lcd_clk;
edge1(1)<= edge1(0);
end if;
end process;
lcd_posedge_s <= ((not edge1(1)) and edge1(0));
--posedge_clk(7) <=( not lcd_posedge_s);
--posedge_clk(6 downto 0) <= "1110001";
-- ** Generate a pulse of 4M width on postive edge of LCD_Clock. ends here
--lcd_clk_led <= lcd_posedge_s;
VHDL Assignment 2 97,98,99,100

--********This FSM Intializes the LCD **************************

process(RESET,CLK_4M,ns_1,lcd_posedge_s)
begin
if(RESET = '1') then
ps_1 <= func_set0;
elsif(CLK_4M'event and CLK_4M = '1') then
if(lcd_posedge_s = '1') then
ps_1 <= ns_1;
end if;
end if;
end process;
--next state decoder
process(ps_1)
begin
case ps_1 is
when func_set0 => ns_1 <= func_set0_t;
when func_set0_t => ns_1 <= func_set0_t1;
when func_set0_t1 => ns_1 <= func_set0_t2;
when func_set0_t2 => ns_1 <= func_set1;
when func_set1 => ns_1 <= func_set1_t;
when func_set1_t => ns_1 <= func_set2;
when func_set2 => ns_1 <= func_set2_t;
when func_set2_t => ns_1 <= func_set3;
when func_set3 => ns_1 <= func_set3_t;
when func_set3_t => ns_1 <= disp_ctrl;
when disp_ctrl => ns_1 <= disp_ctrl_t;
when disp_ctrl_t =>
ns_1 <= cur_set;
when cur_set => ns_1 <= cur_set_t;
when cur_set_t =>
ns_1 <= mode_set;
when mode_set => ns_1 <= mode_set_t;
when mode_set_t => ns_1 <= ddram_add;
when ddram_add => ns_1 <= ddram_add_t;
when ddram_add_t => ns_1 <= clear_disp;
when clear_disp => ns_1 <= clear_disp_t;
when clear_disp_t => ns_1 <= wait_state1;
-- LCD intialization FSM locks itself in wait_state1 after intialization is over
when wait_state1 => ns_1 <= wait_state1;
when others =>
ns_1 <= func_set0;
end case;
end process;
--process output decoder
process(ps_1)
begin
VHDL Assignment 2 97,98,99,100

case ps_1 is
when func_set0 =>

refresh <= '0';

en1 <= '1';
data_s <= "0000110000";
when func_set0_t =>
refresh <= '0';
en1 <= '0';
data_s <= "0000110000";
when func_set0_t1 =>
refresh <= '0';
en1 <= '1';
data_s <= "0000110000";
when func_set0_t2 =>
refresh <= '0';
en1 <= '0';
data_s <= "0000110000";
when func_set1 =>
refresh <= '0';
en1 <= '1';
data_s <= "0000110000";
when func_set1_t =>
refresh <= '0';
en1 <= '0';
data_s <= "0000110000";
when func_set2 =>
refresh <= '0';
en1 <= '1';
data_s <= "0000110000";
when func_set2_t =>
refresh <= '0';
en1 <= '0';
data_s <= "0000110000";
when func_set3 =>
refresh <= '0';
en1 <= '1';
data_s <= "0000111000";
when func_set3_t =>
refresh <= '0';
en1 <= '0';
data_s <= "0000111000";
when disp_ctrl =>
refresh <= '0';
en1 <= '1';
data_s <= "0000001110";
when disp_ctrl_t =>
refresh <= '0';
en1 <= '0';

VHDL Assignment 2 97,98,99,100

data_s <= "0000001110";

when cur_set =>

refresh <= '0';
en1 <= '1';
data_s <= "0000011100";
when cur_set_t =>
refresh <= '0';
en1 <= '0';
data_s <= "0000011100";
when mode_set =>
refresh <= '0';
en1 <= '1';
data_s <= "0000000110" ;
when mode_set_t =>
refresh <= '0';
en1 <= '0';
data_s <= "0000000110" ;
when ddram_add =>
refresh <= '0';
en1 <= '1';
data_s <= "0010000000";
when ddram_add_t =>
refresh <= '0';
en1 <= '0';
data_s <= "0010000000";
when clear_disp =>
refresh <= '0';
en1 <= '1';
data_s <= "0000000001";
when clear_disp_t =>
refresh <= '0';
en1 <= '0';
data_s <= "0000000001";
when wait_state1 =>
refresh <= '1';
en1 <= '0';
data_s <= "0000000000";
when others =>
refresh <= '0';
en1 <= '0';
data_s <= "0000000000";
end case;
end process;
--********LCD Intialization ENDS HERE **************************
--- ******* This FSM writes Data to LCD.
--- This FSM starts after the LCD Initialization is over
VHDL Assignment 2 97,98,99,100

process(RESET,CLK_4M,refresh,lcd_posedge_s)
begin
if(RESET = '1') then
refresh_d <= '0';
elsif(CLK_4M'event and CLK_4M = '1') then
if(lcd_posedge_s = '1') then
refresh_d <= refresh;
end if;
end if;
end process;
refresh_s <= '1' when (refresh = '1' and refresh_d = '0') else
'0';
--state2
process(RESET,CLK_4M,lcd_posedge_s)
begin
if(RESET = '1') then
prst <= wait_state2;
elsif(CLK_4M'event and CLK_4M = '1') then
if(lcd_posedge_s = '1') then
prst <= nxt;
end if;
end if;
end process;
process(prst,refresh_s)
begin
case prst is
-- loop in wait state2 till the LCD is being Intialized
when wait_state2 =>
if(refresh_s = '1') then
nxt <= idle1;
end if;
when idle1 => nxt <=idle;
when idle => nxt <= A;
when A => nxt <= B;
when B => nxt <= C;
when C => nxt <= D;
when D => nxt <= E;
when E => nxt <= F;
when others => nxt <= wait_state2;
end case;
end process;
--output decoder
VHDL Assignment 2 97,98,99,100

else nxt <= wait_state2; --

process(prst)
begin
case prst is
when wait_state2 =>
data_s1 <= "0000000000";
when A => data_s1 <= "1001000001";
when B => data_s1 <= "1001000010";
when C => data_s1 <= "1001000011";
when D => data_s1 <= "1001000100";
when E => data_s1 <= "1001000101";
when F => data_s1 <= "1001000110";
when others =>
data_s1 <= "0000000000";
end case;
end process;
LCD_D <= data_s(7 downto 0) or data_s1(7 downto 0);
LCD_RS <= data_s(9) or data_s1(9);
LCD_RW <= data_s(8) or data_s1(8);
LCD_E <= en1 or en2;
end Behavioral;

Output:

The LCD displays the characters, ABCDEF

VHDL Assignment 2 97,98,99,100

RTL Schematic

VHDL Assignment 2 97,98,99,100

TECHNOLOGY SCHEMATIC

VHDL Assignment 2 97,98,99,100

Summary

Power Analysis

CONCLUSION:

Thus, interfacing of Liquid Crystal Display with Spartan-3 FPGA is done and the FPGA is programmed to display the
characters ABCDEF.

VHDL Assignment 2 97,98,99,100