APPENDIX I

Chapter 8 VHDL Code Examples

I.1

Introduction

Two example VHDL code designs are presented in Chapter 8, the first for controlling
the AD7524 digital-to-analogue converter and the second for controlling an example
thyristor.
This appendix presents the code examples along with commenting to support the
presented code:
Figure 8.18 VHDL code for DAC controller
Figure 8.19 VHDL test bench for DAC controller
Figure 8.55 Thyristor gate control pulse generator
Figure 8.56 Thyristor gate control pulse generator test bench

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I.2

Appendix I

VHDL Code Examples

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY AD7524_Controller IS
PORT ( Clock
: IN
STD_LOGIC;
Reset
: IN
STD_LOGIC;
Data_In
: IN
STD_LOGIC_VECTOR (7 downto 0);
Data_Out
: OUT STD_LOGIC_VECTOR (7 downto 0);
CS
: OUT STD_LOGIC;
WR
: OUT STD_LOGIC);
END ENTITY AD7524_Controller;
ARCHITECTURE Behavioural OF AD7524_Controller IS
SIGNAL Count : STD_LOGIC_VECTOR(2 downto 0);
SIGNAL Update : STD_LOGIC;
BEGIN
PROCESS (Update, Reset, Data_In)
BEGIN
If (Reset = '0') Then
Data_Out(7 downto 0) <= "00000000";
ElsIf (Update'event and Update = '1') Then
Data_Out(7 downto 0) <= Data_In(7 downto 0);
End If;
END PROCESS;
PROCESS (Clock, Reset)
BEGIN
If (Reset = '0') Then
Count(2 downto 0) <= "000";
ElsIf (Clock'event and Clock = '1') Then
If (Count = "100") Then
Count <= "000";
Else
Count <= Count + 1;
End If;

End If;

END PROCESS;
PROCESS (Count)
BEGIN
If (Count = "000") Then
Update <='0'; CS <=
ElsIf (Count = "001") Then
Update <='1'; CS <=
ElsIf (Count = "010") Then
Update <='0'; CS <=
ElsIf (Count = "011") Then
Update <='0'; CS <=
ElsIf (Count = "100") Then
Update <='0'; CS <=
Else
Update <='0'; CS <=
End If;

'1';

WR <= '1';

'1';

WR <= '1';

'0';

WR <= '1';

'0';

WR <= '0';

'0';

WR <= '1';

'1';

WR <= '1';

END PROCESS;
END ARCHITECTURE Behavioural;

Figure 8.18: VHDL code for DAC controller

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Chapter 8 VHDL Code Examples

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY Test_AD7524_Controller_vhd IS
END Test_AD7524_Controller_vhd;
ARCHITECTURE Behavioural OF Test_AD7524_Controller_vhd IS
COMPONENT AD7524_Controller
PORT(
Clock
: IN
Reset
: IN
Data_In
: IN
Data_Out : OUT
CS
: OUT
WR
: OUT
END COMPONENT;
SIGNAL Clock
SIGNAL Reset
SIGNAL Data_In

:
:
:

SIGNAL Data_Out :
SIGNAL CS
:
SIGNAL WR
:

STD_LOGIC;
STD_LOGIC;
STD_LOGIC_VECTOR (7 downto 0);
STD_LOGIC_VECTOR (7 downto 0);
STD_LOGIC;
STD_LOGIC);

STD_LOGIC := '0';
STD_LOGIC := '0';
STD_LOGIC_VECTOR (7 downto 0) := (others=>'0');
STD_LOGIC_VECTOR(7 downto 0);
STD_LOGIC;
STD_LOGIC;

BEGIN
uut: AD7524_Controller PORT MAP(
Clock
=> Clock,
Reset
=> Reset,
Data_In => Data_In,
Data_Out => Data_Out,
CS
=> CS,
WR
=> WR);
Reset_Process : PROCESS
BEGIN
Wait for 0 ns;
Wait for 5 ns;
Wait;
END PROCESS;

Reset <= '0';

Reset <= '1';

Clock_Process : PROCESS
BEGIN
Wait for 0 ns;
Wait for 10 ns;
Wait for 10 ns;
END PROCESS;

Clock <= '0';

Clock <= '1';
Clock <= '0';

END ARCHITECTURE Behavioural;

Figure 8.19: VHDL test bench for DAC controller

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Appendix I
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY Pulse_Generator is
PORT ( Master_Clock
: IN
Master_Reset
: IN
Gate_Control
: OUT
END ENTITY Pulse_Generator;

STD_LOGIC;
STD_LOGIC;
STD_LOGIC);

ARCHITECTURE Behavioural OF Pulse_Generator IS

SIGNAL
SIGNAL
SIGNAL

Divider : STD_LOGIC_VECTOR(15 downto 0);

Int_Clock : STD_LOGIC;
Count
: STD_LOGIC_VECTOR(4 downto 0);

BEGIN
PROCESS(Master_Clock, Master_Reset)
BEGIN
If (Master_Reset = '0') Then
Divider(15 downto 0) <= "0000000000000000";
ElsIf (Master_Clock'event and Master_Clock = '1') Then
If (Divider = "1100001101001111") Then
Divider(15 downto 0) <= "0000000000000000";
Else
Divider(15 downto 0) <= Divider(15 downto 0) + 1;
End If;
End If;
END PROCESS;
PROCESS(Divider)
BEGIN
If (Divider = "1100001101001111") Then
Int_Clock <= '1';
Else
Int_Clock <= '0';
End If;
END PROCESS;
PROCESS(Int_Clock, Master_Reset)

Figure 8.55: Thyristor gate control pulse generator

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Chapter 8 VHDL Code Examples

BEGIN
If (Master_Reset = '0') Then
Count(4 downto 0) <= "00000";
ElsIf (Int_Clock'event and Int_Clock = '1') Then
If (Count = "10011") Then
Count(4 downto 0) <= "00000";
Else
Count(4 downto 0) <= Count(4 downto 0) + 1;
End If;
End If;
END PROCESS;

PROCESS(Count)
BEGIN
If (Count = "00001") Then
Gate_Control <= '1';
Else
Gate_Control <= '0';
End If;
END PROCESS;
END ARCHITECTURE Behavioural;

Figure 8.55: (Continued)

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Appendix I

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY Test_Pulse_Generator_vhd IS
END Test_Pulse_Generator_vhd;

ARCHITECTURE Behavioural OF Test_Pulse_Generator_vhd IS

COMPONENT Pulse_Generator
PORT(
Master_Clock : IN
Master_Reset : IN
Gate_Control : OUT
END COMPONENT;

STD_LOGIC;
STD_LOGIC;
STD_LOGIC);

SIGNAL Master_Clock :
SIGNAL Master_Reset :

STD_LOGIC := '0';
STD_LOGIC := '0';

SIGNAL Gate_Control :

STD_LOGIC;

BEGIN
uut: Pulse_Generator PORT MAP(
Master_Clock => Master_Clock,
Master_Reset => Master_Reset,
Gate_Control => Gate_Control);
Master_Reset_Process : PROCESS
BEGIN
Wait for 0 ns; Master_Reset <= '0';
Wait for 5 ns; Master_Reset <= '1';
Wait;
END PROCESS;
Master_Clock_Process : PROCESS
BEGIN
Wait for 0 ns; Master_Clock <= '0';
Wait for 10 ns; Master_Clock <= '1';
Wait for 10 ns; Master_Clock <= '0';
END PROCESS;
END ARCHITECTURE Behavioural;

Figure 8.56: Thyristor gate control pulse generator test bench

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