Академический Документы
Профессиональный Документы
Культура Документы
// User-defined identifiers
// A user-defined name given to an object with a unique name
Correct Examples:
- data_bus
- _bus3
- n$657
Incorrect Examples
- $data_bus
- 3bus
- *data
// Model 2
// Numbers
Binary: 8'b00001111
Octal: 8'o013
Decimal:
8'd15
Hexadec:
8'h0F
or
15
// Model 3
// 2-to-1 Multiplexer
module 21_mux
input
input
input
ouput
);
(
logic
logic
logic
logic
d0,
d1,
sel,
q
a;
//
[3:0] v; // a 4-bit
signed [3:0] sr; //
[-1:4] b; // a 6-bit
[4:0] x, y, z;
//
A scalar variable
vector MS->LS
a 4-bit vector in range -8 to 7
vector
Declares three 5-bit variables in one line
// Model 5
// Example of packed vs unpacked
bit [2:0] [3:0] array [5]; // 3 Columns, 5 rows, 4 bits
array[2][1] == 4'b1011; // Row 3 Col 2 is assigned the value "1011"
Packed
0
0000
0000
0000
0000
0000
Dimensions
1
2
0000
0000
0000
0000
1011
0000
0000
0000
0000
0000
// Model 6
// Constant Data Objects
0
1
2
3
4
| Unpacked Dimensions
|
|
|
|
// Logic Wires
begin
a | b;
c & d;
x ^ y;
// Model 12
// Concatenation
x = 5'b01001;
y = {x[2 : 0], 1'b0};
y = {x[4] & x[4] & x[4:2]}
y = {x[2:0] & x[4:3]}
// (x << 2) == (00001)
// (x >>> 2) == (11010) <-- Questionable
// x rotate left twice
// Model 13
// Concatenation with comma and replication
// Assuming y index is 0 to 4
y
y
y
y
=
=
=
=
'b0;
{ 'b0, 1'b1};
{1'b1, { 3 {1'b0 }};
{1'b0, 1'b0, 1'b1, 1'b0};
//
//
//
//
0000
0001
1000
0010
// Model 14
// Purely concurrent statement syntax
// assign
assign out = a & b;
//
//
//
//
?
if (condition), output is after "?"
":" represents else if
"4'bz" is the else statement
i0 :
? i1 :
? i2 :
? i3 : 4'bz;
// Model 15
// Simple generate code syntax
genvar i;
generate
for (i = 0; i < MAX; i++) begin: label
[statements]
end
endgenerate
// Model 16
// Loop Example
logic [7:0] x;
logic [15:0] y;
logic [7:0] z;
genvar i;
generate
for (i = 0; i <= 7; i++) begin: g
assign z[i] = x[i] + y[i + 8];
end
endgenerate
// Equivalent Example
assign z[0] = x[0] + y[0 + 8];
.
.
.
assign z[7] = x[7] + y[7 + 8];
// Model 17
// Create a XOR Tree
module xor_tree (
input logic [7:0] x,
ouput logic [7:0] y
);
logic [6:0] temp;
assign
assign
assign
.
.
.
assign
assign
endmodule
temp[0] = x[0];
temp[1] = temp[0] ^ x[1]
temp[2] = temp[1] ^ x[2]
endmodule
// Model 18
// Vertical Shifter
row(0):
row(1):
row(2):
row(3):
row(4):
0
0
0
0
1
0
0
1
1
0
1
1
1
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
1 1 1 1
0
0
0
0
module vshifter (
input logic [3:0] inp,
input logic [3] sel, // Final bit count
output logic [7:0] outp
);
logic [7:0] tempRow [5];
assign
assign
assign
.
.
.
assign
assign
endmodule