17bf5 COMPAL LA-6772P PDF

5
http://hobi-elektronika.net
Compal Confidential
PBL20 Project
LA-6772P REV 1.0 Schematic

B
Intel Sandy Bridge/Cougar Point(UMA)

2010-12-07 Rev. 1.0
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/05/17
Issued Date
Deciphered Date
2011/05/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
Cover Page
Size
Document Number
Rev
1.0
PBL20 LA6772P M/B

Date:
Tuesday, December 07, 2010
Sheet
1
of
45
Mobile Sandy Bridge
Compal Confidential
Model Name : PBL20
File Name : LA-6772P
CK505
Fan Control
page 5
Clock Generator
SLG8SP585VTR
Page 14
CPU Dual Core
Memory BUS(DDRIII)
Socket-rPGA989
1.5V DDRIII 1066/1333
page 5,6,7,8,9,10,11
37.5mm*37.5mm
204pin DDRIII-SO-DIMM X2
Dual Channel
DMI X4
page 15
USB/B Right USB/B Left
Smart Card
USB port 0,1
USB port 9
USB port 2
page 29
page 16
USB
HDMI
Level Shifter
HDMI Conn.
page 17
page 12,13
BANK 0, 1, 2, 3
FDI X4
LCD Conn.
CRT
page 29
page 29
Int. Camera
RTS5138 3IN1
USB port 10
USB port 11
page 15
page 32
Intel Cougar Point
page 17
FCBGA989
25mm*25mm
SATA port 0
5V 1.5GHz(150MB/s)
New Card
PCIeMini Card
WLAN & BT 2.0
USB port 8
PCIe port 5
page 29
USB port 13
PCIe port 2
page 29
SATA HDD0
page 27
USB
SATA port 2
PCIe 1x
5V 1.5GHz(150MB/s)
1.5V 2.5GHz(250MB/s)
SATA ODD
page 27
SPI ROM
page 28
RJ45
Function/B
page 30
RTL8111E Giga
RTL8105E 10/100
page 29
Power/B
PCIe 1x
1.5V 2.5GHz(250MB/s)
page 18,19,20,21
22,23,24,25,26
PCIe port 1
page 30
HD Audio
3.3V 24.576MHz/48Mhz
HDA Codec
page 34
ALC259
LPC BUS
page 31
3.3V 33 MHz
Touch Pad/B
page 34
ENE KB930
TPM 1.2
page 28
page 33
RTC CKT.
Int.
MIC CONN
page 15
page 36
DC/DC Interface CKT.
MIC CONN
page 29
HP CONN
page 29
SPK CONN
page 31
SPI ROM
Int.KBD
page 32
page 32
page 35
Power Circuit DC/DC
2010/05/17
Issued Date
page 36,37,38,39,
40,41,42,43,44
5
Compal Secret Data
Deciphered Date
2011/05/17
4
Title
Block Diagrams
Size
Document Number
Rev
1.0
PBL20 LA6772P M/B

Date:
Sheet
1
of
45
POK
B+
+3VL
+5VL
+5VALW
UP6182CQAG
B+
+VSB
TP0610K
+CPU_CORE
SUSP
ISL95831CRZ
+5VS
SI4800BDY
+VGFX_CORE
SYSON
RB161M
+HDMI_5V_OUT
+1.5V
G5603RU1U
SUSP
RB491D
USB_EN#
+CRT_VCC
+1.5VS
SI4856ADY
+USB_VCCA
RT9715BGS
SUSP#
USB_EN#
+1.05VS_VCCP
G5603RU1U
+USB_VCCB
RT9715BGS
SUSP
SUSP#
+0.75VS
UP7711U8
+1.8VS
SY8033BDBC
SUSP#
+VCCSA
G5603RU1U
+3VALW
PCH_PWR_EN#
+3VALW_PCH
SI4800BDY
SUSP
+3VS
SI4800BDY
VGA_ENVDD
AO3413
+LCD_VDD
+3V_LAN
2010/05/17
Issued Date
Compal Secret Data
2011/05/17
Deciphered Date
5
Title
Power Map
Size
Document Number
Rev
1.0
PBL20 LA6772P M/B

Date:
Sheet
1
of
45
Voltage Rails
Power Plane
Description
Adapter power supply (19V)
VIN
EC SM Bus1 address
S1
S3
S5
N/A
N/A
N/A
BATT+
Battery power supply (12.6V)
N/A
N/A
N/A
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
+VGA_CORE
Core voltage for GPU
ON
OFF
OFF
+VGFX_CORE
Core voltage for UMA graphic
ON
OFF
OFF
+0.75VS
+0.75VP to +0.75VS switched power rail for DDR terminator
ON
OFF
OFF
+1.0VSDGPU
+1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU
ON
OFF
OFF
+1.05VS_VCCP
+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU
ON
OFF
OFF
+1.05VS_PCH
+1.05VS_VCCP to +1.05VS_PCH power for PCH
ON
OFF
OFF
+1.5V
+1.5VP to +1.5V power rail for DDRIII
ON
ON
OFF
+1.5VS
+1.5V to +1.5VS switched power rail
ON
OFF
OFF
+1.5VSDGPU
+1.5VS to +1.5VSDGPU switched power rail for GPU
ON
OFF
OFF
+1.8VS
(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU
ON
OFF
OFF
+3VALW
+3VALW always on power rail
ON
ON
ON*
+3VALW_EC
+3VALW always to KBC
ON
ON
ON*
+3V_LAN
+3VALW to +3V_LAN power rail for LAN
ON
ON
ON*
+3VALW_PCH
+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)
ON
ON
ON*
+3VS
+3VALW to +3VS power rail
ON
OFF
OFF
+5VALW
+5VALWP to +5VALW power rail
ON
ON
ON*
+5VALW_PCH
+5VALW to +5VALW_PCH power rail for PCH (Short resister)
ON
ON
ON*
+5VS
+5VALW to +5VS switched power rail
ON
OFF
OFF
+VSB
+VSBP to +VSB always on power rail for sequence control
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
Device
Address
Smart Battery
0001 011X b
EC SM Bus2 address
Device
Address
D
PCH SM Bus address

Device
Address
Clock Generator (9LVS3199AKLFT,

RTM890N-631-VB-GRT)
1101 0010b
DDR DIMM0
1001 000Xb
DDR DIMM2
1001 010Xb
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
STATE
Full ON
+VALW
+V
+VS
Clock
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
5
Title

Notes List
Size Document Number

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet

1
of
45
T5
<23,33> H_PECI
1
C22
220P_0402_50V8K
H_PECI_ISO
AN33
PECI
PROCHOT#
<23> H_THRMTRIP#
R54
0_0402_5%
1
2
H_THEMTRIP#_R
AN32
THERMTRIP#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
AM34
H_CPUPWRGD_R
R65
130_0402_5%
PM_SYS_PWRGD_BUF 1
2 PM_DRAM_PWRGD_R
Processor Pullups
1 62_0402_5% H_PROCHOT#
AP33
V8
AR33
PM_SYNC
UNCOREPWRGOOD
SM_DRAMPWROK
RESET#
1 10K_0402_5% H_CPUPWRGD_R
JTAG & BPM
<23> H_CPUPWRGD
R64
0_0402_5%
1
2
H_PM_SYNC_R
PWR MANAGEMENT
<20> H_PM_SYNC
R43
R44
1
1
@
@
2 1K_0402_5%
2 1K_0402_5%
2 0_0402_5%
2 0_0402_5%
CLK_BUF_CPU_BCLK <14>
CLK_BUF_CPU_BCLK# <14>
2 0_0402_5%
2 0_0402_5%
CLK_CPU_DMI <19>
CLK_CPU_DMI# <19>
+1.05VS_VCCP
H_DRAMRST#
R8
H_DRAMRST# <7>
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
AK1
A5
A4
SM_RCOMP0 R49
1 140_0402_1%
SM_RCOMP1 R51
1 25.5_0402_1%
SM_RCOMP2 R53
1 200_0402_1%
PU/PD for JTAG signals
+1.05VS_VCCP
XDP_TMS
R55
1 51_0402_5%
AP29
AP27
XDP_PRDY#
XDP_PREQ#
XDP_TDI
R56
1 51_0402_5%
TCK
TMS
TRST#
AR26
AR27
AP30
XDP_TCK
XDP_TMS
XDP_TRST#
XDP_TDO
R57
1 51_0402_5%
XDP_TCK
R59
1 51_0402_5%
TDI
TDO
AR28
AP26
XDP_TDI
XDP_TDO
XDP_TRST# R62
1 51_0402_5%
PRDY#
PREQ#
R58
0_0402_5%
1
2
A16 R234 1
A15 R240 1
1
1
DDR3 Compensation Signals
220P_0402_50V8K
DPLL_REF_CLK
DPLL_REF_CLK#
CLK_CPU_DMI_R
CLK_CPU_DMI#_R
A28
A27
R41
R42
CATERR#
AL32
BUF_CPU_RST#
R50
AL33
H_PROCHOT#_R
R47
H_CATERR#
SKTOCC#
<33> H_PROCHOT#
For ESD
+1.05VS_VCCP
R48
0_0402_5%
1
2
AN34
BCLK
BCLK#
H_CPUPWRGD
C16
PAD
SKTOCC#
R52
56_0402_5%
1
2
H_PM_SYNC
PAD
CLOCKS
T68
PROC_SELECT#
DDR3
MISC
C26
<22> H_SNB_IVB#
THERMAL
MISC
JCPUB
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
PAD
PAD
T11
T59
R266 1K_0402_5%
1
2
+3VS
AL35 XDP_DBRESET#_R 1 R67
2 0_0402_5%
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
2
2
2
2
XDP_BPM#4_R
XDP_BPM#5_R
XDP_BPM#6_R
XDP_BPM#7_R
1
1
1
1
R73
R75
R77
R79
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
XDP_DBRESET#
XDP_DBRESET# <18,20>
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7
R74
R76
R78
R80
1
1
1
1
@
@
@
@
2
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
CFG12
CFG13
CFG14
CFG15
<10>
<10>
<10>
<10>
Sandy Bridge_rPGA_Rev1p0
@
Buffered reset to CPU
+3VS
+5VS
B
U2
NC
BUFO_CPU_RST#
R66
43_0402_1%
1
2 BUF_CPU_RST#
SN74LVC1G07DCKR_SC70-5
2
C863
10U_0805_10V4Z
@
R68
0_0402_5%
PLT_RST# <22,28,29,30,33>
1
2
3
4
+FAN1
<33> EN_DFAN1
10mil
1
2
3
@ C864
@C864
1000P_0402_50V7K
4
5
2
GND
GND
GND
GND
8
7
6
5
G996
C17
10U_0805_10V4Z
@
R219
2
10K_0402_5%
1
+3VS
FAN_SPEED1 <33>
change SA000035G00
R81
200_0402_5%
U3
74AHC1G09GW_TSSOP5
C865@
0.01U_0402_25V7K
PM_SYS_PWRGD_BUF
<20> PM_DRAM_PWRGD
GND
GND
ACES_85205-03001
R82
0_0402_5%
1
2
1
2
3
+1.5V_CPU_VDDQ
<20> SYS_PWROK
EN
VIN
VOUT
VSET
+FAN1
C83
0.1U_0402_16V4Z
1 2
@
R83
39_0402_5%
<35,42>
SUSP
SUSP
Compal Secret Data
D
2
G
3
+3VALW
Follow DG 0.71
JFAN
1
U58
1A
R60
75_0402_5%
PLT_RST# 2
FAN Control Circuit
+1.05VS_VCCP
C82
0.1U_0402_16V4Z
1
B
@
Q4
2N7002_SOT23
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title

PROCESSOR(1/7) PM,FAN

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
of
45
+1.05VS_VCCP
<20>
<20>
<20>
<20>
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
B28
B26
A24
B23
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
<20>
<20>
<20>
<20>
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
G21
E22
F21
D21
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
<20>
<20>
<20>
<20>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
G22
D22
F20
C21
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
<20>
<20>
<20>
<20>
<20>
<20>
<20>
<20>
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
A21
H19
E19
F18
B21
C20
D18
E17
<20>
<20>
<20>
<20>
<20>
<20>
<20>
<20>
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
A22
G19
E20
G18
B20
C19
D19
F17
J18
J17
<20> FDI_INT
H20
<20> FDI_LSYNC0
<20> FDI_LSYNC1
J19
H17
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
<20> FDI_FSYNC0
<20> FDI_FSYNC1
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
DMI
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
R18
24.9_0402_1%
FDI0_LSYNC
FDI1_LSYNC
eDP_COMPIO and ICOMPO signals

should be shorted near balls
and routed with typical
impedance <25 mohms
B27
B25
A25
B24
EDP_COMP
1
@ R90
A18
A17
B16
eDP_COMPIO
eDP_ICOMPO
eDP_HPD
C15
D15
eDP_AUX
eDP_AUX#
1K_0402_5%
C17
F16
C16
G15
C18
E16
D16
F15
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
eDP
+1.05VS_VCCP
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
PCI EXPRESS* - GRAPHICS
+1.05VS_VCCP
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
Intel(R) FDI
<20>
<20>
<20>
<20>
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
J22
J21
H22
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
PEG_COMP
R17
24.9_0402_1%
JCPUA
PEG_ICOMPI and RCOMPO signals should be

shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
@
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
5
Title

PROCESSOR(2/7) DMI,FDI,PEG

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
of
45
JCPUC
<12> DDR_A_D[0..63]
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
V6
<12> DDR_A_BS0
<12> DDR_A_BS1
<12> DDR_A_BS2
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
M_CLK_DDR0 <12>
<13> DDR_B_D[0..63]
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>
AA5
AB5
V10
M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>
AB4
AA4
W9
AB3
AA3
W10
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
AK3
AL3
AG1
AH1
DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]
AH3
AG3
AG2
AH2
M_ODT0 <12>
M_ODT1 <12>
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
SA_CAS#
SA_RAS#
SA_WE#
AB6
AA6
V9
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_BS[0]
SA_BS[1]
SA_BS[2]
AE8
AD9
AF9
<12> DDR_A_CAS#
<12> DDR_A_RAS#
<12> DDR_A_WE#
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
DDR SYSTEM MEMORY A
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
C4
G6
J3
M6
AL6
AM8
AR12
AM15
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS#[0..7]
D4
F6
K3
N6
AL5
AM9
AR11
AM14
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS[0..7]
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
<12>
<12>
DDR_A_MA[0..15] <12>
<13> DDR_B_BS0
<13> DDR_B_BS1
<13> DDR_B_BS2
<13> DDR_B_CAS#
<13> DDR_B_RAS#
<13> DDR_B_WE#
@
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
JCPUD
C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
R6
AA10
AB8
AB9
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
DDR SYSTEM MEMORY B
SB_CAS#
SB_RAS#
SB_WE#
M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>
AE1
AD1
R10
M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB <13>
AA1
AB1
T10
SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]
AD3
AE3
AD6
AE6
DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>
SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]
AE4
AD4
AD5
AE5
M_ODT2 <13>
M_ODT3 <13>
D7
F3
K6
N3
AN5
AP9
AK12
AP15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS#[0..7]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
C7
G3
J6
M3
AN6
AP8
AK11
AP14
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS[0..7]
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
AB2
AA2
T9
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
SB_BS[0]
SB_BS[1]
SB_BS[2]
AE2
AD2
R9
<13>
<13>
DDR_B_MA[0..15] <13>
@
+1.5V
R85
1K_0402_5%
2
@ R84
0_0402_5%
1
2
H_DRAMRST#
DDR3_DRAMRST#_R
1
Q5
BSS138_NL_SOT23-3
3
2
<5> H_DRAMRST#
R86
1K_0402_5%
2
1
R88
0_0402_5%
1
2
<19> DRAMRST_CNTRL_PCH
R89
<33> DRAMRST_CNTRL_EC
+1.5V
DRAMRST_CNTRL
close PJP502
2 0_0402_5%
C233
0.047U_0402_16V4Z
DDR3_DRAMRST# <12,13>
R87
4.99K_0402_1%
C84
0.047U_0402_16V4Z
C232
0.047U_0402_16V4Z
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
4
Title

PROCESSOR(3/7) DDRIII

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
of
45
POWER
JCPUF
+CPU_CORE
1
+
2
1
+ @ C122
330U_D2_2V_Y
2
+1.05VS_VCCP
R98
75_0402_5%
SVID
C121
330U_D2_2V_Y
CORE SUPPLY
C105
22U_0805_6.3V6M
C114
22U_0805_6.3V6M
C117
330U_D2_2V_Y
C92
22U_0805_6.3V6M
C113
22U_0805_6.3V6M
C91
22U_0805_6.3V6M
R99
43_0402_1%
1
2
R100 1
2 0_0402_5%
R101 1
2 0_0402_5%
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
VR_SVID_ALRT# <44>
VR_SVID_CLK <44>
VR_SVID_DAT <44>
Place the PU
resistors close to VR
Place the PU
resistors close to CPU
+CPU_CORE
VCCIO_SENSE
VSSIO_SENSE
B10
A10
2
2
0_0402_5%
0_0402_5%
VCCSENSE <44>
VSSSENSE <44>
R105
100_0402_1%
VCCIO_SENSE <41>
R1370
2
10_0402_5%
Compal Secret Data
Issued Date
R103 1
R104 1
AJ35 VCCSENSE_R
AJ34 VSSSENSE_R
VCC_SENSE
VSS_SENSE
SENSE LINES
R102
100_0402_1%
@
2010/05/17
2011/05/17
Deciphered Date
4
C112
22U_0805_6.3V6M
R97
130_0402_5%
AJ29
AJ30
AJ28
+1.05VS_VCCP
VIDALERT#
VIDSCLK
VIDSOUT
C104
22U_0805_6.3V6M
Bottom Socket Edge
C111
22U_0805_6.3V6M
C90
22U_0805_6.3V6M
C110
22U_0805_6.3V6M
C103
22U_0805_6.3V6M
C109
22U_0805_6.3V6M
J23
+1.05VS_VCCP
C89
22U_0805_6.3V6M
C140
330U_D2_2V_Y
C139
330U_D2_2V_Y
C138
330U_D2_2V_Y
C137
330U_D2_2V_Y
VCCIO40
C108
22U_0805_6.3V6M
+CPU_CORE
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
C88
22U_0805_6.3V6M
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
+1.05VS_VCCP
1
C107
22U_0805_6.3V6M
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
C102
22U_0805_6.3V6M
C136
22U_0805_6.3V6M
C132
22U_0805_6.3V6M
C127
22U_0805_6.3V6M
C120
22U_0805_6.3V6M
C135
22U_0805_6.3V6M
C131
22U_0805_6.3V6M
C94
22U_0805_6.3V6M
C85
22U_0805_6.3V6M
C87
22U_0805_6.3V6M
C130
22U_0805_6.3V6M
C96
22U_0805_6.3V6M
C98
22U_0805_6.3V6M
C133
22U_0805_6.3V6M
C86
22U_0805_6.3V6M
C129
22U_0805_6.3V6M
C93
22U_0805_6.3V6M
C99
22U_0805_6.3V6M
C100
22U_0805_6.3V6M
1
C
C116
22U_0805_6.3V6M
C97
22U_0805_6.3V6M
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
C106
22U_0805_6.3V6M
+CPU_CORE
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
Top Socket Cacity 22U *9

Bottom Socket Cacity 22U *10
C101
22U_0805_6.3V6M
C134
10U_0805_10V6K
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
C126
10U_0805_10V6K
C115
10U_0805_10V6K
C123
10U_0805_10V6K
C95
10U_0805_10V6K
C125
10U_0805_10V6K
C118
10U_0805_10V6K
C128
10U_0805_10V6K
C124
10U_0805_10V6K
2
D
C119
10U_0805_10V6K
8.5A
PEG AND DDR
94A
Title

PROCESSOR(4/7) PWR,BYPASS

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
of
45
+1.5V_CPU_VDDQ Source
+1.5V
Q6
AO4728L_SO8
+VSB
+3VALW
R107
470_0603_5%
RUN_ON_CPU1.5VS3
R108
100K_0402_5%
+1.5V_CPU_VDDQ
+1.5V
D
R106
100K_0402_5%
+1.5V_CPU_VDDQ
1
2
3
8
7
6
5
RUN_ON_CPU1.5VS3#
4
@ R111
0_0402_5%
1
2
R109
330K_0402_5%
Q7A
2N7002DW-T/R7_SOT363-6
C142
S
0.1U_0402_16V4Z
2 RUN_ON_CPU1.5VS3#
G
Q8
2N7002E-T1-GE3_SOT23-3
C141
1 0.1U_0402_10V7K
C143
1 0.1U_0402_10V7K
<28,29,33,35,39,41,43> SUSP#
1
3
<33> CPU1.5V_S3_GATE
Q7B
2N7002DW-T/R7_SOT363-6
R110
0_0402_5%
1
2
POWER
SENSE
LINES
1
2
1
+V_SM_VREF
@ Q9
AP2302GN-HF_SOT23-3
R115
1K_0402_1%
1
2
RUN_ON_CPU1.5VS3
VREF
C156
0.1U_0402_16V4Z
SA RAIL
PJ4
2
@ JUMP_43X118
C169
330U_D2_2V_Y
Bottom Socket Edge

B
6A
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA_SENSE
FC_C22
VCCSA_VID1

Bottom Socket Edge 10U *1
+VCCSA
+VCCSA
M27
M26
L26
J26
J25
J24
H26
H25
H23
R116
2 0_0402_5%
VCCSA_SENSE
1
+
C174
330U_D2_2V_Y
VCCSA_SENSE <43>
C22 H_FC_C22
C24
VCCSA_SEL <43>
1
MISC
VCCPLL1
VCCPLL2
VCCPLL3
+1.5V
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
10A
C168
10U_0603_6.3V6M
DDR3 -1.5V RAILS
+1.5V_CPU_VDDQ
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
C167
10U_0603_6.3V6M
R119
10K_0402_5%
@
@ R120
0_0402_5%
B6
A6
A2
+V_SM_VREF_CNT
C173
10U_0603_6.3V6M
C178
1U_0402_6.3V6K
C177
1U_0402_6.3V6K
C176
10U_0603_6.3V6M
C175
330U_D2_2V_Y
AL1
R114
1K_0402_1%
C172
10U_0603_6.3V6M
+1.8VS_VCCPLL
1
SM_VREF
C171
10U_0603_6.3V6M
R118
0_0805_5%
1
2
+V_SM_VREF should
have 20 mil trace width
C170
10U_0603_6.3V6M
+1.8VS
+1.5V_CPU_VDDQ
R113
0_0402_5%
2
1
C166
10U_0603_6.3V6M
Bottom Socket Edge

B
Follow DG 0.71 page 6
VCC_AXG_SENSE <44>
VSS_AXG_SENSE <44>
C165
10U_0603_6.3V6M
AK35
AK34
C164
10U_0603_6.3V6M
VAXG_SENSE
VSSAXG_SENSE
GRAPHICS
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
C163
10U_0603_6.3V6M
C162
22U_0805_6.3V6M
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
UMA@
C152
22U_0805_6.3V6M
UMA@
C148
22U_0805_6.3V6M
C161
22U_0805_6.3V6M
UMA@
C151
22U_0805_6.3V6M
UMA@
C147
22U_0805_6.3V6M
C160
22U_0805_6.3V6M
UMA@
C155
22U_0805_6.3V6M
C159
22U_0805_6.3V6M
UMA@
C154
22U_0805_6.3V6M
UMA@
C158
470U_D2_2VM_R4.5M
UMA@
C157
470U_D2_2VM_R4.5M
UMA@
C150
22U_0805_6.3V6M
UMA@
C149
22U_0805_6.3V6M
UMA@
C146
22U_0805_6.3V6M
UMA@
C145
22U_0805_6.3V6M
UMA@
C144
22U_0805_6.3V6M
UMA@
C153
22U_0805_6.3V6M
Top Socket Cacity 22U *2

Top Socket Edge 22U *6
Bottom Socket Edge 22U *6
JCPUG
26A
1.8V RAIL
+VGFX_CORE
Bottom Socket Edge

Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
5
Title

PROCESSOR(5/7) PWR

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
of
45
CFG Straps for Processor

JCPUE
PEG Static Lane Reversal - CFG2 is for the 16x
CFG7
<5>
<5>
<5>
<5>
CFG12
CFG13
CFG14
CFG15
CFG12
CFG13
CFG14
CFG15
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
L7
AG7
AE7
AK2
W8
RSVD33
RSVD34
RSVD35
AT26
AM33
AJ27
RSVD37
RSVD38
RSVD39
RSVD40
T8
J16
H16
G16
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
AR35
AT34
AT33
AP35
AR34
1: Normal Operation; Lane #

socket pin map definition
CFG2
definition matches
0:Lane Reversed
Display Port Presence Strap
1 : Disabled; No Physical Display Port

attached to Embedded Display Port
CFG4
0 : Enabled; An external Display Port device is

connected to the Embedded Display Port
PCIE Port Bifurcation Straps

C
PAD
PAD
PAD
PAD
AJ31
AH31
AJ33
AH33
AJ26
R93
1K_0402_1%
2
R92
1K_0402_1%
2
B4
D1
RSVD5
RSVD6
RSVD7
CPU_RSVD6
CPU_RSVD7
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
J20
B18
A19
J15
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RESERVED
T6
T7
T8
T9
RSVD24
RSVD25
VCCIO_SEL
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG[6:5]
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
B34
A33
A34
B35
C35
PEG DEFER TRAINING
CFG7
RSVD51
RSVD52
VCC_DIE_SENSE
*10: x8, x8 - Device 1 function 1 enabled ; function 2
1: (Default) PEG Train immediately following xxRESETB

de assertion
0: PEG Wait for BIOS for training
AJ32
AK32
PAD
AH27
T10
R94
CFG7
RSVD54
RSVD55
AN35
AM35
CLK_RES_ITP <19>
CLK_RES_ITP# <19>
2
1K_0402_1%
B
RSVD56
RSVD57
RSVD58
AT2
AT1
AR1
RSVD27
KEY
B1
@
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
5
Title

PROCESSOR(6/7) RSVD,CFG

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
10
of
45
JCPUH
D
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
JCPUI
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
@
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
@
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
5
Title

PROCESSOR(7/7) VSS

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
11
of
45
+1.5V
DDR_A_DQS#1
DDR_A_DQS1
All VREF traces should

DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_MA10
DDR_A_BS0
<7> DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
<7> DDR_A_WE#
<7> DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
<7> DDR_CS1_DIMMA#
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
+3VS
2
1
D_CK_SCLK
Q2
2N7002E-T1-GE3_SOT23-3
2
G
D
D
2
G
3
R135
10K_0402_5%
R134
10K_0402_5%
<19> PCH_SMBCLK
C200
2.2U_0603_6.3V6K
R4
4.7K_0402_5%
1
2
+3VS
C199
0.1U_0402_16V4Z
+0.75VS
+3VS
205
G2
206
G1
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
1
+
2
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>
DDR_CS0_DIMMA# <7>
M_ODT0 <7>
M_ODT1
<7>
1
DDR_A_D38
DDR_A_D39
+1.5V
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDR_A_D36
DDR_A_D37
R124
1K_0402_1%
+VREF_CA
DDR_A_D44
DDR_A_D45
Layout Note:
Place near JDIMM1.203,204
+0.75VS
R125
1K_0402_1%
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
For EMI
+3VS
+0.75VS
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
D_CK_SDATA
D_CK_SCLK
D_CK_SDATA <13,14,29>
D_CK_SCLK <13,14,29>
+0.75VS
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
4
LCN_DAN06-K4526-0100
@
Issued Date
C238
0.1U_0402_16V4Z
Q1
2N7002E-T1-GE3_SOT23-3
+3VS
C237
0.1U_0402_16V4Z
D_CK_SDATA
DDR_CKE1_DIMMA <7>
DDR_A_MA15
DDR_A_MA14
C236
0.1U_0402_16V4Z
+1.5V
DDR_CKE1_DIMMA
C235
0.1U_0402_16V4Z
DDR_A_D58
DDR_A_D59
DDR_A_D30
DDR_A_D31
C234
0.1U_0402_16V4Z
R1
4.7K_0402_5%
1
2
+3VS
C198
1U_0402_6.3V6K
DDR_A_D48
DDR_A_D49
C197
1U_0402_6.3V6K
DDR_A_D42
DDR_A_D43
C196
1U_0402_6.3V6K
DDR_A_D40
DDR_A_D41
C195
1U_0402_6.3V6K
DDR_A_D34
DDR_A_D35
B
DDR_A_DQS#3
DDR_A_DQS3
C194
0.1U_0402_16V4Z
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D28
DDR_A_D29
C193
2.2U_0603_6.3V6K
DDR_A_D32
DDR_A_D33
DDR_A_D22
DDR_A_D23
C192
330U_D2_2V_Y
<7> M_CLK_DDR0
<7> M_CLK_DDR#0
+1.5V
C191
10U_0603_6.3V6M
M_CLK_DDR0
M_CLK_DDR#0
Layout Note:
Place near JDIMM1
DDR_A_D20
DDR_A_D21
C190
10U_0603_6.3V6M
DDR_A_MA3
DDR_A_MA1
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_A_D14
DDR_A_D15
C189
10U_0603_6.3V6M
DDR_A_MA8
DDR_A_MA5
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
DDR3_DRAMRST#
C188
10U_0603_6.3V6M
DDR_A_MA12
DDR_A_MA9
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
C187
10U_0603_6.3V6M
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
<7>
DDR_A_D12
DDR_A_D13
C186
10U_0603_6.3V6M
DDR_A_BS2
<7> DDR_A_BS2
DDR_A_D[0..63]
DDR_A_MA[0..15] <7>
DDR_A_D6
DDR_A_D7
C185
10U_0603_6.3V6M
<7> DDR_CKE0_DIMMA
<7>
C184
1U_0402_6.3V6K
DDR_CKE0_DIMMA
<7>
DDR_A_DQS[0..7]
C183
1U_0402_6.3V6K
DDR_A_D26
DDR_A_D27
DDR_A_DQS#0
DDR_A_DQS0
C182
1U_0402_6.3V6K
DDR_A_D24
DDR_A_D25
DDR_A_DQS#[0..7]
DDR_A_D4
DDR_A_D5
C181
1U_0402_6.3V6K
DDR_A_D18
DDR_A_D19
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
DDR_A_D8
DDR_A_D9
R123
1K_0402_1%
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
DDR_A_D2
DDR_A_D3
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
DDR_A_D0
DDR_A_D1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
C180
0.1U_0402_16V4Z
+V_DDR_REF
C179
2.2U_0603_6.3V6K
+V_DDR_REF
<19> PCH_SMBDATA
+1.5V
JDDRL
+V_DDR_REF
R122
1K_0402_1%
+1.5V
Title

DDRIII DIMMA

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
12
of
45
+V_DDR_REF
+1.5V
+1.5V
JDDRH
+V_DDR_REF
C202
0.1U_0402_16V4Z
All VREF traces should

C201
2.2U_0603_6.3V6K
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
<7> DDR_B_WE#
<7> DDR_B_CAS#
<7> DDR_CS3_DIMMB#
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
+3VS
+3VS
C222
2.2U_0603_6.3V6K
C221
0.1U_0402_16V4Z
DDR_B_D56
DDR_B_D57
1
R149
10K_0402_5%
DDR_B_D50
DDR_B_D51
DDR_B_D58
DDR_B_D59
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
Layout Note:
Place near JDIMMB
+1.5V
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB <7>
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
1
+
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>
DDR_B_BS1 <7>
DDR_B_RAS# <7>
DDR_CS2_DIMMB#
M_ODT2
DDR_CS2_DIMMB# <7>
M_ODT2 <7>
M_ODT3
M_ODT3
Layout Note:
Place near JDIMMB.203,204
+0.75VS
<7>
+VREF_CA
1
DDR_B_D36
DDR_B_D37
1
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
D_CK_SDATA
D_CK_SCLK
D_CK_SDATA <12,14,29>
D_CK_SCLK <12,14,29>
+0.75VS
+0.75VS
C218
1U_0402_6.3V6K
DDR_B_D42
DDR_B_D43
C217
1U_0402_6.3V6K
DDR_B_D40
DDR_B_D41
C216
1U_0402_6.3V6K
DDR_B_D28
DDR_B_D29
C215
1U_0402_6.3V6K
DDR_B_D34
DDR_B_D35
C220
0.1U_0402_16V4Z
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D22
DDR_B_D23
C219
2.2U_0603_6.3V6K
DDR_B_D32
DDR_B_D33
+1.5V
DDR_B_D20
DDR_B_D21
C214
330U_D2_2V_Y
<7> DDR_B_BS0
DDR_B_MA10
DDR_B_BS0
DDR_B_D14
DDR_B_D15
C213
10U_0603_6.3V6M
<7> M_CLK_DDR2
<7> M_CLK_DDR#2
DDR3_DRAMRST#
C212
10U_0603_6.3V6M
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
<7>
DDR_B_MA[0..15] <7>
C211
10U_0603_6.3V6M
DDR_B_MA8
DDR_B_MA5
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
DDR_B_D[0..63]
C210
10U_0603_6.3V6M
DDR_B_MA12
DDR_B_MA9
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
<7>
DDR_B_D12
DDR_B_D13
C209
10U_0603_6.3V6M
DDR_B_BS2
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
<7>
DDR_B_DQS[0..7]
DDR_B_D6
DDR_B_D7
C208
10U_0603_6.3V6M
<7> DDR_B_BS2
DDR_CKE2_DIMMB
DDR_B_DQS#[0..7]
DDR_B_DQS#0
DDR_B_DQS0
C207
10U_0603_6.3V6M
<7> DDR_CKE2_DIMMB
DDR_B_D4
DDR_B_D5
C206
1U_0402_6.3V6K
DDR_B_D26
DDR_B_D27
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
C205
1U_0402_6.3V6K
DDR_B_D24
DDR_B_D25
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
C204
1U_0402_6.3V6K
DDR_B_D18
DDR_B_D19
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
C203
1U_0402_6.3V6K
DDR_B_DQS#2
DDR_B_DQS2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
205
R150
10K_0402_5%
G1
G2
206
A
LCN_DAN06-K4926-0100
@
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
5
Title

DDRIII DIMMB

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
13
of
45
SM010014520 3000ma 220ohm@100mhz DCR 0.04

@ L1
FBMA-L11-201209-221LMA30T_0805
2
1
+3VS
@ L2
FBMA-L11-201209-221LMA30T_0805
2
1
+1.05VS_PCH
+1.5VS
C12
0.1U_0402_16V4Z
C13
0.1U_0402_16V4Z
C9 @
10U_0603_6.3V6M
C11
0.1U_0402_16V4Z
@ L4
2
1
FBMA-L11-201209-221LMA30T_0805
C10
10U_0603_6.3V6M
40mil
C8
0.1U_0402_16V4Z
+CLK_1.5VS
1
C5 @
10U_0603_6.3V6M
C7
0.1U_0402_16V4Z
+CLK_1.05VS
40mil
C6
10U_0603_6.3V6M
C4
0.1U_0402_16V4Z
1
@ L3
FBMA-L11-201209-221LMA30T_0805 2
2
1
C3
0.1U_0402_16V4Z
C2
10U_0603_6.3V6M
@ C1
10U_0603_6.3V6M
+CLK_3VS
40mil
Use internal Clock first, reseve external clock.
@ U1
+CLK_1.5VS
+CLK_3VS
1
5
+CLK_1.05VS
15
18
17
24
29
+CLK_1.5VS
+CLK_3VS
VDD_DOT
VDD_27
CPU_0
23
CLK_BCLK
CPU_0#
22
CLK_BCLK# R3 @ 2
1 33_0402_5% CLK_BUF_CPU_BCLK#
10
CLK_SATA
1 33_0402_5% CLK_BUF_PCIE_SATA
CLK_BUF_PCIE_SATA <19>
11
CLK_SATA# R6 @ 2
1 33_0402_5% CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA# <19>
13
CLK_DMI
R7 @ 2
1 33_0402_5% CLK_BUF_CPU_DMI
CLK_BUF_CPU_DMI <19>
14
CLK_DMI#
R8 @ 2
1 33_0402_5% CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI# <19>
CLK_96M
R10 @ 2
1 33_0402_5% CLK_BUF_DREF_96M
CLK_BUF_DREF_96M <19>
CLK_96M#
R11 @ 2
1 33_0402_5% CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M# <19>
VDDSRC_IO
VDDCPU_IO
CPU_1
VDDSRC_3.3
VDDCPU_3.3
VDDREF_3.3
CPU_1#
SRC_1/SATA
SRC_1/SATA#
Silego Have Internal Pull-Up

+CLK_3VS
<12,13,29> D_CK_SDATA
IDT 9LVS3199AKLFT NC
<12,13,29> D_CK_SCLK
D_CK_SDATA
D_CK_SCLK
@ R25 0_0402_5%
D_CK_SDATA_R
2
1
2
D_CK_SCLK_R
31
32
SDA
SRC_2
SCL
SRC_2#
R2 @ 2
1 33_0402_5% CLK_BUF_CPU_BCLK
CLK_BUF_CPU_BCLK <5>
CLK_BUF_CPU_BCLK# <5>
20
19
R5 @ 2
@ R26 0_0402_5%
@R9
@
R9
H_STP_CPU#
2 10K_0402_5%
H_STP_CPU#
@ R12
0_0402_5%
2
1
<20,33,44> VGATE
16
DOT_96
CPU_STOP#
DOT_96#
CK505_PWRGD
25
CKPWRGD/PD#
27MHz
27MHz_SS
6
7
CLK_XTAL_OUT
CLK_XTAL_OUT
27
14.31818MHZ_20P_1BX14318BE1A
@
2
2
C15
33P_0402_50V8J
28
CLK_XTAL_IN
Y1
2
CLK_XTAL_IN
<19> CLK_BUF_ICH_14M
C14
33P_0402_50V8J
CLK_BUF_ICH_14M
@ R15
@R15
33_0402_5%
2
1
REF_0/CPU_SEL 30
XTAL_IN
XTAL_OUT
VSS_DOT
VSS_27
VSS_SATA
VSS_SRC
VSS_CPU
VSS_REF
EP
REF_0/CPU_SEL
2
8
9
12
21
26
33
SLG8SP585VTR_QFN32_5X5
Standard
IDT: 9LRS3199AKLFT, SA000030P00
SILEGO: SLG8SP587V(WF), SA00002XY10
IDT Have Internal Pull-Down
FOR Realtek
R16
2 10K_0402_5% REF_0/CPU_SEL
1
@
PIN 30
CPU_0
0 (Default)
133MHz
133MHz
100MHz
100MHz
CPU_1
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
A
Title
Clock Generator (CK505)

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
G
Sheet
14
H
of
45
1
+LCD_VDD
R1438
+3VS
Vds=-20V
Id=-3A
Rds=130m ohm
Vgs=-4.5
Vth=-1
1
Q61A
2N7002DW-T/R7_SOT363-6
R688
2
100K_0402_5%
C908
0.1U_0402_16V7K
C958
180P_0402_50V8J
1
R697
Q61B
<21> VGA_ENVDD
C712
0.01U_0402_25V7K
5
4
R1379
0_0402_5%
2
47K_0402_5%
R1441
+LCD_VDD
1
2N7002DW-T/R7_SOT363-6
W=80mils
1
@ C711
4.7U_0805_10V4Z
R693
100K_0402_5%
Q18
AO3413_SOT23
0_0402_5%
+3VS
<21> VGA_BL_PWM
R698
300_0603_5%
+3VS
4.7K_0402_5%
LCD_BL_PWM
6 2
R1440
2
@ 0_0402_5%
1
<33> INVT_PWM
+LCDVDD_R
L24 2
1
0_0805_5%
C713
0.1U_0402_16V4Z
C710
4.7U_0805_10V4Z
C709
0.1U_0402_16V4Z
Close to JLVDS
LCD/PANEL BD. Conn.
<22> USB20_P10
<22> USB20_N10
L26
@2
USB20_P10_R
WCM2012F2SF-900T04_0805
USB20_N10_R
1
+5VS
R1426
2
<21>
<21>
<21>
<21>
<21>
<21>
LCD_TXOUT0+
LCD_TXOUT0LCD_TXOUT1+
LCD_TXOUT2-
<21>
<21>
<21>
<21>
<21>
<21>
LCD_TZOUT0+
LCD_TZOUT0LCD_TZOUT1+
LCD_TZOUT2-
R433 0_0402_5%
+3VS
+LCD_INV
W=30mils
0_0603_5%
1
0_0603_5%
1
USB20_P10_R
USB20_N10_R
47P_0402_50V8J
1
@ JLVDS
LCD_TXOUT0+
LCD_TXOUT2LCD_TZOUT0+
LCD_TZOUT2-
C912
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
GND2GND1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
LCD_TXCLK+
LCD_TXCLK-
@
PJDLC05C_SOT23-3
D21
LCD_TZCLK+ <21>
LCD_TZCLK- <21>
EDID_CK
EDID_DAT
R1382 1
R1392 1
2 0_0402_5%
2 0_0402_5%
LCD_EDID_CLK <21>
LCD_EDID_DATA <21>
+3VS
LCD_BL_PWM
+LCDVDD_R
BKOFF#_R
@
+LCD_INV
ACES_87142-4041-BS
1
C715
68P_0402_50V8J
1.5A
C399
C714
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
B+
L23
2
1
FBMA-L11-201209-221LMA30T_0805
1 Rated Current 1MAX:3000mA
C319
0.1U_0402_25V4K
100K_0402_5%
R1191
8/25 For +3VS leakage

B
@ C400
680P_0402_50V7K
LCD_TXCLK+ <21>
LCD_TXCLK- <21>
LCD_TZCLK+
LCD_TZCLK-
R432 0_0402_5%
2
1
@
R1427
2
BKOFF#
R27
33_0402_5%
2
1
BKOFF#_R
<33>
R1421
10K_0402_5%
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
5
Title
LVDS Connector
Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
15
of
45
R703
CRT@
1
C723
CRT@
C722
CRT@
CRT_B_L
C720
CRT@
1
C724
CRT@
C721
CRT@
C719
CRT@
@ C716
470P_0402_50V8J
R702
CRT@
CRT_G_L
L20 CRT@
1
2
NBQ100505T-800Y_0402
2.2P_0402_50V8C
R701
CRT@
L19 CRT@
1
2
NBQ100505T-800Y_0402
2.2P_0402_50V8C
CRT_R_L
2.2P_0402_50V8C
L18 CRT@
1
2
NBQ100505T-800Y_0402
2.2P_0402_50V8C
CRT_DDC_CK
2N7002DW-T/R7_SOT363-6
1
@ C717
@ C867
470P_0402_50V8J
33P_0402_50V8K
2
2.2P_0402_50V8C
<21> VGA_CRT_B
2.2P_0402_50V8C
CRT_DDC_DAT
2
1
150_0402_1%
5
1
@C866
@
C866
33P_0402_50V8K
<21> VGA_CRT_G
2N7002DW-T/R7_SOT363-6
CRT@ Q157B
4
<21> VGA_CRT_CLK
<21> VGA_CRT_R
2
1
150_0402_1%
2
1
<21> VGA_CRT_DATA
CRT@
R700
4.7K_0402_5%
CRT@
Q157A
6
4.7K_0402_5%
CRT@
R699
2
1
150_0402_1%
+CRT_VCC
+3VS
D31
@
PESD5V0U2BT_SOT23-3
3
D30
@
PESD5V0U2BT_SOT23-3
+5VS
40mil
D58
2
3
+CRT_VCC_R
+CRT_VCC
F3 CRT@
1
1
2
RB491D_SOT23-3
1
1.1A_6V_MINISMDC110F-2
CRT@
C718
0.1U_0402_16V4Z
2
@
+CRT_VCC
R1436
2
P
OE#
D_CRT_HSYNC
<21> VGA_CRT_HSYNC
10K_0402_5%
1
CRT@
5
1
CRT@
1
2
C725
0.1U_0402_16V4Z
+CRT_VCC
CRT@
1
2
L21
10_0402_5%
HSYNC
3
U46
SN74AHCT1G125GW_SOT353-5
CRT@
JCRT
PAD
CRT_DDC_DAT
CRT_G_L
Y
U45
SN74AHCT1G125GW_SOT353-5
CRT@
1
@ C726
@ C727
@C727
HSYNC
CRT_B_L
+CRT_VCC
10P_0402_50V8J
VSYNC
10P_0402_50V8J
P
OE#
CRT@
D_CRT_VSYNC1
2
L22
10_0402_5%
<21> VGA_CRT_VSYNC
CRT_TEST1
CRT_R_L
T76
5
1
CRT@
1
2
C868
0.1U_0402_16V4Z
PAD
VSYNC
CRT_TEST2
T75
CRT_DDC_CK
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
16
17
RGND
ID0
Red
GGND
SDA
Green
BGND
Hsync
Blue
+5V
Vsync
res
SGND
SCL
GND
GND
GND
SUYIN_070546FR015S293ZR
@
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
A
Title
CRT Connector
Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
E
16
of
45
For EMI
Change 90 ohm
P/N:SM070000K00
VGA_DVI_TXD0-
1
L15
1
4
2 R237
0_0402_5%
HDMI@
2 2
HDMI@
1
1.1A_6V_MINISMDC110F-2
F2 HDMI@
2
1
+HDMI_5V_OUT
1
C308
HDMI@
0.1U_0402_16V4Z
2
HDMI_R_CK+
+3VS
HDMI_R_D0-
R1568
1M_0402_5%
WCM-2012-121T_0805
@
1
2 R236
0_0402_5%
VGA_DVI_TXD0+
RB161M-20_SOD123-2 D53
2
+5VS
40mil
WCM-2012-121T_0805
@
1
2 R227
0_0402_5%
VGA_DVI_TXC+
@
1
HDMI_HPD
HDMI_R_D0+
+3VS
C728
HDMI@
0.1U_0402_16V4Z
+3VS
+HDMI_5V_OUT
2 R251
0_0402_5%
HDMI@
2 2
HDMI_R_D2-
HDMI_SDATA
1
1
R1331
2.2K_0402_5%
HDMI@
VGA_HDMI_CLK <21>
BSH111_SOT23-3
HDMI@
Q183
3
Q182
BSH111_SOT23-3
HDMI@
1
VGA_HDMI_DATA <21>
HDMI_R_D2+
HDMI_R_CK+ 1
R1560
HDMI_R_CK- 1
R1561
HDMI_R_D1- 1
R1562
HDMI_R_D1+ 1
R1563
HDMI_R_D0- 1
R1564
HDMI_R_D0+ 1
R1565
HDMI_R_D2+ 1
R1566
HDMI_R_D2- 1
R1567
PCIE_MTX_GRX_HDMI_N3
<21>
<21>
<21>
<21>
PCIE_MTX_GRX_HDMI_P3
HDMI@
20K_0402_1%
R573
WCM-2012-121T_0805
@
1
2 R223
0_0402_5%
<21>
<21>
<21>
<21>
VGA_HDMI_HPD <21>
2
2
R1332
2.2K_0402_5%
HDMI@
CV174 1
CV179 1
CV178 1
2 0.1U_0402_16V7K HDMI@
CV172 1
2 0.1U_0402_16V7K HDMI@
2 0.1U_0402_16V7K HDMI@
CV176 1
2 0.1U_0402_16V7K HDMI@
CV173 1
2 0.1U_0402_16V7K HDMI@
2 0.1U_0402_16V7K HDMI@
2 0.1U_0402_16V7K HDMI@
2
680_0402_5%
2
680_0402_5%
2
680_0402_5%
2
680_0402_5%
2
680_0402_5%
2
680_0402_5%
2
680_0402_5%
2
680_0402_5%
HDMI Connector
JHDMI
HDMI_HPD
+HDMI_5V_OUT
HDMI_SDATA
HDMI_SCLK
HDMI_R_CK-
2
G
+3VS
VGA_DVI_TXCVGA_DVI_TXD2VGA_DVI_TXD1VGA_DVI_TXD0-
Intel spec suggest

to use 680 ohm
R1329
2.2K_0402_5%
HDMI@
1
L13
1
HDMI_SCLK
HDMI_R_D1+
VGA_DVI_TXD2-
R1328
2.2K_0402_5%
HDMI@
WCM-2012-121T_0805
@
1
2 R247
0_0402_5%
VGA_DVI_TXD1+
VGA_DVI_TXD2+
HDMI_R_D1-
G S
2
2 R249
0_0402_5%
HDMI@
2 2
L12
1
1
1
2
2
VGA_DVI_TXD1-
2N7002_SOT23-3
Q16 HDMI@
1
+5VS_HDMI
RB161M-20_SOD123-2 D32
2
+5VL
2
G
HDMI_R_CK-
2 R225
0_0402_5%
HDMI@
2 2
1
L14
VGA_DVI_TXCD
HDMI_R_CK+
HDMI_R_D0HDMI@
Q15
2N7002_SOT23-3
HDMI_R_D0+
HDMI_R_D1HDMI_R_D1+
HDMI_R_D2-
1 HDMI@ 2
1 R704 100K_0402_5%
C309
HDMI_R_D2+
CV175 1
CV177 1
2 0.1U_0402_16V7K HDMI@
VGA_DVI_TXC+
VGA_DVI_TXD2+
VGA_DVI_TXD1+
VGA_DVI_TXD0+
0.1U_0402_16V4Z
2
HDMI@
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
SUYIN_100042MR019S153ZL
@
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
5
Title
HDMI Level Shift & Conn

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
17
of
45
<31> HDA_SPKR
R176 1
HDA_SPKR
2 1K_0402_5%
@ R179
1K_0402_5%
2
1
@ R178
0_0402_5%
2
1
HDA_SDO
HDA_SYNC_R
+3VALW_PCH
@ R188
0_0402_5% <31> HDA_SDIN0
HIGH= Enable ( No Reboot )

LOW= Disable (Default)
HDA_SDOUT
SM_INTRUDER#
K22
PCH_INTVRMEN
C17
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
HDA_RST#
K34
HDA_RST#
HDA_SDOUT
Prevent back drive issue.
PCH_KILL_SW#
<29> PCH_KILL_SW#
E34
HDA_SDIN0
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
R189
51_0402_5%
2
1
This signal has a weak internal pull-down
<31> HDA_SYNC_AUDIO
<31> HDA_RST_AUDIO#
<31> HDA_SDOUT_AUDIO
K5
PCH_JTAG_TDO
H1
JTAG_TMS
JTAG_TDI
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AM3
AM1
AP7
AP5
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
AM10
AM8
AP11
AP10
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AD7
AD5
AH5
AH4
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
AB8
AB10
AF3
AF1
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
Y7
Y5
AD3
AD1
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
Y3
Y1
AB3
AB1
SATAICOMPO
SATAICOMPI
JTAG_TDO
SATA3RCOMPO
SATA3COMPI
PCH_SPI_CLK
1
R1457
<28> PCH_SPI_CS0#
2 PCH_SPICLK T3
0_0402_5%
PCH_SPI_CS0#
Y14
T1
<28> PCH_SPI_MOSI
<28> PCH_SPI_MISO
PCH_SPI_MOSI
V4
PCH_SPI_MISO
U3
SPI_CLK
LPC_FRAME# <28,33>
SATA3RBIAS
SERIRQ
NB HDD
SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2
AH1
+3VS
R192
37.4_0402_1%
1
2
SATA_COMP
AB12
AB13
SATA_PRX_C_DTX_N2 <27>
SATA_PRX_C_DTX_P2 <27>
SATA_PTX_DRX_N2 <27>
SATA_PTX_DRX_P2 <27>
NB ODD
Y11
Y10
<28,33>
SATA3_COMP
RBIAS_SATA3
R195
49.9_0402_1%
1
2
1
R200
BBS_BIT0_R
R182
1 10K_0402_5%
SERIRQ
R174
1 10K_0402_5%
SATA_LED#
R175
1 10K_0402_5%
PCH_GPIO21
@ R205
1 10K_0402_5%
R207
1 10K_0402_5%
+1.05VS_VCC_SATA
+1.05VS_SATA3
+3VS
2
750_0402_1%
SPI_CS0#
SPI_CS1#
SATALED#
SPI_MOSI
SATA0GP / GPIO21
SPI_MISO
SATA1GP / GPIO19
P3
SATA_LED#
V14
PCH_GPIO21
P1
BBS_BIT0_R
SATA_LED# <34>
T72
PAD
XDP Connector
COUGARPOINT_FCBGA989~D
1
R199
200_0402_5%
PCH_JTAG_TMS
<20,33> PCH_RSMRST#
<20,33> PBTN_OUT#
PCH_JTAG_TDI
+1.05VS_VCCP
@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
R399
0_0402_5%
2
1
1
2
@ R264 0_0402_5%
XDP_RSMRST#
XDP_HOOK1
1
2
@ R398 0_0402_5%
+3VS
R203
100_0402_1%
XDP_DBRESET#
<5,20> XDP_DBRESET#
PCH_JTAG_TDO
R202
100_0402_1%
2
R201
100_0402_1%
H7
PCH_JTAG_TDI
LPC_FRAME#
<28,33>
<28,33>
<28,33>
<28,33>
E36
K36
SERIRQ
HDA_DOCK_RST# / GPIO13
JTAG_TCK
D36
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
R198
200_0402_5%
PCH_JTAG_TDO
R197
200_0402_5%
PCH_JTAG_TMS
10P_0402_50V8J
<28> PCH_SPI_CLK
J3
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
+3VALW_PCH
+3VALW_PCH
+3VALW_PCH
C929
2
R184
33_0402_5%
1
2 HDA_BIT_CLK
R186
33_0402_5%
HDA_SYNC_R
1
2
R190
33_0402_5%
1
2 HDA_RST#
R191
33_0402_5%
1
2 HDA_SDOUT
<31> HDA_BITCLK_AUDIO
For EMI
On Die PLL VR Select is supplied by

1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Huron River platfrom
PCH_JTAG_TCK
C38
A38
B37
C37
V5
SERIRQ
G34
N32
LDRQ0#
LDRQ1# / GPIO23
INTVRMEN
1M_0402_5%
1 1K_0402_5% HDA_SYNC
INTRUDER#
HDA_SPKR
+3VALW_PCH
R181
FWH4 / LFRAME#
SRTCRST#
N34
HDA_SDO
ME debug mode,this signal has a weak internal PD
Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]
RTCRST#
HDA_SYNC
R172
1
RTCX2
HDA_BIT_CLK
HDA_SDIN0
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
G22
+3VS
<33>
Q10
BSS138_NL_SOT23-3
1
(INTVRMEN should always be pull high.)
D20
PCH_SRTCRST#
RTCX1
SATA 6G
H Integrated VRM enable

L Integrated VRM disable
C20
PCH_RTCRST#
SATA
+3VS
PCH_RTCX2
RTC
C227
1U_0603_10V6K
INTVRMEN
A20
IHDA
PCH_INTVRMEN
2 330K_0402_5%
U4A
PCH_RTCX1
SPI
SM_INTRUDER#
C226
1U_0603_10V6K
1
2
R177 20K_0402_5%
1
2
R180 20K_0402_5%
JME1
SHORT PADS
R171 1
JTAG
+RTCVCC
2 1M_0402_5%
CMOS
R170 1
C225
18P_0402_50V8J
2
JCMOS1
SHORT PADS
+RTCVCC
4
OSC
OSC
NC
NC
2
C224
2
32.768KHZ_12.5PF_Q13MC14610002
18P_0402_50V8J
Y2
PCH_RTCX2
2
10M_0402_5%
1
R151
PCH_RTCX1
PCH_JTAG_TDI
PCH_JTAG_TMS
PCH_JTAG_TCK
W=20mils
trace width 10mil
+RTCBATT
W=20mils
+CHGRTC +RTCVCC
27
28
ACES_87152-26051
D1
R209
1K_0402_5%
2
1
JXDP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 G1
26 G2
2
1
3
BAS40-04_SOT23-3
C230
1U_0603_10V6K
Place CH7 close to PCH.
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title
4

PCH (1/8) SATA,HDA,SPI, LPC, XDP

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
18
of
45
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2
BE34
BF34
BB32
AY32
BG36
BJ36
AV34
AU34
NewCard
<29>
<29>
<29>
<29>
PCIE_PRX_NEWTX_N5
PCIE_PRX_NEWTX_P5
PCIE_PTX_C_NEWRX_N5
PCIE_PTX_C_NEWRX_P5
NEW@
C499 2
1 0.1U_0402_16V7K
C500 2
1 0.1U_0402_16V7K
PCIE_PRX_NEWTX_N5
PCIE_PRX_NEWTX_P5
PCIE_PTX_NEWRX_N5
PCIE_PTX_NEWRX_P5
NEW@
PERN4
PERP4
PETN4
PETP4
BG37
BH37
AY36
BB36
PERN5
PERP5
PETN5
PETP5
BJ38
BG38
AU36
AV36
PERN6
PERP6
PETN6
PETP6
BG40
BJ40
AY40
BB40
PERN7
PERP7
PETN7
PETP7
BE38
BC38
AW38
AY38
PERN8
PERP8
PETN8
PETP8
PCH_GPIO73
R152 1
R1212 1
<29> CLK_WLAN#
<29> CLK_WLAN
WLAN
2 0_0402_5%
2 0_0402_5%
CLK_R_WLAN#
CLK_R_WLAN
CLKREQ_WLAN#
<29> CLKREQ_WLAN#
J2
AB49
AB47
M1
R218
R220
1 10K_0402_5%
1 10K_0402_5%
CLKREQ_WLAN#
PCH_GPIO20
PCH_GPIO20
R1213 1
R1214 1
<30> CLK_LAN#
<30> CLK_LAN
LAN
2 0_0402_5%
2 0_0402_5%
Y37
Y36
CLK_NEW#
CLK_NEW
Y43
Y45
CLKREQ_NEW#
L12
A8
<30> CLKREQ_LAN#
<29> CLK_NEW#
<29> CLK_NEW
NewCard
V10
CLK_R_LAN#
CLK_R_LAN
<29> CLKREQ_NEW#
H14
PCH_SMBCLK
SML0ALERT# / GPIO60
SML0CLK
SML0DATA
SML1ALERT# / PCHHOT# / GPIO74

SML1CLK / GPIO58
SML1DATA / GPIO75
CL_CLK1
CLKOUT_PCIE1N
CLKOUT_PCIE1P
LID_SW_OUT# <33>
PCH_SMBCLK <12>
PCH_SMBDATA
C9
PCH_SMBDATA <12>
DRAMRST_CNTRL_PCH
A12
DRAMRST_CNTRL_PCH <7>
E14
PCH_SML1CLK
M16
PCH_SML1DATA
PEG_A_CLKRQ# / GPIO47
M10
10K_0402_5%
DRAMRST_CNTRL_PCH
R211
1K_0402_5%
PCH_SMBCLK
R212
2.2K_0402_5%
PCH_SMBDATA
R213
2.2K_0402_5%
PCH_GPIO74
R214
10K_0402_5%
PCH_SML1CLK
R215
2.2K_0402_5%
PCH_SML1DATA
R216
2.2K_0402_5%
PCH_GPIO47
R217
10K_0402_5%
PCH_SML0CLK
R242
2.2K_0402_5%
PCH_SML0DATA
R244
2.2K_0402_5%
PCH_SML1CLK
M7
P10
PCH_GPIO74
C13
CL_RST1#
PCH_SML0DATA
G12
CL_DATA1
R210
PCH_SML0CLK
C8
T11
CLKOUT_PCIE0N
CLKOUT_PCIE0P
PCIECLKRQ0# / GPIO73
+3VALW_PCH
LID_SW_OUT#
Q11A
2N7002DW-T/R7_SOT363-6
EC_SMB_CK2
1
EC_SMB_CK2 <33>
PCH_SML1DATA 3
Q11B
2N7002DW-T/R7_SOT363-6
EC_SMB_DA2
4
EC_SMB_DA2 <33>
+3VS
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
+3VS
AA48
AA47
SMBCLK
SMBDATA
PERN3
PERP3
PETN3
PETP3
BF36
BE36
AY34
BB34
Y40
Y39
C
PERN2
PERP2
PETN2
PETP2
LID_SW_OUT#
C231 1
C229 1
SMBALERT# / GPIO11
E12
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_C_WLANRX_N2
PCIE_PTX_C_WLANRX_P2
PCIE_PTX_LANRX_N1
PCIE_PTX_LANRX_P1
SMBUS
<29>
<29>
<29>
<29>
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
PERN1
PERP1
PETN1
PETP1
Controller
WLAN
C223 1
C228 1
BG34
BJ34
AV32
AU32
CLOCKS
LAN
PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_C_LANRX_N1
PCIE_PTX_C_LANRX_P1
Link
U4B
<30>
<30>
<30>
<30>
PCI-E*
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKIN_DMI_N
CLKIN_DMI_P
CLKOUT_PCIE3N
CLKOUT_PCIE3P
CLKIN_DMI2_N
CLKIN_DMI2_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
PCH_GPIO47
AB37
AB38
CLK_CPU_DMI#
CLK_CPU_DMI
AV22
AU22
CLK_CPU_DMI# <5>
CLK_CPU_DMI <5>
T73
T74
AM12
AM13
BF18
BE18
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
BJ30
BG30
CLKIN_DMI2#
CLKIN_DMI2
G24
E24
CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M
AK7
AK5
CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA
K45
CLK_BUF_ICH_14M
H45
CLK_PCI_LPBACK
PAD
PAD
CLK_BUF_CPU_DMI# <14>
CLK_BUF_CPU_DMI <14>
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
R238
R239
1
1
2
2
10K_0402_5%
10K_0402_5%
CLKIN_DMI2#
CLKIN_DMI2
R241
R243
1
1
2
2
10K_0402_5%
10K_0402_5%
CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M
R245
R246
1
1
2
2
10K_0402_5%
10K_0402_5%
CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA
R248
R250
1
1
2
2
10K_0402_5%
10K_0402_5%
CLK_BUF_ICH_14M
R252
10K_0402_5%
CLK_BUF_DREF_96M# <14>
CLK_BUF_DREF_96M <14>
CLK_BUF_PCIE_SATA# <14>
CLK_BUF_PCIE_SATA <14>
XTAL25_IN
R224
B
1 10K_0402_5%
PCH_GPIO73
R226
1 10K_0402_5%
CLKREQ_LAN#
R228
1 10K_0402_5%
CLKREQ_NEW#
R229
1 10K_0402_5%
PCH_GPIO44
R230
1 10K_0402_5%
PCH_GPIO45
R231
1 10K_0402_5%
PCH_GPIO46
R235
1 10K_0402_5%
PCH_GPIO56
PCH_GPIO44
L14
AB42
AB40
PCH_GPIO56
E6
V40
V42
PCH_GPIO45
T13
V38
V37
PCH_GPIO46
<10> CLK_RES_ITP#
<10> CLK_RES_ITP
R258
R260
2
2
@
@
1 0_0402_5%
1 0_0402_5%
CLK_BCLK_ITP#
CLK_BCLK_ITP
K12
AK14
AK13
CLKOUT_PCIE5N
CLKOUT_PCIE5P
REFCLK14IN
CLKIN_PCILOOPBACK
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
XTAL25_IN
XTAL25_OUT
CLK_BUF_ICH_14M <14>
XCLK_RCOMP
XTAL25_OUT
1
R255
CLK_PCI_LPBACK <22>
2
1M_0402_5%
Y3
V47
V49
XTAL25_IN
XTAL25_OUT
Y47
XCLK_RCOMP
K43
CLK_FLEX0
T70
PAD
F47
CLK_FLEX1
T69
PAD
H47
CLK_FLEX2 R299
K49
CLK_FLEX3
T71
PAD
R256
90.9_0402_1%
1
2
PEG_B_CLKRQ# / GPIO56
+1.05VS_VCCDIFFCLKN
C239
18P_0402_50V8J
25MHZ_20PF_7A25000012 1
C240
18P_0402_50V8J
CLKOUT_PCIE6N
CLKOUT_PCIE6P
CLKOUT_PCIE7N
CLKOUT_PCIE7P
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
FLEX CLOCKS
V45
V46
+3VALW_PCH
CLKOUTFLEX0 / GPIO64
2 0_0402_5%
CLK_48M_CR <32>
For EMI
CLK_BUF_ICH_14M
CLK_PCI_LPBACK
@ R265
33_0402_5%
2
1
@ C241
22P_0402_50V8J
1
2
@ R269
33_0402_5%
2
1
@ C242
22P_0402_50V8J
1
2
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
5
Title
PCH (2/8) PCIE, SMBUS, CLK

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
19
of
45
U4C
<6>
<6>
<6>
<6>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
<6>
<6>
<6>
<6>
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
<6>
<6>
<6>
<6>
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
BC24
BE20
BG18
BG20
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
BE24
BC20
BJ18
BJ20
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
AW24
AW20
BB18
AV18
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
AY24
AY20
AY18
AU18
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
+1.05VS_PCH
DMI_IRCOMP
2
49.9_0402_1%
RBIAS_CPY
2
750_0402_1%
1
R274
1
R275
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
2 PCH_DBRESET#_R
0_0402_5%
<5,18> XDP_DBRESET#
R280
IN1
IN2
VCC
5
2
<14,33,44> VGATE
GND
<33> PM_PWROK
PM_PWROK
U6
OUT
<33> PCH_APWROK
R276
1 10K_0402_5%
SYS_PWROK
R288
1
R290
<33> SUSWARN#
1
R291
<18,33> PBTN_OUT#
<33,37>
SUSACK#_R
R283
0_0402_5%
2
1
@
ACIN
D2
SUSWARN#_R
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
AV14
FDI_LSYNC0
FDI_LSYNC1
BB10
FDI_LSYNC1
DSWVRMEN
A18
BH21
C12
K3
P12
L22
APWROK
0_0402_5%
L10
PCH_RSMRST#_R
2
0_0402_5%
C21
SUSWARN#_R
0_0402_5%
K16
PBTN_OUT#_R
2
0_0402_5%
E20
AW16
BC10
PM_DRAM_PWRGD B13
1
FDI_INT
AV12
DMI2RBIAS
SUSACK#
SYS_RESET#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
MC74VHC1G08DFT2G_SC70-5
<18,33> PCH_RSMRST#
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_FSYNC1
PM_PWROK_R
0_0402_5%
<5> PM_DRAM_PWRGD
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
FDI_FSYNC0
R286
SYS_PWROK <5>
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
DMI_IRCOMP
1
R285
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
DMI_ZCOMP
SYS_PWROK
+3VS
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BJ24
System Power Management
2 SUSACK#_R
0_0402_5%
1
R278
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
BG25
4mil width and place

within 500mil of the PCH
<33> SUSACK#
FDI
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI
<6>
<6>
<6>
<6>
PCH_ACIN
2
CH751H-40PT_SOD323-2
H20
PCH_GPIO72
E10
RI#
A10
RSMRST#
DPWROK
WAKE#
CLKRUN# / GPIO32
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SLP_A#
ACPRESENT / GPIO31
BATLOW# / GPIO72
SLP_SUS#
PMSYNCH
RI#
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
DSWODVREN
<6>
FDI_FSYNC1
<6>
FDI_LSYNC0
<6>
FDI_LSYNC1
<6>
N3
PM_CLKRUN#
G8
SUS_STAT#
N14
SUSCLK
220P_0402_50V8K
C23
+RTCVCC
R272
R273
1 330K_0402_5%
@
1 330K_0402_5%
DSWODVREN - On Die DSW VR Enable

H Enable
L Disable
@ R277
0_0402_5%
2 PCH_RSMRST#_R
+3VALW_PCH
EC_DPWROK <33>
R281
0_0402_5%
1
2
WAKE#
H_PM_SYNC
DSWODVREN
FDI_FSYNC0
EC_DPWROK
B9
For ESD
PCH_PCIE_WAKE# <29,30>
WAKE#
R279
PCH_GPIO29
R282
2 10K_0402_5%
R305
2 8.2K_0402_5%
PM_CLKRUN# R284
2 10K_0402_5%
PM_CLKRUN# <28>
+3VS
SUS_STAT# / GPIO61
SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3#

PWRBTN#
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
FDI_INT <6>
1
E22
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
SLP_LAN# / GPIO29
SUS_STAT# <28>
1 10K_0402_5%
SUSCLK <33>
D10
PM_SLP_S5#
H4
PM_SLP_S4#
F4
PM_SLP_S3#
T13
PAD
T14
PAD
T15
PAD
PM_SLP_S5# <33>
PM_SLP_S4# <33>
PM_SLP_S3# <33>
Can be left NC
when IAMT is not
support on the
platfrom
G10
G16
PM_SLP_SUS#
AP14
H_PM_SYNC
K14
PCH_GPIO29
T16
PAD
T17
PAD
PM_SLP_SUS# <33>
H_PM_SYNC <5>
+3VALW_PCH
R289
1 200_0402_5%
PM_DRAM_PWRGD
R292
1 10K_0402_5%
SUSWARN#
R293
1 330K_0402_5%
PCH_ACIN
R294
1 10K_0402_5%
PCH_GPIO72
R295
1 10K_0402_5%
RI#
R296
1 10K_0402_5%
PCH_RSMRST#
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
5
Title

PCH (3/8) DMI,FDI,PM,

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
20
of
45
ENBKL
ENBKL
R297
IGPU_BKLT_EN
1 0_0402_5%
2
<33>
R298
100K_0402_5%
Pull high at LVDS conn side.

U4D
CTRL_CLK
L_BKLTEN
L_VDD_EN
2 2.2K_0402_5%
CTRL_DATA
<15> VGA_BL_PWM
P45
L_BKLTCTL
<15> LCD_EDID_CLK
<15> LCD_EDID_DATA
T40
K47
L_DDC_CLK
L_DDC_DATA
T45
P39
L_CTRL_CLK
L_CTRL_DATA
CTRL_CLK
CTRL_DATA
2.37K_0402_1%
2
1
RH244
RH290
<15> LCD_TXCLK<15> LCD_TXCLK+
+3VS
RH291
2 2.2K_0402_5%
VGA_CRT_CLK
RH292
2 2.2K_0402_5%
VGA_CRT_DATA
RH131
0_0402_5%
2
1
2 150_0402_1%
<15> LCD_TXOUT0<15> LCD_TXOUT1<15> LCD_TXOUT2-
RH132
2 150_0402_1%
VGA_CRT_G
RH133
2 150_0402_1%
VGA_CRT_R
<15> LCD_TZCLK<15> LCD_TZCLK+

<15> LCD_TZOUT0<15> LCD_TZOUT1<15> LCD_TZOUT2<15> LCD_TZOUT0+
<15> LCD_TZOUT1+
<15> LCD_TZOUT2+
+3VS
R301
2 2.2K_0402_5%
LCD_EDID_CLK
R304
2 2.2K_0402_5%
LCD_EDID_DATA
AF37
AF36
LVD_IBG
LVD_VBG
LVD_VREF
AE48
AE47
LVD_VREFH
LVD_VREFL
LCD_TXCLKLCD_TXCLK+
AK39
AK40
LVDSA_CLK#
LVDSA_CLK
LCD_TXOUT0LCD_TXOUT1LCD_TXOUT2-
AN48
AM47
AK47
AJ48
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
AN47
AM49
AK49
AJ47
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LCD_TXOUT0+
LCD_TXOUT1+
LCD_TXOUT2+
<15> LCD_TXOUT0+
<15> LCD_TXOUT1+
<15> LCD_TXOUT2+
VGA_CRT_B
LVDS_IBG
<16> VGA_CRT_B
<16> VGA_CRT_G
<16> VGA_CRT_R
<16> VGA_CRT_CLK
<16> VGA_CRT_DATA
LCD_TZCLKLCD_TZCLK+
AF40
AF39
LCD_TZOUT0LCD_TZOUT1LCD_TZOUT2-
AH45
AH47
AF49
AF45
LCD_TZOUT0+
LCD_TZOUT1+
LCD_TZOUT2+
AH43
AH49
AF47
AF43
VGA_CRT_B
VGA_CRT_G
VGA_CRT_R
N48
P49
T49
VGA_CRT_CLK
VGA_CRT_DATA
T39
M40
SDVO_TVCLKINN
SDVO_TVCLKINP
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
AM42
AM40
SDVO_INTN
SDVO_INTP
AP39
AP40
AT49
AT47
AT40
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
VGA_CRT_HSYNC
VGA_CRT_VSYNC
2
R1250
1 CRT_IREF
1K_0402_1%
M47
M49
T43
T42
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
SDVO_CTRLDATA strap pull high

at level shift page
P38
M39
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
<16> VGA_CRT_HSYNC
<16> VGA_CRT_VSYNC
AP43
AP45
SDVO_STALLN
SDVO_STALLP
SDVO_CTRLCLK
SDVO_CTRLDATA
Digital Display Interface
R302
2 2.2K_0402_5%
LVDS
R300
J47
M45
<15> VGA_ENVDD
CRT
IGPU_BKLT_EN
+3VS
VGA_HDMI_CLK <17>
VGA_HDMI_DATA <17>
VGA_HDMI_HPD <17>
<17>
<17>
<17>
<17>
<17>
<17>
<17>
<17>
HDMI D2
HDMI D1
HDMI D0
HDMI CLK
P46
P42
AP47
AP49
AT38
R1475
100K_0402_5%
2
1
@
R1476
100K_0402_5%
2
1
@
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
5
Title

PCH (4/9) LVDS,CRT,DP,HDMI

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
21
of
45
RP3
PCH_WL_OFF#
PCH_GPIO51
PCH_GPIO5
PCH_GPIO53
1
2
3
4
8.2K_0804_8P4R_5%
RP2
8
7
6
5
PCH_GPIO2
PCH_GPIO54
PCH_GPIO4
ODD_DA#
1
2
3
4
B21
M20
AY16
BG46
TP21
TP22
TP23
TP24
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40
8.2K_0804_8P4R_5%
R310
R311
2 8.2K_0402_5%
2 8.2K_0402_5%
PCH_GPIO52
<29> PCH_WL_OFF#
<27>
R112 100K_0402_5%
1
2
<5,28,29,30,33> PLT_RST#
<19> CLK_PCI_LPBACK
<33> CLK_PCI_LPC
<28> CLK_PCI_TPM
ODD_DA#
PAD
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
K40
K38
H38
G38
PCH_GPIO50
PCH_GPIO52
PCH_GPIO54
C46
C44
E40
PCH_GPIO51
PCH_GPIO53
PCH_WL_OFF#
D47
E42
F46
PCH_GPIO2
ODD_DA#
PCH_GPIO4
PCH_GPIO5
G42
G40
C42
D44
T18 @
K10
PLT_RST#
CLK_PCI_LPBACK
CLK_PCI_LPC
CLK_PCI_TPM
C6
R316
R317
R318
2
1
1
PAD
PAD
1 22_0402_5%
2 22_0402_5%
2 22_0402_5%
T20 @
T21 @
CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4
H49
H43
J48
K42
H40
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
AY7
AV7
AU3
BG4
NV_DQS0
NV_DQS1
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
NV_ALE
NV_CLE
AV5
AY1
NV_RCOMP
PCH_GPIO50
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
NV_RB#
AT8
AY5
BA2
NV_WE#_CK0
NV_WE#_CK1
NV_CLE
AV10
NV_RE#_WRB0
NV_RE#_WRB1
DMI Termination Voltage

Set to Vcc when HIGH
NV_CLE
Set to Vss when LOW
AT12
BF3
+1.8VS
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USB
8
7
6
5
PCI
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
USBRBIAS#
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
<29>
<29>
<29>
<29>
<29>
<29>
R-CONN
8.2K_0804_8P4R_5%
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
L-CONN
NV_CLE
2
R314
1
1K_0402_5%
H_SNB_IVB# <5>
CLOSE TO THE BRANCHING POINT
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N8 <29>
USB20_P8 <29>
USB20_N9 <27,29>
USB20_P9 <27,29>
USB20_N10 <15>
USB20_P10 <15>
USB20_N11 <32>
USB20_P11 <32>
USB20_N13
USB20_P13
USBRBIAS
USB20_N13 <29>
USB20_P13 <29>
NewCard
+3VALW_PCH
Smart Card
RP4
Camera
USB_OC1#
PCH_GPIO9
EXP_CPPE#
USB_OC0#
Card Reader
4
3
2
1
5
6
7
8
10K_1206_8P4R_5%
BT
Within 500 mils

1
R315
2
22.6_0402_1%
PCH_GPIO10
USBRBIAS
R23
10K_0402_5%
B33
PME#
PLTRST#
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
USB_OC0#
USB_OC1#
PCH_GPIO41
PCH_GPIO42
PCH_GPIO43
PCH_GPIO9
PCH_GPIO10
EXP_CPPE#
A14
K20
B17
C16
L16
A16
D14
C14
USB_OC0# <29>
USB_OC1# <29>
EXP_CPPE# <29>
+3VALW_PCH
BBS bit1
/BBS bit0
PCI
SPI
LPC
PBL11
Reserved
PBL20
PBL21
R20
10K_0402_5%
R21
10K_0402_5%
R22
10K_0402_5%
@
A
*
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
5
PBL10
PCH_GPIO41
PCH_GPIO42
PCH_GPIO43
R19
10K_0402_5%
R14
10K_0402_5%
@
PBL01
R13
10K_0402_5%
@
Boot BIOS
Destination
Bit10
GPIO41
Boot BIOS Strap bit1 BBS1
GPIO42
GPIO43
PBL00
Bit11
R313
2.2K_0402_5%
R-CONN
2
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#
1
2
3
4
RSVD
RP1
8
7
6
5
NVRAM
U4E
+3VS
Title

PCH (5/9) PCI, USB, NVRAM

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
22
of
45
R327
+3VALW_PCH
R352
2 10K_0402_5%
@
2 1K_0402_5%
EC_SMI#
H_CPUPWRGD
220P_0402_50V8K
C19
GPIO28
On-Die PLL Voltage Regulator

This signal has a weak internal pull up
H
L
For ESD
voltage regulator enable

On-Die
On-Die PLL Voltage Regulator disable
+3VS
+3VALW_PCH
KB_RST#
2 1K_0402_5%
PCH_GPIO28
U4F
<33>
EC_SCI#
<33>
EC_SMI#
PCH_GPIO0
T7
PCH_GPIO1
2 10K_0402_5%
PCH_GPIO27
R426
R332
1
1
TACH1 / GPIO1
TACH5 / GPIO69
B41
PCH_GPIO69
@ T24
PAD
PCH_GPIO6
H36
TACH2 / GPIO6
TACH6 / GPIO70
C41
PCH_GPIO70
@ T25
PAD
+3VS
EC_SCI#
E38
TACH3 / GPIO7
TACH7 / GPIO71
A40
PCH_GPIO71
@ T22
PAD
EC_SMI#
C10
GPIO8
2 10K_0402_5%
<29> PCH_BT_PWRON
PCH_GPIO37
2 10K_0402_5%
<27> ODD_DETECT#
C4
LAN_PHY_PWR_CTRL / GPIO12
PCH_GPIO15
G2
GPIO15
U2
PCH_GPIO17
D40
PCH_GPIO22
T5
PCH_GPIO24
E8
PCH_GPIO27
E16
PCH_GPIO28
P8
PCH_BT_PWRON
K1
PCH_GPIO35
K4
ODD_DETECT#
V8
PCH_GPIO37
M5
+3VS
N2
PCH_GPIO39
M3
PCH_GPIO48
V13
PCH_GPIO49
V3
PCH_GPIO57
D6
R425
2 10K_0402_5%
PCH_GPIO24
R424
2 10K_0402_5%
PCH_GPIO0
PAD
T30 @
A4
R335
2 10K_0402_5%
PCH_GPIO1
PAD
T32 @
A44
R336
2 10K_0402_5%
PCH_GPIO6
PAD
T34 @
A45
R337
2 10K_0402_5%
PCH_GPIO16
PAD
T36 @
A46
R338
2 10K_0402_5%
PCH_GPIO17
PAD
T38 @
A5
R339
2 10K_0402_5%
PCH_GPIO22
PAD
T40 @
A6
R340
2 10K_0402_5%
PCH_GPIO38
PAD
T42 @
B3
R341
2 10K_0402_5%
PCH_GPIO39
PAD
T44 @
B47
R342
2 10K_0402_5%
ODD_DETECT#
PAD
T46 @
BD1
R343
2 10K_0402_5%
PCH_BT_PWRON
PAD
T48 @
BD49
R344
2 10K_0402_5%
PCH_GPIO48
PAD
T50 @
BE1
R345
2 10K_0402_5%
PCH_GPIO49
PAD
T52 @
BE49
PAD
T54 @
BF1
PAD
T56 @
BF49
R346
2 10K_0402_5%
PCH_GPIO12
R347
2 1K_0402_5%
PCH_GPIO15
R349
2 10K_0402_5%
PCH_GPIO57
A20GATE
SATA4GP / GPIO16
TACH0 / GPIO17
SCLOCK / GPIO22
PECI
RCIN#
PROCPWRGD
THRMTRIP#
GPIO24 / MEM_LED
INIT3_3V#
GPIO28
NC_1
STP_PCI# / GPIO34
NC_2
GPIO35
NC_3
SATA2GP / GPIO36
NC_4
SATA3GP / GPIO37
NC_5
KB_RST#
1
0_0402_5%
2
R331
<5,33>
KB_RST# <33>
AY11
AY10
H_PECI
H_CPUPWRGD <5>
PCH_THRMTRIP#_R 1
R334
H_THRMTRIP#
2
390_0402_5%
H_THRMTRIP# <5>
T14
INIT3_3V
This signal has weak internal

PU, can't pull low
AH8
AK11
AH10
AK10
Intel schematic review recommand.

P37
SDATAOUT0 / GPIO39
SDATAOUT1 / GPIO48
VSS_NCTF_15
SATA5GP / GPIO49
VSS_NCTF_16
GPIO57
VSS_NCTF_17
VSS_NCTF_1
VSS_NCTF_19
VSS_NCTF_2
VSS_NCTF_20
VSS_NCTF_3
VSS_NCTF_21
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_6
VSS_NCTF_24
VSS_NCTF_7
VSS_NCTF_25
VSS_NCTF_8
VSS_NCTF_26
VSS_NCTF_9
VSS_NCTF_27
VSS_NCTF_10
VSS_NCTF_28
VSS_NCTF_11
VSS_NCTF_29
VSS_NCTF_12
VSS_NCTF_30
VSS_NCTF_13
VSS_NCTF_31
VSS_NCTF_14
VSS_NCTF_32
Issued Date
2 10K_0402_5%
AU16
P5
SLOAD / GPIO38
BG2
@ T26
PAD
BG48
@ T27
PAD
BH3
@ T28
PAD
BH47
@ T29
PAD
BJ4
@ T31
PAD
BJ44
@ T33
PAD
BJ45
@ T35
PAD
BJ46
@ T37
PAD
BJ5
@ T39
PAD
BJ6
@ T41
PAD
C2
@ T43
PAD
C48
@ T45
PAD
D1
@ T47
PAD
D49
@ T49
PAD
E1
@ T51
PAD
@ T55
PAD
E49
F1
F49
Compal Secret Data
1
GATEA20 <33>
PCH_PECI_R
@
R350
P4
GPIO27
VSS_NCTF_18
+3VALW_PCH
ODD_EN# <27>
R329
10K_0402_5%
PCH_GPIO12
PCH_GPIO38
2 10K_0402_5%
+3VS
A42
PCH_GPIO37
R428
C40
PCH_GPIO16
+3VS
ODD_EN#
TACH4 / GPIO68
10K_0402_5% 2
BMBUSY# / GPIO0
PCH_GPIO27 (Have internal Pull-High)

VCCVRM VR Enable
*High:
Low: VCCVRM VR Disable
R328
CPU/MISC
R325
R326
2 10K_0402_5%
GPIO
NCTF
R351
PCH_GPIO35
2010/05/17
2011/05/17
Deciphered Date
4
Title

PCH (6/9) GPIO, CPU, MISC

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
23
of
45
L5
+1.05VS_VCCP
@ JP2
+3VS
1300mA
+1.05VS_PCH
+1.05VS_VCCDPLLEXP AN19
1 0_0603_5%
CRT
VCCADAC
VSSADAC
U47
2
1mA VCCALVDS
VSSALVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
AK36
+VCCA_LVDS
60mA VCCTX_LVDS[3]
AP36
VCCTX_LVDS[4]
AP37
R356
0_0805_5%
1
2
+1.05VS_VCC_EXP
VCCIO[18]
AN27
VCCIO[19]
AP21
VCCIO[20]
AP23
VCCIO[21]
AP24
VCCIO[22]
AP26
VCCIO[23]
AT24
AN34
R359
0_0805_5%
1
2
+3VS_VCCA3GBG
BH29
VCCIO[24]
+VCCAFDI_VRM
AP16
1
@ C264
@C264
1U_0402_6.3V6K
BG6
+1.05VS_PCH R363
1
2 +1.05VS_VCCDPLL_FDI AP17
0_0805_5%
+VCCP_VCCDMI
AU20
C251
0.01U_0402_16V7K
1
C252
0.01U_0402_16V7K
+3VS
R355
0_0805_5%
+3VS_VCC3_3_6 1
2
V33
1
VCC3_3[7]
V34
2
VCCVRM[3]
AT16
VCCDMI[1]
20mA
VCCIO[1]
AT20
AB36
190mA VCCPNAND[2]
VCC3_3[3]
VCCVRM[2]
VCCFDIPLL
VCCIO[27]
VCCDMI[2]
0.001
0.001
Vcc3_3
3.3
0.266
VccADAC
3.3
0.001
VccADPLLA
1.05
0.08
VccADPLLB
1.05
0.08
VccCore
1.05
1.3
VccDMI
1.05
0.042
VccIO
1.05
2.925
VccASW
1.05
1.01
VccSPI
3.3
0.02
VccDSW
3.3
0.003
VccpNAND
1.8
0.19
VccRTC
3.3
6 uA
VccSus3_3
3.3
0.119
+VCCAFDI_VRM
+1.05VS_VCCP
R357
0_0805_5%
1
2
+VCCP_VCCDMI
R358
0_0805_5%
1
2
+1.05VS_VCC_DMI_CCI
+1.05VS_PCH
2
VCCPNAND[1]
V5REF_Sus
C254
0.1U_0402_10V7K
C255
1U_0402_6.3V6K
C261
1U_0402_6.3V6K
VCCIO[25]
VCCIO[26]
V5REF
0.1uH inductor, 200mA
+VCCP_VCCDMI
Place C264 Near BG6 pin

+1.05VS_VCCAPLL_FDI
VCC3_3[6]
2925mA
C262
0.1U_0402_10V7K
2
@ R361
0_0603_5%
2
1
VCCIO[17]
AN26
AN33
+1.05VS_PCH
C260
1U_0402_6.3V6K
C259
1U_0402_6.3V6K
C258
1U_0402_6.3V6K
+3VS
C257
1U_0402_6.3V6K
C256
10U_0603_6.3V6M
VCCIO[16]
AN21
FDI
+1.05VS_PCH
HVCMOS
AN17
VCCIO[15]
DMI
AN16
0.001
+1.8VS
L6
0.1UH_MLF1608DR10KT_10%_1608
2
1
+VCCTX_LVDS
1
AG16
+VCCPNAND
AG17
R360
0_0805_5%
1
2
VccSusHDA
3.3 / 1.5
0.01
VccVRM
1.8 / 1.5
0.16
VCCPNAND[4]
20mA VCCSPI
AJ16
AJ17
V1
+1.8VS
VccCLKDMI
VCCPNAND[3]
S0 Iccmax
Current (A)
+3VS
R423
0_0805_5%
1
2
AM38
VCCAPLLEXP
NAND / SPI
This pin can be left as no connect in

On-Die VR enabled mode (default).
BJ22
Voltage
1.05
V_PROC_IO
C250
10U_0603_6.3V6M
AM37
VCCIO[28]
VCCIO
+VCCAPLLEXP
T58 @
Voltage Rail
AK37
2
PAD
L5
MBK1608221YZF_2P
2
1
@
C253
22U_0805_6.3V6M
R353
1mA
C249
0.1U_0402_10V7K
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
+VCCADAC
1
U48
C248
0.01U_0402_16V7K
C247
1U_0402_6.3V6K
C244
1U_0402_6.3V6K
C246
1U_0402_6.3V6K
C245
10U_0603_6.3V6M
PAD-OPEN 4x4m 1
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
LVDS
+1.05VS_PCH
VCC CORE
PCH Power Rail Table
2.2_0603_5%
POWER
U4G
C263
0.1U_0402_10V7K
1.05
0.02
VccSSC
1.05
0.095
VccDIFFCLKN
1.05
0.055
R362
0_0805_5%
1
2
+3V_VCCPSPI
VccALVDS
3.3
0.001
VccTX_LVDS
1.8
0.06
+3VS
1
C265
1U_0402_6.3V6K
+VCCAFDI_VRM
+1.5VS
A
R364
0_0603_5%
0_0603_5%
+VCCAFDI_VRM
+1.8VS
R365
Intel recommand
stuff R364 and unstuff R365
VCCVRM==>1.5V FOR MOBILE

VCCVRM==>1.8V FOR DESKTOP
Issued Date
VCCVRM = 160mA detal waiting for newest spec
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
4
Title

PCH (7/9) PWR

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
24
of
45
2
+1.05VS_PCH
R379
0_0805_5%
1
2
C282
1U_0402_6.3V6K
C281
1U_0402_6.3V6K
C280
1U_0402_6.3V6K
2
L9
10UH_LB2012T100MR_20%
+VCCA_DPLL_L
1
2
C278
22U_0805_6.3V6M
+1.05VM_VCCASW
1
C277
22U_0805_6.3V6M
AL24
@
C275
1U_0402_6.3V6K
+1.05VS_VCCA_A_DPL
+1.05VS_VCCA_B_DPL
VCCASW[2]
AA24
VCCASW[3]
AA26
VCCASW[4]
AA27
VCCASW[5]
AA29
VCCASW[6]
AA31
VCCASW[7]
AC26
VCCASW[8]
AC27
VCCASW[9]
R386
0_0603_5%
2
1
AC29
VCCASW[10]
AC31
VCCASW[11]
W23
W24
W26
W29
W31
W33
+VCCRTCEXT
+1.05VS_VCCDIFFCLKN
C293
0.1U_0402_10V7K
VCCASW[14]
VCCASW[15]
Y49
VCCIO[34]
T26
1mA V5REF_SUS
M26
+PCH_V5REF_SUS
DCPSUS[4]
AN23
+VCCA_USBSUS
VCCSUS3_3[1]
AN24
+3V_VCCPSUS
1mA V5REF
P34
+PCH_V5REF_RUN
VCCSUS3_3[2]
N20
+3V_VCCPSUS
VCCSUS3_3[3]
N22
VCCSUS3_3[4]
P20
+5VALW_PCH
+1.05VS_VCCAUPLL
C295
1U_0402_6.3V6K
BD47
VCCSUS3_3[5]
VCC3_3[1]
VCC3_3[8]
VCC3_3[4]
C279
+3VS_VCCPCORE
2
1
R385
0_0603_5%
2
1
VCC3_3[2]
AJ2
+VCC3_3_2
VCCVRM[4]
VCCIO[13]
+1.05VS_VCCA_B_DPL
BF47
+VCCDIFFCLK
AF17
AF33
AF34
AG34
+1.05VS_SSCVCC
+1.05VS_VCCDIFFCLKN
VCCADPLLB
80mA
80mA
VCCIO[6]
VCCAPLLSATA
VCCVRM[1]
VCCIO[7]
VCCIO[8]
55mA
VCCIO[9]
VCCIO[11]
VCCIO[2]
VCCIO[3]
C297
1U_0402_6.3V6K
+1.05VS_SSCVCC
AG33
VCCIO[10]
VCCIO[4]
95mA
+1.05VS_SATA3
C292
1U_0402_6.3V6K
@
@
L11
R389
10UH_LB2012T100MR_20%
0_0805_5%
+VCCSATAPLL_R2
1
2
1
+VCCSATAPLL
+VCCAFDI_VRM
AC16
+VCCAFDI_VRM
+1.05VS_VCC_SATA R391 +1.05VS_PCH
0_0805_5%
+1.05VS_VCC_SATA
2
1
AC17
AD17
+1.05VS_PCH
@ C296
10U_0603_6.3V6M
Place C296 Near AK1 pin
C298
1U_0402_6.3V6K
@ R392
0_0603_5%
2
1
+1.05VM_VCCSUS
C300
1U_0402_6.3V6K
+VCCSST
V16
+1.05VM_VCCSUS
T17
V19
1
C299
0.1U_0402_10V7K
+1.05VS_VCCP R395
0_0603_5%
1
2
+V_CPU_IO
BJ8
+1.05VS_PCH
DCPSST
DCPSUS[1]
DCPSUS[2]
V_PROC_IO 1mA
VCCASW[22]
VCCASW[23]
VCCASW[21]
T21
+VCCME_22
R393
1 0_0603_5%
V21
+VCCME_23
R394
1 0_0603_5%
T19
+VCCME_21
R396
1 0_0603_5%
P32
+VCCSUSHDA
R397
1 0_0603_5%
+RTCVCC
+3VALW_PCH
A22
C306
0.1U_0402_10V7K
C305
0.1U_0402_10V7K
C304
1U_0402_6.3V6K
C303
0.1U_0402_10V7K
C302
0.1U_0402_10V7K
C301
4.7U_0603_6.3V6K
VCCRTC
10mA VCCSUSHDA
C307
0.1U_0402_16V4Z
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
5
+1.05VS_PCH
R387
0_0805_5%
2
1
AF14
AF11
+3VS
AH13
AK1
C284
1U_0603_10V6K
C290
0.1U_0402_10V7K
+1.05VS_SATA3
C291
0.1U_0402_10V7K
AH14
+PCH_V5REF_RUN
1
AF13
2
DCPRTC
+3VS
+3VS
R384
0_0603_5%
1
D4
C285
0.1U_0402_10V7K
+3VS_VCCPPCI
VCCASW[18]
VCCASW[20]
R383
0_0805_5%
2
1
W16
+3VS
R381
100_0402_5%
C283
1U_0402_6.3V6K
T34
+3VALW_PCH
R380
0_0603_5%
2
1
P22
AA16
C276
0.1U_0603_25V7K
2 1U_0402_6.3V6K
VCCASW[17]
VCCASW[19]
+PCH_V5REF_SUS
+5VS
VCCASW[16]
VCCADPLLA
D3
SATA
+1.05VS_VCCA_A_DPL
+3VALW_PCH
R377
100_0402_5%
+1.05VS_PCH
R378
0_0603_5%
2
1
+3VALW_PCH
R376
0_0603_5%
+3V_VCCAUBG 2
1
1
C274
0.1U_0402_10V7K
V23
V24
VCCIO[12]
+VCCAFDI_VRM
<35> PCH_PWR_EN#
+3VALW_PCH
R374
0_0603_5%
2
1
R390
0_0603_5%
2
1
VCCASW[13]
T24
P24
+1.05VS_VCCDIFFCLKN
+1.05VS_PCH
N16
+1.05VS_PCH
VCCASW[12]
+3V_VCCPUSB
T23
VCCSUS3_3[6]
VCCIO[5]
C294
1U_0402_6.3V6K
T29
VCCSUS3_3[10]
MISC
R388
0_0603_5%
2
1
+VCCDIFFCLK
1
+1.05VS_PCH
VCCSUS3_3[9]
1010mA
HDA
+1.05VS_PCH
DCPSUS[3]
VCCASW[1]
W21
C289
1U_0402_6.3V6K
C287
220U_B2_2.5VM_R35
C288
1U_0402_6.3V6K
C286
220U_B2_2.5VM_R35
L10
10UH_LB2012T100MR_20%
VCCSUS3_3[8]
VCCIO[14]
AA21
AD31
1
VCCAPLLDMI2
AA19
AD29
C269
1U_0402_6.3V6K
T27
VCC3_3[5]
119mA VCCSUS3_3[7]
+5VALW_PCH
AL29
VCCIO[33]
P28
BH23
+VCCDPLL_CPY
VCCIO[32]
P26
Q14
AO3413_SOT23-3
+VCCAPLL_CPY_PCH
DCPSUSBYP
R372
0_0603_5%
2
1
T38
USB
+3VS_VCC_CLKF33
PCI/GPIO/LPC
3mA
VCCDSW3_3
+1.05VS_VCCUSBCORE
1
R373
20K_0402_5%
V12
N26
+PCH_VCCDSW
+VCCSUS1
VCCIO[30]
VCCIO[31]
2 0_0603_5%
VCCIO[29]
C273
0.1U_0402_10V7K
@ C272
10U_0603_6.3V6M
R375
T16
VCCACLK
AD49
C268
0.1U_0402_10V7K
@R368
@
R368
0_0603_5%
2
1
+1.05VS_PCH
C271
0.1U_0402_10V7K
C270
0.1U_0402_10V7K
2
1
@
+1.05VS_PCH
R369
0_0603_5%
2
1
+VCCPDSW
1
L8
10UH_LB2012T100MR_20%
+VCCAPLL_CPY 1
2
1
POWER
U4J
R370
0_0603_5%
1
2
C267
1U_0402_6.3V6K
C266
10U_0603_6.3V6M
+1.05VS_PCH
R382
0_0805_5%
1
2
VCCDMI = 42mA detal waiting for newest spec
Clock and Miscellaneous
+3VALW_PCH
+3VS_VCC_CLKF33
1
@ R371
0_0603_5%
1
2
VCC3_3 = 266mA detal waiting for newest spec
+VCCACLK
+5VALW
L7
10UH_LB2012T100MR_20%
1
2
+1.05VS_PCH
+1.05VS_PCH @ R367
0_0603_5%
2
1
@ R366
0_0805_5%
2
CPU
RTC
+3VS
Have internal VRM
Title

PCH (8/9) PWR

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
25
of
45
U4I
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
U4H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
5
Title

PCH (9/9) VSS

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
26
of
45
SATA HDD1 Conn.

+5VS
1.2A
SATA ODD Conn
Place closely JP25 SATA CONN.
+5VS_ODD
1.7A
1
C387
10U_0805_10V4Z
C388
0.1U_0402_16V4Z
C389
0.1U_0402_16V4Z
C390
0.1U_0402_16V4Z
C952
C414
@
ODD@
10U_0805_10V4Z
10U_0805_10V4Z
2
2
C415
ODD@
10U_0805_10V4Z
C416
@
1U_0402_6.3V6K
C417
C418
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 ODD@
2 ODD@
Place component's closely ODD CONN.
13.3" HDD
13.3" ODD
JHDD
JODD
GND
A+
AGND
BB+
GND
24
23
GND
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
1
2
3
4
5
6
7
SATA_PTX_C_DRX_P0C512 1
SATA_PTX_C_DRX_N0C513 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
C410 1
C412 1
14
15
GND1
GND2
GND
A+
AGND
BB+
GND
1
2
3
4
5
6
7
DP
+5V
+5V
MD
GND
GND
8
9
10
11
12
13
SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2
SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
ODD@
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
ODD@
ODD_DETECT#_R
0_0402_5%
2 ODD@ 1
ODD_DA#_R
0_0402_5%
2 ODD@ 1
R833
0_0402_5%
0_0402_5%
2 SCO@ 1
2
1
SCO@
R836
R835
SANTA_206001-1
@
+5VS
ODD@
C518 1
C519 1
ODD@
C424 1
C425 1
R834
+5VS_ODD
ODD_DETECT# <23>
+5VS_ODD
ODD_DA# <22>
USB20_N9 <22,29>
USB20_P9 <22,29>
Smart Card
SUYIN_127085FR022G211ZR
@
+5VS_ODD
+5VS
R415
0_0805_5%
1
2
@
1.7A
S
Q62
SI3456BDV-T1-E3 1N TSOP6
Q63
SSM3K7002FU_SC70-3
ODD@
1
2
G
ODD@
C870 ODD@
0.1U_0402_16V4Z
ODD_EN#
R831 ODD@
1.5M_0402_5%
<23>
ODD_EN
D
6
5
2
1
G
CS27 ODD@
1U_0402_6.3V6K
R832
470K_0402_5%
ODD@
+VSB
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
5
Title
HDD & ODD Connector

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet

1
27
of
45
TPM 1.2
SPI ROM For Basic ME ROM size

(w/o Braidwood & system BIOS):
4MByte
C764 close pin 24
C765 close pin 10

+3VS
+5VALW
C398
2
1
8
10K_0402_5%
10K_0402_5%
Debug@
Debug@
<18,33>
<18,33>
<18,33>
<18,33>
PCH_SPI_CLK_R
@
1
2
R1455 0_0402_5%
@
C928
10P_0402_50V8J
<22>
<18,33>
<5,22,29,30,33>
<18,33>
<20>
+3VS
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
26
23
20
17
CLK_PCI_TPM
CLK_PCI_TPM
LPC_FRAME#
LPC_FRAME#
PLT_RST#
PLT_RST#
SERIRQ
SERIRQ
PM_CLKRUN#
PM_CLKRUN#
1
2
R665
4.7K_0402_5%
IN_TPM@
21
22
16
27
15
7
LAD0
LAD1
LAD2
LAD3
XTALO
XTALI
14
13
TPM_XTALO
TPM_XTALI
LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
PP
GPIO2
GPIO
2
4.7K_0402_5%
SUS_STAT# <20>
NC
NC
NC
R659
1
TPM_TEST1
1
2
IN_TPM@
0_0402_5%
R661
2
6
+3VS
4.7K_0402_5%
IN_TPM@
R662
@
Base I/O Address

0 = 02Eh
* 1 = 04Eh
1
3
12
SLB-9635-TT-1.2_TSSOP28
IN_TPM@
2
R772
0_0402_5%
@
1
PCH_SPI_MISO
SUS_STAT#_R
+3VS
0_0402_5%
2
1 0_0402_5%
MP@
2 R1551 1 0_0402_5%
MP@
2 R1552 1 0_0402_5%
MP@
2 R1553 1 0_0402_5%
MP@
PCH_SPI_CS0#
1
R667
LPCPD#
TESTB1/BADD
TEST1
28
9
8
4
11
18
25
+VTPM
2 R1550
PCH_SPI_CLK
IN_TPM@
R733
10K_0402_5%
1
2
R726 1
@
TPM
SLB 9635 TT 1.1
For EMI close U59
PCH_SPI_MOSI
1
U37
VDD
VDD
VDD
+VTPM
+3V_SPI
R417
100K_0402_5%
Debug@
R61
1
+3VS
R46
2
+5VALW
Q19
AO3416_SOT23-3
Debug@
2
G
R1429
0_0603_5%
@
C396
0.1U_0402_16V4Z
Debug@
IN_TPM@
4.7K_0402_5%
G
4
LM393DG_SO8
Debug@
R1428
0_0603_5%
D5 Debug@
RB715F_SOT323-3
2
1
3
U142B
+3VL
VSB
+3VALW
+3VALW
R419
10K_0402_5%
Debug@
8
+
24
19
10
+5VALW
<9,29,33,35,39,41,43> SUSP#
GND
GND
GND
GND
C397
LM393DG_SO8
0.1U_0402_16V4Z
Debug@
Debug@
+5VALW
R418
100K_0402_5%
Debug@
0.1U_0402_16V4Z
IN_TPM@ 2
C765
IN_TPM@
1U_0402_6.3V4Z
0.1U_0402_16V4Z
Debug@
U142A
EC_ON
100K_0402_5%
C764
Debug@
R303
1
+5VALW
R416
10K_0402_5%
Debug@
1
+5VALW
<18>
<18>
<18>
<18>
PCH_SPI_MISO
PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_MOSI
PCH_SPI_MISO
PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_MOSI
2
5
9
12
14
+3VS
1
Debug@
1OE#
2OE#
3OE#
4OE#
1A
2A
3A
4A
VCC
PCH_SPI_MISO_R
U59
1B
2B
3B
4B
GND
3
6
8
11
PCH_SPI_MOSI_R
PCH_SPI_CLK_R
PCH_SPI_CS0#_R
CS
HOLD
SN74CBT3125PWRG4_TSSOP14
C395
0.1U_0402_16V4Z
Debug@
SA00000CA00
U11 Debug@
For KB930
A
<32,33>
<32,33>
<32,33>
<32,33>
EC_ON
1
4
10
13
KSI3
KSI7
KSI6
KSI5
+3V_SPI
1
C394
SO
SCLK
WP
VCC
GND
For ESD
C766
IN_TPM@
15P_0402_50V8J
MX25L3205AZMC-20G_SON8
CLK_PCI_TPM
C393
0.1U_0402_16V4Z
R669
@ 10_0402_5%
P/N: SA00003K800
1OE#
2OE#
3OE#
4OE#
2
5
9
12
1A
2A
3A
4A
14
VCC
TPM_XTALI
<33,34,38> EC_ON
+3V_SPI
SI
IN_TPM@
R668
10M_0402_5%
2
1
1
4
10
13
U7
2
1B
2B
3B
4B
GND
3
6
8
11
change to 4MB for SW demand
C768
@ 15P_0402_50V8J
OSC
NC
OSC
NC
Y4
2
3
32.768KHZ_12.5PF_Q13MC14610002
TPM_XTALO
C767
IN_TPM@
15P_0402_50V8J
A
7
R1549
SN74CBT3125PWRG4_TSSOP14
+3VS
0.1U_0402_16V4Z
Debug@
0_0402_5%
MP@
+3V_SPI
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
5
Title
SPI ROM
Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
28
of
45
Function Board
Left USB
+5VALW
+USB_VCCB
+5VALW
U26
<33>
1
2
3
4
USB_EN#
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
AP2301SG_SO8-13
W=30mils
1
1 R427
2
0_0402_5%
D22
C439
1U_0603_10V6K
@
<22> USB_OC0#
+USB_VCCB
L16
2
WCM2012F2SF-900T04_0805
USB20_P2_R
1
D19
PJDLC05C_SOT23-3
@
R421 0_0402_5%
@
USB20_N2_R
USB20_P2_R
JUSB3
USB20_N2_R
For EMI
P/N:SM070000K00
1
2
3
4
5
6
7
8
VBUS
DD+
GND
GND
GND
GND
GND
HeadPhone/LINE Out JACK
USB20_N1
USB20_P1
<22>
<22>
USB20_N0
USB20_P0
USB20_N0
USB20_P0
<31>
<31>
<31>
<31>
<31>
<31>
Ext.MIC/LINE IN JACK
ACON_UARBG-4K1926
USB20_P2 <22>
USB20_N1
USB20_P1
HP_R
HP_L
MIC1_L
MIC1_R
NBA_PLUG
MIC_SENSE
MIC1_L
MIC1_R
@
1
25
26
For ESD
1
+5VS
C21
0.1U_0402_16V4Z
PJDLC05C_SOT23-3
@
USB_EN#
<22>
<22>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C20
0.1U_0402_16V4Z
USB20_N2 <22>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
USB_OC1# <22>
@
R420 0_0402_5%
2
1
ACES_85201-24051
W=60mils
GND1
GND2
@ JUSB
Smart Card
+5VS
<22,27> USB20_N9
<22,27> USB20_P9
USB20_N9
USB20_P9
0_0402_5%2 SC@
0_0402_5%2
SC@
@
1
2
3
4
5
6
1 R838
1 R837
CM20
2
4.7U_0805_10V4Z
CM21
D24
DAN217_SC59
@
47P_0402_50V8J
For SED request
R580
100K_0402_5%
CM22
2
0.1U_0402_16V4Z
1
CM19
47P_0402_50V8J
For SED request
JSMART
+3VS
CM18
2
CM17
+1.5VS
0.1U_0402_16V4Z
1
+3VS
+3VS
Kill SWITCH
Slot 1 Half PCIe Mini Card-WLAN & BT2.0
Smart Card and New Card
1BS003-1211L_3P
2
4.7U_0805_10V4Z
KILL_SW#
1
2
3
4
G1
G2
1
SW2
ACES_85201-0405N
+1.5VS
+3VS
JWLAN
PCH_PCIE_WAKE# 1
R126
BT_PWRON
<19> PCIE_PTX_C_NEWRX_N5
<19> PCIE_PTX_C_NEWRX_P5
<19> CLKREQ_NEW#
+3VALW
<22> EXP_CPPE#
<9,28,33,35,39,41,43> SUSP#
<33,35,40> SYSON
CLKREQ_NEW#
EXP_CPPE#
PCH_PCIE_WAKE#
SUSP#
SYSON
+3VS
D_CK_SCLK
D_CK_SDATA
PLT_RST#
+1.5VS
4
G2
G1
28
27
<19> CLK_WLAN#
<19> CLK_WLAN
ES2@
BT_PWRON
2
0_0402_5%
R127
<19> PCIE_PRX_WLANTX_N2
<19> PCIE_PRX_WLANTX_P2
<19> PCIE_PTX_C_WLANRX_N2
<19> PCIE_PTX_C_WLANRX_P2
WLAN/ WiFi
+3VS
<33>
<33>
1
2
1R1430 0_0402_5%
2
R1431 0_0402_5%
E51_TXD
E51_RXD
53
Debug card using
100K_0402_5%
R1315
PS_HPF05052-261000R
@
GND1
GND2
<33> EC_BT_PWRON
XMIT_OFF#
PLT_RST#
1
0_0402_5%
R28
1.1K_0402_1%2_5%
QS@
0_0402_5%
Bluetooth 2.0
+3VS
CM29 0.1U_0402_16V4Z
1
2
54
BT_PWRON
<33> EC_WL_OFF#
<22> PCH_WL_OFF#
<33> EC_KILL_SW#
R136
1
R137
@
1
R130
1
R131
0_0402_5%
2 WL_OFF#
0_0402_5%
2 KILL_SW#
0_0402_5%
2
0_0402_5%
2
1
Y
A
XMIT_OFF#
4
UM1
NC7SZ08P5X_NL_SC70-5
Compal Secret Data

2010/05/17
2011/05/17
Deciphered Date
B
BT_PWRON
0_0402_5%
D_CK_SCLK <12,13,14>
D_CK_SDATA <12,13,14>
ACES_88910-5204
@
R133
USB20_N13 <22>
USB20_P13 <22>
<18> PCH_KILL_SW#
Issued Date
PLT_RST# <5,22,28,30,33>
+3VS
R129
1
R132
<23> PCH_BT_PWRON
<19> PCIE_PRX_NEWTX_N5
<19> PCIE_PRX_NEWTX_P5
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
<19> CLK_NEW#
<19> CLK_NEW
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
USB20_N8
USB20_P8
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
USB20_N8
USB20_P8
<22>
<22>
NewCard
<19> CLKREQ_WLAN#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
JNEW
2 WLAN_WAKE
0_0402_5%
<20,30> PCH_PCIE_WAKE#
Title
Function Board/Left USB Port/WLAN/BT

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
E
29
of
45
UL1
<19> PCIE_PRX_C_LANTX_P1
CL1
2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1
22
<19> PCIE_PRX_C_LANTX_N1
CL2
2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1
23
<19> PCIE_PTX_C_LANRX_P1
<19> PCIE_PTX_C_LANRX_N1
PCIE_PTX_C_LANRX_P1
PCIE_PTX_C_LANRX_N1
RL19
<19> CLKREQ_LAN#
<5,22,28,29,33> PLT_RST#
+3V_LAN
@
<19>
<19>
2PCH_PCIE_WAKE#
100K_0402_5%
CLK_LAN
CLK_LAN#
RTL8105E
Pin15
NC
Pin38
1K ohm Pull-high
CLKREQB
MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3
1
2
4
5
7
8
10
11
DVDD10
DVDD10
DVDD10
13
29
41
+LAN_VDD10
+3V_LAN
19
20
LAN_X1
43
CKXTAL1
LAN_X2
44
CKXTAL2
PCH_PCIE_WAKE#
28
LANWAKEB
ISOLATEB
26
ISOLATEB
DVDD33
DVDD33
27
39
14
15
38
NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT
AVDD33
AVDD33
AVDD33
AVDD33
12
42
47
48
33
ENSWREG
34
35
VDDREG
VDDREG
<20,29> PCH_PCIE_WAKE#
NC
10K ohm PD
RL7
15K_0402_5%
+3V_LAN
RL21 2 8111E@ 1 10K_0402_5%

RL22 1
2 1K_0402_5%
ENSWREG
+LAN_VDDREG
PERSTB
REFCLK_P
REFCLK_N
2
2.49K_0402_1%
46
24
49
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-
LL1,CL13 will be changed to

2.2uH&4.7uF after EVT test
+LAN_REGOUT
1
2
4.7UH_1008HC-472EJFS-A_5%_1008
RSET
GND
PGND
+3V_LAN
Close to Pin 27,39,12,47,48
1
Layout Note: LL1 must be
within 200mil to Pin36,
CL13
CL13,CL9 must be within 22U_0805_6.3V6M
2
200mil to LL1
CL9
0.1U_0402_16V4Z
2
CL10
2
CL4
1
2
0.1U_0402_16V4Z
CL5
1
2
0.1U_0402_16V4Z
CL6
1
2
0.1U_0402_16V4Z
CL7 8111E@
CL7 close to pin12
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+LAN_VDD10
+3V_AVDDXTAL
+LAN_EVDD10
2
0_0603_5%
1
LL2
1U_0402_6.3V6K
CL18
+3V_LAN
CL17
0.1U_0402_16V4Z
1
Close to Pin 3,6,9,13,29,41,45

+LAN_VDD10
Close to Pin 21
EVDD10
21
+LAN_EVDD10
0.1U_0402_16V4Z
AVDD10
AVDD10
AVDD10
AVDD10
3
6
9
45
+LAN_VDD10
0.1U_0402_16V4Z
1
+3V_LAN
+LAN_VDDREG
0.1U_0402_16V4Z
+LAN_REGOUT
36
REGOUT
1
0.1U_0402_16V4Z
60 mils
2
0_0603_5%
RTL8111E-GR_QFN48_6X6
0.1U_0402_16V4Z
1
LL3
CL28
4.7U_0603_6.3V6K
+3VALW TO +3V_LAN
CL29
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
CL19
2
CL20
2
CL21
2
CL22
2
CL23
2
CL24
2
CL25
8111E@
8111E@
8111E@
CL23,CL24,CL25 close to pin6,9,41, respectively

+3V_AVDDXTAL
Vgs=-4.5V,Id=3A,Rds<97mohm
RL8
+3V_LAN
0_0402_5%
+3VALW
+LAN_VDD10
LL1
1
RL5
1 10K_0402_5%
1 10K_0402_5%
EECS/SCL
EEDI/SDA
25
RL6
1K_0402_1%
RL2 2
RL1 2
30
32
HSIP
HSIN
+3VS
RTL8111E
NC
HSON
CLK_LAN
CLK_LAN#
Pin14
0_0402_5% 16
31
37
40
LED3/EEDO
LED1/EESK
LED0
PLT_RST#
1
RL3
17
18
8111E@
HSOP
RL9
@ 0_0402_5%
+3V_LAN
+LAN_VDD10
+3V_LAN
LAN Conn.
Reserved For 1.05V Crystal

1
PJ35
2
2
1
JUMP_43X79
@
CL840
4.7U_0805_10V4Z
@
CL11
0.1U_0402_16V4Z
RL4
0_0402_5%
JLAN
RJ45_MIDI3-
RJ45_MIDI3+
RJ45_MIDI1-
RJ45_MIDI2-
RJ45_MIDI2+
RJ45_MIDI1+
RJ45_MIDI0-
RJ45_MIDI0+
CL11 close to pin42
ENSWREG
1
1U_0402_6.3V6K
CL841
YL1
LAN_X1
RL23
0_0402_5%
@
LAN_X2
25MHZ_20PF_7A25000012
1
CL26
27P_0402_50V8J
2
CL27
27P_0402_50V8J
PR4PR4+
PR2PR3PR3+
B
PR2+
PR1SHLD1
SHLD2
PR1+
9
10
SANTA_130452-C
UL5
For P/N and footprint

Please place them to ISPD page
LAN_MDI3LAN_MDI3+
1
2
3
LAN_MDI2LAN_MDI2+
4
5
6
7
8
9
LAN_MDI1LAN_MDI1+
UL1
10
11
12
LAN_MDI0LAN_MDI0+
8105E 10/100M
8105E@
Place CL34 colse
to LAN chip
TCT1
TD1+
TD1-
MCT1
MX1+
MX1-
TCT2
TD2+
TD2-
MCT2
MX2+
MX2-
TCT3
TD3+
TD3-
MCT3
MX3+
MX3-
TCT4
TD4+
TD4-
MCT4
MX4+
MX4-
24
23
22
21
20
19
CL39 1000P_0402_50V7K
2
1
1 8111E@ 2
8111E@
RL11
75_0402_1%
CL40 1000P_0402_50V7K
2
1
1 8111E@ 2
8111E@
RL12
75_0402_1%
CL41 1000P_0402_50V7K
2
1
1
2
RL13
75_0402_1%
18
17
16
CL42 1000P_0402_50V7K
2
1
1
2
RL15
75_0402_1%
15
14
13
@
RJ45_MIDI3RJ45_MIDI3+
RJ45_GND
LANGND
2 1000P_1808_3KV7K
1
CL36
CL37
0.1U_0402_16V4Z
CL38
4.7U_0603_6.3V6K
RJ45_GND
UL5
8111E@
SUPERWORLD_SWG150401
For ESD
CL34
0.1U_0402_25V4K
D6
2
3
D7
2
1
@
AZC199-02SPR7G_SOT23-3
AZC199-02SPR7G_SOT23-3
10/100M transformer
8105E@
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
5
Title
RTL8105E/8111E
Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
30
of
45
+PVDD1
CA57
GND
GND
MIC
1
2
CA8
CA7
10U_0805_10V4Z 0.1U_0402_16V4Z
2
3
4
RA32 0_0603_5%
2
1
+3VS
JA1
JUMP_43X39
CA1
CA2
0.1U_0402_16V4Z 10U_0805_10V4Z
2
@
2
+1.5VS
+DVDD_IO
1
1
ACES_88231-02001
+AVDD
0.1U_0402_16V4Z
CA61
RA3
10U_0805_10V4Z 0.1U_0402_16V4Z 2
1
0_0603_1%
68 mA
2
10U_0805_10V4Z
place close to chip
+PVDD2
@
place close to chip
+5VS
CA43
2
10U_0805_10V4Z
RA33 0_0603_5%
place close to chip
0.1U_0402_16V4Z
1
1
CA44
CA56
@ JMIC
1
2
+3VS_DVDD
35 mA
RA1
2
0_0603_5%
1
+3VS
RA2
2
1
0_0603_1%
600 mA 0.1U_0402_16V4Z
+5VS
RA12
2
1
0_0603_1%
CA60
@
@
0.1U_0402_16V4Z
+5VS
1
1
CA59
CA58
@
@
2
10U_0805_10V4Z
2
10U_0805_10V4Z
UA12
MIC
MIC1_LINE1_R_R
CA9
2 4.7U_0402_4V7K
MIC1_LINE1_R_L
CA11 1
2 4.7U_0402_4V7K
CA26 2
1U_0402_6.3V6K
CA28 2
1U_0402_6.3V6K
1
2 MIC2R_R
RA25 1K_0402_5%
1
2 MIC2R_L
RA26 1K_0402_5%
RA39
0_0402_5%
@
Ext.
Mic/LINE IN
22
21
MIC2_R 17
MIC2_L 16
31
30
29
+MIC1_VREFO_L
+MIC1_VREFO_R
+MIC2_VREFO
RA34
0_0402_5%
@
2
2
2
2
10U_0805_10V4Z 0.1U_0402_16V4Z
PVDD1
PVDD2
39
46
SPKR+
SPKRSPKL+
SPKL-
+PVDD1
+PVDD2
DA10
PESD5V0U2BT_SOT23-3
CA6
25
38
MIC1_VREFO_L
MIC1_VREFO_R
MIC2_VREFO
CA5
AVDD1
AVDD2
MIC2_R
MIC2_L
CA4
CA3
DVDD
DVDD_IO
place close to chip

For EMI
RA72
15
14
LINE2_R
LINE2_L
SPK_OUT_R+
SPK_OUT_R-
45
44
20
MONO_OUT
40
41
12
SPK_OUT_L+
SPK_OUT_L-
PCBEEP_IN
10
SYNC
HPOUT_R
HPOUT_L
33
32
11
RESET#
HDA_BITCLK_AUDIO
CA30
10_0402_5%
3
1
2
1
9
MIC1_R
MIC1_L
+MIC2_VREFO
RA51 4.7K_0402_5%
1
CA12
<18> HDA_SYNC_AUDIO
MONO_IN
2
100P_0402_50V8J
HDA_SYNC_AUDIO
<18> HDA_RST_AUDIO#
1
CA17
10U_0805_10V4Z
20K_0402_1% 1
RA10 2 AC_JDREF
19
CA35
2
110U_0805_10V4Z28
AC_VREF 27
CPVEE
2.2U_0603_6.3V6K 2
CA14
1
34
1
2
35
CA16
36
2.2U_0603_6.3V6K
JDREF
LDO_CAP
VREF
CPVEE
CBN
CBP
SDATA_OUT
SDATA_IN
5
8
BITCLK
NC
NC
NC
CA18
2
3
2
2
0.1U_0402_16V4Z
SENSE_A
SENSE_B
place close to chip

<33> EAPD
<33> EC_MUTE#
+AVDD
13
18
EAPD
EC_MUTE#
47
4
1
2
RA27 1K_0402_5%
GPIO0/DMIC_DATA
GPIO1/DMIC_CLK
SENSE_A
SENSE_B
EAPD
PD#
AVSS1
AVSS2
PVSS1
PVSS2
DVSS
THERMAL_PAD
RA4
75_0402_1%
RA5
75_0402_1%
HDA_SDOUT_AUDIO
HDA_SDIN0_R
2
1
RA6 33_0402_5%
HDA_BITCLK_AUDIO
HP_R
<29>
HP_L
<29>
10P_0402_50V8J
HDA_SDOUT_AUDIO <18>
HDA_SDIN0 <18>
HDA_BITCLK_AUDIO <18>
24
23
48
Speaker Connector
26
37
42
43
7
placement near Audio Codec
AGND
RA13
2
1
0_0603_1%
SPKL+
DGND
SPK_L1
1
DA8
CA19
@ 10U_0805_10V4Z
2
49
ALC259-VB5-GR_QFN48_7X7
1
CA46
RA14
@ 10U_0805_10V4Z
2
2
1
0_0603_1%
RA15
2
1
0_0603_1%
1
SPKL-
Ext.MIC/LINE IN JACK
SPKR+
CA42
1U_0402_6.3V6K
@
PESD5V0U2BT_SOT23-3
JSPK
SPK_L2
SPK_L1
SPK_R2
SPK_R1
SPK_L2
1
2
3
4
SPK_R1
DA9
2 0.1U_0603_50V7K
CA48 1
2 0.1U_0603_50V7K
CA49 1
2 0.1U_0603_50V7K
CA50 1
1
RA43
RA47
2 RA48 1
1K_0402_5% 4.7K_0402_5%
2
1
MIC1_LINE1_R_R
MIC1_LINE1_R_L
2
1
1K_0402_5%
RA45
2 0.1U_0603_50V7K
RA46 1
2
4.7K_0402_5%
2
0_0603_5%
MIC1_R
<29>
MIC1_L
<29>
SENSE A
Codec Signals
39.2K
PORT-A (PIN 39, 41)
20K
PORT-B (PIN 21, 22)
10K
PORT-C (PIN 23, 24)
5.1K
PORT-D (PIN 35, 36)
39.2K
PORT-E (PIN 14, 15)
SPKR-
Beep sound
Headphone out
Ext. MIC
<29> MIC_SENSE
<29>
RA18 20K_0402_1%
1
2
NBA_PLUG
<33>
SENSE_A
CA45
1U_0402_6.3V6K
@
RA8
1
2
47K_0402_5%
EC_BEEP#
CA15
1
2
RA9
1
2
47K_0402_5%
<18> HDA_SPKR
RA19 20K_0402_1%
1
RA11
10K_0402_5%
2
20K
PORT-F (PIN 16, 17)
10K
PORT-H (PIN 37)
5.1K
PORT-I (PIN 32, 33)
CA20
0.1U_0402_16V4Z
Int. MIC
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
5
MONO_IN
0.1U_0402_16V4Z
SENSE_B
SENSE B
PESD5V0U2BT_SOT23-3
SPK_R2
PCI Beep
RA16 39.2K_0402_1%
EC Beep
Function
Impedance
CA39
@ 10U_0805_10V4Z
RA44
2
2
1
0_0603_1%
5
6
1
2
+MIC1_VREFO_L
place close to chip

Sense Pin
CA51
@ 10U_0805_10V4Z
2
+MIC1_VREFO_R
G1
G2
ACES_88266-04001
@
2
CA47 1
1
2
3
4
Title
HD Audio Codec ALC259

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
31
of
45
3 in 1 Card Reader
For EMI
RC2
CLK_48M_CR
RC4
6.19K_0402_1%
2
1
CARD@
<22>
<22>
+3VS_CR
RC5
0_0603_5%
USB20_N11
USB20_P11
USB20_N11
USB20_P11
1 CC8
0.1U_0402_16V4Z
CC11
CARD@
4.7U_0805_10V4Z
+VCC_3IN1
1
2
2
CARD@
1U_0402_6.3V6K
CC12
REFE
GPIO0
2
3
+3VS_CR
CARD@
CARD@
DM
DP
4
5
6
V1_8
1
RC25
2
0_0402_5%
XD_D7
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6
XD_CD#
8
9
10
11
12
SP1
SP2
SP3
SP4
SP5
25
CC14
10P_0402_50V8J
@
SDWP_MSCLK
MSCD#
SD_DATA1
SD_DATA0
MS_DATA3_SD_DATA7
CLK_IN
3V3_IN
CARD_3V3
V18
7
SDWP_MSCLK_R
10_0402_5%
10P_0402_50V8J
CLK_48M_CR <19>
< 48MHz >
UC2
1
EPAD
+3VS
CC2
1
2
@ CC15 100P_0402_50V8J
17
24
CLK_48M_R
1
RC28
2
0_0402_5%
23
22
21
20
19
18
16
15
14
13
MSBS
SD_DATA2_MS_DATA5
MS_DATA1_SD_DATA3
SDCMD
MS_DATA0_SD_DATA5
MS_DATA2_SDCLK
1
RC23
MS_DATA2_SDCLK_R
2
0_0402_5%
SDCD#
1 CC13
10P_0402_50V8J
@
RTS5138-GR_QFN24_4X4
CARD@
@ JCR
SDWP_MSCLK_R
SD_DATA1
SD_DATA0
MSBS
MS_DATA2_SDCLK_R
MS_DATA1_SD_DATA3
MS_DATA0_SD_DATA5
+VCC_3IN1
1 CARD@
CC16
MSCD#
MS_DATA3_SD_DATA7
SDCMD
0.1U_0402_16V4Z
CARD@
1U_0402_6.3V6K
CC17
Close to OSC1
48MHz_SSW048000I3CH
2
SD_DATA2_MS_DATA5
SDCD#
CLK_48M_R
1
RC26
@
TAITW_R009-121-LK_RV
OSC_48M_CR
2
0_0402_5%
GND CONT
OUT
VDD
1
RC27
@
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
KSO2
KSO1
KSO0
KSO4
KSO3
4
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
JKB
28
27
GND
GND
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
KSO17
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SPI Flash (1MByte*1)
Lid SW
1
2
R744 3VALW@
0_0402_5%
1
2
R745
3VL@
0_0402_5%
+3VALW
+3VL
C789
2
0_0402_5%
+3VALW
R748
2
0_0402_5%
1
@
+3VL
R747
20mils
U49
8
0.1U_0402_16V4Z
3
7
1
<33> SPI_CS#
<33> SPI_CLK
<33> EC_SO_SPI_SI
VCC
VSS
KSO11
VDD
KEYBOARD CONN.
W
HOLD
1
S
C
D
GND
KSO10
EMC
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
CC7
0.1U_0402_16V4Z
@
LID_SW#
EC_SI_SPI_SO <33>
<33>
U36
AH180WG-7_SC59-3
C648
0.1U_0402_16V4Z
KSO16
For
1
C809
1
C806
1
C803
1
C804
1
C805
1
C807
1
C808
1
C810
1
C824
1
C826
1
C823
1
C825
1
C871
1
C822
1
C793
1
C790
1
C791
1
C792
1
C795
1
C796
1
C797
1
C798
1
C799
1
C800
1
C801
1
C802
+3VS_CR
+3VS_CR
OSC1
@
KSO17
2
0_0402_5%
22
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
OUTPUT
SD-WP-SW
SD-DAT1
SD-DAT0
SD-GND
MS-GND
MS-BS
SD-CLK
MS-DAT1
MS-DAT0
SD-VCC
MS-DAT2
SD-GND
MS-INS
MS-DAT3
SD-CMD
MS-SCLK
MS-VCC
SD-DAT3
MS-GND
GND1 SD-DAT2
GND2SD-CD-SW
C649
0.1U_0402_16V4Z
MX25L2005CMI-12G SO8
P/N :SA00002C100
ACES_88514-2601
@
@ C931
@R1369
@
R1369
2
1 2
1
6P_0402_50V
KSI[0..7]
KSO[0..17]
KSI[0..7]
SPI_CLK
10_0402_5%
<28,33>
KSO[0..17] <33>
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
B
Title
RTS5138 CR/KB/EC SPI/LID

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
E
32
of
45
R715
+3VALW 0_0805_5% 3VALW@
1
2
VCC
VCC
VCC
VCC
VCC
VCC
U32
C742
1000P_0402_50V7K
C741
1000P_0402_50V7K
C740
0.1U_0402_16V4Z
C739
0.1U_0402_16V4Z
L53
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA
+3VALW_EC
C738
0.1U_0402_16V4Z
C737
0.1U_0402_16V4Z
R714
0_0805_5% 3VL@
2
1
ECAGND
R718 2
+3VALW_EC
1 47K_0402_5%
C745 2
<23> GATEA20
<23> KB_RST#
<18,28> SERIRQ
<18,28> LPC_FRAME#
<18,28> LPC_AD3
<18,28> LPC_AD2
<18,28> LPC_AD1
<18,28> LPC_AD0
+3VALW_EC
10/1 ENE Recommand

R723
2 47K_0402_5%
KSO1
R728
2 47K_0402_5%
KSO2
R743
2 10K_0402_5% USB30_OC#
<22> CLK_PCI_LPC
<5,22,28,29,30> PLT_RST#
<23> EC_SCI#
PAD
T64 @
+3VALW_EC
C
R729
2 2.2K_0402_5%
R731
2 2.2K_0402_5%
@ C748
22P_0402_50V8J
2
1
EC_SMB_DA1
EC_SMB_CK1
<28,32>
<32>
@ R732
33_0402_5%
1
2
KSI[0..7]
KSI[0..7]
KSO[0..17]
KSO[0..17]
Reserve for EMI please close to U32

+3VS
R738
2 2.2K_0402_5% EC_SMB_CK2
C743
0.1U_0402_16V4Z
ECRST#
0.1U_0402_16V4Z
67
+3VL
CLK_PCI_LPC
AVCC
@ R716
33_0402_5%
2
1
9
22
33
96
111
125
@ C744
22P_0402_50V8J
2
1
R739
2 2.2K_0402_5% EC_SMB_DA2
R741
2 10K_0402_5% EC_SCI#
<36>
<36>
<19>
<19>
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
1
2
3
4
5
7
8
10
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &
CLK_PCI_LPC
12
13
37
20
38
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
ECRST#
EC_SCI#
21
23
26
27
CPU1.5V_S3_GATE
EC_BEEP#
EC_DPWROK
ACOFF
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
63
64
65
66
75
76
BATT_TEMPA
P_USB_EN#
ADP_I
Board_ID
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
68
70
71
72
EN_DFAN1
IREF
CHGVADJ
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
83
84
85
86
87
88
EC_MUTE#
USB_EN#
PWR_USB_LED#
DRAMRST_CNTRL_EC
TP_CLK
TP_DATA
97
98
99
109
SUSACK#
EC_WL_OFF#
HDA_SDO
VGATE
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
PWM Output
MISC
AD
DA Output
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
77
78
79
80
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
GFX_CORE_PWEGD
WL_BT_LED#
PM_SLP_SUS#
SUSWARN#
INVT_PWM
FAN_SPEED1
PCH_PWR_EN
E51_TXD
E51_RXD
EAPD
USB30_OC#
NUM_LED#
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
PS2 Interface
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
BATT_TEMPA <36>
ADP_I
2
R742
1
0_0402_5%
GPIO
SM Bus
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
<36,37>
EC_MUTE# <31>
USB_EN# <29>
PWR_USB_LED# <34>
DRAMRST_CNTRL_EC <7>
TP_CLK <34>
TP_DATA <34>
SUSACK# <20>
EC_WL_OFF# <29>
HDA_SDO <18>
VGATE <14,20,44>
EC_SI_SPI_SO
EC_SO_SPI_SI
SPI_CLK_R
SPI_CS#
73
74
89
90
91
92
93
95
121
127
PM_PWROK
EC_PECI R740 1
FSTCHG
BATT_FULL_LED#
CAPS_LED#
BATT_CHG_LOW_LED#
PWR_ON_LED#
SYSON
VR_ON
PM_SLP_S4#
100
101
102
103
104
105
106
107
108
PCH_RSMRST#
LID_SW_OUT#
PWR_USB_EN#
EC_BT_PWRON
H_PROCHOT#_EC
BKOFF#
ENBKL
PCH_APWROK
SA_PGOOD
110
112
114
115
116
117
118
EC_ACIN
EC_ON
ON/OFFBTN#
LID_SW#
SUSP#
PBTN_OUT#
EC_KILL_SW#
124
+EC_V18R
1
SPI_CLK <32>
IMVP_IMON <44>
P_USB_EN#
119
120
126
128
10_0402_5%
SPI_CLK_R
2
1
0_0402_5% R1458
@
1
R750
EN_DFAN1 <5>
IREF
<37>
CHGVADJ <37>
SPI Device Interface

SPI Flash ROM
R1458
10P_0402_50V8J
1 100P_0402_50V8J ECAGND
C746 2
IMON
C930
For EMI
CPU1.5V_S3_GATE <9>
EC_BEEP# <31>
EC_DPWROK <20>
ACOFF
<37>
2
@
PWR_USB_EN#
0_0402_5%
+3VALW_EC
C
Board_ID
R117
R749
2 100K_0402_5%
2 0_0402_5%
1
@
+3VALW_EC
LID_SW#
R766
2 47K_0402_5%
TP_CLK
R720
4.7K_0402_5%
TP_DATA
R727
4.7K_0402_5%
GFX_CORE_PWEGD R722
2 10K_0402_5%
BKOFF#
R724
2 10K_0402_5%
R717
EC_SI_SPI_SO <32>
EC_SO_SPI_SI <32>
+5VS
SPI_CS# <32>
PM_PWROK <20>
H_PECI
<5,23>
FSTCHG <37>
BATT_FULL_LED# <34>
CAPS_LED# <34>
BATT_CHG_LOW_LED# <34>
PWR_ON_LED# <34>
SYSON
<29,35,40>
VR_ON
<44>
PM_SLP_S4# <20>
2 43_0402_1%
+3VS
+3VALW
V18R
11
24
35
94
113
KB930QF A1 LQFP 128P
EC_MUTE#
BKOFF# <15>
ENBKL
<21>
PCH_APWROK <20>
SA_PGOOD <43>
+3VALW_EC
R730
1 200K_0402_5%
2
2
EC_ON <28,34,38>
ON/OFFBTN# <34>
LID_SW# <32>
SUSP# <9,28,29,35,39,41,43>
PBTN_OUT# <18,20>
EC_KILL_SW# <29>
1 10K_0402_5%
@
1
D15
EC_ACIN
C749
ACIN
<20,37>
1 100P_0402_50V8J
C753
4.7U_0805_10V4Z
20mil
<36,44> VR_HOT#
L54
ECAGND 2
1
FBMA-L11-160808-800LMT_0603
VR_HOT#
R737
0_0402_5%
2
1
H_PROCHOT# <5>
1
XCLK1
XCLK0
PCH_RSMRST# <18,20>
LID_SW_OUT# <19>
PWR_USB_EN# <34>
EC_BT_PWRON <29>
122
123
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
GPI
GND
GND
GND
GND
GND
<20> SUSCLK
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
AGND
<34> NUM_LED#
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
69
<20> PM_SLP_S3#
<20> PM_SLP_S5#
<23>
EC_SMI#
<44> GFX_CORE_PWEGD
<34> WL_BT_LED#
<20> PM_SLP_SUS#
<20> SUSWARN#
<15> INVT_PWM
<5> FAN_SPEED1
<35> PCH_PWR_EN
<29> E51_TXD
<29> E51_RXD
<31> EAPD
H_PROCHOT#_EC
2
G
Q37
2N7002_SOT23
C18
R24
0_0402_5%
100K_0402_5%
C18
2
10P_0402_50V8J
For EMI
R24
SUSCLK
Compal Secret Data
10_0402_5%
C747
22P_0402_50V8J
2
1
Issued Date
2010/05/17
2011/05/17
Deciphered Date
5
Title

EC ENE-KB930

Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
33
of
45
Touch/B Connector
+5VS
1
2
ON/OFFBTN#_R
ON/OFFBTN# <33>
1
1 R746
2
3VALW@ 0_0402_5%
CHN202UPT SC-70
3
@ C646
0.1U_0402_16V4Z
%RWWRP6LGH
ACES_85201-06051
@
<36>
D18
PJDLC05C_SOT23-3
TP_CLK <33>
TP_DATA <33>
D16
PJDLC05C_SOT23-3
SW9
SMT1-05-A_4P
1
D
LEFT_BTN#
Q20
2N7002_SOT23-3
2
G
3
<28,33,38> EC_ON
51_ON#
3VL@
R765
100K_0402_5%
1
3VALW@
R168
100K_0402_5%
D9
1
10K_0603_5%
1
10K_0603_5%
2
220P_0402_50V8K
LEFT_BTN#
RIGHT_BTN#
C759
100P_0402_50V8J
1
C24
1
2
3
4
5
6
7
8
C757
100P_0402_50V8J
1
2
3
4
5
6
GND
GND
+3VL
LEFT_BTN#
RIGHT_BTN#
3
JTP
+3VALW
RIGHT_BTN#
SW4
SMT1-05-A_4P
1
5
6
R514
10K_0402_5%
Screw Hole
1
H_2P8
PWR_ON_LED#
PCB LA-6772P REV01

DAZ@
H7
H8
H9
H_2P8
H10
H11
H_2P8
H_2P8
H_2P8
H_2P8
H_2P8
PJPDC1
PJPDC1
45@
JWLAN
H12
H_3P6x2P6N
H_2P8
1 LED3
H_2P8
+5VALW
R660
820_0402_5%
1
2
H_2P8
PCB LA-6772P REV01

DA6@
H5
@
H6
SATA_LED# <18>
HT-191NB_BLUE_0603
H4
1 LED2
ZZZ1
H3
+5VS
ZZZ
PCB
H2
R658
820_0402_5%
1
2
H1
LED
ISPD
H_2P6N
HT-191NB_BLUE_0603
DC-IN
H20
Blue
BATT_FULL_LED# <33>
HT-191NB_BLUE_0603
CPU
Amber
HT-191UD_Amber_0603
WL_BT_LED# <33>
+5VALW
BT/WLAN LED
PWR_USB
PWR_USB_LED#
CAPS_LED#
NUM_LED#
<33> PWR_USB_LED#
<33> CAPS_LED#
<33> NUM_LED#
2
3
PWR_USB_EN#
51_ON#
PWR_USB_EN# <33>
For ESD
P/N:SCA00000W00
D34
PSOT24C_SOT23
PWR_USB_LED#
220P_0402_50V8K
H_4P2
H_4P2
H_4P2
FD1
FD2
FD3
H_4P2
FD4
2010/05/17
Deciphered Date
Compal Secret Data
Issued Date
C25
H25
BAV70W_SOT323-3
For ESD
H24
PCB Fedical Mark PAD
2
1
GND
GND
8
7
6
5
4
3
2
1
@
ACES_85201-08051
D33
PSOT24C_SOT23
10K_0402_5%
D25
PWR_USB
1
R515
H23
JLED
10
9
8
7
6
5
4
3
2
1
W=20mils
+3VALW
H22
+5VS
LED6
2
R666
820_0402_5%
1
2
+5VS
H_1P1
1 LED5
BATT_CHG_LOW_LED# <33>
Amber
1 LED4
R664
1
2
820_0402_5%
+5VALW
HT-191UD_AMBER_0603
+5VALW
R663
820_0402_5%
1
2
2
R153 @
2
R154 @
TP_CLK
TP_DATA
1
2
D20
7236LGH
2
0.1U_0402_16V4Z
ACES_85201-0405N
3
PWR_ON_LED#
For ESD
P/N:SCA00001900
C755
PJDLC05C_SOT23-3
ON/OFFBTN#_R
For ESD
P/N:SCA00000W00
+5VALW
PWR_ON_LED# <33>
5
6
JPOWER @
1 1
2 2
3 3
4 4
G1 5
G2 6
Power Button/ PWR/B
2011/05/17
Title
Power B/TP/LED
Size
B
Date:
Document Number
Rev
1.0
PBL20 LA6772P M/B

Sheet
34
of
45
+3VALW TO +3VALW_PCH
+5VALW
R802
100K_0402_5%
+5VS
6
0.1U_0402_16V7K
0.1U_0402_16V7K
1
2
3
4
S
S
S
G
C848
C839
1U_0402_6.3V6K
SI4800BDY_SO8
SB548000210
C849
2
0.1U_0402_16V7K
C847
10mil
R792
330K_0402_5%
C874
0.1U_0402_16V7K
R791
1 R790
2
47K_0402_5%
+VSB
20mil
Q216A
C875 C846
DMN66D0LDW-7_SOT363-6
+5VALW
Q216B
PCH_PWR_EN#5
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
R805
100K_0402_5%
D
D
D
D
Q44A
SYSON
<29,33,40> SYSON
R808
100K_0402_5%
SB548000210
SUSP
SUSP
<5,42>
8
7
6
5
2
2
Q38
0.1U_0402_16V7K
0.1U_0402_16V7K
1
4.7U_0805_10V4Z
3 1
40mil
Q36B
Q36A
SUSP 5
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
SYSON#
JUMP_43X79
470_0805_5%
J2
C855
470_0805_5%
+VSB
R788
330K_0402_5%
R782
C853
0.022U_0402_25V7K
1
C843
1 R785
2
47K_0402_5%
C842
2
RUN_ON
1
C845
4.7U_0805_10V4Z
4.7U_0805_10V4Z
0.1U_0603_25V7K
4.7U_0805_10V4Z
SI4800BDY_SO8
2
3 1
C852
1U_0402_6.3V6K
1
2
3
4
S
S
S
G
D
D
D
D
Q33
8
7
6
5
+3VALW_PCH
1
+3VALW
C856
+5VALW TO +5VS
+5VALW
+3VALW TO +3VS
Q44B
DMN66D0LDW-7_SOT363-6
Vgs=-0V,Id=9A,Rds=18.5mohm
+3VS
0.1U_0402_16V7K
1 R784
2
47K_0402_5%
R787
330K_0402_5%
+VSB
1
+5VALW
Q35A
R813
100K_0402_5%
Q35B
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
C834
C830
2
0.022U_0402_25V7K
C872
4.7U_0805_10V4Z
SI4800BDY_SO8
2
R781
PCH_PWR_EN#
<25> PCH_PWR_EN#
SB548000210
R809
10K_0402_5%
2
C873 C844
1
2
3
4
S
S
S
G
D
D
D
D
1
4.7U_0805_10V4Z
3 1
8
7
6
5
C828
C827
1U_0402_6.3V6K
470_0805_5%
Q32
<9,28,29,33,39,41,43> SUSP#
0.1U_0402_16V7K
0.1U_0402_16V7K
+3VALW
Q49
2N7002E-T1-GE3_SOT23-3
2
G
<33> PCH_PWR_EN
R816
100K_0402_5%
+1.5V to +1.5VS
Vgs=10V,Id=14.5A,Rds=6mohm
+1.5V
+1.5VS
C838
1U_0402_6.3V6K
R783
R789
820K_0402_5%
C837
2
1
1
C836
FDS6676AS
0.1U_0603_25V7K
4.7U_0805_10V4Z
SI4856ADY_SO8
1
C829
4.7U_0805_10V4Z
1
2
3
4
1 R786
2
+VSB
220K_0402_5%
3 1
S
S
S
G
Q214A
Q214B
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
+3VS
+3VS
@ C878
2
0.1U_0402_16V7K
1
+3VALW
+3VS
@ C876
2
0.1U_0402_16V7K
1
+3VALW
@ C877
0.1U_0402_16V7K
D
D
D
D
470_0805_5%
Q34
8
7
6
5
+1.05VS_PCH
For EMI
2009/08/14
CP_S3PowerReduction
WhitePaper_Rev0.9
0.75VS speed up discharge
@ C880
@ C881
+CPU_CORE
+1.8VS
+1.5V
C889
0.1U_0402_16V7K
@
2
R827
470_0603_5%
R828
470_0603_5%
@C879
@
C879
+1.05VS_PCH
+3VS
1 0.1U_0402_16V7K 1
C890
0.1U_0402_16V7K
@
C882
0.1U_0402_16V7K
@
@ C886
+3VALW
1 0.1U_0402_16V7K 1
C883
0.1U_0402_16V7K
@
C884
0.1U_0402_16V7K
@
+3VS
C885
0.1U_0402_16V7K
@
C887
0.1U_0402_16V7K
@
@ R829
470_0603_5%
2 SUSP
G
Q57
S
2N7002E-T1-GE3_SOT23-3
2 SUSP
G
Q58
S
2N7002E-T1-GE3_SOT23-3
2 SUSP
G
Q59
S
2N7002E-T1-GE3_SOT23-3
C888
0.1U_0402_16V7K
@
For ESD
1 1
1 1
1 1
+3VALW
1 0.1U_0402_16V7K 1
R826
22_0603_5%
+1.05VS_VCCP
+3VS
1 0.1U_0402_16V7K 1
+0.75VS
4
+3VS
2 SYSON#
G
@ Q60
2N7002E-T1-GE3_SOT23-3
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
C
Title
DC Interface
Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
E
35
of
45
CPU thermal protection at 93 +-3 degree C

Recovery at 56 +-3 degree C
VIN
GND RHYST1
OTP_N_002
OT1 TMSNS2
ADP_OCP_3
OT2 RHYST2
ADP_OCP_2
1
EN0
PL4
HCB2012KF-121T50_0805
1
2
If EC use 3VL and can not detect VGATE,

must connect EN0
Install when EC use +3VL
and SUSP was Pull high to +3VL.
PC7
0.01U_0402_25V7K
Reserve when EC use +3VALW.

PJ1
2
JUMP_43X39
VL
+3VALW
PR29
6.49K_0402_1%
POK
PR16
0_0402_5%
2VSB_N_002 2
G
1
<38>
BATT_TEMPA <33>
1
2
2
PQ1
TP0610K-T1-E3_SOT23-3
VSB_N_001
PQ2
SSM3K7002FU_SC70-3
Reserve when EC use +3VL.

Install when EC use +3VALW.
VIN
1VSB_N_003
PR13
100K_0402_1%
PC10
.1U_0402_16V7K
1
PR30
1K_0402_1%
EC_SMB_DA1 <33>
PR12
22K_0402_1%
1
2
EC_SMB_CK1 <33>
1
3
PC8
0.22U_0603_25V7K
PD2
2
+VSBP
1
PC9
0.1U_0603_25V7K
B+
@PJSOT24CW _SOT323-3
VS_ON <38>
1
2
PC6
1000P_0402_50V7K
PH1
100K_0402_1%_NCP15W F104F03RC
PR27
1K_0402_1%
1
PR28
100_0402_1%
2
2
1
PR31
100_0402_1%
2
1
PR10
100K_0402_1%
PD1
@ALLTO_C144FE-109A7-L
0_0402_5%
GND
PR4
<38>
BATT+
B/I
TS_A
EC_SMDA
EC_SMCA
@PJSOT24CW_SOT323-3
11
10
9
8
7
6
5
4
3
2
1
@0_0402_5%
VMB
GND
GND
9
8
7
6
5
4
3
2
1
PR3
10K_0402_1%
2
PR25
100K_0402_1%
1
PR2
PR24 51.1K_0402_1%
G718TM1U_SOT23-8
S
PL3
HCB2012KF-121T50_0805
1
2
VCC TMSNS1
ADP_OCP_1
OTP_N_001
OTP_N_003
2
PR23
1
2
G
100K_0402_1%
PQ4
SSM3K7002FU_SC70-3
PU1
1
PR26
7.87K_0402_1%
X7R type
<33,44> VR_HOT#
PR1
21.5K_0402_1%
1
PC5
0.1U_0603_16V7K
VL
PJP2
ADP_I
2
<33,37>
PC4
100P_0402_50V8J
PC3
1000P_0402_50V7K
VL
1
2
1
2
PJPDC1
PC1
1000P_0402_50V7K
@ SINGA_4TRJW T-R2513
1 1
2 2
3 3
4 4
PC2
100P_0402_50V8J
PL2
HCB2012KF-121T50_0805
1
2
ADPIN
PH1 under CPU botten side :
PL1
HCB2012KF-121T50_0805
1
2
DCIN jack P/N:DC301008L00

need doble confirm P/N with ME
PD3
RLS4148_LL34-2
VS_N_001
1
1
1
1
2
PR22
22K_0402_1%
51_ON#
+VSB
+3VL
VS
PBJ1
PR19
PR20
560_0603_5%
560_0603_5%
+RTCBATT1 1
2+RTCBATT2 1
2
PC12
0.1U_0603_25V7K
3.3V
PJ3
+RTCBATT
+CHGRTC
JUMP_43X39
MAXEL_ML1220T10
Must close PBJ1
<34>
RTC Battery
PR18
68_1206_5%
PC11
0.22U_0603_25V7K
PR21
100K_0402_1%
(120mA,40mils ,Via NO.= 1)
JUMP_43X39
PQ3
PR17
TP0610K-T1-E3_SOT23-3 68_1206_5%
N1
PD4
RLS4148_LL34-2
BATT+
PJ2
+VSBP
VS_N_002
SP093MX0000
Change RTC For Cost Down
Reserve when EC use +3VL.

Install when EC use +3VALW.
Issued Date
Compal Secret Data
2010/05/17
Deciphered Date
2011/05/17
A
Title
DCIN / BATT CONN / OTP

Size
Document Number
Rev
1.0
NCL61 LA-6321P M/B

Date:

D
Sheet
36
of
45
PC127 @10U_0805_25V6K
1
2
1CHG_N_0081
PR111
14.3K_0402_1%
22
PQ106
DTC115EUA_SC70-3
ICOMP
CSIN
20
VCOMP
CSIP
19
ICM
PHASE
18
LX_CHG
VREF
UGATE
17
DH_CHG
3
2
1
PL101
PR102
10U_LF919AS-100M-P3_5.3A_20%
0.02_1206_1%
CHG
1
2
1
4
CHLIM
BOOT
16
6251aclim
10
ACLIM
VDDP
15
11
VADJ
LGATE
14
GND
PGND
13
PC121
0.1U_0603_25V7K
BST_CHGA 2
1
4
PD106
RB751V-40TE17_SOD323-2
6251VDDP
12
DL_CHG
26251VDD
PR129
4.7_0603_5%
PR128
20K_0402_1%
CHG_SNUB 2
2 ACPRN
G
PQ109
@SSM3K7002FU_SC70-3
2
PQ110
AO4468L_SO8
PC123
4.7U_0805_6.3V6K
Rtop
<33> CHGVADJ
CHG_CHLIM
PR122
2.2_0603_1%
PR126
0_0603_5%
BST_CHG 1
CSOP
ISL6251AHAZ-T QSOP 24P
BATT+
3
PC101
10U_0805_25V6K
2
1
21
CSOP
PR125
@4.7_1206_5%
CELLS
D
PC114
@2200P_0402_25V7K
AON7408L_DFN8-5
CHG_N_001
CHG_N_006
PQ108
CSON
PR118
20_0603_5%
CHG_CSON 1
2
PC113
0.047U_0603_16V7K
CHG_CSOP 1
2
PR119
20_0603_5%
CHG_CSIN
2
1
PC118
PR120
0.1U_0603_25V7K
20_0603_5%
CHG_CSIP
1
2
5
6
7
8
PR127
226K_0402_1%
6251VREF 1
2
ACPRN
CSON
PR115
100K_0402_1%
1
2
PC102
10U_0805_25V6K
2
1
1
1
2
EN
DCIN
23
6251VREF
PC106
2200P_0402_25V7K
1
2
PC105
0.1U_0402_25V6
2
1
ACSET ACPRN
VIN
PC124
@680P_0603_50V7K
3
2
1
PR104
140K_0402_1%
24
PQ111
DTC115EUA_SC70-3
DCIN
ACOFF
VDD
PC112
1U_0603_25V6K
1
2
1
ACOFF
<33>
1
2
PC120
.1U_0402_16V7K
CHG_VADJ
IREF
<33>
ADP_I
PR110
47K_0402_1%
1
2
PR112
10K_0402_1%
PC120 must close EC pin.

PR103
<33,36>
150K_0402_1%
2
1
CHG_VCOMP
PR123 100_0402_1%
1
2CHG_ICM
0.01U_0402_25V7K
PC122
0.01U_0402_25V7K
2
1
PACIN
6.81K_0402_1%
2
10_1206_5%
PR105
18.2K_0402_1%
1
2
1
PR124
22K_0402_5%
1
2
6800P_0402_25V7K
CHG_ICOMP
2
PU101
8
7
6
5
CHG_N_005
PC116
1
PC117
PR121
1
2CHG_VCOMP1 1
PQ107B
SSM6N7002FU-2N_SOT363-6
PR113
6251_EN
PC110
1000P_0402_25V8J
3CHG_N_002
CHG_N_009
PQ107A
2
PD101
CHG_VIN 1
PC109
2.2U_0603_6.3V6K
2
1
1
PR116
150K_0402_1%
PC125
@10U_0805_25V6K
2
1
1
1
2
2
1
<33> FSTCHG
ACSETIN
RB751V-40TE17_SOD323-2
ACSETIN
PR114
10K_0402_1%
2
1
PR117
100K_0402_1%
CHG_N_001
PQ105
DTC115EUA_SC70-3
PR108
191K_0402_1%
1
2
6251VDD
CSIN
CHG_N_003
PQ103
AO4407AL_SO8
1
2
3
PC104
4.7U_0805_25V6-K
2
1
B+
CHG_B+
PL102
@HCB2012KF-121T50_0805
1
2
0.02_2512_1%
1
4
CSIP
PR107
200K_0402_1%
PC108
0.1U_0603_25V7K
PR109
47K_0402_1%
1CHG_N_010
PQ104
DTA144EUA_SC70-3
B+
PL103
1.2UH_1231AS-H-1R2N=P3_2.9A_30%
1
2
VIN
PC126 @10U_0805_25V6K
PC103
10U_0805_25V6K
2
1
1
2
3
8
7
6
5
P3
PQ102
S TR AO4409 1P SO8
1
8
2
7
3
6
5
PC107
5600P_0402_25V7K
1
2
VIN
P2
PR101
PQ101
AO4407AL_SO8
need change to 1206 size

since ME limit
PR106
31.6K_0402_1%
PR131
47K_0402_1%
ACIN
PR132
10K_0402_1%
<20,33>
PACIN
ACPRN
PQ112
2
B
Iada=0~4.737A(90W);CP=4.03A;where Racdet=0.020ohm,where Rtop=12.4K

90W for Dis:Rtop:SD00000AJ80
Iada=0~3.421A(65W);CP=2.91A;where Racdet=0.020ohm,where Rtop=226K
65W for UMA:Rtop:SD034226380
Astro2010_01_15 need confirm P/N
CP= 85%*Iada;
PR133
10K_0402_1%
1
2
6251VDD
PR136
20K_0402_1%
Add
E
MMBT3904W _SOT323-3
CP mode
Vaclim=VREF*(Rbot//Rinternal/(Rtop//Rinternal+Rbot//Rinternal))
when 90W Vaclim=2.39*(20K//152K/(20K//152K+12.4K//152K))=1.44966V
when 65W Vaclim=2.39*(20K//152K/(20K//152K+226K//152K))=0.38914V
Iinput=(1/Racdet)*((0.05*Vaclim/VREF+0.05))
when 90W,Iinput=(1/0.02)*(0.05*1.44966/2.39+0.05)=4.02A
when 65W,Iinput=(1/0.02)*(0.05*0.38914/2.39+0.05)=2.92A
CC=0.25A~3A
CHGVADJ=(Vcell-4)/0.10627
IREF=1.016*Icharge
Vcell
IREF=0.254V~3.048V
4V
VCHLIM need over 95mV
4.2V
CHGVADJ
Issued Date
Compal Secret Data
0V
1.882V
2010/05/17
Deciphered Date
2011/05/17
A
Title
CHARGER
Size
Document Number
Rev
1.0
NCL61 LA-6321P M/B

Date:

D
Sheet
37
of
45
2VREF_6182
VO2
VREG3
BOOT2
VO1
24
PGOOD
23
1
2
PC306
10U_0805_25V6K
PC312
2200P_0402_50V7K
2
1
ENTRIP1
PR307
105K_0402_1%
2
2
FB1
REF
B++
PQ305
AON7408L_DFN8-5
1
2
3
PR306
20K_0402_1%
2
ENTRIP1
P PAD
TONSEL
25
2
PU301
PC313
10U_0805_6.3V6M
PR305
30.9K_0402_1%
2
PQ303
AON7408L_DFN8-5
FB2
1
2
PC304
4.7U_0805_25V6-K
PC310
2200P_0402_50V7K
2
1
PR303
105K_0402_1%
1
FB_5V 1
ENTRIP2
+3VLP
2
PC309
0.1U_0402_25V6
2
1
LG_5V
EN
PR314
499K_0402_1%
2
18
17
PQ306
3
2
1
EN0
<36>
S IC RT8205EGQW WQFN 24P PWM
1
PC318
4.7U_0805_10V6K
PC305
150U_B2_6.3VM_R45M
PC320
@1U_0603_10V6K
1
2
PR315
95.3K_0402_1%
IRF8707GTRPBF_SO8
VL
<36>
16
POK
+5VALWP
PC317
680P_0603_50V7K
19
PR313
4.7_1206_5%
2
1
LGATE1
PL305
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
1
2
SNUB_5V
LGATE2
3
2
1
LX_5V
5
6
7
8
20
NC
PHASE1
VREG5
UG_5V
PHASE2
13
22
21
VIN
12
BOOT1
UGATE1
15
8
7
6
5
1
2
1
2
B++
AO4468L_SO8
1
2
3
150U_B2_6.3VM_R45M
LG_3V
4
SNUB_3V
11
PQ304
PC316
@680P_0603_50V7K
PR312
@4.7_1206_5%
1
PC303
LX_3V
PR309
PC315
2.2_0402_5%
0.1U_0402_10V7K
BST_5V 1
2 BST1_5V 1
2
UGATE2
GND
UG_3V 10
PL303
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
2
1
+3VALWP
BST_3V
SKIPSEL
PC314
PR308
0.1U_0402_10V7K
BST1_3V 1
1
2
2
0_0402_5%
14
FB_3V
ENTRIP2
PL301
HCB2012KF-121T50_0805
PR302
20K_0402_1%
1
2
B++
B+
PC311
0.1U_0402_25V6
2
1
PR301
13.7K_0402_1%
1
PC308
1U_0603_16V6K
B++
PQ307A
PQ307B
N_3_5V_001
5
4
PR317
100K_0402_5%
PR318
10K_0402_1%
1
2
PJP302
PJP305
1
+5VALWP
1
2
2
+5VALW
(4.5A,180mils ,Via NO.= 9)
+3VALW
(3A,120mils ,Via NO.= 6)
VL
PAD-OPEN 2x2m
+3VALWP
PJP301
PAD-OPEN 2x2m
EC:+3VL, reserve PR319, install PR318, PR320 100K

EC:+3VALW, reserve PR318, install PR319, PR320 40.2K
Compal Secret Data
2010/05/17
Issued Date
2011/05/17
Deciphered Date
A
PR319
100K_0402_1%
2
PC321
@0.01U_0402_16V7K
+5VL
VL
PQ308
DTC115EUA_SC70-3
2
1
PR320
40.2K_0402_1%
VS
PAD-OPEN 4x4m
PJP303
PAD-OPEN 4x4m
<36> VS_ON
+3VL
+3VLP
1
<28,33,34> EC_ON
PC319
0.1U_0603_25V7K
2VREF_6182
6 ENTRIP1
ENTRIP2
Title

3.3VALWP/5VALWP

Custom
Date:
Rev
1.0
PBL20 LA6772P M/B
Sheet
E
38
of
45
1
2
PC402
22U_0805_6.3VAM
PC404
22P_0402_50V8J
2
1
1
PR402
10K_0402_1%
PC401
22U_0805_6.3VAM
SY8033BDBC_DFN10_3X3
PR401
20K_0402_1%
2
1.8VSP_FB
<Vo=1.8V> VFB=0.6V
Vo=VFB*(1+PR401/PR402)=0.6*(1+20K/10K)=1.8V
+1.8VSP
NC
TP
PR405
@47K_0402_5%
11
EN_1.8VSP
PR404 0_0402_5%
FB
EN
PR403
4.7_1206_5%
LX
SVIN
PC405
@0.1U_0402_10V7K
<9,28,29,33,35,41,43> SUSP#
PL401
1UH_FMJ-0630T-1R0 HF_11A_20%
1
2
1.8VSP_LX
SNUB_1.8VSP
PVIN
PC406
680P_0603_50V7K
LX
NC
PVIN
PC403
22U_0805_6.3VAM
10
1.8VSP_VIN
PU401
HCB1608KF-121T30_0603
1
2
PG
PL402
+5VALW
PJP401
+1.8VSP
+1.8VS
(2A, 80mils, Via NO.= 4)
PAD-OPEN 3x3m
3
Issued Date
Compal Secret Data
2010/05/17
Deciphered Date
2011/05/17
A
Title
+1.8VSP
Size
Document Number
Rev
1.0
NCL61 LA-6321P M/B

Date:

D
Sheet
39
of
45
1.5V_B+
PR503
<29,33,35> SYSON
B+
PC505
@0.1U_0402_10V7K
1
2
1
2
PC507
0.1U_0402_25V6
2200P_0402_50V7K
PC506
PR504
2.2_0402_5%
BST_1.5V 1
2BST1_1.5V
PC504
4.7U_0805_25V6-K
PC503
10U_0805_25V6K
0_0402_5%
PL502
HCB1608KF-121T30_0603
2
1
EN_1.5V
PR502
2.15K_0402_1%
+5VALW
LG_1.5V
+5VALW
PR509
4.7_1206_5%
PC510
4.7U_0805_10V6K
PQ502
PC501
NC
3
2
1
LGATE
TRIP_1.5V 1
15K_0402_1%
4
RT8209BGQW _W QFN14_3P5X3P5
PC511
680P_0603_50V7K
3
2
1
IRF8707GTRPBF_SO8
220U_6.3V_M
PGOOD
11
10
PR508
CS
VDDP
+1.5VP
PL501
2.2UH_MMD-06CZ-2R2M-V1_8A_20%
1
2
5
6
7
8
FB
PHASE
LX_1.5V
14
15
VDD
UG_1.5V
1SNUB_1.5V
2.21K_0402_1%
PC509
4.7U_0603_10V6K
FB_1.5V
13
12
PQ501
AON7408L_DFN8-5
VOUT_1.5V
PR501
PGND
PR507
100_0402_1%
VOUT
UGATE
TON
GND
+5VALW 1
+5VALW
VOUT_1.5V
2
0_0402_5%
V5FILT_1.5V
+1.5VP
1
PR505
2
BOOT
EN/DEM
PU501
PR506
255K_0402_1%
1
2TON_1.5V
PC508
0.1U_0402_10V7K
PJP502
2
PAD-OPEN 4x4m
PJP501
+1.5VP
+1.5V
PAD-OPEN 4x4m
Compal Secret Data
2010/05/17
Issued Date
Deciphered Date
2011/05/17
5
Title

+1.5VP
Size
Document Number
Rev
1.0
PBL20 LA6772P M/B

Date:
Sheet
1
40
of
45
VCCP_B+
PR703
<9,28,29,33,35,39,43> SUSP#
PL702
HCB1608KF-121T30_0603
2
1
EN_VCCP
0_0402_5%
1
2
PC707
0.1U_0402_25V6
1
2
2200P_0402_50V7K
PC706
1
2
PC704
4.7U_0805_25V6-K
PC702
10U_0805_25V6K
PQ701
S TR AO4406AL 1N SO8
PR704
2.2_0402_5%
BST_VCCP1
2BST1_VCCP 1
5
6
7
8
PC705
@0.1U_0402_10V7K
B+
4
14
3
2
1
VDDP
LGATE
+5VALW
LG_VCCP
+5VALW
PR709
4.7_1206_5%
PQ702
S TR AO4726L 1N SO8
PC710
4.7U_0805_10V6K
4
PC711
680P_0603_50V7K
3
2
1
PC701
TRIP_VCCP1 PR708 2 13.7K_0402_1%
NC
BOOT
11
10
220U_D2_2VY_R15M
PR702
10.2K_0402_1%
CS
+VCCPP
PL701
0.68UH_FMJ-0630T-R68 HF_15.5A_20%
1
2
FB_VCCP1
15
PGOOD
PHASE
LX_VCCP
1SNUB_VCCP 2
4.12K_0402_1%
PC709
4.7U_0603_10V6K
FB
UG_VCCP
5
6
7
8
FB_VCCP 5
13
12
PR701
UGATE
VDD
PGND
PR707
100_0402_1%
VOUT
+5VALW 1
TON
GND
+5VALW
VOUT_VCCP
2
0_0402_5%
V5FILT_VCCP
+VCCPP
C
1
PR706
2
EN/DEM
PU701
PR705
255K_0402_1%
1
2TON_VCCP 2
PC708
0.1U_0402_10V7K
PR710
+3VS
PR711
0_0402_5%
VTTPW RGOOD <43>
10K_0402_1%
PR712
10_0402_5%
PJP701
2
PAD-OPEN 4x4m
VOUT_VCCP
PJP702
VCCIO_SENSE
+VCCPP
<8>
+1.05VS_VCCP
(8.5A,340mils ,Via NO.= 17)
PAD-OPEN 4x4m
PJP703
VSSIO_SENSE connect to GND directly.
2
PAD-OPEN 4x4m
Compal Secret Data
2010/05/17
Issued Date
Deciphered Date
2011/05/17
5
Title

PWR+1.05VSP/+VCCPP
Size
Document Number
Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
41
of
45
+1.5V
VIN
VCNTL
GND
NC
VREF
NC
VOUT
NC
TP
+3VALW
PR601
1K_0402_1%
2
PC601
4.7U_0805_6.3V6K
PU601
1
PC603
1U_0603_10V6K
G2992F1U_SO8
+0.75VSP
0_0402_5%
2
1
PC604
0.1U_0402_16V7K
PR602
1K_0402_1%
2
<5,35> SUSP
2
G
3
10.75VS_N_002
PQ602
SSM3K7002FU_SC70-3
PR604
2
VREF_G2992
PC605
10U_0805_6.3V6M
PC606
@0.1U_0402_10V7K
PJP601
+0.75VSP
+0.75VS
PAD-OPEN 3x3m
Compal Secret Data
Issued Date
2010/05/17
Deciphered Date
2011/05/17
5
Title

0.75VSP
Size
Document Number
Rev
1.0
PBL20 LA6772P M/B

Date:
Sheet

1
42
of
45
PR817
D
<41> VTTPWRGOOD
@0_0402_5%
VCCSA_B+
PR803
<9,28,29,33,35,39,41> SUSP#
0_0402_5%
B+
PL802
HCB1608KF-121T30_0603
2
1
EN_VCCSA
14
PR808
15K_0402_1%
TRIP_VCCSA
1
2
VDDP
LGATE
+5VALW
LG_VCCSA
+5VALW
PC809
4.7U_0805_10V6K
PQ802
IRF8707GTRPBF_SO8
4
PC806
0.1U_0402_25V6
1
2
2200P_0402_50V7K
PC805
PC810
680P_0603_50V7K
3
2
1
2
PR811
0_0402_5%
PR809
4.7_1206_5%
PR810
+3VS
3
2
1
11
10
15
NC
BOOT
CS
+VCCSAP
PL801
2.2UH_MMD-06CZ-2R2M-V1_8A_20%
1
2
220U_D2_2VY_R15M
PR802
30K_0402_1%
PHASE
LX_VCCSA
PC801
FB_VCCSA_1
PGOOD
UG_VCCSA
1SNUB_VCCSA 2
2K_0402_1%
PC808
4.7U_0603_10V6K
FB
13
12
5
6
7
8
FB_VCCSA5
UGATE
PR801
PC807
0.1U_0402_10V7K
VDD
PGND
PR807
100_0402_1%
VOUT
+5VALW 1
TON
+VCCSAP
+5VALW
VOUT_VCCSA
2
0_0402_5%
V5FILT_VCCSA
GND
PR805
255K_0402_1%
1
2TON_VCCSA 2
EN/DEM
PU801
PQ801
AON7408L_DFN8-5
4
PR804
2.2_0402_5%
BST_VCCSA
1
2BST1_VCCSA1
1
PR806
2
PC802
10U_0805_25V6K
PC804
@0.1U_0402_10V7K
SA_PGOOD <33>
10K_0402_1%
PR812
10_0402_5%
VOUT_VCCSA
PJP801
+VCCSAP
VCCSA_SENSE <9>
+VCCSA(6A,240mils ,Via NO.= 12)
2
PAD-OPEN 4x4m
+5VS
0_0402_5%
PC811
0.01U_0402_16V7K~D
PR816
15K_0402_1%
1 1
2
VID[0]
0
0
VID[1]
0
1
VCCSA Vout
0.9V
0.8V
FB_VCCSA
PR815
1
PR819
<9> VCCSA_SEL
PR814
2
1
10K_0402_5%
PQ804
PMBT2222A_SOT23-3
100K_0402_5%
PR813
10K_0402_5%
PQ803
SSM3K7002FU_SC70-3
PR818
10K_0402_5%
A
Compal Secret Data
2010/05/17
Issued Date
Deciphered Date
2011/05/17
5
Title

PWR+VCCSAP
Size
Document Number
Custom
Rev
1.0
PBL20 LA6772P M/B
Date:
Sheet
1
43
of
45
UGATE1
25
BOOT1
VGN1
VGN3
@100_0402_1%
PC230
.1U_0402_16V7K
1
2
PR220
590_0402_1%
PC273
@0.01U_0402_16V7K
PC234
@470P_0402_50V7K
PC240
2
3
2
1
PL203
@0.36UH_PCMC104T-R36MN1R15_30A_20%
1
4
PR229
2
1
@10K_0402_1%
LF3 2
+
2
PC219
1
100U_25V_M
+CPU_CORE
PR230
2
1ISEN1
@10K_0402_1%
V3N
ISEN3
B+
1
PC218
PC239
@0.1U_0402_25V6
2
1
PL205
HCB2012KF-121T50_0805
2
1
PL206
HCB2012KF-121T50_0805
2
1
100U_25V_M
CPU_B+
CPU_B+
PR232
VSUM+ 2
PR233
2
1ISEN2
@10K_0402_1%
1
@3.65K_0805_1%
VSUM-
PR238
1
@1_0402_5%
CPU_B+
PQ204
UGATE2
PC247
0.1U_0402_25V6
2
1
PHASE1
10KB_0603_5%_ERTJ1VR103J
2
11K_0402_1%
2
1 PR214
ISNG
4
0_0402_5%
1U_0603_10V6K
PC243
2
1
LGATE1
26
PC238
@2200P_0402_50V7K
2
1
PR228
1CPU_SNUB3
2
1
@4.7_1206_5%
LGATE3
@S TR AON6788 1N DFN
28
27
ISPG
PC232
2
3
2
1
+5VALW
1 PR234
PWM3_CPU
29
@680P_0603_50V7K
PQ208
PR231
0_0402_5%
1
2
VGN2 1
1 PR212
@RJK03B9DPA-00-J53_WPAK8-5
VDDP_CPU
30
PQ211
S TR TPCA8057
2BOOT3_1
1
@0.22U_0603_10V7K
7
4
PR227
LGATE2
31
PH202
PR210
1
7.5K_0402_1%
PR208
1_0402_5%
PC224 .1U_0402_16V7K
10K_0603_1%
PHASE3
33
32
PQ207
PC209
@10U_0805_25V6K
2
1
PC210
@10U_0805_25V6K
2
1
1PWM3_CPU1
PHASE2
LGATE
UGATE3
@ISL6208CRZ-T_QFN8
@0_0603_5%
34
GND
1
8
+VGFX_CORE
VGN
CPU_B+
1U_0603_10V6K
PROG1
UGATE2
BOOT
PWM PHASE
24
VIN
BOOT1
23
VDD
22
ISUMP
ISUMN
RTN
NTC_CPU
21
VW
BOOT2
35
PC237
FCCM UGATE
PH1
UG1
36
BOOT3
1
PC233
2
37
LGG
VR_HOT#
VCC
PC242
1
39
38
PHG
BOOTG
UGG
40
42
41
PROG2
43
ISNG
NTCG
45
44
ISPG
RTNG
VSENG
FBG
46
47
48
VSSP1
NTC
@1U_0603_10V6K
2
1
@0_0603_5%
FCCM_CPU
LGATEG
PHASEG
UGATEG
2
1
PR222
@16.5K_0402_1%
BOOTG
@10K_0402_5%
NTCG
ISNG
ISPG
PR207
PC205
10U_0805_25V6K
2
1
PC206
10U_0805_25V6K
2
1
47P_0402_50V8J
1
PC246
1
@470P_0402_50V7KPH203
2CPU_N_001 1
2
LG1
ISL95831CRZ-T_TQFN48_6X6
IMON
20
2
PR240
PWM3
PU201
PGOOD
13
PC245
PR239
1
2
499_0402_1%
VR_ON
19
12
VDDP
VSEN
11
<14,20,33>
LG2
SCLK
ISEN1
10
1.91K_0402_1%
ALERT#
18
VSSP2
17
SDA
ISEN2
PH2
16
BOOT2
PR221
2
1
@2.2_0603_5%
PU202
PGOODG
ISEN3/ FB2
VGATE
PR219
UG2
15
VR_SVID_CLK
VRON_CPU
0_0402_5%
+3VS
VR_SVID_ALRT#
PR236
1
GND
49
1 PR235
VR_ON
+5VALW
IMONG
FB
VR_SVID_DAT
VWG
COMP
COMPG
14
1
PC241
2
0.047U_0603_16V7K
26.7K_0402_1%
PR270
2
1
VWG 1
PR226
2
10K_0402_1%
GFX_CORE_PWEGD
Alert# PU resister need close CPU,

so the PU resister in HW schematic.
but DAT and CLK need close PWM-IC,
so the PU resister in POWER schematic.
<33>
FBG
COMPG
2
1
54.9_0402_1%
PR224
2
1
130_0402_1%
PR223
<33>
PROG2_GFX
2
PR218
1
PC235
2
0.047U_0603_16V7K
@.1U_0402_16V7K
1
2
<8> VR_SVID_CLK
<33,36> VR_HOT#
PR217
2
1
10_0402_1%
+3VS
<8> VR_SVID_ALRT#
+1.05VS_VCCP
0.22U_0603_10V7K
LGATEG
+5VALW
<8> VR_SVID_DAT
<33> IMVP_IMON
<9>
<9>
LFG2
PR206
1GFX_SNUB 2
1
4.7_1206_5%
680P_0603_50V7K
0.01U_0402_16V7K
+1.05VS_VCCP
VSSSENSE
1BOOTG_1
2.2_0603_5%
VCC_AXG_SENSE
VSS_AXG_SENSE
330P_0402_50V7K
PC229
2
1
PC236
PC222
2
1
3
2
1
1
PC227
1
PC228
2
BOOTG 2 PR205
2
1
10_0402_1%
PC225
1
2
PL204
0.36UH_PCMC104T-R36MN1R15_30A_20%
1
4
S TR AON6428L 1N DFN-8
PHASEG
IMONG
16.2K_0402_1%
PR237
2
1
VSS_AXG_SENSE
+VGFX_CORE
PR209
680P_0402_50V7K
PR216
2
1
2.55K_0402_1%
PC231
PR215
1GFX_N_0022
1
475K_0402_1%
150P_0402_50V8J
PQ210
27.4K_0402_1%
PR213
2
1GFX_N_001
422_0402_1%
2 470KB_0402_5%_ERTJ0EV474J
PC272
0.1U_0402_25V6
2
1
UGATEG
330P_0402_50V7K
39P_0402_50V7K
2
1
PH204
1
PR204
1
3
2
1
1
2
PR211
GFX_N_003
PC226
@499K_0402_1%
2
1
3.83K_0402_1%
1000P_0402_50V7K
PC223
2
PR201
8.06K_0402_1%
PR203
PC271
2200P_0402_50V7K
2
1
NTCG
@470P_0402_50V7K
CPU_B+
PC244
2200P_0402_50V7K
2
1
2K_0402_1%
PC215
10U_0805_25V6K
2
1
330P_0402_50V7K
CPU_B+
PC221
2
1
PC214
10U_0805_25V6K
2
1
PR271
PC276
2
1
3.83K_0402_1%
1
3
2
1
V2N
ISEN1
PR252
2
1 ISEN3
@10K_0402_1%
PR255
VSUM-
1
1_0402_5%
VSUM-
PC262
0.1U_0402_25V6
2
1
TPC8065_SO8
PL201
0.36UH_PCMC104T-R36MN1R15_30A_20%
1
4
PHASE1
PR264
BOOT1
2
2.2_0603_5%
PC269
1BOOT1_1 2
1
PQ202
0.22U_0603_10V7K
LGATE1
3
2
1
S TR TPCA8059-H 1N PPAK56-8
ISEN1
PR265
1
10K_0402_1%
VSUM+
PR267
1
3.65K_0805_1%
PC270
2
LF1
+CPU_CORE
3
V1N
@100_0402_1%
PR250
2
1
10K_0402_1%
PR251
VSUM+ 2
1
3.65K_0805_1%
PC261
2200P_0402_50V7K
2
1
PR263
1CPU_SNUB1 2
1
4.7_1206_5%
680P_0603_50V7K
+CPU_CORE
PR249
2
1
10K_0402_1%
ISEN2
PC254
2
PC201
10U_0805_25V6K
2
1
PC202
10U_0805_25V6K
2
1
UGATE1
PR262
PR246
1CPU_SNUB2 2
1
4.7_1206_5%
680P_0603_50V7K
5
3
2
1
5
10KB_0603_5%_ERTJ1VR103J
PR256
1CPU_N_004 2
2.61K_0402_1%
1
@330P_0402_50V7K
PR261
2
1
1.47K_0402_1%
PC267
2
1 CPU_N_003 2
PQ201
PC266
0.01U_0402_16V7K
LF2 2
CPU_B+
PH201
PC268
2
.1U_0402_16V7K
<8> VSSSENSE
0.068U_0402_16V7K
PR259
2
1
11K_0402_1%
<8> VCCSENSE
LGATE2
VSUM+
PC260
2
2K_0402_1%
+5VALW
0.22U_0603_10V7K
316K_0402_1%
PC263
2
1
330P_0402_50V7K
PQ205
0.22U_0603_10V7K
1
PC258
2
1
0.22U_0603_10V7K
PC249
1BOOT2_1 2
1
S TR TPCA8059-H 1N PPAK56-8
1
3.32K_0402_1%
PR260
2
BOOT2 2
2.2_0603_5%
VIN_CPU
VDD_CPU
PC253
1
ISUMN_CPU
1
0.22U_0603_10V7K
470P_0402_50V7K
1
@0.22U_0603_10V7K
PC265
2
PC275
1
470P_0402_50V7K
PR258
2
PC257
2
PL202
0.36UH_PCMC104T-R36MN1R15_30A_20%
1
4
1_0603_5%
150P_0402_50V8J
2
499_0402_1%
VSUM-
PR247
PR248
0.1U_0402_16V7K
PC274
2
1
33P_0402_50V8J
PC259
PR257
1CPU_N_002 2
1
PC256
1
TPC8065_SO8
PHASE2
PR244
0_0402_5%
CPU_B+
0_0603_5%
PC264
2
1FB1_CPU 2
0.22U_0603_16V7K
@499K_0402_1%
PR254
330P_0402_50V7K
PC255
2
1
1U_0603_10V6K
PC251
2
1
PR253
PR243
PC252
2
ISEN1
FB_CPU
ISEN2
PC250 10P_0402_50V8J
2
1
COMP_CPU
3
2
1
PROG1_CPU
ISEN3
1
PC248
2
470KB_0402_5%_ERTJ0EV474J
PR242 1
27.4K_0402_1%
VW_CPU
1000P_0402_50V7K
1
2
PR245
8.06K_0402_1%
PR266
1 ISEN2
10K_0402_1%
PR268
2
1 ISEN3
@10K_0402_1%
PR269
VSUM-
1
1_0402_5%
Compal Secret Data
Issued Date
2010/05/17
Deciphered Date
2011/05/17
Title
PWR-CPU_CORE
Size
C
Date:

Document Number
Rev
1.0
PBL20 LA6772P M/B

1
Sheet
44
of
45
PIR (Product Improve Record)

PBL20 LA-6772P SCHEMATIC CHANGE LIST
REVISION CHANGE:
Revision Change: 0.1 to 0.2

NO DATE PAGE MODIFICATION LIST
PURPOSE
----------------------------------------------------------------------------------------D
08/03
17
DELETE U47, C869, R1530 and R572
For HDMI detect issue
08/03
17
Change R573 to 20K
For HDMI detect issue
08/03
31
Change RA16 to 39.2K
For Headphone detect issue
08/03
15
DELETE L25, C320 and C401
For cost down
08/04
31
Add RA19
For Headphone detect issue
08/20
For remove XDP connector
08/20
Delete R61, R63, R206, R257, R208, R261, R259 and

C16
Add C233 and C232
08/20
15
Delete L25, C401 and C320
For cost down
08/20
17
Delete U10, R405, R407, R410, R705, R409, R408,

R406, R411, R403, R404, R402, R221, R253, R254
, R412, R413, R414 and R222
Remove level shift for cost down
10
08/20
19
Add C499 and C500
For add new card function
11
08/20
19
Delete R258 and R260
For remove XDP connector
12
08/20
23
Add R425
ODD_EN# pull-up 10K to +3VS
13
08/20
28
Add R303, R46 and R61
For SPI and ME ROM
14
08/20
29
Add JSMART connector
For add smart card connector
15
08/20
29
Add JNEW
For add new card connector
16
08/20
29
Add R127 ,R28 and R129
For support intel W/L
17
08/20
29
Add R132, R133, R136, R137, R130 and R131
For SW GPIO common
18
08/20
33
Delete X1, C751 and C752
For cost down
19
08/20
34
Add D20
For ESD issue
For DDR3 1333 EMI issue

PURPOSE
-----------------------------------------------------------------------------------------
09/01
34
Add R515
PWR_USB_EN# pull-up 10K to +3VALW
09/01
Add C16
FOR ESD issue
09/02
35
Add C880, C889, C890, C881, C882, C883, C879, C884

,C885, C886, C887 and C888
FOR ESD issue
10/06
34
Add D25
For USB issue
10/11
18
Add R172
For Power Saving
10/14
27
Add R835 and R836
For smart card with ODD
10/14
29
Add R837 and R838
For smart card with ODD
10/18
30
Add D6 and D7
For ESD issue
10/20
33
Add R743
For common design
10
10/20
22
Add R318
For add TPM 1.2
11
10/20
28
Add C764, C765, U37, R733, R726, R659, R662, R661,

R665, R772, R669, C768, R668, C766, C767 and Y4
For add TPM 1.2

PURPOSE
----------------------------------------------------------------------------------------1
12/01
29
Change JNEW conn.
For ME
12/03
33
Add R117, R749 and R750
For EC
12/01
29
Add D22
For USB power switch issue
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
5
Title
HW-PIR
Size
Document Number
Rev
1.0
PBL20 LA6772P M/B

Date:
Sheet
1
45
of
45

17bf5 COMPAL LA-6772P PDF

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5

LA-6772P REV 1.0 Schematic

Intel Sandy Bridge/Cougar Point(UMA)

Compal Electronics, Inc.

Compal Secret Data

PBL20 LA6772P M/B

Tuesday, December 07, 2010

CPU Dual Core

1.5V DDRIII 1066/1333

USB/B Right USB/B Left

USB port 0,1

Intel Cougar Point

DC/DC Interface CKT.

Power Circuit DC/DC

Compal Electronics, Inc.

Compal Secret Data

PBL20 LA6772P M/B

Tuesday, December 07, 2010

Compal Electronics, Inc.

Compal Secret Data

PBL20 LA6772P M/B

Tuesday, December 07, 2010

Battery power supply (12.6V)

AC or battery power rail for power circuit.

Core voltage for CPU

Core voltage for GPU

Core voltage for UMA graphic

+0.75VP to +0.75VS switched power rail for DDR terminator

+1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU

+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU

+1.05VS_VCCP to +1.05VS_PCH power for PCH

+1.5VP to +1.5V power rail for DDRIII

+1.5V to +1.5VS switched power rail

+1.5VS to +1.5VSDGPU switched power rail for GPU

(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU

+3VALW always on power rail

+3VALW always to KBC

+3VALW to +3V_LAN power rail for LAN

+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)

+3VALW to +3VS power rail

+5VALWP to +5VALW power rail

+5VALW to +5VALW_PCH power rail for PCH (Short resister)

+5VALW to +5VS switched power rail

+VSBP to +VSB always on power rail for sequence control

PCH SM Bus address

Clock Generator (9LVS3199AKLFT,

Compal Secret Data

Compal Electronics, Inc.

Size Document Number

PBL20 LA6772P M/B

Tuesday, December 07, 2010

JTAG & BPM

PU/PD for JTAG signals

DDR3 Compensation Signals

Buffered reset to CPU

Compal Secret Data

FAN Control Circuit

Compal Electronics, Inc.

Size Document Number

PBL20 LA6772P M/B

Tuesday, December 07, 2010

eDP_COMPIO and ICOMPO signals