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Full adder VHDL code

File 1 -library IEEE;


use IEEE.STD_LOGIC_1164.ALL;

entity full_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
s : out STD_LOGIC;
cout : out STD_LOGIC);
signal p,q,r : STD_LOGIC;
end full_adder;
architecture Heimdall of full_adder is
component half_adder is
port(x,y: IN STD_LOGIC;
w,v: OUT STD_LOGIC);
end component;
component OR_gate is
port(x1,y1: IN STD_LOGIC;
w1: OUT STD_LOGIC);
end component;
begin
L1: half_adder port map(a,b,p,q);
L2: half_adder port map(cin,p,s,r);
L3: OR_gate port map(r,q,cout);
end Heimdall;
File 2 (HA) -library IEEE;
use IEEE.std_logic_1164.all;
entity half_adder is
port (x,y : in STD_LOGIC;
w,v : out STD_LOGIC);
end half_adder;
architecture dataflow of half_adder is
begin
w <= (x xor y);
v <= (x and y);
end dataflow;
File 3 (OR) -library IEEE;
use IEEE.std_logic_1164.all;

entity OR_gate is
port (x1,y1 : in STD_LOGIC;
w1: out STD_LOGIC);
end OR_gate;
architecture dataflow of OR_gate is
begin
w1<= x1 OR y1;
end dataflow;
-- Full Subtractor VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Full_sub is
Port ( A : in STD_LOGIC;
E : in STD_LOGIC;
F : in STD_LOGIC;
D : out STD_LOGIC;
B : out STD_LOGIC);
end Full_sub;
architecture Ultron of Full_sub is
begin

D <= A XOR E XOR F;


B <= (((NOT A) AND E) OR ((NOT E) AND F) OR ((NOT F) AND A));

end Ultron;
-- Half Subtractor VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity half_sub is
Port ( A : in STD_LOGIC;
C : in STD_LOGIC;
D : out STD_LOGIC;
B : out STD_LOGIC);
end half_sub;
architecture spock of half_sub is
begin

D <= A XOR C;
B <= (NOT A)AND C;

end spock;

-- Decoder VHDL Code


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Decoder is
Port ( D : in STD_LOGIC_VECTOR (1 downto 0);

end Decoder;

Z : out STD_LOGIC_VECTOR (3 DOWNTO 0));

architecture Hawkeye of Decoder is


begin

with D select
z <= "1000" when "00",
"0100" when "01",
"0010" when "10",
"0001" when others;

end Hawkeye;
-- Multiplexer VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux is
Port ( w : in STD_LOGIC_VECTOR (0 TO 3);
s : in STD_LOGIC_VECTOR (0 TO 1);
y : out STD_LOGIC);
end mux;
architecture Thor of mux is
begin y <= w(0) when s = "00" else
w(1) when s="01" else
w(2) when s="10" else
w(3) when s="11";
end Thor;
-- serial-in-parallel-out Shift register
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SIPO is
Port ( clk : in STD_LOGIC;
si : in STD_LOGIC;
po : inout STD_LOGIC_VECTOR(7 downto 0));

end SIPO;
architecture Odin of SIPO is
begin

process(clk)
begin

if (clk='1' and clk'event)then


po(7 downto 1) <= po(6 downto 0);
po(0) <= si;
end if;

end process;
end Odin;

-- Universal Shift Register VHDL Code


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity universal_sr is
Port ( din : in STD_LOGIC_VECTOR (3 downto 0);
SIR : in STD_LOGIC;
SIL : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (1 downto 0);
dout : inout STD_LOGIC_VECTOR (3 downto 0));
end universal_sr;
architecture Heimdall of universal_sr is
begin
process(clk,rst,s)
begin
if rst='1' then
dout <= "0000";
elsif (clk'event and clk='1') then
case s is
when "00" => dout <= dout;
when "01" => dout <= SIR & dout(3 downto 1);
when "10" => dout <= dout (2 downto 0) & SIL;
when "11" => dout <= din;
when others => null;
end case;
end if;
end process;
end Heimdall;

-- Mealy machine VHDL Code


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mealy is
Port ( w : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
z : out STD_LOGIC);
end mealy;
architecture Tesseract of mealy is
type state_type is (a,b,c,d);
signal y : state_type;
begin
process(clk,rst)
begin
if rst = '0' then
y <= a;
elsif clk'event and clk = '1' then
case y is
when a =>
if w = '0' then y <= a;
else y <= b;
end if;
when b =>
if w = '0' then y <= c;
else y <= b;
end if;
when c =>
if w = '0' then y <= a;
else y <= d;
end if;
when d =>
if w = '0' then y <= c;
else y <= b;
end if;
end case;
end if;
end process;
process(y,w)
begin
case y is
when a => z <= '0';
when b => z <= '0';
when c => z <= '0';
when d => z <= w;
end case;

end process;
end Tesseract;
-- Moore Machine VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity moore is
Port ( w : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
z : out STD_LOGIC);
end moore;
architecture Mjolnir of moore is
type state_type is (A,B,C);
signal y: state_type;
begin
process(clk,rst)
begin
if rst = '0' then
y <= A;
elsif clk' event and clk = '1' then
case y is
when a =>
if w = '0' then y <= a;
else y <= b;
end if;
when b =>
if w = '0' then
y <= a;
else y <= c;
end if;
when c =>
if w = '0' then
y <= a;
else y <= c;
end if;
end case;
end if;
end process;
z <= '1' when y = c else '0';
end Mjolnir;