Final Year Report

ROBOTIC ARM CONTROL THROUGH FPGA
PROJECT REPORT
Design &Design
Implementation
of FPGA Based
& Implementation of FPGA
Robotic
ArmArm
Control
Based Robotic
Control
PROJECT ADVISOR
ENGR. TAUHEED-UR-REHMAN
PROJECT TEAM
MUHAMMAD MAJID ALTAF
2006-EE-04
MUHAMMAD WAQAS BASHIR
2006-EE-10
MEHRAN ZAFAR
2006-EE-24
SESSION
2006-2010
DEPARTMENT OF ELECTRICAL ENGINEERING

UNIVERSITY COLLEGE OF ENGINEERING AND TECHNOLOGY
BAHAUDDIN ZAKARIYA UNIVERSITY MULTAN
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PROJECT REPORT
A thesis submitted in partial fulfillment of the requirement of the Degree of
Design & Implementation of FPGA Based

Engineering and Technology
Bahauddin
Zakariya
University Multan.
Robotic
Arm
Control
Bachelor of Science in Electrical Engineering from University College of
PROJECT TEAM
MUHAMMAD MAJID ALTAF
2006-EE-04
MUHAMMAD WAQAS BASHIR
2006-EE-10
MEHRAN ZAFAR
2006-EE-24
INTERNAL EXAMINER
__________________________________
Engr. Tauheed-ur-Rehman
Lecturer EED, UCE&T BZU, Multan
H.O.D.
__________________________________
Engr. Nek Muhammad
EXTERNAL EXAMINER ___________________________________

Engr. Abdul Manan
Assistant Professor
EED, NFC IET Multan
DEPARTMENT OF ELECTRICAL ENGINEERING

UNIVERSITY COLLEGE OF ENGINEERING AND TECHNOLOGY
BAHAUDDIN ZAKARIYA UNIVERSITY MULTAN
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PROJECT REPORT
To
Our beloved Parents, Teachers &
Friends
For their patience and understanding
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PROJECT REPORT
DECLARATION
We declare that the data in this Robotic arm controlling through FPGA report is not
our work only; it is pirated to some extent.
It is our own effort and hard work, no other person helps us in collecting data for
this Robotic arm controlling through FPGA report.
This report is not copied from any other report, but the motivation was given by my
honored teacher
Engr. TAUHEED-UR-REHMAN.
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PROJECT REPORT
ACKNOWLEDGEMENT
The whole praise to almighty ALLAH, Creator of the universe, who made us the
Super Creature, blessed us with Knowledge and able to Accomplish the Work.
We are indebted to our class fellows and friends who have helped, inspired, and
given moral support and encouragement, in various ways, in completing this task.
I owe a special debt to my honored and respected Teacher Engr. TAUHEEDUR-REHMAN for his support, sacrifices, patience, understanding and
encouragement during the completion of this Feasibility Report. We also thanks to
ENGR. ADIL BASHIR whose guidance was always a source of encouragement
for us.
We are pleased to acknowledge the helpful comments and suggestions provided
by faculty of
Electrical Engineering Department.

Our eternal gratitude goes to our parents for their love, support, inspiration, and
dedication.
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PROJECT REPORT
ABSTRACT
A robotic arm is a robotic manipulator, usually programmable, with

similar functions to a human arm. The links of such a manipulator are connected
by joints allowing either rotational motion (such as in an articulated robot) or
translational (linear) displacement. The links of the manipulator can be considered
to form a kinematic chain. The business end of the kinematic chain of the
manipulator is called the end effector and it is analogous to the human hand. It has
a lot of applications in industries like automobile industries, where end effectors
of the robotic arm can be designed to perform any designed tasks such as welding
gripping spinning and pick and drop, and in space it has application of supporting
the astronauts just like CANADARM and CANADARM2 robotic arms being
used now a days.
These robotic arms have two types of controls.
Manual control.
Automatic control.
To implement both the controls a controller is normally used. This controller
can be a microcontroller or programmable logic devices like FPGAs. If multiple
robots are to be controlled by a single controller at a time then FPGAs are best
suited for this kind of applications. Because it has more i/os then a controller and
it allows the parallel processing. These FPGAs are programmed by hardware
descriptive languages (VHDL) to implement any control logic. Moreover FPGAs
allows the instant redesign of logic and instant reprogramming.
Manual control of the robotic arm through the FPGAs requires external
control circuit consisting of buttons of switches to operate the robotic arm. This
complexity of this control circuit depends on the application and degree of
freedom. For applications like pick and drop it may consists of switches or push
buttons.
Automatic control only requires proper coding. It does not require external
circuit. Only proper interfacing is required. That is provided through optocouplers.
So the combination of all these , the FPGA, the robotic arm, the control and
interface circuits and the HDL produces an effective and efficient robot to do a
particular job and provides batter efficiency than a worker. And this is all what we
tried to design and implement in our project.
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PROJECT REPORT
LIST OF FIGURES
Figure 1-1 Robotic Arm
Figure 1-2 Basic Robot Parts
Figure 1-3 Application of Robots in Space
Figure 1-4 Robotics in Bomb Disposal
Figure 2- 1 Robot Links
13
Figure 2- 2 Two Dimensional Robot Workspace
15
Figure 2- 3 Three Dimensional Robot Workspace
15
Figure 3- 1 FPGA Insight
20
Figure 3- 2 FPGA vs ASIC/Custom Microprocessor Design
22
Figure 4- 1 Servo Motor Block Diagram
27
Figure 4- 2 Components of a Servo Motor
27
Figure 4- 3 Servo Motor Pulse vs Position
28
Figure 4- 4 Performance Characteristics of Servo Motor
29
Figure 4- 5 DC Servo Motor with Position Control System
30
Figure 4-6 Structure of PAL & PLA
33
Figure 4- 7 Structure of CPLD
33
Figure 4- 8 FPGA types w.r.t. their Memory
35
Figure 4- 9 EPROM Memory Cell
36
Figure 4- 10 EEPROM Memory Cell
36
Figure 4- 11 SRAM Based Memory Cell
37
Figure 4- 12 FPGA Architecture
39
Figure 4- 13 Row Based Architecture
40
Figure 4- 14 Hierarchical PLDs
41
Figure 4- 15 XILINX Logic Block
41
Figure 4- 16 LUT Architecture
42
Figure 4- 17 Logic Pin Block Location
42
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PROJECT REPORT
Figure 4- 18 Logic Block Pin to Routing Channel Interconnect
43
Figure 4- 19 Un-segmented FPGA Routing
43
Figure 4- 20 Switch Bus Topology
44
Figure 4- 21 Programmable logic design process
46
Figure 4- 22 VHDL Evolution & Progress
52
Figure 4- 23VHDL Sample Code
54
Figure 4- 24 VHDL Levels of Abstraction
55
Figure 4- 25 VHDL Design Methodology
56
Figure 5-1 SPARTAN-3A FPGA
59
Figure 5- 2 FPGA Slide Switches
62
Figure 5- 3 FPGA Push Buttons
62
Figure 5- 4 Push Button Switch Internal Diagram
63
63
Figure 5- 5 FPGA Differential I/O Connector Pins
64
Figure 5- 6 FPGA I/O Pins
64
Figure 5- 7 4N25 Connection Diagram
65
Figure 5- 8 FPGA Interface using 4N25
66
Figure 5- 9 Input and Output Pulses
66
Figure 5- 10 Input out pulses after changing code
67
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PROJECT REPORT
TABLE OF CONTENTS
Chapter 1
ABSTRACT
vi
LIST OF FIGURES
vii
Introduction to Robotics
1.1
Robotics
1.2
Robotics Terminology
1.3
Need for Robotics
1.4
History of Robotics
1.5
Robotics Kinematics
1.5.1
Open Chain Kinematics
1.5.2
Closed Chain Kinematics
1.5.3
Direct vs Indirect Kinematics
1.6
Types of Robots By Locomotion and Kinematics
1.7
Robotic Arm
1.8
Robotic Parts
1.9
Robot Power Sources/ Sensors

1.9.1 The Robot Drive System
6
6
1.10
1.11
Applications
1.10.1 Space Application of Robotic Arm
1.10.2 Bomb Disposal Applications of Robotic Arm
Robotics Future
8
8
9
10
1.12
The Main Challenges for Intelligent Robotics
11
1.9.2
Chapter 2
Robot Sensors
Robot Terminologies
12
Page ix
2.1
Chapter 3
3.1
3.2
3.3
3.4
Chapter 4
4.1
PROJECT REPORT
Robot Terminologies
12
Implementation Plan for Robotic Arm
16
Selection Of Motor for Project
16
3.1.1
Comparison Servo/Stepper Motor
17
3.1.2
Stepper Motor Disadvantages i n Robotics
18
3.1.3
Why we Select Servo Motors?
18
Control Mechanism
18
3.2.1
War Between FPGA and Micro Controller
18
3.2.2
War Between Micro Processor and FPGA
19
3.2.3
War Between CPLD And FPGA
19
A Gateway to FPGA
20
3.3.1
Critical Analysis About FPGA Selection
20
3.3.2
Final Conclusion
22
Modeling Language
22
3.4.1
Languages Used for FPGA Programming
23
3.4.2
Advantage of HDL
23
3.4.3
Why Preferred VHDL Over Verilog HDL? 24
Hardware Description
Servo Motors
26
26
4.1.1 What is Servo Motor?
26
4.1.2 How Does the Servo Work?
27
4.1.3 Construction
27
4.1.4 Pulse Width and Position
28
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4.2
4.3
PROJECT REPORT
4.1.5 Requirement for Good Servomotor
28
4.1.6 Color Convention
29
4.1.7 Position Control System
29
What Is FPGA?
30
4.2.1 FPGA or Microprocessor/Controller?
31
4.2.2 Evaluation of FPGA
32
4.2.3 Technology Background of FPGA
34
4.2.4 FPGA Architecture
39
4.2.5 FPGA Structural Classification
39
4.2.6 Xilinx Logic Block
41
4.2.7 RAM Blocks
44
4.2.8 FPGA Design Flow
45
4.2.9 FPGA Download Cables
47
4.2.10 FPGA Configuration
48
What is VHDL?
4.3.1 A Brief History of VHDL
50
51
4.3.2 Structure of VHDL & Design Description 52
4.4
Chapter 5
4.3.3 Levels of Abstraction
54
4.3.4 Design Methodology
55
4.3.5 Languages Under Development
57
Software Used for FPGA Programming
57
Hardware Implementation
58
5.1
Xilinx FPGA (Spartan 3A)
58
5.2
Servo Motor
59
5.2.1 HS-805 BB Servo
60
5.2.2 HS-645 Mg Servo
60
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5.2.3 HS-475HB Servo

5.3
Hardware Design
PROJECT REPORT
60
61
5.3.1 Input to FPGA
61
5.3.2 Output form FPGA
64
5.4
Level Shifting or Isolation
65
5.5
Robotic Arm Interface
67
Future Developments
68
APPENDIX A
69
APPENDIX B
76
REFRENCES
79
Chapter 6
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PROJECT REPORT
CHAPTER 1
INTRODUCTI`ON TO ROBOTICS
1.1 Robotics
Robotics is the branch of technology that deals with the design, construction,
operation, structural disposition, manufacture and application of robots. Technically
defining robot is a reprogrammable multi functional manipulator designed to do
functions generally assigned to human beings i.e., moving objects from one place to
another, repairing parts, tools etc. through programmed motions so that the robots
perform a variety of tasks. Precisely speaking robots are general purpose
reprogrammable workers with inbuilt sensors that perform various assembly tasks.
Robotics brings together several very different engineering areas and skills.
There is metalworking for the body. There is mechanics for mounting the wheels on
the axles, connecting them to the motors and keeping the body in balance. You need
electronics to power the motors and connect the sensors to the controllers. At last
you need the software to understand the sensors and drive the robot.
1.2 Robotics Terminology
Isaac Asimov popularized the term robotics; robots do not threaten humans since
Asimov invented the three laws of robotics:
1) A robot may not harm a human or, through inaction, allow a human to come to
harm.
2) A robot must obey the orders given by human beings, except when such orders
conflict with the First Law.
3) A robot must protect its own existence as long as it does not conflict with the First
or Second Laws.
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PROJECT REPORT
1.3 Need for Robotics

As the proverb goes Necessity is the mother of Invention, Human beings
always thought of bringing in technology in every walk of life to make things
work better for them without any hard work. Man always tried to bring changes
according to the circumstances for his easy living. For example the Industrial
Revolution completely changed the face of the world. Technology took the
Industries by storm. The world saw the Automatic machines remove the problems
of man power. The concept of Robots or say the reprogrammable workers came
into the minds of human beings to save time and get the desired levels of
production within the stipulated time frame with minimum errors. That caused the
world to introduce the labors driven with technology. Their requirement is
basically to eliminate the need of high cost, specialized equipment in the
manufacturing industries.
1.4 History Of Robotics
The notion of robots or robot-like automates can be traced back to
medieval times. Though the people of that era didnt have a term to describe what
we would. In medieval times, automatons, human-like figures run by hidden
mechanisms, were used to impress peasant worshippers in church into believing in a
higher power. In the 18th century, miniature automatons became popular as toys for
the very rich. They were made to look and move like humans or small animals.
In 1921, Karel Capek, a Czech playwright, name up with an intelligent,
artificially created person, which he called robot. While the concept of a robot has
been around for a very long time, it wasnt until the 1940s that the modern day
robot was born, with the arrival of computers.
After the advent of Mechanization & Automation in the technical world,
many researches were carried out to develop solutions for the problems in the
Industry. The Industrial World saw many innovative engineering solutions to reduce
the creeping errors in the technology. And then began the Age of Robots with the
demonstration of first manipulator with playback memory by George Devol in
1954.The device could exhibit point-to-point motions (repeat the actions as
programmed by the users). Five years later the Industrial Robot was designed by
Unimation Incorporation. Early 1960s saw the development of walking machines
using the same playback memory feature backed by Servo Controlled technology.
This machine was developed by General Electric with the funding provided by
Department of Defense.
The first autonomous walking machine was developed at Ohio state
university in the year 1985.This machine was loaded with 80 sensors, 17 on board
single board computers and a 900 c.c. motorcycle engine rated a 50 KW or 70 hp.
This model was created as Adaptive Suspension Vehicle (ASV) designed to operate
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PROJECT REPORT
in rough terrain that is not navigable by conventional vehicles. Robotics was

revolutionized by Honda when it demonstrated the Honda Humanoid Robot in
1996. This model had 2 legs & 2 arms designed for use in a typical domestic
environment. It is equipped with cameras, gyroscopes, accelerometers, sensors at
the wrists and feet. It is able walk around, climb stairs, sit down on a chair, stand up
from a sitting position & lift payloads of 10 lbs. or pounds.
Thus from the history of Robots, the robot could well be defined as The
robot is a computer controlled device that combines the technology of digital
computers with technology of servo-controlled machines.
1.5 Robot Kinematics
KINEMATICS the analytical study of the geometry of motion of a mechanism:
With respect to a fixed reference co-ordinate system.

Without regard to the forces or moments that cause the motion.
In order to control and programme a robot we must have knowledge of

both its spatial arrangement and a means of reference to the environment.
1.5.1
Open Chain Kinematics
Mechanics of a manipulator can be represented as a kinematic chain of rigid

bodies (links) connected by revolute or
prismatic joints.
One end of the chain is constrained to a base,
while end effectors are mounted to the other
end of the chain.
The resulting motion is obtained by
composition of the elementary motions of each link with respect to the previous
one.
1.5.2
Closed Kinematic Chain
Much more difficult.

Even analysis has to take into account statics,
constraints from other links, etc.
Synthesis of closed kinematic mechanisms is
very difficult.
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PROJECT REPORT
1.5.3 Direct Vs. Inverse Kinematics

In manipulator robotics, there are two kinematics tasks:
1. Direct (also forward) kinematics
Given: are joint relations (rotations, translations) for the robot arm.
Task: What is the orientation and position of the end effectors?
2. Inverse kinematics
Given: is desired end effectors position and orientation.
Task: What are the joint rotations and orientations to achieve this?
1.6 Types of Robots By Locomotion and Kinematics
1. Stationary robots (including robotic arms with a global axis of movement)
Cartesian/Gantry robots
Cylindrical robots
Spherical robots
SCARA robots
Articulated robots (robotic arms)
Parallel robots
2. Wheeled robots
Single wheel (ball) robots

Two-wheeled robots
Three and more wheel robots
3. Legged robots
Bipedal robots (humanoid robots)

Tripedal robots
Quadrupedal robots
Hexapod robots
Other numbers of legs
4. Swimming robots
5. Flying robots
6. Mobile spherical robots (robotic balls)
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1.7 Robotic Arm

A robotic arm is a robotic manipulator, usually programmable, with
similar functions to a human arm. The links of such a manipulator are connected
by joints allowing either rotational motion (such as in an articulated robot) or
translational (linear) displacement. The links of the manipulator can be considered
to form a kinematics chain. The business end of the kinematics chain of the
manipulator is called the end effector and it is analogous to the human hand.
Figure 1-1 Robotic Arm
The end effector can be designed to perform any desired task such as welding,
gripping, spinning etc., depending on the application. For example robot arms in
automotive assembly lines perform a variety of tasks such as welding and parts
rotation and placement during assembly.
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PROJECT REPORT
1.8 Robotic Parts
Figure 1-2 Basic Robot Parts
Base
Shoulder
Elbow
Wrist
Tool-plate
End-effectors
1.9 Robot Power Sources/ Sensors

1.9.1
The Robot Drive System

The robot drive system and power source determine characteristics such as
speed, load-bearing capacity, accuracy, and repeatability.
Electric Motors
A robot with an electrical drive uses electric motors to position the robot.
These robots can be accurate, but are limited in their load-bearing capacity.
Hydraulic Cylinders (Fluid Pressure)
A robot with a hydraulic drive system is designed to carry very heavy
objects, but may not be very accurate.
Pneumatic Cylinders (Air Pressure)
A pneumatically-driven robot is similar to one with a hydraulic drive
system; it can carry less weight, but is more compliant (less rigid to disturbing
forces).
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PROJECT REPORT
1.9.2
Robot Sensors
Robots under computer control interact with a variety of sensors, which
are small electronic or Electro-mechanical components that allow the robot to react
to its environment. Some common sensors are described below.
Vision
A vision system has a computer-controlled camera that allows the robot to
see its environment and adjust its motion accordingly. Used commonly in
electronics assembly to place expensive circuit chips accurately through holes in the
circuit boards. Note that the camera is actually under computer control and the
computer sends the signals to the robot based upon what it sees.
Voice
Voice systems allow the control of the robots using voice commands. This
is useful in training Robots when the trainer has to manipulate other objects.
Tactile
Tactile sensors provide the robot with the ability to touch and feel. These
sensors are used for measuring applications and interacting gently with the
environment.
Force/Pressure
Force/pressure sensors provide the robot with a sense of the force being
applied on the arm and the direction of the force. These sensors are used to help the
robot auto-correct for misalignments, or to sense the distribution of loads on
irregular geometry. Can also measure torques, or moments, which are forces acting
through a distance. Can be used in conjunction with haptic interfaces to allow the
human operator to feel what the robot is exerting on the environment during teleoperation tasks.
Proximity
Proximity sensors allow the robots to detect the presence of objects that
are very close to the arm before the arm actually contacts the objects. These sensors
are used to provide the robot with a method of collision avoidance.
Limit Switches
Limit switches may be installed at end-of-motion areas in the workspace to
automatically stop the robot or reverse its direction when a move out-of-bounds is
attempted; again, used to avoid collisions.
Other Sensors
Encoder measures angle
Potentiometer measures angle or length
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1.10
PROJECT REPORT
LVDT measures length (linear variable displacement transducer
Applications
The robotic arm comes under the type of the robots that is the stationary
robots. It has a lot of uses depending on the type (Cartesian, cylindrical, spherical
and so on as mentioned above). Some of the uses of the robotic arm along with the
type of the robotic arm is given below.
Cartesian Robot /Gantry Robot: Used for pick and place work, application
of sealant, assembly operations, handling machine tools and arc welding. It's a
robot whose arm has three prismatic joints, whose axes are coincident with a
Cartesian coordinator.
Cylindrical Robot: Used for assembly operations, handling at machine tools,
spot welding, and handling at die-casting machines. It's a robot whose axes
form a cylindrical coordinate system.
Spherical/Polar Robot: Used for handling at machine tools, spot welding,
die-casting, fettling machines, gas welding and arc welding. It's a robot whose
axes form a polar coordinate system.
SCARA Robot: Used for pick and place work, application of sealant,
assembly operations and handling machine tools. It's a robot which has two
parallel rotary joints to provide compliance in a plane.
Articulated Robot: Used for assembly operations, die-casting, fettling
machines, gas welding, arc welding and spray painting. It's a robot whose arm
has at least three rotary joints.
Parallel Robot: One use is a mobile platform handling cockpit flight
simulators. It's a robot whose arms have concurrent prismatic or rotary joints.
1.10.1 Space Application of Robotic Arm
The application of robotic arm is the mobile serving system. The Mobile
Servicing System (MSS), better known by its primary component Canadarm2, is a
robotic arm system and associated equipment on the International Space Station.
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Figure1-3Application of Robots in Space
It plays a key role in station assembly and maintenance: moving

equipment and supplies around the station, supporting astronauts working in
space, and servicing instruments and other payloads attached to the space station.
Astronauts receive specialized training to enable them to perform these functions
with the various systems. The robotic arm is also the part of robot that is sent to
different planets for collecting soil samples.
1.10.2 Bomb Disposal/ Handling Applications of Robotic Arm
The most important application of the robotic arm is the bomb handling.
This allows the bomb disposal squad to work at the bomb to dispose it by keeping
themselves far away from it (the bomb). The basic idea is shown in fig.
Figure 1-4 Robotics in Bomb Disposal
The squad operates the robotic arm through wireless connection and the
camera interfaced at the arm provides the vision of the bomb. This is the very best
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PROJECT REPORT
application of the robotic arm in the countries like Pakistan and Afghanistan. It
can save lives if used by the experienced persons.
1.11
Robotics Future
Future missions to space will include many robotic vehicles designed to

perform specific tasks both autonomous and remote controlled. The Mars 2003
Rover Project is designed to have two scientific rovers going to Mars in 2003. Each
rover will search for evidence of liquid water that may have been present in Mars
past. The rovers will be identical to each other, but will land at different regions of
Mars.
Application domains where robotic technology is most likely to be used are:
Transport (public and private)
Exploration (oceans, space, deserts etc.)
Mining (dangerous environments)
Civil Defense (search and rescue, fire fighting etc.)
Security/Surveillance (patrol, observation and intervention)
Domestic Services (cleaning etc.)
Entertainment (robotic toys etc.)
Assistive Technologies (support for the fragile)
War Machines
Scientific Instrumentation (e.g. synchrotron sample preparation, chemical
screening etc.)
An interesting way to approach autonomous operation whilst realizing
useful applications along the way is to devise the means by which humans can
interact and intervene with robots which are richly sensor equipped, providing the
missing capabilities such as subtle judgments, risk analysis, fine dexterity and
reaction t unpredicted events but in such as way that a continuum between full
autonomy and full Tele-operation can be smoothly engaged. As the technology
matures, the human support can be gracefully withdrawn with less and less
intervention over more and more of the tasks. For example there are many situations
in, say, fire fighting where a robotic vehicle carrying water may move along a fire
front spraying water at hot spots detected using a thermal camera fairly
autonomously, but a human may need to direct the vehicle to move to another more
critical, fire front or assist in a delicate rescue mission under direct tele-operation
control.
As another example, a transport vehicle may safely negotiate a highway
navigation task, changing lanes and speed as required, preplanning routes and so on,
yet a human operator may need to take over at an unexpected construction site or
scene of an accident.
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1.12
PROJECT REPORT
The Main Challenges for Intelligent Robotics
Improvements of the quality, robustness, smaller size and reduced cost of camera,
laser range, ultrasonics, radar, and inertial sensors.
Improvements in computational power at low cost. This aspect will not need any
special attention because of existing market forces.
Improvement in mechanisms for robot platforms in terms of weight, strength, and
capability and the use of new materials, including ceramics, carbon fiber, titanium
etc.
Improvements in navigation algorithms including natural landmark based
approaches, recovery mechanisms, accommodation of varying cost structures
related to navigability, collision risk, visibility etc.
Improvements of Human/Machine cooperation, including communication, task
refinement, intervention etc.
Improvement in risk assessment and endurance in terms of operational times and
graceful degradation.
Clarification of legal aspects of humans and robots working together.
Better understanding of emotional aspects of robots working with humans.
Evolution of the robot/biology cross-inspirational trend.
Development of robotic ethics.
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PROJECT REPORT
CHAPTER 2
ROBOT TERMINOLOGIES
Robot arms come in all shapes and sizes. The arm is the part of the robot
that positions the end-effecter and sensors to do their pre-programmed business.
Many (but not all) resemble human arms, and have shoulders, elbows, wrists, even
fingers. This gives the robot a lot of ways to position itself in its environment.
In robotics several specific terminologies are used to describe certain
conditions and components. In this chapter we are going to include some important
terminologies used for the robotic arm design for a particular application.
2.1 Robotics Terminologies

Actuator: A piece of equipment that allows a robot to move by conversion of
different energy types such as electrical or mechanical processes using liquid or air
Arm Sagging: Arm sagging is a common affliction of badly designed robot arms.
This is when an arm is too long and heavy, bending when outwardly stretched.
When designing your arm, make sure the arm is reinforced and lightweight. The
sagging problem is even worse when the arm wobbles between stop-start motions.
The solve this, implement a PID controller so as to slow the arm down before it
makes a full stop.
To avoid arm sagging, keep the heaviest components, such as motors, as
close to the robot arm base as possible. It might be a good idea for the middle arm
joint to be chain/belt driven by a motor located at the base (to keep the heavy motor
on the base and off the arm).
Base: Part of a structure that supports the manipulator arm.
Chassis: The parts making up a machine not including the body or casing. In the
case of an automobile this would include parts such as the frame and engine but not
the body surrounding these parts.
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PROJECT REPORT
Control Device: An instrument that allows a person to have control over a robot or
automated system for times such as startup or an emergency.
Control Program: The control information built into the robot or automated system
that allows for possible behaviors. The control information is not expected to be
altered.
Degree of Freedom: The degree of freedom, or DOF, is a very important term to
understand. Each degree of freedom is a joint on the arm, a place where it can bend
or rotate or translate. You can typically identify the number of degrees of freedom
by the number of actuators on the robot arm. A simple robot arm with 3 degrees of
freedom could move in 3 ways: up and down, left and right, forward and backward.
Most working robots today have 6 degrees of freedom. Humans have many more
and some robots have 8, 12, or even 20 degrees of freedom, but these 6 are enough
for most basic tasks. As a result, most jointed-arm robots in use today have 6
degrees of freedom. Figure below shows a robot with 3 Degree of Freedom
configuration because it is simple, yet isnt limiting in its ability.
Figure 2- 1 Robot Links
Drive Power: Actuators convert this source of energy into usable energy for the
robot's movement.
End-Effector: Any object attached to the robot flange (wrist) that serves a function.
This would include robotic grippers, robotic tool changers, robotic crash protection,
robotic rotary joint, robotic press tooling, compliance device, robotic paint gun,
robotic arc welding gun etc. End effector is also known as robotic peripheral,
robotic accessory, robot or robotic tool, end of arm (EOA) tooling, or end-of-arm
device. End effector may also be hyphenated as "end-effector.
End-effector space: The area of the robot's end-effector movement with respect to
its base. (Common Misspellings: end-effecter space, end-affecter space, end-affecter
space).
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PROJECT REPORT
Energy Source: Energy is provided by conversion of various types of sources such

as chemical, thermal, mechanical etc.
Hybrid: The robot has a combination of pick and place and servo controlled parts.
Hazardous Motion: A possible dangerous or harmful motion.
Industrial Robot: A manipulator that is designed to perform various programmed

tasks during manufacturing. Industrial robots are automated by a program that
controls its duties that tend to be dangerous or difficult for humans. (Common
Misspellings include: industrial robot, industrial robot, industrial robots, industry
robot, industrial robot).
Interface: The separation between robots and the equipment not nearby. The sensors
that are required for communication between the devices use signals relaying input
and output data.
Joint: The device which allows relative motion between two adjoining links in a
robot. A robot joint is a mechanism that permits relative movement between parts of
a robot arm. The joints of a robot are designed to enable the robot to move its endeffectors along a path from one position to another as desired.
Joint Motion: A way to regulate the joint's movement so that all reach the specified
position at the same time.
Jointed Arm Robot: The arm of the robot has two junctions allowing for rotation
and enhanced movement much like a person's shoulder and elbow on their arm.
Link: A rigid piece of material connecting joints in a robot.
Motion axis: The line defining the axis of motion either linear or rotary, of a
segment of a manipulator.
Reach: The distance from the center of the robot to the fullest extension of the
robotic arm. The work envelope is determined from this distance.
Robot Workspace: The robot workspace (sometimes known as reachable space)
is all places that the end effector (gripper) can reach. The workspace is dependent
on the DOF angle/translation limitations, the arm link lengths, the angle at which
something must be picked up at, etc. The workspace is highly dependent on the
robot configuration.
Now lets assume that all joints rotate a maximum of 180 degrees,
because most motors cannot exceed that amount. To determine the workspace, trace
all locations that the end effector can reach as in the image below.
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PROJECT REPORT
Figure 2- 2 Two Dimensional Robot Workspace
Now rotating that by the base joints another 180 degrees to get 3D, we
have this workspace image. Remember that because it uses servos, all joints are
limited to a max of 180 degrees. This creates a workspace of a shelled semi-sphere
(its a shape because I said so).
Figure 2- 3 Three Dimensional Robot Workspace
If you change the link lengths you can get very different sizes of
workspaces, but this would be the general shape. Any location outside of this space
is a location the arm cant reach. If there are objects in the way of the arm, the
workspace can get even more complicated.
Sensing: Most robot arms only have internal sensors, such as encoders. But for
good reasons you may want to add additional sensors, such as video, touch, haptic,
etc. A robot arm without video sensing is like an artist painting with his eyes closed.
Using basic visual feedback algorithms, a robot arm could go from point to point on
its own without a list of preprogrammed positions. Giving the arm a red ball, it
could actually reach for it (visual tracking and servoing). If the arm can locate a
position in X-Y space of an image, it could then direct the end effector to go to that
same X-Y location (by using inverse kinematics).
Swing: A robot's rotational movement with respect to its centerline.
Yaw: The side-to-side motion of the end-effector's rotation at an axis.
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PROJECT REPORT
CHAPTER 3
IMPLEMENTATION PLAN FOR
ROBOTIC ARM
After a broad theoretical study regarding project next step was to select
hardware components and coding techniques. A comparison was made between
different methods and actuators to finally select the best suited for the project.
Process of selection went through following steps:
3.1 Selection of Motor For Project

Robot motors enable a robot to move. There are several different
types of motors. Each motor type has several advantages as well as disadvantages
depending on a particular robots design. Tough their re no hard and fast rules for
motor selection in robotics motors used in robotics should have fast response and
accurate position control. Another parameter for motor selection is torque required
by the system and the speed at which the motor will run. Usually stepper, servo,
some AC and DC (Brushless and Brushed) Motors are used in robotics
applications but stepper and servo motors are most widely used.
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PROJECT REPORT
3.1.1 Comparison: Servo/Stepper Motor
Characteristics
Servo Motor
Stepper Motor
Flexibility in
motor resolution
Since the encoder on a

servo motor determines the Stepper motors usually
motor resolution servos
have 1.8 or 0.9 degree
have a wide range of
resolution.
resolutions available.
Torque to Inertia
Ratio
Servo motors are very

capable of accelerating
loads.
Servo motors will do fine

with low speed
Low Speed High
applications given low
Torque
friction and the correct
gear ratio
Stepper motors may stall

and skip steps if the motor
is not powerful enough.
Stepper motors provide

most torque at low speed
(RPM).
Stepper motors are less

Servo motors have an
efficient than servo motors
Power to
excellent power to weight which usually mean a
Weight/Size ratio
ratio given their efficiency. smaller power to
weight/size ratio.
Efficiency
Servo motors are very

efficient. Yielding 80-90%
efficiency given light
loads.
Stepper motors consume a

lot of power given their
output, much of which is
converted to heat.
Noise
Stepper motors produce a

slight hum due to the
Servo motors produce very
control process. However a
little noise.
high quality driver will
decrease the noise level.
Resonance and
Vibration
Servo motors do not

vibrate or have resonance
issues.
Stepper motors vibrate

slightly and have some
resonance issues because of
how the stepper motor
operates.
Page 17
Power Range
Because servo motors are

available in DC and AC
servo motors have a very
wide power availability
range.
PROJECT REPORT
The power availability

range for stepper motors is
not that of servo motors.
3.1.2 Stepper Motor Disadvantages in Robotics

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Low efficiency. Motor draws substantial power regardless of load.

Torque drops rapidly with speed (torque is the inverse of speed).
Low accuracy. 1:200 at full load, 1:2000 at light loads.
Prone to resonances. Requires micro stepping to move smoothly.
No feedback to indicate missed steps.
Low torque to inertia ratio. Cannot accelerate loads very rapidly.
Motor gets very hot in high performance configurations.
Motor will not "pick up" after momentary overload.
Motor is audibly very noisy at moderate to high speeds.
Low output power for size and weight.
3.1.3 Why we Select Servo Motors?

After searching all different types of motors we selected servo motor for
robotic arm application. Selection of the servo motors for controlling the robotics
arm generally based on the observed disadvantages of the commonly used stepper
and dc-motors in the robotics field.
In general servo motors are better than other motors because of their fast
response, smooth motion, quiet operation, enormous standing torque, small size,
low weight, resonance and vibration free environment, ease of control and low
energy requirements. All that led us to use servo motors in robotic arm.
3.2 Control Mechanism
After selecting the motor for robotic arm the next step was the next step
was to choose the control mechanism. For which a comparison was made between
different modern day technologies.
3.2.1
War Between FPGA and Microcontrollers

Are FPGAs and microcontrollers the same thing? No
FPGA is mainly for programmable logic but microcontroller is
mainly hardcore processing.
In digital signal processor, the hardcore would enhance the
hardware architecture by increasing pipelining to certain level of
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PROJECT REPORT
parallel instruction processing. Instead, FPGA is totally hardware

based programmable.
The parallel processing in FPGA is not depends to the pipelining,
but it is hardware based parallel architecture
FPGAs implement programmable logic elements running in a
parallel fashion.
Microcontrollers are based on a CPU architecture (executes a set of
instructions in a sequential manner).
Microcontrollers have on-chip peripherals that also execute in
parallel with their CPU. But they are still much less configurable
than FPGAs.
Who is Winner?
For general application, microcontroller is good enough for system
implementation. However, in some critical arithmetic processing such as DSP
algorithm would need real-time processing that is time critical. In this case, FPGA
would be the best solution.
3.2.2 War Between Microprocessors and FPGA
Are FPGAs and microprocessors the same thing? No

Microprocessor (CPU) works in sequential manner while FPGA in
Parallel manner.
Speed of Microprocessor (CPU) is slower than FPGA.
Microprocessor (CPU) has different PCB for different projects
while FPGA has same PCB for different projects.
Who Is Winner?
Although again choice between them is Particular design dependent but
still FPGA has more flexibility, speed and provide Faster Time to Market solution
as compared to microprocessor
3.2.3
War Between CPLDS and FPGA

Are FPGAs and CPLDs the same thing? No.
Are programmable digital logic chips and are made by the same
companies. But they have different characteristics.
FPGAs are "fine-grain" devices - that means that they contain a lot
(up to 100000) of tiny blocks of logic with flip-flops. CPLDs are
"coarse-grain" devices - they contain relatively few (a few 100's
max) large blocks of logic with flip-flops.
FPGAs are RAM based - they need to be "downloaded"
(configured) at each power-up. CPLDs are EEPROM based - they
are active at power-up
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PROJECT REPORT
FPGAs have special routing resources to implement efficiently

arithmetic functions. CPLDs do not.
Who Is Winner?
In general, FPGAs can contain large digital designs, while CPLDs
can contain small designs only. The choice between CPLDs and
FPGAs depend upon specific application.
3.3 A Gateway to FPGA

In last two decades applications of FPGAs in DSP and Electronics has
brought some very attractive and revolutionary change in control world. So before
formally enter into the world of FPGA, it is necessary to know why we should use
FPGA. In the presence of other controlling devices like Microcontrollers,
Microprocessors, CPLDs etc. and what is the place of FPGA in the kingdom of
digital worlds and Electronics. To better know about it we first meet with opponents
of FPGA, and critically compare them with FPGA.
Figure 3- 1 FPGA Insight
3.3.1 Critical Analysis About FPGA Selection

There are numerous options for designers in selecting a hardware platform for
custom electronics design, ranging from embedded processors, Application Specific
Integrated Circuits (ASICs), Programmable Micro-processors (PICs), FPGAs to
Programmable Logic Devices (PLDs).
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PROJECT REPORT
The decision to choose a specific technology such as an FPGA should depend

primarily on the design requirements rather than a personal preference for one
technique over another.
For example, if the design requires a programmable device with many design
changes, and algorithms using complex operations such as multiplications and
looping, then it may make more sense to use a dedicated signal processor device
such as a DSP that can be programmed and reprogrammed easily using C or some
other high-level language.
If the speed requirements are not particularly stringent, and a compact cheap
platform is required, then a general purpose microprocessor such as a PIC would be
an ideal choice. Finally, if the hardware requirements require a higher level of
performance, say up to several 100 MHz operation, then an FPGA offers a suitable
level of performance, while still retaining the flexibility and reusability of
programmable logic.
Other issues to consider are the level of optimization in the hardware design
required. For example, a simple software program can be written in C, and then a
PIC device programmed, but the performance may be limited by the inability of the
processor to offer parallel operation of key functions. This can be implemented
much more directly in an FPGA using parallelism and pipelining to achieve much
greater throughput than would be possible using a PIC.
A general rule of thumb when choosing a hardware platform is to identify both the
design requirements and the hardware options, and then select a suitable platform
based on those considerations.
For example, if the design requires a basic clock speed of up to 100MHz then an
FPGA would be a suitable platform. If the clock speed could be 34 MHz, then the
FPGA may be an expensive (overkill) option.
If the design requires a flexible processor option, although the FPGAs available
today support embedded processors, it probably makes sense to use a DSP or PIC. If
the design requires dedicated hardware functionality, then an FPGA is the route to
take.
Performing Cost
Very High
Medium
Time Until
Running
Very Long
Long
Time to High
Performance
Very Long
Long
Time to Change Code

Functionality
Impossible
Long
ASIC
Custom Processor
DSP
FPGA
Generic
Low Medium
Low Medium
Short
Short
Short
Not Attainable
Short
Short
Page 21
Relaxability
Speed
Technology
PROJECT REPORT
If the design requires specific hardware functions such as multiplication and

addition, then a DSP may well be the best route, but if custom hardware design is
required, then an FPGA would be the appropriate choice.
If the design requires small simple hardware blocks, then a PLD or CPLD
(Complex Programmable Logic Device) may be the best option (compact, simple
programmable logic), however, if the design has multiple functions, or a
combination of complex controller and specific hardware functions, then the FPGA
is the route to take.
Examples of this kind of decision can be dependent on the complexity of the
hardware involved. For example, a Video Graphics Array (VGA) controller will
probably require an FPGA rather than a PLD device, simply due to the complexity
of the hardware involved.
Another related issue is that of flexibility and programmability. If an FPGA is
used, and the resources are not used upon a specific device (say up to 60 per cent for
example), then if a communications protocol changes, or is updated, then the device
may well have enough headroom to support several variants, or updates, in the
future.
Figure 3- 2 FPGA vs ASIC/Custom Microprocessor Design
3.3.2
Final Conclusion
Using these simple guidelines, an intelligent choice can be made about the
best platform to choose, and also which hardware device to select based on these
assumptions. The nice aspect of most synthesis software packages is that multiple
design platforms can be tested for performance and utilization (e.g. PLD or
FPGA) prior to making a final decision on the hardware of choice.
3.4 Modeling Language

FPGAs use hardware descriptive language. Two of the most common
languages are VHDL and Verilog. We selected VHDL for our project.
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3.4.1
PROJECT REPORT
Languages used for FPGA Programming
The FPGA works with hardware description language (HDL) or a

schematic design. The HDL is preferred over schematic design due to HDL's
capability in handling large design blocks. It easy to specify them numerically
rather than schematic diagram type entry. The advantage of schematic entry is it's
easy to visualize a design. Please note advanced EDA tools make the life of FPGA
designer far easier by offering lot of automation.
Through such EDA tools technology-mapped netlist is generated. The
netlist is fitted into the actual FPGA architecture by using a process called placeand-route, mostly done by the proprietary place-and-route software supplied by
FPGA vendor. Designer got to validate the map, place and route results by using
timing analysis, simulation, and other verification methodologies. After the
validation process, the binary file is generated. Binary file is transferred into
FPGA/CPLD via a serial interface (JTAG) or to an external memory device like
an EEPROM to make the device to work as per the design.
Advantages of HDL
A design methodology that uses HDLs has several fundamental
advantages over a traditional gate-level design methodology. Some of the
advantages are listed below.
You can verify design functionality early in the design process and
immediately simulate a design written as an HDL description.
Design simulation at this higher level, before implementation at the
gate level, allows you to test architectural and design decisions.
HDL descriptions supply technology-independent documentation of a
design and its functionality.
An HDL description is more easily read and understood than a
netlist or schematic description. Because the initial HDL design
description is technology-independent, you can later reuse it to
generate the design in a different technology, without having to
translate from the original technology.
HDL, like most high-level software languages, provides strong type
checking.
A component that expects a four-bit-wide signal type cannot be
connected to a three- or five-bit-wide signal; this mismatch causes
an error when the HDL description is compiled. If a variables
range is defined as 1 to 15, an error results from assigning it a
value of 0. Incorrectly using types is a major source of errors in
descriptions. Type checking catches this kind of error in the HDL
description even before a design is generated.
3.4.2
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3.4.3
PROJECT REPORT
Why we Preferred VHDL over Verilog?
This section compares and contrasts individual aspects of the two languages; they
are listed in alphabetical order.
1. Data types
VHDL A multitude of language or user defined data types can be used. This
may mean dedicated conversion functions are needed to convert objects
from one type to another.
Verilog Unlike VHDL, all data types used in a Verilog model are defined by
the Verilog language and not by the user.
2. Design reusability
VHDL Procedures and functions may be placed in a package so that they are
avail able to any design-unit that wishes to use them.
Verilog There is no concept of packages in Verilog. Functions and
procedures used within a model must be defined in the module.
3. Easiest to learn
Verilog Starting with zero knowledge of either language, Verilog is probably
the easiest to grasp and understand.
VHDL may seem less intuitive at first for two primary reasons. First, it is
very strongly typed; a feature that makes it robust and powerful for the
advanced user after a longer learning phase. Second, there are many ways to
model the same circuit, especially those with large hierarchical structures.
4. Compilation
VHDL multiple design units (entity/architecture pairs), that reside in the same
system file, may be separately compiled if so desired.
The Verilog language is still rooted in its native interpretative mode.
Compilation is a means of speeding up simulation, but has not changed the
original nature of the language.
5.
High level constructs

VHDL There are more constructs and features for high-level modeling are
in VHDL than there are in Verilog.
Verilog Except for being able to parameterize models by overloading
parameter constants, there is no equivalent to the high-level VHDL
modeling statements in Verilog.
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PROJECT REPORT
6. Language extensions
Although the use of language extensions will make a model non standard and
most likely not portable across other design tools. However, sometimes they
are necessary in order to achieve the desired results.
VHDL has an attribute called 'foreign that allows architectures and
subprograms to be modeled in another language.
7.
Libraries
VHDL A library is a store for compiled entities, architectures, packages
and configurations. Useful for managing multiple design projects.
Verilog There is no concept of a library in Verilog. This is due to it's
origins as an interpretive language.
8. Managing large designs

VHDL Configuration, generate, generic and package statements all help
manage large design structures.
Verilog There are no statements in Verilog that help manage large designs.
9. Procedures and tasks
Procedures and tasks VHDL allows concurrent procedure calls.
Verilog does not allow concurrent task calls.
10. Structural replication
VHDL Generates statement replicates a number of instances of the same
design-unit or some sub part of a design, and connects it appropriately.
Verilog There is no equivalent to the generate state.
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PROJECT REPORT
CHAPTER 4
HARDWARE DESCRIPTION
In this chapter we explain a brief theory about the selections we made
about our project.
4.1 Servo Motors

When the objective of the system is to control the position of an object the
system is called servomechanism. These systems are used widely in robotics. Servo
motors are usually used for this purpose, which convert an electrical signal into an
angular displacement of the shaft.
4.1.1 What is a Servo Motor?

A servo motor is an ac or dc motor with combined with a digital position
sensing device (e.g. decoder) for feedback. A servomotor is used within a positioncontrol or speed-control feedback control System. A servo motor is a three terminal
device. Apart from power and ground terminal servo motor has a control terminal to
which control pulse is applied.
Three basic types of servo motors are used in modern servo systems: ac
servo motors, based on induction motor designs; dc servo motors, based on dc
motor designs; and ac brushless servo motors, based on synchronous motor designs.
Page 26
PROJECT REPORT
Figure 4- 1 Servo Motor Block Diagram
4.1.2 How Does The Servo Work?

Servo motor works on the principle of proportional control. This means
that motor will run only as hard as necessary. The amount of power applied to the
motor is proportional to the distance it needs to travel. So, if the shaft needs to turn a
large distance, the motor will run at full speed. If it needs to turn only a small
amount, the motor will run at a slower speed. This is called proportional control.
Servos are extremely useful in robotics. The motors are small, have built in control
circuitry, and are extremely powerful for their size. Servos are commonly electrical
or partially electronic in nature, using an electric motor as the primary means of
creating mechanical force.
4.1.3 Construction
The servo motor has some control circuit and a potentiometer that is
connected to the output shaft. Potentiometer allows the control circuitry top monitor
the current angle of the servo motor. If the circuit finds that angle is not correct
direction until the angle is correct. If the shaft is at the correct angle, it shuts off.
The output shaft of the servo is capable of rotating some where around 180 degrees.
Figure 4- 2 Components of a Servo Motor
Page 27
PROJECT REPORT
4.1.4 Pulse Width= Position

The angle or position of the servo motor is determined by the duration of
the pulse applied to the control wire. This is called Pulse Width Modulation. The
servos control board interprets the pulses and rotates its shaft either clockwise or
counterclockwise based on the pulse widths. Servos will not respond to just any
pulse width; rather, they are limited to a well-defined range of pulse widths. Most
servos have a minimum pulse width limit around 0.0010s (1.0ms) and a maximum
limit around 0.0020s (2.0ms), although the actual minimum and maximum pulse
widths will vary slightly between the various servo brands. Sending a pulse whose
pulse width is outside this range may damage the servos control board. Repeatedly
sending these bad pulses will almost certainly destroy the servo.
Figure 4- 3 Servo Motor Pulse vs Position
Motors intended for use in a servomechanism have well-documented

characteristics for speed, torque, power. The dynamic response characteristics such
as winding inductance and Rotor inertia are also important; these factors limit the
overall performance of the servomechanism loop. AC or DC motors and drive
systems with position or speed feedback on the motor. As dynamic response
requirements increase, more specialized motor designs such as coreless motors are
used.
4.1.5 Requirements of a Good Servo Motor

Servo motors are designed to be used in control system and should fulfill
following requirements.
1. Linear relation ship between electrical control signal and the rotor angle over a
wide range.
2. Inertia of the motor should be a small as possible. A servo motor must stop
running without any time delay, if the control signal is kept constant.
3. Its response should be very fast. For quickly changing error signals, it must react
with good response.
This is achieved by keeping torque to weight ratio high. Hence, these motors can
be stopped, started and reversed very quickly as compared to normal motors.
Page 28
PROJECT REPORT
4. It should be quickly reversible.

5. It should have linear torque/speed characteristic.
6. The operation should be stable without any oscillations and overshoot.
Figure 4- 4 Performance Characteristics of Servo Motor
4.1.6 Color Convention

It is a common convention in electronics to wire electrical components with
wires of distinguishable colors. Usually, sensors and servos are wired from lightto-dark the wire of the lightest color carries the
signal, the darkest wire is the ground wire, and the
middle wire carries the power. All servos have three
wires
Black or Brown is for ground.

Red is for power (~4.8-6V).
Yellow, Orange, or White is the signal
wire.
4.1.7 Position Control System

In such applications, it is required to keep the position of the load constant.
Such a system where the position of the output is kept constant is called position
controlled system. The output position is sensed and is feedback to potentiometer
used as an error detector. For any change in output position L, the potentiometer
generates an error signal proportional to the difference between L and r . The r is
the reference position corresponding to the ideal output position. The error signal
is given to amplifier and the output of the amplifier is given to armature of the DC
motor. The DC motor maintains the output shaft position constant. The entire
scheme is called DC Position Control System.
Page 29
PROJECT REPORT
Figure 4- 5 DC Servo Motor with Position Control System
4.2 What is FPGA?

We can describe FPGA (field programmable gate arrays) as the integrated circuits
of which their hardware configuration can be changed by the user according to the desired
functions. FPGA is an integrated circuit and is a programmable logic device. However the
difference from the others is that they can be configurable as we wish. We can explain
this as follows: In ordinary or standard ICs which can not be programmable, there are
fixed interconnections between the transistors. Unless they are burned or another
unfortunate event does not come, they can not be changed. We may consider FPGAs as
crude ICs of which their transistors were produced independently. Interconnections
between transistors can be done according to the function we defined, then they perform
the function we want. So theoretically, any operation that comes to our minds can be done
by FPGAs, depending on the transistor capacity.
One of the most important features of FPGAs is the ability to do parallel

processing. For example, you wanted to make real time filtering on a high
resolution video signal. Video signal is actually a series of pictures which
sequentially come to the scene. Each of these pictures are called frames. Basically
you need to get a frame from an input port, filter this frame and send it through an
output port. Then you should do the same job as real time process for the coming
frames.
If you use standard ICs like microprocessors, you start to get second frame
after processing three operations (get, filter and send) for the first frame. If this
process can not be fast enough, you may miss the next frame. FPGAs do all these
operations in parallel. That means while we processing of filtering the first frame,
we might begin to take the second frame. And while we sending the first frame to
the output, we begin to filter the second frame and get the third frame at the same
time.
Furthermore, filtering process requires extensive multiplication process.
With standard ICs, we have to do this process sequentially. Whereas this process
can be done in parallel with an FPGA so it can be done very quickly.
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PROJECT REPORT
In summary, FPGAs are hardware-programmable integrated circuits that

provide us parallel processing capabilities and opportunity to change the internal
structure and its function according to the desired application.
4.2.1 FPGA or Microprocessor/Microcontroller?

Of course, the answer to this question will vary according to the application.
In this section we will provide information on the differences between FPGA and
hard processors, Pros and Cons, and which applications are widely used with
FPGAs, which applications are widely used with processors.
The main and the most significant difference between the microcontroller and
the FPGA is that FPGA doesnt have a fixed hardware structure; on the contrary it
is programmable according to user applications. However processors have a fixed
hardware structure. It means that all the transistors memory, peripheral structures
and the connections are constant. Operations which processor can do (addition,
multiplication, I/O control, etc.) are predefined. And users make the processor do
these operations "in a sequential manner" by using a software, in accordance with
their own purposes.
Hardware structure in the FPGA is not fixed so it is defined by the user.
Although logic cells are fixed in FPGA, functions they perform and the
interconnections between them are determined by the user. So operations that
FPGAs can do are not predefined. You can have the processes done according to
the written HDL code "in parallel" which means simultaneously. Ability of
parallel processing is one of the most important features that separate FPGA from
processor and make it superior in many areas.
Lets explain this with an analogy: FPGA can be likened to a plasticine that
we can give the shape we want; hard processors can be likened to the toy car. You
can make any toys from plasticine included the car you want. You have to adopt
toy car as it stands and play just a toy car. Nevertheless, it is quite difficult and
tricky to make a toy car identical with the toy car you bought. So it is very
convenient to buy the toy car instead of buying a plasticine, if it is the one you
exactly need. However if you can not find the toy car of your dreams, you have to
make it on your own with the plasticine.
Processors are generally more useful for routine control of particular circuits.
For example, using FPGA for simple functions such as turn on and off any device
from a computer may be overstated. This process can be easily done with many
ordinary microcontrollers (PIC series, etc.). However, FPGA solution is more
reasonable, if you want to process on a high-resolution video data on the
computer.
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PROJECT REPORT
Because video processing requires processing large data in high speed and
make these types of applications are very suitable for FPGA that is capable of
parallel processing.
Since the user can determine the hardware structure of FPGAs, you can
program FPGA to process larger data with few clock cycles. But this is not
possible with the processor. Because data flow is limited by processor bus (16-bit,
32 bit, etc.) and the processing speed. As a result, applications that require more
performance such as intensive data processing FPGA has come to the fore, and
processor / microcontroller has come to the fore for routine control operations.
Nevertheless, processors / microcontrollers can be embedded into the FPGA
since they are logic circuits in fact.
Thus it possible to define and use processor and user-specific hardware
functions on only one chip by using FPGA. This solution gives engineers the
opportunity to control the hardware because of its great flexibility. You can
modify and update whole design (FPGA on the processor and other logic circuits)
by only changing the code on FPGA, without any change on circuit board layout.
4.2.2 Evaluation of FPGA

In the world of digital electronic systems, there are three basic kinds of
devices: memory, Microprocessors, and logic. Memory devices store random
information such as the contents of a spreadsheet or database. Microprocessors
execute software instructions to perform a wide variety of tasks such as running a
word processing program or video game. Logic devices provide specific
functions, including device-to-device interfacing, data communication, signal
processing, data display, timing and control operations, and almost every other
function a system must perform. The first type of user-programmable chip that
could implement logic circuits was the Programmable Read-Only Memory
(PROM), in which address lines can be used as logic circuit inputs and data lines
as outputs. Logic functions, however, rarely require more than a few product
terms, and a PROM contains a full decoder for its address inputs. PROMS are thus
an inefficient architecture for realizing logic circuits, and so are rarely used in
practice for that purpose. The device that came as a replacement for the PROMs
are programmable logic devices or in short PLA. Logically, a PLA is a circuit that
allows implementing Boolean functions in sum-of-product form. The typical
implementation consists of input buffers for all inputs, the programmable ANDmatrix followed by the programmable OR-matrix, and output buffers. The input
buffers provide both the original and the inverted values of each PLA input. The
input lines run horizontally into the AND matrix, while the so-called product-term
lines run vertically. Therefore, the size of the AND matrix is twice the number of
inputs times the number of product-terms. When PLAs were introduced in the
early 1970s, by Philips, their main drawbacks were that they were expensive to
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PROJECT REPORT
manufacture and offered somewhat poor speed-performance. Both disadvantages

were due to the two levels of configurable logic, because programmable logic
planes were difficult to manufacture and introduced significant propagation
delays. To overcome these weaknesses, Programmable Array Logic (PAL)
devices were developed. PALs provide only a single level of programmability,
consisting of a programmable wired AND plane that feeds fixed OR-gates.
PALs usually contain flip-flops connected to the OR-gate outputs so that
sequential circuits can be realized. These are often referred to as Simple
Programmable Logic Devices (SPLDs). Fig. shows a simplified structure of PLA
and PAL.
Figure 4-6 Structure of PAL & PLA
With the advancement of technology, it has become possible to produce

devices with higher capacities than SPLDs. As chip densities increased, it was
natural for the PLD manufacturers to evolve their products into larger (logically,
but not necessarily physically) parts called Complex Programmable Logic
Devices (CPLDs). For most practical purposes, CPLDs can be thought of as
multiple PLDs (plus some programmable interconnect) in a single chip. The larger
size of a CPLD allows implementing either more logic equations or a more
complicated design.
Figure 4- 7 Structure of CPLD
Figure contains a block diagram of a hypothetical CPLD. Each of the four

logic blocks shown there are equivalent to one PLD. However, in an actual CPLD
there may be more (or less) than four logic blocks. These logic blocks are
themselves comprised of macro cells and interconnect wiring, just like an ordinary
PLD. Unlike the programmable interconnect within a PLD, the switch matrix
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PROJECT REPORT
within a CPLD may or may not be fully connected. In other words, some of the
theoretically possible connections between logic block outputs and inputs may not
actually be supported within a given CPLD. The effect of this is most often to
make 100% utilization of the macrocells very difficult to achieve. Some hardware
designs simply won't fit within a given CPLD, even though there are sufficient
logic gates and flip-flops available. Because CPLDs can hold larger designs than
PLDs, their potential uses are more varied. They are still sometimes used for
simple applications like address decoding, but more often contain highperformance control-logic or complex finite state machines. At the high-end (in
terms of numbers of gates), there is also a lot of overlap in potential applications
with FPGAs.
Traditionally, CPLDs have been chosen over FPGAs whenever highperformance logic is required. Because of its less flexible internal architecture, the
delay through a CPLD (measured in nanoseconds) is more predictable and usually
shorter. The development of the FPGA was distinct from the SPLD/CPLD
evolution just described. FPGAs offer the highest amount of logic density, the
most features, and the highest performance. The largest FPGA now shipping, part
of the Xilinx Vertex line of devices, provides eight million "system gates" (the
relative density of logic). These advanced devices also offer features such as builtin hardwired processors (such as the IBM Power PC), substantial amounts of
memory, clock management systems, and support for many of the latest, very fast
device-to-device signaling technologies.
FPGAs are used in a wide variety of applications ranging from data
processing and storage, to instrumentation, telecommunications, and digital signal
processing. The value of programmable logic has always been its ability to
shorten development cycles for electronic equipment manufacturers and help them
get their product to market faster. As PLD (Programmable Logic Device)
suppliers continue to integrate more functions inside their devices, reduce costs,
and increase the availability of time-saving IP cores, programmable logic is
certain to expand its popularity with digital designers
4.2.3 Technology Background of FPGA

Programmable logic devices (PLDs) use different process technologies to
build the memory cells used to program a device. Nearly all of the current
available PLDs are based on a unipolar CMOS-process. Some few bipolar devices
are also available, because the bipolar Fuse-technology was the original
programming technology of the first days. The CMOS-process technology for
PLDs can be divided up into five sub-technologies (see technology-tree below).
Every technology has its advantages and disadvantages regarding to reliability,
power-up or programming behavior.
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PROJECT REPORT
Figure 4- 8 FPGA types w.r.t. their Memory

Five sub technologies to build a memory cell of FPGA are explained below.
1. EPROM Memory Technology

Electrically Programmable Read-Only Memory is similar to the technology
used in standard EPROM memory devices. Commonly used in both SPLD and
CPLD devices, EPROM cells are electrically programmed in a device
programmer. Some EPROM-based devices are erasable using ultra-violet (UV)
light if they are in a windowed package. However, most EPROM-based
SPLD/CPLDs are in low-cost plastic packaging for production. Plastic packages
cannot be UV erased. EPROM memory cell is shown in figure. It utilizes the
EPROM with floating gate witch is inside the control gate that is connected to the
line.
In its un-programmed state, the floating gate is uncharged and doesnt affect
the normal operation of the control gate. In order to program the transistor, a
relatively high voltage (on the order of 12V) is applied between the control gate
and drain terminals. This causes the transistor to be turned hard on, and energetic
electrons force their way through the oxide into the floating gate in a process
known as hot (high energy) electron injection. When the programming signal is
removed, a negative charge remains on the floating gate. This charge is very
stable and will not dissipate for more than a decade under normal operating
conditions. The stored charge on the floating gate inhibits the normal operation of
the control gate and, thus, distinguishes those cells that have been programmed
from those that have not. This means we can use such a transistor to form a
memory cell.
In its un-programmed state, as provided by the manufacturer, all of the
floating gates in the EPROM transistors are uncharged. In this case, placing a row
line in its active state will turn on all of the transistors connected to that row,
thereby causing all of the column lines to be pulled down to logic 0 via their
respective transistors. In order to Program the device, engineers can use the inputs
to the device to charge the floating gates associated with selected transistors,
thereby disabling those transistors. In these cases, the cells will appear to contain
logic 1 values.
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PROJECT REPORT
Figure 4- 9 EPROM Memory Cell
Typical data retention time: greater than 10.. 20 years

Typical erase/program cycles: OTP.. 10,000 times
Typical erase/program times: some minutes UV-light / about 0.1 msec. per cell
2. EEPROM Memory Technology
The next rung up the technology ladder was electrically erasable
programmable read-only memories (EEPROMs or E2PROMs). An E2PROM cell
is approximately 2.5 times larger than an equivalent EPROM cell because it
comprises two transistors and the space between them.
Figure 4- 10 EEPROM Memory Cell
The E2PROM transistor is similar to an EPROM transistor in that it contains

a floating gate, but the insulating oxide layers surrounding this gate are very much
thinner. The second transistor can be used to erase the cell electrically. E2PROMs
first saw the light of day as computer memories, but the same technology was
eventually applied to PLDs, which became known as electrically erasable PLDs
(EEPLDs or E2PLDs).
Typical data retention time: greater than 10 .. 20 years
Typical erase/program cycles: greater than 1,000 .. 10,000 times
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PROJECT REPORT
Typical erase/program times: some milliseconds per cell / about 0.1 msec. per
cell
3. Static Memory Technology (SRAM)
Similar to the technology used in static RAM devices but with a few
modifications. The RAM cells in a memory device are designed for fastest
possible read/write performance. The RAM cells in a programmable device are
usually designed for stability instead of read/write performance. Consequently,
RAM cells in a programmable device have a low-impedance connect to VCC and
ground to provide maximum stability over voltage fluctuations.
Because static memory is volatile (i.e.-the contents disappear when the power
is turned off), SRAM-based devices are "booted" after power-on. This makes
them in-system programmable and re-programmable, even in real-time. As a
result, SRAM-based FPGA is common in reconfigurable computing applications
where the device's function is dynamically changed.
The configuration process typically requires only a few hundred milliseconds
at most. Most SRAM-based devices can boot themselves automatically at poweron much like a microprocessor. Furthermore, most SRAM-based devices are
designed to work with either standard byte-wide PROMs or with sequential-access
serial PROMs.
SRAM based memory cell is shown in figure. The entire cell comprises a multi
transistor SRAM storage element whose output drives an additional control
transistor. Depending on the contents of the storage element (logic 0 or logic 1),
the control transistor will be either OFF (disabled) or ON (enabled).
Figure 4- 11 SRAM Based Memory Cell
This is the most widely used technology. SRAM cells are also used in
many non-volatile CPLDs to hold some configuration bits to reduce internal
capacitive loading.
Typical data retention time: only at stable power-on (volatile)
Typical erase/program cycles: unlimited
Typical erase/program times: about some milliseconds / milliseconds.. minutes
for whole chip (depends on ROM-interface)
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PROJECT REPORT
Advantages and Disadvantages

1. A disadvantage of SRAM-based programmable devices is that each cell
consumes a significant amount of silicon real estate because the cells are
formed from four or six transistors configured as a latch.
2. Another disadvantage is that the devices configuration data (programmed
state) will be lost when power is removed from the system, so these
devices always have to be reprogrammed when the system is powered on.
3. Advantages are that such devices can be reprogrammed quickly and
easily, and SRAM uses a standard fabrication technology that is always
being improved upon.
4. Anti-Fuse Memory Technology
Antifuse cells are non-volatile and only one-time programmable (OTP).
Instead of breaking a metal connection by passing current through (like fusetechnology), a link is grown to make a connection. Antifuse-based devices are
very good for high reliability applications, cause of their unlimited data-retention
time. Antifuse cells are electrically programmed in a device programmer. There
are different kinds of CMOS-based PLD-Antifuse-technologies known, like
PLICE, ViaLink or MicroVia. This technology is not used today because of its
one time programmability.
Typical data retention time: unlimited
Typical erase/program cycles: 1 time (OTP)
Typical erase/program times: not erasable / some minutes for whole chip
(depends on chip complexity)
5. Fuse Memory Technology
Fuse cells are non-volatile and only one-time programmable (OTP). Fusetechnology was the original programming technology for programmable logic. A
fuse is a metal link that can be programmed (blown) by passing a current through.
Fuse cells are electrically programmed in a device programmer.
Typical data retention time: unlimited
Typical erase/program cycles: 1 time (OTP)
Typical erase/program times: not erasable / some minutes for whole chip
(depends on chip complexity).
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PROJECT REPORT
Volatile
Re-Prog
Chip Area
R (ohm)
C (FF)
Static RAM
Yes
In circuit
1 -2 K
10-20 FF
Plice anti fuse
No
No
Anti-fuse --- small--prog. Trans.--- large
300 - 500
3-5 FF
Vialink AntiFuse
No
No
Anti-fuse--- small
prog. Trans.--- large
50 - 60
3-5 FF
EPROM
No
Out of circuit
Small
2-4k
10-20 FF
EEPROM
No
Out of circuit
2x EPROM
2-4k
10-20 FF
Large
----
Table 4- 1 Characteristics of FPGA Technology
4.2.4 FPGA Architecture

FPGA is basically consists of Logic Cells, I/O Blocks (Input/Output) and
interconnections. The basic architecture of the FPGA is shown in the figure that
shows the I/O blocks logical block and the inter connection.
Figure 4- 12 FPGA Architecture
4.2.5 FPGA Structural Classification

Basic structure of an FPGA includes logic elements, programmable
interconnects and memory. Arrangement of these blocks is specific to particular
manufacturer. On the basis of internal arrangement of blocks FPGAs can be
divided into three classes:
Symmetrical Arrays
This architecture consists of logic elements (called CLBs) arranged in
rows and columns of a matrix and interconnect laid out between them shown. This
symmetrical matrix is surrounded by I/O blocks which connect it to outside world.
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Each CLB consists of n-input Lookup table and a pair of programmable flip flops.
I/O blocks also control functions such as tri-state control, output transition speed.
Interconnects provide routing path. Direct interconnects between adjacent logic
elements have smaller delay compared to general purpose interconnect
Row Based Architecture
Row based architecture shown in figure consists of alternating rows of
logic modules and programmable interconnect tracks. Input output blocks is
located in the periphery of the rows. One row may be connected to adjacent rows
via vertical interconnect. Logic modules can be implemented in various
combinations. Combinatorial modules contain only combinational elements which
Sequential modules contain both combinational elements along with flip flops.
This sequential module can implement complex combinatorial-sequential
functions. Routing tracks are divided into smaller segments connected by anti-fuse
elements between them.
Figure 4- 13 Row Based Architecture
Hierarchical PLDs
This architecture is designed in hierarchical manner with top level
containing only logic blocks and interconnects. Each logic block contains number
of logic modules. And each logic module has combinatorial as well as sequential
functional elements. Each of these functional elements is controlled by the
programmed memory. Communication between logic blocks is achieved by
programmable interconnects arrays. Input output blocks surround this scheme of
logic blocks and interconnects. This type of architecture is shown in figure.
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PROJECT REPORT
Figure 4- 14 Hierarchical PLDs
4.2.6 Xilinx Logic block

In Xilinx logic block Look up table is used to implement any number of different
functionality. The input lines go into the input and enable of lookup table. The output of
the lookup table gives the result of the logic function that it implements. Lookup table is
implemented using SRAM.
Figure 4- 15 XILINX Logic Block

A k-input logic function is implemented using 2^k * 1 size SRAM. Number of
different possible functions for k input LUT is 2^2^k. Advantage of such an architecture
is that it supports implementation of so many logic functions, however the disadvantage is
unusually large number of memory cells required to implement such a logic block in case
number of inputs is large. Fig. shows 5-input LUT based implementation of logic block
LUT based design provides for better logic block utilization. A k-input LUT based logic
block can be implemented in number of different ways with tradeoff between
performance and logic density.
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Figure 4- 16 LUT Architecture

An n-lut can be shown as a direct implementation of a function truth-table. Each
of the latches holds the value of the function corresponding to one input combination. For
Example, 2-lut shown in figure below implements 2 input AND and OR functions.
Figure 4- 17 Logic Pin Block Location
Each logic block input pin can connect to any one of the wiring segments
in the channel adjacent to it. Each logic block output pin can connect to any of the
wiring segments in the channels adjacent to it. (In the usual FPGA terminology,
then, Fc = the number of tracks per channel, W). The figure below should make
the situation clear.
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Figure 4- 18 Logic Block Pin to Routing Channel Interconnect
Similarly, an I/O pad can connect to any one of the wiring segments in the
channel adjacent to it. For example, an I/O pad at the top of the chip can connect
to any of the W wires (where W is the channel width) in the horizontal channel
immediately below it.
The FPGA routing is un-segmented. That is, each wiring segment spans
one logic block before it terminates in a switch box. By turning on some of the
programmable switches within a switch box, longer paths can be constructed.
Figure 4- 19 Un-segmented FPGA Routing
Whenever a vertical and a horizontal channel intersect there is a switch

box. In this architecture, when a wire enters a switch box, there are three
programmable switches that allow it to connect to three other wires in adjacent
channel segments. (In terms of the usual FPGA terminology then, Fs = 3.) The
pattern, or topology, of switches used in this architecture is the planar or domainbased switch box topology. In this switch box topology, a wire in track number
one connects only to wires in track number one in adjacent channel segments,
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PROJECT REPORT
wires in track number 2 connect only to other wires in track number 2 and so on.
The figure below illustrates the connections in a switch box.
There are four types of wire routing segments available:
General purpose segments, the ones that pass through switches in the switch
block.
Direct interconnect : ones which connect logic block pins to four surrounding
connecting blocks
long line : high fan out uniform delay connections
Clock lines: clock signal provider which runs all over the chip.
Figure 4- 20 Switch Bus Topology
Switch box topology is used in the FPGAs. A switch box exists at the
junction of vertical and horizontal lines in the FPGA. The switch box allows the
dedicated path between two different logic blocks performing different operations.
A switching block and its location is shown in the above figure.
4.2.7 RAM Blocks

In almost all of today's FPGAs, memory units called RAMs are allocated.
They are used for temporary storage needs which occur during the operation of
logic circuits. This RAMs can support single or multiple access.
With multiple access, multiple applications can run read /write operations
on the RAM. Multiple access is a good solution for transferring data between
different process blocks that have different clocks.
For example, in order to transfer data to a data processing unit which
works with 50 MHz clock from a data storage unit which works with 25 MHz
clock, we can use a 2 port-RAM. The data storage unit working with 25 MHz
writes data to RAM, and data processing unit uses these data by reading it from
RAM at 50 MHz. For great RAM needs, there are Block RAMs in FPGA.
However there are small scattered (distributed) RAMs which are interspersed
among the logic cells for small data storage needs. According to the needs, Xilinx
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uses some of the logic cells as RAM as a distributed RAM. For the same purpose,
Block RAMs in Altera FPGAs are shared in different sizes.
4.2.8 FPGA Design Flow

One of the most important advantages of FPGA based design is that users can
design it using CAD tools provided by design automation companies. Generic
design flow of an FPGA includes following steps:
System Design
At this stage designer has to decide what portion of his functionality has to be
implemented on FPGA and how to integrate that functionality with rest of the
system.
I/O integration with rest of the system
Input Output streams of the FPGA are integrated with rest of the Printed
Circuit Board, which allows the design of the PCB early in design process. FPGA
vendors provide extra automation software solutions for I/O design process.
Design Description
Designer describes design functionality either by using schematic editors or by
using one of the various Hardware Description Languages (HDLs) like Verilog or
VHDL.
Synthesis
Once design has been defined CAD tools are used to implement the design on
a given FPGA. Synthesis includes generic optimization, slack optimizations,
power optimizations followed by placement and routing. Implementation includes
Partition, Place and route. The output of design implementation phase is bitstream file.
Design Verification
Bit stream file is fed to a simulator which simulates the design functionality
and reports errors in desired behavior of the design. Timing tools are used to
determine maximum clock frequency of the design. Now the design is loading
onto the target FPGA device and testing is done in real environment.
Hardware design and development
The process of creating digital logic is not unlike the embedded software
development process. A description of the hardwares structure and behavior is
written in a high-level hardware description language (usually VHDL or Verilog)
and that code is then compiled and downloaded prior to execution. Of course,
schematic capture is also an option for design entry, but it has become less
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PROJECT REPORT
popular as designs have become more complex and the language-based tools have
improved. The overall process of hardware development for programmable logic
is shown in Fig. and described in the paragraphs that follow. Perhaps the most
striking difference between hardware and software design is the way a developer
must think about the problem. Software developers tend to think sequentially,
even when they are developing a multithreaded application. The lines of source
code that they write are always executed in that order, at least within a given
thread. If there is an operating system it is used to create the appearance of
parallelism, but there is still just one execution engine. During design entry,
hardware designers must think-and program-in parallel. All of the input signals
are processed in parallel, as they travel through a set of execution engines-each
one a series of macrocells and interconnections-toward their destination output
signals. Therefore, the statements of a hardware description language create
structures, all of which are "executed" at the very same time.
Figure 4- 21 Programmable logic design process
Typically, the design entry step is followed or interspersed with periods of

functional simulation. That's where a simulator is used to execute the design and
confirm that the correct outputs are produced for a given set of test inputs.
Although problems with the size or timing of the hardware may still crop up later,
the designer can at least be sure that his logic is functionally correct before going
on to the next stage of development. Compilation only begins after a functionally
correct representation of the hardware exists. This hardware compilation consists
of two distinct steps. First, an intermediate representation of the hardware design
is produced. This step is called synthesis and the result is a representation called a
netlist. The netlist is device independent, so its contents do not depend on the
particulars of the FPGA or CPLD; it is usually stored in a standard format called
the Electronic Design Interchange Format (EDIF). The second step in the
translation process is called place & route. This step involves mapping the logical
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PROJECT REPORT
structures described in the netlist onto actual macrocells, interconnections, and

input and output pins. This process is similar to the equivalent step in the
development of a printed circuit board, and it may likewise allow for either
automatic or manual layout optimizations. The result of the place & route process
is a bitstream. This name is used generically, despite the fact that each CPLD or
FPGA (or family) has its own, usually proprietary, bitstream format. Suffice it to
say that the bitstream is the binary data that must be loaded into the FPGA or
CPLD to cause that chip to execute a particular hardware design. Increasingly
there are also debuggers available that at least allow for single-stepping the
hardware design as it executes in the programmable logic device. But those only
complement a simulation environment that is able to use some of the information
generated during the place & route step to provide gate-level simulation.
Obviously, this type of integration of device-specific information into a generic
simulator requires a good working relationship between the chip and simulation
tool vendors.
In the previous chapters we have included the very basic theory knowledge
about the FPGAs. The deep theory about the FPGAs is beyond the scope of this
project. Now we will include the theory about FPGA that is only relevant to our
project.
Moving further, now suppose we have an FPGA and we want to configure
it to perform a particular task or to develop a particular circuit. The question
arises, how to configure it? As we have previously mentioned that FPGAs can be
programmed. Now a days, two types of programming languages are mostly used
i.e. VERILOG HDL and VHDL. The one that we selected is VHDL. The reason
for selection and the importance and features of this language is also mentioned in
the previous chapters. Now let us again suppose we have a design of circuit in
VHDL language then how to download this in FPGA to configure it? The answer
to this question is, use the interface of FPGA to the pc or boot-PROM. The
interface to pc is provided by special kinds of cables called the JTAG cables. The
FPGA configuration and the interface cables are discussed in the FPGA download
cables and FPGA configuration section down here.
4.2.9 FPGA Download Cables

FPGA vendors provide many ways to "configure" (i.e. download) their devices. One
way is using a cable that connects from your PC to the FPGA board. The most popular
cables connect to your PC's parallel or USB interface.
These cables are sometimes called "JTAG cables" (because they often connect to the
JTAG pins of an FPGA). FPGA cables are vendor specific. The FPGA configuration
interfaces from all the FPGA vendors are very much alike. That doesn't prevent each
vendor to have their own proprietary connectors and cables.
The download cables for the Xilinx FPGA are
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PROJECT REPORT
o The most popular one is the Platform Cable USB (and its PDF).
o Xilinx parallel cable is called Parallel cable III.
About parallel cables: a parallel cable connects to your PC's parallel (printer)
port. It buffers a few pins of the PC parallel interface, and connects to the target board
using a flat cable or flying leads. The parallel cable is an active device and needs power.
It is usually powered from the target FPGA board. FPGA vendors sometimes provide the
schematic of the cable, which is valuable if you want to build a cable yourself.
4.2.10 FPGA Configuration

An FPGA can be into 2 states: "configuration mode" or "user mode". When the
FPGA wakes up after power-up, it is in configuration mode, sitting idle with all its
outputs inactive. You need to configure it.
Configuring an FPGA means downloading a stream of 0's and 1's into it through
some special pins. Once the FPGA is configured, it goes into "user-mode" and becomes
active, performing accordingly to your programmed "logic function".
There are 3 classical ways to configure your FPGA:

You use a cable from your PC to the FPGA, and run software on your PC to send
data through the cable.
You use a microcontroller on your board, with an adequate firmware to send data
to the FPGA.
You use a "boot-PROM" on your board, connected to the FPGA, that configures
the FPGA automatically at power-up (FPGA vendors have such special bootPROMs in their catalogs)
During development, the first method is the easiest and quickest. Once your FPGA
design works, you probably don't need the PC anymore, so the other 2 methods come in
use.
Configuration works in a surprisingly identical way between Xilinx and Altera

devices. The differences is mostly in the naming (pin names and modes of operation are
named differently), but the functionality provided is similar.
Most FPGAs can be configured in multiple ways, using either:
The JTAG interface.
The "synchronous serial" interface.
FPGA configuration can quickly become a complex subject, so you might want to
skip this section, especially if you intend to use an already-made FPGA development
board. Development boards usually come with a special cable that you can use to
configure the FPGA from your PC with no knowledge of the underlying interface.
The JTAG interface (or JTAG "port")

JTAG was originally designed for test and manufacturing purposes (as electronic
boards became more and more compact, testing that a board was "good" became more
and more difficult).
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JTAG primary purpose is to allow a computer to take control of the state of all the
device pins on a board. In turn, this allows all device-to-device combinations on the board
to be tested. Standard JTAG commands can be used for this purpose.
FPGAs are JTAG-aware and so all the FPGA IO pins can be controlled from the JTAG
interface. FPGAs add the ability to be configured through JTAG (using proprietary JTAG
commands).
How JTAG works

JTAG consists of 4 signals: TDI, TDO, TMS and TCK.
A fifth pin, TRST, is optional.
A single JTAG port can connect to one or multiple devices (as long as they are all
JTAG-aware parts). With multiple devices, you create what is called a "JTAG chain". The
TMS and TCK are tied to all the devices directly, but the TDI and TDO form a chain:
TDO from one device goes to TDI of the next one in the chain. The master controlling the
chain (a computer usually) closes the chain.
TCK is the clock, TMS is used to send commands to the devices, and TDI/TDO
are used to send and receive data. Each device in the chain has an ID, so the computer
controlling the JTAG chain can figure out which devices are present.
The "synchronous serial" interface

It is a simple data/clock interface. It is synchronous and you provide one bit at a
time to the FPGA.
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Here's a description of the 5 most important pins of this interface:

Xilinx
pin
name
Altera pin
Direction
name
data
data0
input to the
configuration data bit
FPGA
clk
dclk
input to the configuration clock, the configuration data bit is shifted

FPGA
in the FPGA at the clock rising-edge
Pin function
prog_b nConfig
When asserted (i.e. when it goes low - this is an active

low pin), the FPGA is reset-ed and looses its
input to the
configuration. If the FPGA was in user-mode, it stops
FPGA
operation immediately, and all IOs go back into tristate mode.
init_b
nStatus
This pin indicates when the FPGA is ready to start the

configuration process, soon after prog_b is de-asserted.
output
It is useful in combination with prob_b because it takes
from the
a few milliseconds for the FPGA is get into a "clean
FPGA
state of mind", once prog_b is de-asserted, after which
pumping configuration data can actually start.
done
output
When high, indicates that the FPGA is configured (in
ConfDone from the
user-mode).
FPGA
Note: the init_b and done pins are actually open-collector pins, so pull-up
resistors are required on these. Also if multiple FPGAs are to be configured, these pins
are usually connected together on all FPGAs, so that all the FPGAs switch into "usermode" together. There is many more details, so for a complete description, check your
FPGA datasheet. Among all the ways to download the VHDL design to FPGA we
selected the JTAG method for downloading.
4.3 What is VHDL?

VHDL is the VHSIC (Very High Speed Integrated Circuit) Hardware
Description Language. It can describe the behavior and structure of electronic
systems, but is particularly suited as a language to describe the structure and
behavior of digital electronic hardware designs, such as ASICs and FPGAs as well
as conventional digital circuits.
VHDL is a notation, and is precisely and completely defined by the
Language Reference Manual (LRM). This sets VHDL apart from other hardware
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PROJECT REPORT
description languages, which are to some extent defined in an ad hoc way by the
behavior of tools that use them. VHDL is an international standard, regulated by
the IEEE. The definition of the language is non-proprietary.
VHDL divides entities (components, circuits, or systems) into an external
or visible part (entity name and connections) and an internal or hidden part (entity
algorithm and implementation). After you define the external interface to an
entity, other entities can use that entity when they all are being developed. This
concept of internal and external views is central to a VHDL view of system
design. An entity is defined, relative to other entities, by its connections and
behavior. You can explore alternate implementations (architectures) of an entity
without changing the rest of the design.
After you define an entity for one design, you can reuse it in other designs
as needed. You can develop libraries of entities to use with many designs or a
family of designs.
4.3.1 A Brief History of VHDL

The development of VHDL was initiated in 1981 by the United States
Department of Defense to address the hardware life cycle crisis. The cost of
reproducing electronic hardware as technologies became obsolete was reaching
crisis point, because the function of the part was not adequately documented, and
the various components making up a system were individually verified using a
wide range of different and incompatible simulation languages and tools. The
requirement was for a language with a wide range of descriptive capability that
would work the same on any simulator and was independent of technology or
design methodology.
The standardization process for VHDL was unique in that the participation
and feedback from industry was sought at an early stage. A baseline language
(version 7.2) was published 2 years before the standard so that tool development
could begin in earnest in advance of the standard. All rights to the language
definition were given away by the DoD to the IEEE in order to encourage industry
acceptance and investment.
VHDL '93
As an IEEE standard, VHDL must undergo a review process every 5 years
(or sooner) to ensure its ongoing relevance to the industry. The first such revision
was completed in September 1993, and tools conforming to VHDL '93 are now
available.
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Year
1981
1983-85
1986
1987
1987
1994
PROJECT REPORT
Achievements
Initiated by US DoD to address hardware life-cycle crisis
Development of baseline language by Intermetrics, IBM and TI
All rights transferred to IEEE
Publication of IEEE Standards
Mil Std 454 requires comprehensive VHDL descriptions to be
delivered with ASICs
Revised standard (named VHDL 1076-1993)
Table 4-2 History of VHDL
Figure 4- 22 VHDL Evolution & Progress
4.3.2 Structure of VHDL & Design Description

Before we go any further, lets define some of the terms that we use
throughout the book. These are the basic VHDL building blocks that are used in
almost every description, along with some terms that are redefined in VHDL to
mean something different to the average designer.
Entity
All designs are expressed in terms of entities. An entity is the most
basic building block in a design. The uppermost level of the design is the
top-level entity. If the design is hierarchical, then the top-level description
will have lower-level descriptions contained in it. These lower-level
descriptions will be lower-level entities contained in the top-level entity
description.
Architecture
All entities that can be simulated have an architecture description.
The architecture describes the behavior of the entity. A single entity can
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PROJECT REPORT
have multiple architectures. Architecture might be behavioral while

another might be a structural description of the design.
Configuration
A configuration statement is used to bind a component instance to
an entity-architecture pair. A configuration can be considered like a parts
list for a design. It describes which behavior to use for each entity, much
like a parts list describes which part to use for each part in the design.
Package
A package is a collection of commonly used data types and
subprograms used in a design. Think of a package as a toolbox that
contains tools used to build designs.
Driver
This is a source on a signal. If a signal is driven by two sources,
then when both sources are active, the signal will have two drivers.
Bus
The term bus usually brings to mind a group of signals or a
particular method of communication used in the design of hardware. In
VHDL, a bus is a special kind of signal that may have its drivers turned
off.
Attribute
An attribute is data that are attached to VHDL objects or
predefined data about VHDL objects. Examples are the current drive
capability of a buffer or the maximum operating temperature of the device.
Generic
A generic is VHDLs term for a parameter that passes information
to an entity. For instance, if an entity is a gate level model with a rise and a
fall delay, values for the rise and fall delays could be passed into the entity
with generics.
Process
A process is the basic unit of execution in VHDL. All operations
that are performed in a simulation of a VHDL description are broken into
single or multiple processes.
The basic organization of VHDL design description is shown in
Figure. The Sample shown here includes an entity-architecture pair and a
package.
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PROJECT REPORT
Figure 4- 23VHDL Sample Code
4.3.3 Levels of Abstraction

VHDL can be used to describe electronic hardware at many different
levels of abstraction. When considering the application of VHDL to FPGA design,
it is helpful to identify and understand the three levels of abstraction shown
opposite - algorithm, register transfer level (RTL), and gate level. Algorithms are
unsynthesizable, RTL is the input to synthesis, gate level is the output from
synthesis. The difference between these levels of abstraction can be understood in
terms of timing.
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PROJECT REPORT
Figure 4- 24 VHDL Levels of Abstraction
Algorithm
A pure algorithm consists of a set of instructions that are executed in
sequence to perform some task. A pure algorithm has neither a clock nor detailed
delays. Some aspects of timing can be inferred from the partial ordering of
operations within the algorithm. Some synthesis tools (behavioral synthesis) are
available that can take algorithmic VHDL code as input.
RTL
An RTL description has an explicit clock. All operations are scheduled to
occur in specific clock cycles, but there are no detailed delays below the cycle
level. Commercially available synthesis tools do allow some freedom in this
respect. A single global clock is not required but may be preferred. In addition,
retiming is a feature that allows operations to be re-scheduled across clock cycles,
though not to the degree permitted in behavioral synthesis tools.
Gates
A gate level description consists of a network of gates and registers
instanced from a technology library, which contains technology-specific delay
information for each gate.
4.3.4 Design Methodology

The following figure shows a typical design process that uses Foundation
Express and a VHDL simulator.
The numbers in the above figure are explained below.
1. Write a design description in VHDL.
This description can be a combination of structural and functional
elements (as shown in the Design Descriptions chapter).
Both Foundation Express and a VHDL simulator use this design
description.
2. Provide VHDL test drivers for the simulator
The drivers supply test vectors for simulation and gather output data. To
learn about writing these drivers, see the appropriate simulator manual.
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PROJECT REPORT
3. Simulate the design by using a VHDL simulator and verify that the
description is correct.
4. Using Foundation Express, synthesize and optimize the VHDL design
descriptions into a gate-level netlist.
Foundation Express generates optimized netlists to satisfy timing
constraints for a targeted FPGA architecture.
5. Using your Foundation development system, link the FPGA technologyspecific version of the design to the VHDL simulator.
The development system includes simulation models and interfaces
required for the design flow.
6. Simulate the technology-specific version of the design with the VHDL
simulator.
You can use the original VHDL simulation drivers from Step 2, because
module and port definitions are preserved through the translation and
optimization processes.
7. Compare the output of the gate-level simulation (Step 6) against the
output of the original VHDL description simulation (Step 3) to verify that
the implementation is correct.
Figure 4- 25 VHDL Design Methodology

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PROJECT REPORT
4.3.5 Languages Under Development:

System Verilog:
1. Extending Verilog to higher levels of abstraction for architectural and
algorithm design and advanced verification
VHDL 200x:
1. Goal of VHDL Analysis and Standards Group (VASG):
Enhance/update VHDL for to improve performance, modeling capability,
ease of use, simulation control, and the type system
Analog world
VHDL has not yet been standardized for analog electronics
Standardization is in progress on VHDL with an analog extension (AHDL)
to allow analog systems to be described as well
This new standard will be based wholly on the VHDL standard and will
have a number of additions for describing analog functions.
4.4 Software used for FPGA Programming

Few of the software tools used in FPGA design
Viewlogic pro Series

Synopsis
Cadence VHDL
Data I/O Synario
Xilinx XACT
Exemplar Logic Synthesis System
Aldec Active FPGA
Through such EDA tools technology-mapped netlist is generated. The netlist

is fitted into the actual FPGA architecture by using a process called place-androute, mostly done by the proprietary place-and-route software supplied by FPGA
vendor. Designer got to validate the map, place and route results by using timing
analysis, simulation, and other verification methodologies. After the validation
process, the binary file is generated. Binary file is transferred into FPGA/CPLD
via a serial interface (JTAG) or to an external memory device like an EEPROM to
make the device to work as per the design.
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PROJECT REPORT
CHAPTER 5
HARDWARE IMPLMENTATION
FPGA, servo motors were combined through an interface to produce motion.
FPGA gives instructions in form of signals and servo motors follow the
instructions moving in accordance to the signals indicated by the FPGA. Few
characteristics of the FPGAs and servo motors are as follows.
5.1 XILINX FPGA (SPARTAN 3A)

XILINX Field Programmable Gate Arrays (FPGAs) are highly flexible,
reprogrammable logic devices that leverage advanced CMOS manufacturing
technologies, similar to other industry-leading processor and processor
peripherals. Like processors and peripherals, Xilinx FPGAs are fully user
programmable. For FPGAs program is called a configuration bitstream, which
defines FPGA functionality. The bitstream loads into the FPGA at system powerup or upon demand by system.
The Spartan-3A family of Field-Programmable Gate Arrays (FPGAs)
solves the design challenges in most high-volume, cost-sensitive, I/O-intensive
electronic applications. The five-member family offers densities ranging from
50,000 to 1.4 million system gates. Because of their exceptionally low cost,
Spartan-3A FPGAs are ideally suited to a wide range of consumer electronics
applications, including broadband access, home networking, display/projection,
and digital television equipment.
The Spartan-3A family is a superior alternative to mask programmed
ASICs. FPGAs avoid the high initial cost, lengthy development cycles, and the
inherent inflexibility of conventional ASICs, and permit field design upgrades.
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PROJECT REPORT
Some of the features of Spartan-3A FPGAs are shown below.
Figure 5-1 SPARTAN-3A FPGA
Features
Very low cost, high-performance logic solution for high-volume, costconscious applications
Dual-range VCCAUX supply simplifies 3.3V-only design
Suspend, Hibernate modes reduce system power
Multi-voltage, multi-standard Select IO interface pins
Up to eight Digital Clock Managers (DCMs)
5.2 Servo Motors

Main feature for Servo motors used in robotic arm should have high
torque/weight ratio and instant response so as to lift heavy loads.
Specifications of servo motors used for robotic arms are shown below.
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PROJECT REPORT
5.2.1 HS-805 BB Servo

The HS-805BB is one monster of a servo. The HS-805 uses a heavy duty
nylon gear train and a heavy duty 10mm 15 tooth output shafts. The HS-805BB
develops enough torque to move just about anything so whether its a boat, or maybe
your just flinging a spike hammer. Whatever it may be the HS-805BB can move it
and move it fast.
Some of the motor specifications are given below;
Motor Type
3 Pole Ferrite
Bearing type
Dual Ball Bearing
Torque 4.8/6.0V 19.8/24.7kg

Speed 4.8/6.0V 0.19 / 0.14 second
Size
66 x 30 x 58 mm
Weight
152 g
5.2.2
HS-645 Mg Servo
The powerful HS-645MG is one of Hitecs most popular servos. Its the
perfect choice for those larger sport planes or monster trucks and buggies
requiring a durable high torque servo. Featuring our unique M/P and metal gear
train technology, the HS-645MG offers one of the strongest gear trains available
in any servo.
Some of the motor specifications are given below:
Motor Type
3 Pole Ferrite
Bearing type
Dual Ball Bearing
Torque 4.8/6.0V 8/10kg
Speed4.8/6
0.24 / 0.20 second
Size
40.39 x 19.56 x 37.59 mm
Weight
55g
5.2.3
HS-475HB SERVO
Is a durable and reliable servo that features one ball bearing and Karbonite
gear train. Karbonite is four times stronger than the standard nylon gears and even
after hundreds of thousands of cycles it will not show any signs of wear . With
single ball bearing, and powerful motor, the HS-475HB offers plenty of torque and
speed, and a sweet price. It's the perfect choice for any application where more
speed and torque are needed from a standard size servo.
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PROJECT REPORT
Motor Type
3 Pole Ferrite Motor
Operating Speed (4.8V)
0.23sec/60 degrees at no load
0.18sec/60 degrees at no load
Stall Torque 4.8V/6.0 V 61 oz/in.(4.3kg.cm)/ 76 oz/in.

(5.5kg.cm)
Dimensions
1.50" x 0.8"x 1.4" (41 x 20 x 37mm)
Weight
1.4oz (39g)
Complete specifications of the motor are detailed in appendix.
5.3 Hardware Design

To control robotic arm we were to control servo motors as movement of servo
motors causes the movement of robot links. Servos can be controlled using PWM
also called PCM modulation. We were to implement PCM using FPGA. The
program algorithm implementing PWM in FPGA is shown below.
1. User control
Manual Control
o Select the motor that is the be moved by the FPGA
o Increase the Pulse width (Duty cycle) using increment switch
or Decrease the Pulse width using the decrement switch
Automatic Control
o Take the states and the sequence as defined in the program
2. Take the motor pulse width from the part one and create a pulse of the
duration as specified by the PCM Variable for each motor.
5.3.1
Input to FPGA
Input was given to FPGA with the help of slide switches and push buttons
at the bottom of FPGA and clock was used for synchronization. These buttons
can represent the binary value that is 0 or 1.
Slide switches
The Spartan 3A/3AN FPGA Starter Kit board has four slide switches, as
shown in figure. The slide switches are located in the lower right corner of the
board and are labeled SW3 through SW0. Switch SW3 is the left-most switch,
and SW0 is the right-most switch.
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Figure 5- 2 FPGA Slide Switches
When in the UP or ON position, a switch connects the FPGA pin to 3.3V,

a logic High. When DOWN or in the OFF position, the switch connects the
FPGA pin to ground, a logic Low. The switches typically exhibit about 2 ms
of mechanical bounce. There is no active Debouncing circuitry, although such
circuitry could easily be added to the FPGA.
Push-Button Switches
The Spartan-3A/3AN Starter Kit board has four momentary-contact pushbutton switches, shown in figure. The push buttons are located in the lower
right corner of the board and are labeled BTN_NORTH, BTN_EAST,
BTN_SOUTH, and BTN_WEST. The FPGA pins that connect to the push
buttons appear in parentheses in figure.
Figure 5- 3 FPGA Push Buttons
Pressing a push button connects the associated FPGA pin to 3.3V, as

shown in Figure above. Use an internal pull-down resistor within the FPGA
pin to generate a logic Low when the button is not pressed. Figure velow
shows how to specify a pull-down resistor. There is no active Debouncing
circuitry on the push button.
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PROJECT REPORT
Clock sources
Clocks are used to produce synchronization for the generation of pulses.
The Spartan-3A/3AN Starter Kit board supports three primary clock input
sources, as shown.
The board includes an on-board 50 MHz clock oscillator.
Clocks can be supplied off-board via an SMA-style connector.
Alternatively, the FPGA can generate clock signals or other high-speed
signals on the SMA-style connector.
A 133 MHz clock oscillator is installed in the CLK_AUX socket.
Optionally substitute a separate eight-pin DIP-style clock oscillator in the
provided socket.
We selected 50 MHz clock oscillator for use in our program. The board
includes a 50 MHz oscillator with a 40% to 60% output duty cycle. The
oscillator is accurate to 2500 Hz or 50 ppm.
Figure 5- 5 FPGA Clocks

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PROJECT REPORT
5.3.2 Out put from FPGA

The output was taken out of the FPGA with the help of the panel of
transmitter pins in the J15 header. These are differential pairs which can
provide up to 6 differential pairs and 12 single ended outputs. We required 5
single ended outputs.
Differential I/O Connectors
The Spartan-3A/3AN Starter Kit board includes stake pin headers
with excellent signal integrity and matched impedance traces to
demonstrate high-performance differential I/O. Each differential pair
supports approximately 600 Mbits per second (Mbps) data rates. The J15
connector is primarily designed to transmit output data
Figure 5- 6 FPGA Differential I/O Connector Pins
Figure 5- 7 FPGA I/O Pins
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PROJECT REPORT
5.4 Level Shifting and Isolation

1. Voltage output of the pins is 3.3 volts but the servo motors require a signal
voltage of 5 volts.
2. In addition to the level shifting problem there is another problem that is of
isolation. The back EMF generated by the motor can hurt FPGA which are
low power sophisticated electronic devices.
To sort out this problem optocoupler (4N25) was used for level shifting as
well as for isolation. The Optocoupler 4N25 IC pin configuration is shown in
figure. It utilizes a photo transistor and a light emitting diode.
Figure 5- 8 4N25 Connection Diagram
The general purpose optocoupler consist of a gallium arsenide infrared

emitting diode driving a silicon phototransistor in a 6-pin dual in-line package.
They can isolate a voltage as high as 7500 volts (peak ac).
Now to get the output pulse from the FPGA we connect the motors of
robotic arm to the FPGA transmit header pins. But as explained above it is
done with optocoupler. Witch isolates the motor circuit from the FPGA
transmit header. The transmit header connected with optocoupler is shown in
figure.
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PROJECT REPORT
Figure 5- 9 FPGA Interface using 4N25
Here in figure vin 3.3V is the output of the FPGA. Whis is to be shifted to
5V and is given to the motors.
Vout is the output of the opto coupler that is isolated from the input or
FPGA output. R1 and R2 are small resistances of ohms and 220ohm
respectively. As the program downloaded in the FPGA uses the PWM. That
generates pulses of 3.3V that is shown in figure. Now these 3.3 V when given
to the opto coupler then pulse output for the motors is shown in figure.
Figure 5- 10 Input and Output Pulses
There is a problem with the configuration; this configuration is a common

emitter configuration which is inverting configuration. So output is the
inverted replica of the input. So the pulse that is required by the servos in the
robotic arm is not the one that is required. Now here are to option to get the
required pulse for the servos of robotic arm.
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PROJECT REPORT
1. Again invert the output of optocoupler

2. Change the coding to get the FPGA output already inverted so that the
optocoupler invert this FPGA output to make them useable for servos.
The second option was best suited and was too easy. Just changing the
code is batter than using another inverter inform of coupler. After changing
the code we get these kinds of pulses at the input and the output of the
optocoupler as shown in the figure.
Figure 5- 11 Input out pulses after changing code
5.5 Robotic arm interface

Now we can see the Vout is the one that is required. It is isolated from
the fpga output and the other importand thing is that the voltage level is
shifted to 5v too. Now this is available to be given to the sevos of the
robotic arm.
The next important thing is the servo motor requires separate power to
besides the PWM signal. This power makes the servo motor respond to the
PWM control signal. Here in our project as mentioned earlier we used the
dc servo motors that require 5 volts. So 5 volt dc is separately provided to
all of the 5 motors with the control PWM signal. After the 3 signals are
provide (power ground and PWM signal) to all motors. And the code is
downloaded to the FPGA then the arm is ready to work according to the
code designed.
The next interface is the robotic Aram interface with the servo motors
of the robotic arm. In the arm we have 5 motors. So we need to get 5
different PWM signals for all the motors. Now all these motor signals are
given to the motors using optocoupler in the way that is mentioned above.
So we need 5 couplers carrying 5 PWM signals for the 5 motors.
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PROJECT REPORT
CHAPTER 6
FUTURE DEVELOPMENT
The application developed here in our project is just the pick and drop. We
can pick and drop using manual control and the automatic control. Here we will
discuss some improvements that can be made in this project. When using manual
control for pick and drop application we have selection mechanism. We used
switches located at FPGA to select a particular motor out of five in the robotic
arm. We used three switches to select one servo. Now here using this selection
mechanism only one motor can be operated at a time. More than one motor can
also be operated at the same time manually. But the need is to have nearly 10
switches/pushbuttons and of course we dont have too much switches. So here the
improvement that can be made is to use the receiver header of FPGA. The header,
that allows the pin connections from which we can give signals to FPGA. And by
designing an external control circuit containing buttons or switches that can give
control signals to FPGA and appropriate code for the PWM we can move all the
servos of robot at the same time, it means all the parts can be moved at the same
time. So in short there is a possibility to improve the manual pick and drop
application.
Secondly the most important field in robotics is the kinematics both
forward and reverse kinematics. In our project we didnt included them because
those are related to the physics of motion and is more related to the mechanical
engineering. But, for future improvement it should be included in the project.
Now if we consider the automatic control. Then this pick and drop
application can further be improved by using a camera on the top of wrist motor
of the robot. The FPGA as we know is batter suited for image processing. So
proper coding of FPGA and camera with the robot arm can be used to provide
color selection pick and drop application. Color sorting shape sorting and similar
to these applications can be developed. Of course the better coding can made the
robotic arm intelligent. That is the need today.
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PROJECT REPORT
APPENDIX A
VHDL Code for Robotic Arm Control
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Servo_Timing is
Port (
Clock : in STD_LOGIC;
s1,s2 : in STD_LOGIC;
sel0, sel1, sel2,sel3: in STD_LOGIC;
Pulse1 : out STD_LOGIC;
Pulse5 : out STD_LOGIC
);
end Servo_Timing;
architecture Behavioral of Servo_Timing is
signal width1 :Integer range 100 to 500;
begin
process(Clock)
variable w1: integer range 100 to 500:=190;
variable tmp: integer range 0 to 499;
variable Counter : integer := 800000;
begin
if( rising_edge(Clock) ) then
counter:=counter-1;
if (counter=0) then
counter:=800000; -- execute hoe her 20ms ka bad
tmp:=tmp-1;
-- normal state
if (sel3='0' and sel0='1' and sel1='1' and sel2='1') then
w1:=190;
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w2:=280;
w3:=280;
w4:=1100;
w5:=320;
end if;
-- 1st servo control PWM-if (sel3='0' and sel0='0' and sel1='0' and sel2='0' and s1='1' and w1<420) then
-- this is done to ensure thar grip does not expand much so drop it from 480 to 420.
w1:=w1+1;
elsif(sel3='0' and sel0='0' and sel1='0' and sel2='0' and s2='1' and w1>185)
then
w1:=w1-1;
end if;
-- 2nd servo control PWM-if (sel3='0' and sel0='0' and sel1='0' and sel2='1' and s1='1' and w2<440) then
-- this is done to ensure that servo does not get grip out of limit upwords
w2:=w2+1;
then
w2:=w2-1;
end if;
-- 3rd servo control PWM-if (sel3='0' and sel0='0' and sel1='1' and sel2='0' and s1='1' and w3<460) then
w3:=w3+1;
then
w3:=w3-1;
end if;
-- 4th servo control PWM-if (sel3='0' and sel0='0' and sel1='1' and sel2='1' and s1='1' and w4<1280)
then -- this is dine that servo setup remins upwords
w4:=w4+1;
then
w4:=w4-1;
end if;
-- 5th servo control PWM-if (sel3='0' and sel0='1' and sel1='0' and sel2='0' and s1='1' and w5<480) then
w5:=w5+1;
then
w5:=w5-1;
end if;
if (sel3='1') then
case tmp is
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when 498 => w5:=240;

when 445 => w4:=960;
when 429 => w3:=330;
when 402 => w2:=280;
when 348 => w1:=210; -- pick
when 297 => w2:=350;
when 275 => w3:=404;
when 263 => w4:=990;
when 197 => if (sel0='0') then
w5:=400;
elsif (sel0='1') then
w5:=440;
end if;
when 185 => w4:=960;
when 155 => if (sel0='0') then
w3:=330;
elsif (sel0='1') then
w3:=300;
end if;
when 132 => w2:=280;
when 110 => w1:=380; -- drop
when 85 => w2:=350;
when 70 => w3:=404;
when 55 => w4:=990;
when others => null;
end case;
end if;
end if;
end if;
width1<=w1;
width2<=w2;
width3<=w3;
width4<=w4;
width5<=w5;
end process;
-- 1st servo control PWM-process (Clock)

Variable Pulse_Count_Start1 : integer;
Variable Pulse_Count1
: integer;
Variable Sync1
: integer := 4000;
Variable Sync_Start1
: integer;
variable Counter1
: integer := 250;
variable Pulses1
: std_logic;
begin
Counter1 := Counter1-1;
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if( Counter1 = 0 ) then

Counter1 := 250;
if( Pulse_Count1 = 0) then
Pulses1 := '0';
Pulse1 <= not Pulses1;
if( Sync1 = 0) then
pulse_count_start1:=width1;
Pulse_Count1 := Pulse_Count_Start1;
else
Sync1 :=Sync1-1;
end if;
else
Pulse_Count1 := Pulse_Count1-1;
Sync_Start1 := 4000 - Pulse_Count_Start1;
Sync1 := Sync_Start1;--oper Chula jaye ga
Pulses1 := '1';
end if;
end if;
end if;
end process;
-- 2nd servo control PWM-process (Clock)
: integer;
Variable Sync2
: integer := 4000;
: integer;
variable Counter2
: integer := 250;
variable Pulses2
: std_logic;
begin
Counter2 := 250;
Pulses2:= '0';
if( Sync2 = 0) then
else
Sync2 :=Sync2-1;
end if;
else
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Sync2 := Sync_Start2;
Pulses2 := '1';
end if;
end if;
end if;
end process;
-- 3rd servo control PWM-process (Clock)
: integer;
Variable Sync3
: integer := 4000;
: integer;
variable Counter3
: integer := 250;
variable Pulses3
: std_logic;
variable abc: integer;
begin
Counter3 := 250;
Pulses3 := '0';
if( Sync3 = 0) then
else
Sync3 :=Sync3-1;
end if;
else
Pulses3 := '1';
end if;
end if;
end if;
end process;
-- 4th servo control PWM-process (Clock)
: integer;
Variable Sync4
: integer := 4000;
Page 73
variable Counter4
variable Pulses4
PROJECT REPORT
: integer;
: integer :=250;
: std_logic;
begin
Counter4 := 250;
Pulses4 := '0';
Pulse4<= not Pulses4;
if( Sync4 = 0) then
pulse_count_start4:=width4/4;
else
Sync4 :=Sync4-1;
end if;
else
Pulses4:= '1';
end if;
end if;
end if;
end process;
-- 5th servo control PWM-process (Clock)
: integer;
Variable Sync5
: integer := 4000;
: integer;
variable Counter5
: integer := 250;
variable Pulses5
: std_logic;
begin
Counter5 := 250;
Pulses5 := '0';
Pulse5 <= not pulses5;
if( Sync5 = 0) then
Page 74
PROJECT REPORT
else
Sync5 :=Sync5-1;
end if;
else
Pulses5 := '1';
end if;
end if;
end if;
end process;
end Behavioral;
User Constraint File (UCF File)

NET "Clock" LOC = E12;
NET "Pulse1" LOC = AB2;
NET "Pulse2" LOC = AB3;
NET "Pulse3" LOC = AA6;
NET "Pulse4" LOC = Y7;
NET "Pulse5" LOC = AA8;
NET "s1" LOC = T15;
NET "s2" LOC = T16;
NET "sel0" LOC = U8;
NET "sel1" LOC = U10;
NET "sel2" LOC = V8;
NET "sel3" LOC = T9;
Page 75
PROJECT REPORT
APPENDIX-B
HS 475-HB Standard Deluxe Servo
Operation voltage range
4.8 to 6.0 V
Test Voltage
4.8 V
Operating Speed
0.23 sec/60 degree To 0.18 sec/degree at No Load
Stall Torque
4.4Kg.cm To 5.5Kg.cm
Idle Current
7.4 mA at Stop & 7.7 mA at No Load
Running Current
160 mA /60 degree to 180 mA /60 degree at No Load
Stall Current
900 mA To 1100 mA
Dead Bandwidth
5 usec
Direction
Clockwise Pulse Travelling at 1500 at 1900 us
Motor Type
Cored Metal Brush
Potentiometer Type
Indirect Drive
Amplifier Type
Analogue Controller And Transistor Driver
Connector Wire Gauge
22AWG
Weight
40g
Ball Bearing
Top/MR106
Gear Material
Heavy Duty Resin
Page 76
PROJECT REPORT
HS-805BB Servo
Required Pulse
3-5 Volt Peak to Peak Square Wave
Operating Voltage
4.8-6.0 Volts
Operating Temperature Range
20 to +60 Degree C
0.19sec/60 at no load
Operating Speed (6.0V
Stall Torque (4.8V)
274.96 oz/in. (19.8kg.cm)
Stall Torque (6.0V)
343.01 oz/in. (24.7kg.cm)
Operating Angle
45 Deg. one side pulse traveling 400usec
Direction
Clockwise/Pulse Traveling 1500 to 1900usec
Current Drain (4.8V
8mA/idle and 700mA no load operating
Current Drain (6.0V
8.7mA/idle and 830mA no load operating
Dead Band Width
8usec
Motor Type
3 Pole Ferrite
Potentiometer Drive
Indirect Drive
Bearing Type
Dual Ball Bearing
Gear Type
All Heavy Duty Nylon Gears
Page 77
PROJECT REPORT
Hs-645MG Standard Ultra Torque Servo

Required Pulse
3-5 Volt Peak to Peak Square Wave
Operating Voltage
4.8-6.0 Volts
Operating Temperature Range:
-20 to +60 Degree C
Operating Speed (6.0V):
Stall Torque (4.8V)
106.93 oz/in. (7.7kg.cm)
Stall Torque (6.0V
133.31 oz/in. (9.6kg.cm)
Operating Angle
45 Deg. one side pulse traveling 400usec
Direction
Clockwise/Pulse Traveling 1500 to 1900usec
Current Drain (4.8V):
Current Drain (6.0V):
Dead Band Width
8usec
Motor Type
3 Pole Ferrite
Potentiometer Drive:
Indirect Drive
Bearing Type
Dual Ball Bearing
Gear Type
3 Metal Gears and 1 Resin Metal Gear
Page 78
PROJECT REPORT
REFRENCES
Charles H. Roth, Jr. (1997) Digital System Design Using VHDL, PWS
Publishing Company, pp 265-283
Clive "Max" Maxfield, (2009), FPGA: World Class Design, pp 4-102
Douglas L. Perry, McGraw-Hill, (2002), VHDL: Programming by Example,
4th edition, pp 173-201
Steve Kilts, Wiley-IEEE, (2007), Advanced FPGA Design Architecture,
Implementation and Optimization, pp 37-46
Voleni A. Pedroni, (2004) Circuit Design with VHDL, MIT Press Cambridge,
Massachusetts, pp 13-84
http://www.crustcrawler.com
http://www.fpga4fun.com/
http://www.seattlerobotics.org/guide/servos.html
http://www.xilinx.com
Page 79

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ROBOTIC ARM CONTROL THROUGH FPGA

MUHAMMAD MAJID ALTAF

MUHAMMAD WAQAS BASHIR

DEPARTMENT OF ELECTRICAL ENGINEERING

ROBOTIC ARM CONTROL THROUGH FPGA

A thesis submitted in partial fulfillment of the requirement of the Degree of

Design & Implementation of FPGA Based

Bachelor of Science in Electrical Engineering from University College of

MUHAMMAD WAQAS BASHIR

EXTERNAL EXAMINER ___________________________________

DEPARTMENT OF ELECTRICAL ENGINEERING

ROBOTIC ARM CONTROL THROUGH FPGA

ROBOTIC ARM CONTROL THROUGH FPGA

ROBOTIC ARM CONTROL THROUGH FPGA

Electrical Engineering Department.

ROBOTIC ARM CONTROL THROUGH FPGA

A robotic arm is a robotic manipulator, usually programmable, with

ROBOTIC ARM CONTROL THROUGH FPGA

Figure 1-1 Robotic Arm

Figure 1-2 Basic Robot Parts

Figure 1-3 Application of Robots in Space

Figure 1-4 Robotics in Bomb Disposal

Figure 2- 1 Robot Links

Figure 2- 2 Two Dimensional Robot Workspace

Figure 2- 3 Three Dimensional Robot Workspace

Figure 3- 1 FPGA Insight

Figure 3- 2 FPGA vs ASIC/Custom Microprocessor Design

Figure 4- 1 Servo Motor Block Diagram

Figure 4- 2 Components of a Servo Motor

Figure 4- 3 Servo Motor Pulse vs Position

Figure 4- 4 Performance Characteristics of Servo Motor

Figure 4- 5 DC Servo Motor with Position Control System

Figure 4-6 Structure of PAL & PLA

Figure 4- 7 Structure of CPLD

Figure 4- 8 FPGA types w.r.t. their Memory

Figure 4- 9 EPROM Memory Cell

Figure 4- 10 EEPROM Memory Cell

Figure 4- 11 SRAM Based Memory Cell

Figure 4- 12 FPGA Architecture

Figure 4- 13 Row Based Architecture

Figure 4- 14 Hierarchical PLDs

Figure 4- 15 XILINX Logic Block

Figure 4- 16 LUT Architecture

Figure 4- 17 Logic Pin Block Location

ROBOTIC ARM CONTROL THROUGH FPGA

Figure 4- 18 Logic Block Pin to Routing Channel Interconnect

Figure 4- 19 Un-segmented FPGA Routing

Figure 4- 20 Switch Bus Topology

Figure 4- 21 Programmable logic design process

Figure 4- 22 VHDL Evolution & Progress

Figure 4- 23VHDL Sample Code

Figure 4- 24 VHDL Levels of Abstraction

Figure 4- 25 VHDL Design Methodology

Figure 5-1 SPARTAN-3A FPGA

Figure 5- 2 FPGA Slide Switches

Figure 5- 3 FPGA Push Buttons

Figure 5- 4 Push Button Switch Internal Diagram

Figure 5- 5 Push Button Switch Internal Diagram

Figure 5- 5 FPGA Differential I/O Connector Pins

Figure 5- 6 FPGA I/O Pins

Figure 5- 7 4N25 Connection Diagram

Figure 5- 8 FPGA Interface using 4N25

Figure 5- 9 Input and Output Pulses

Figure 5- 10 Input out pulses after changing code