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79
3 authors, including:
Lionel R Orama
University of Puerto Rico at Mayagez
13 PUBLICATIONS 25 CITATIONS
SEE PROFILE
I. INTRODUCTION
V2
(MW)
(3)
Zc
where V is the voltage in kV and Zc is the characteristic
impedance of the line in ohms.
When a line is terminated with a load of equivalent
impedance equal to Zc, then the line is operating at is SIL level
and the voltage profile across the line is flat. However, when
the load impedance is greater than Zc, the line is lightly loaded
and the receiving end voltage is greater than the sending end
voltage, and viceversa. It is not practical to hold the load at
the SIL level; especially with the objective to increase the
power transfer among interconnected areas. The SIL can be
increased by decreasing the line reactance, i.e., inserting series
capacitors [2].
X L X Cs
X L (1 k )
(4)
Z comp =
=
= Zc 1 k
BC
BC
Pn 0 = SIL =
Pn =
Pn 0
(5)
1 k
where k is the degree of series compensation and Xcs is the
reactance of the series capacitor. Thus, the increasing of the
degree of compensation results in lower characteristic
impedance and higher SIL.
VR ( 2
Vs (1
With Compensation
Without Compensation
1.8
1.6
1.4
1.2
Power (pu)
1
0.8
P-load
0.6
0.4
0.2
0
0
0.5
1.5
2
Angle (radianes)
2.5
3.5
XL
Fig. 1. Equivalent network configuration for two interconnected systems
Vs (1
XL
XC
XL
series reactance in lines 1-5 and 4-5 are proposed. The result
is a considerable reduction in the apparent power that flows
on line 1-2 as well as a considerable improvement in the
power transfer of line 1-5 and 4-5, as shown in Table 1. All
other lines are also affected by the installation of series
compensation, especially those lines that are in the
neighborhood of the compensated lines. However, with the
installation of this type of compensation, the voltage profile
across the system is practically unaffected. The effectiveness
of the series compensation improving the power transfer
capability of the transmission line is demonstrated with this
simple case.
IV. TRANSIENT ANALYSIS
Fig. 7. ATP model for the modified IEEE-14 bus test system
120.81
94.59
100
59.81
86.17
100
73.86
68.63
100
46.56
35.34
100
34.06
25.84
50
33.45
38.93
50
53.48
71.70
100
30.77
30.24
50
4.96
4.70
50
14.26
15.03
50
11
19.90
19.57
50
12
17.17
17.12
50
13
41.01
40.82
50
88.40
88.46
100
58.32
58.76
100
10
10.45
10.66
50
50
14
18.60
18.82
10
11
11.23
10.91
50
12
13
4.10
4.07
50
13
14
14.05
13.82
50
B. Capacitor reinsertion
The second case analyzed is a modification of the original
case to consider the capacitor reinsertion with a trapped
charge after the fault on line 1 5 is cleared locally in 4.16 ms
by opening the breaker S1-1, and remotely by opening the
breakers S2-1 9.16 ms. The one line schematic for this case
is shown in Figure 12.
300
[kV]
200
100
-100
-200
-300
-400
0
10
v:X0076B-X0077B
15
20
25
[ms]
v:X0076C-X0077C
900
[kV]
700
700
500
[kV]
300
440
100
180
-100
-300
-80
-500
-700
0.00
0.02
0.04
v:X0077B-X0122B
0.06
0.08
0.10
[s]
-340
v:X0077C-X0122C
-600
0.00
0.02
0.04
v:X0077B-X0095B
0.06
0.08
[s]
0.10
v:X0077C-X0095C
200
300
[kV]
[kV]
150
200
100
100
50
-100
-200
-50
-300
-100
-400
-150
0.00
0.02
0.04
v:X0124B-
0.06
0.08
[s]
v:X0124C-
0.10
-500
0.00
0.02
0.04
v:X0076B-X0077B
0.06
0.08
v:X0076C-X0077C
[s]
0.10
300
[kV]
200
100
-100
-200
-300
-400
-500
59.99
60.00
60.01
60.02
v:X0076B-X0077B
60.03
60.04
60.05
[ms]
60.06
v:X0076C-X0077C
150
[kV]
100
200
50
100
0
-50
-100
-100
-150
0.00
0.02
0.04
v:X0134B-
0.06
0.08
[s]
0.10
v:X0134C-
-200
-300
0.00
0.02
0.04
v:X0076B-X0077B
0.06
0.08
[s]
0.10
v:X0076C-X0077C
110
20
-160
-250
0
11
22
v:X0077B-X0140B
33
44
[ms]
v:X0077C-X0140C
55
8
200
104.1
[kV]
U [kV]
150
100
95.3
50
86.5
-50
77.8
-100
-150
I [kA]
69.0
-200
0.00
0.02
0.04
v:X0142B-
0.06
0.08
[s]
0.10
1.5
v:X0142C-
11.1
20.8
30.4
40.0
Fig. 21. Non linear characteristic of the arresters installed in parallel of the
series capacitor banks
300
[kV]
200
100
-100
-200
0.00
0.02
0.04
v:X0076B-X0077B
0.06
0.08
[s]
0.10
[s]
0.10
v:X0076C-X0077C
100
-100
-200
-300
0.00
0.02
0.04
v:X0077B-X0126B
0.06
0.08
v:X0077C-X0126C
5
[MA]
V. CONCLUSIONS
0
0.00
0.02
0.04
c:X0302B-X0077B
0.06
0.08
[s]
0.10
c:X0302C-X0077C
Fig. 24. Energy dissipation for arresters installed in parallel with the series
capacitors
100
50
-50
-100
-150
0.00
0.02
0.04
v:X0128B-
0.06
0.08
[s]
v:X0128C-
E. Summary of results
Table 2 presents a summary of the results obtained with the
case studies. The results are compared with rated values
provided in the standard of preferred ratings and related
required capabilities of AC High-Voltage breakers [16].
TABLE II
COMPARISON OF RESULTS
TRV
RRRV
Load
Case
Peak Value
Peak Value
Standard
(kV)
(kV/s)
(kV/s)
(kV)
840.68
3.220
2.0
150.9
684.17
2.469
2.0
200.2
212.25
1.656
2.0
176.1
203.05
0.848
2.0
144.4
0.10
[3]
Peak Value
[4]
[5]
[6]
[7]
[8]
[9]
10
Transmission System," Proceedings of the International Conference on
Power System Transients (IPST'01), pp. 1-6, June 2001.
O. Trad, G. Ratta, and M. Torres, "Experiences in Setting Protection of
Series Capacitor Compensated Lines," Proceedings of the International
Conference on Power System Transients (IPST'01), pp. 1-6, June 2001.
Q. Bui-Van, E. Portales, D. McNabb, and V. Gajardo, "Transient
Performance of 500-kV Equipment for the Chilean Series-Compensated
Transmission System," Proceedings of the nternational Conference on
Power System Transients (IPST'03), pp. 1-6, October 2003.
IEEE
14-bus
test
system
data
available
at:
http://www.ee.washington.edu/research/pstca/
Puerto Rican Electric Power Authority Standard of Construction of
Overhead Transmission Lines, May 1992.
R. Zimmerman, D. Gan, Matpower 3.0, PSERC Cornell University,
USA,
December
1997.
Available
at:
http://www.pserc.cornell.edu/matpower/
ABB Metal Oxide Surge Arresters EXLIM P, ABB Electrical
Apparatus, May 2005.
AC High-Voltage Circuit Breakers Rated on a Symmetrical Current
Basis Preferred Ratings and Related Capabilities, ANSI Standard
C37.06.2000, May 2000.
[10]
[11]
[12]
[13]
[14]
[15]
[16]
From
To
1/2 B
MVA
Limits
0.0194
0.0592
0.0264
100
0.0540
0.2230
0.0246
100
3
4
2
2
3
4
0.0470
0.0581
0.1980
0.1763
0.0219
0.0187
100
100
0.0570
0.1739
0.0170
50
0.0670
0.1710
0.0173
50
0.0134
0.0421
0.0064
100
0.0000
0.2091
0.9780
50
0.0000
0.5562
0.9690
50
10
0.0000
0.2520
0.9320
50
11
11
0.0950
0.1989
0.0000
50
12
12
0.1229
0.2558
0.0000
50
13
13
0.0662
0.1303
0.0000
50
14
0.0000
0.1762
0.0000
100
15
0.0000
0.1100
0.0000
100
16
10
0.0318
0.0845
0.0000
50
17
14
0.1271
0.2704
0.0000
50
18
10
11
0.0821
0.1921
0.0000
50
19
12
13
0.2209
0.1999
0.0000
50
20
13
14
0.1709
0.3480
0.0000
50
TABLE A.II
BUS DATA
Bus
Qc
(MW)
(MVAr)
(MVAr)
43.4
25.4
188.4
38.0
95.6
-7.8
44.7
19.8
20
22.4
15.0
29.5
16.6
10
10
18.0
11.6
11
7.0
3.6
12
12.2
3.2
13
27.0
11.6
14
29.8
10.0
TABLE A.III
GENERATOR DATA
Bus
Voltage
Qmax
Qmin
MW
MVAr
MVAr
1.06
100
1000
-1000
1.045
80
1000
-1000
1.01
84
1000
-1000
1.07
100
1000
-1000
1.09
86
1000
-1000