DATA CONVERTERS

MID-SEM REPORT

Rohit Goel | BITS F421 | October 6, 2016

Modern Systems
Most of the modern day systems consist of a Digital Signal Processor, A/d conversion circuits, d/a
conversion circuits. Thanks to Advances in digital signal processing all the processing can now be
done in digital domain.

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But as real world is analog a/d , d/a circuits become extremely important as they have to match the
performance of digital signal processors (which are becoming faster) to not become a bottleneck in
the entire system.

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Analog to digital converter

Analog signals can take any value and are defined at every
instant of time however digital signals are defined at
certain instants of time and can only take limited number
of values.
Due to this the analog signals are first sampled and then
quantized.
Depending on the architecture used and the desired
output different encoding schemes are employed.

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011/slides/slide_4.jpg

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Sampling
We are already aware of multiple sampling schemes.
Ideal sampling
Sampling using an impulse train.

3http://blog.oureducation.in/wpcontent/uploads/2013/10/Ideal-SamplingWave-form.gif

Zero order hold

Sampling instantly and holding that value
for 1 clock cycle.

Both of the above sampling techniques

should work in an ideal world.

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mons/thumb/1/15/Zeroorderhold.signal.svg/220
px-Zeroorderhold.signal.svg.png

But both of the above techniques requires the input to be captured instantly and hence cannot be
used in the real world.

Track and Hold

Track and hold is the techniques which can be implemented in
the real world using a capacitor to store the voltage.
For half cycle the output tracks the input and next half output
holds the final value

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p-content/uploads/2011/06/inputand-output-waveforms.png

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Sample and Hold Architectures

PERFORMANCE MATRICES
The following performance matrices will be used to characterize the sample and hold circuits.

Acquisition time the time required after sampling command to settle within specified
error limit
Hold time time required after hold command to settle.
Dynamic range maximum input range / minimum input level
Nonlinearity error
Aperture jitter
Pedestal error voltage error introduced after hold command (usually due to charge
injection)
Gain error
Hold mode feed through even in hold mode some signal may pass through due to
parasitic capacitances
Droop rate degradation in stored voltage over time
Signal to noise ratio
Signal to noise-distortion ratio

The following images help in understanding the concepts better

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ARCHITECTURES
Open loop sample and hold

Benefits

Simplicity

Drawbacks

Node x takes full input and output swing

o Makes design of b1 , b2 complex
o Input dependent charge injection takes place

The speed of b1 plays an important role for acquisition time.

Closed loop architecture

Two stage opamp buffer is used to store charge on miller capacitor.

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Benefits

We know from opamp theory that the above configuration in track mode employs unity
feedback which reduce the swing on x making it a virtual ground.
o No more input dependent charge injection
o Simplifies the design of gm and 2nd stage

Drawbacks

Usually two pole systems introduce multiple poles and compensating all of them reduces
the speed
Output capacitance may destabilize the system limiting the use to on chip ADC.

Only used in high precision but slow circuits.

THE ABOVE ARCHITECTURES ARE BASED ON REDUCING THE SWING AT THE SWITCH
TANSISTOR TO REDUCE PEDESTIAL ERROR VOLTAGE
THE OTHER EFFICIENT WAY TO DEAL WITH THE SAME PROBLEM IS TO USE DIFFERENT
CAPACITORS FOR TRACKING AND HOLDING

OPEN LOOP MILLER CAPACITOR ARCHITECTURE

In tracking mode the capacitance at node z is c1 + c2

In the hold mode switch m1, m2 open and the final
capacitance is A*c2 (A being gain of opamp)
Benefits

Input dependent charge injection leads to very

less voltage due to high capacitance

Charge injected by m2 is not input dependent as

swing on it is negligible due to feedback

Voltage swing on opamp is low hence high speed

design is possible

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Multiplexed-input architecture

In this architecture input and output are multiplexed at the input to get smaller charge injection
Gm1*r=gm2*r=1
In track mode Vout follows Vin as gm1*r=1
In hold mode gm2*r=1 and vout is retained
Benefits

Charge injected by gm1 is absorbed by gm2

Easy implementation
o Gm1,gm2 as diff pairs multiplexed by a third diff pair
o Often results in high speed circuit

Drawbacks

Gm1 , gm2 should be very precisely monitored as droop rate and acquisition time have a
tradeoff controlled by accuracy of gm2
o Matched devices must be used to overcome it

Switched capacitor architecture

Acquisition mode S1, S2 are on
Transition mode
1. S2 turns off
2. S1turns off , s3 turns on
This leads to voltage being stored on Ch

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Benefits

As S2 turns of first the input dependent charge injection from S1 is not seen on capacitor
Variation in output capacitance wont make the circuit unstable
Simplicity makes it popular for uses employing many SHAs at the same time

Drawbacks

S1 experiences full input swing and introducing input dependent delay

Performance degrades with resistive loads limiting the use to on chip adcs

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Bibliography
1.
2.
3.

Principles of Data Conversion System Design - Behzad Razavi.

DATA ACQUISITION SYSTEM FOR A 1-GHz DIGITIZING OSCILLOSCOPE k rush
Charge Injection in Analog MOS Switches GEORGE WEGMANN

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