1

INTRODUCTION
1.1 MOSFET Metal Oxide Semiconductor Field Effect Transistor
MOSFET Field effect transistor is a unipolar transistor, which acts as a voltagecontrolled current device and is a device in which current at two electrodes drain and
source is controlled by the action of an electric field at another electrode gate having
in-between semiconductor and metal very a thin metal oxide layer.
For any type of MOSFET, the gate voltage modulates the conductivity of the ptype channel by raising or lowering the height of an energy barrier between the source
and channel. Under low drain voltages the device operates like a resistor with the gate
voltage controlling the resistance, while under high drain bias, the device operates like
a current source with the gate voltage controlling the magnitude of the current. The
transistor designer's challenge is to engineer an appropriate energy barrier between the
sources and drain so that the device can be turned off while at the same time designing
a gate structure that can effectively modulate the barrier and turn the transistor on. The
design of a bulk MOSFET for proper electrical performance involves producing
sophisticated two-dimensional doping profiles in the p-type channel, an ultrathin gate
oxide, and heavily doped, ultra-shallow source/drain extensions. Double gate, tri-gate,
and gate-all-around MOSFETs provide strong gate control of the channel conductivity,
which allows the source and drain to be placed more closely. The channel length, L,
sets the scale of the device. Device scaling refers to the process of shrinking L to
reduce the device size, but a complete MOSFET is typically 10-15 times larger than L.
The associated dimensions (oxide thickness, shallow extension junction depth, etc.)
also need to be reduced accordingly to maintain good electrical characteristics.
The drain current, I d vs. drain-to-source voltage, Vds, characteristics of the
MOSFET. On a linear scale, essentially no current flows until the gate voltage reaches
a critical value, the threshold voltage, VT. For low VDS, the MOSFET operates like a
gate voltage dependent resistor, but for high VDS, it operates more like a gate voltage
controlled current source (with a finite output conductance). The voltage that separates
these two regions is the so called "drain saturation voltage," VDsat.

Figure: 1.1: Id vs. Vds characteristics of the MOSFET

Figure: 1.2: N-channel enhancement type

MOSFET

Planar MOSFET
The last decade has witnessed tremendous innovation in transistor architecture
with the introduction of strained silicon channel, high-k/metal gate stack and non
planar 3D transistor architecture, marking the end of the era of the traditional planar
2

transistors calling. A power limited era has begun where new materials and new
switching mechanisms need to be embraced with the framework of 3D transistors to
continue the relentless forward march of technology in shrinking transistors and
integrating more functionality on silicon to produce ever higher- performance and
more energy efficient computational and memory devices.

1.2

MOSFET Scaling and VLSI(road map)

Figure 1.3: Evolution of microelectronics devices since the invention of

integrated circuits in 1958. On the double Y-axis, the number of
transistors per chip (on the left hand side) and their critical dimension
(gate length) (right hand side) are reported. Fabrication technology
(arrows) and System (bubble) innovations are indicated.

Since the invention of the rst electronic calculation machines,

miniaturization has been a constant challenge to increase the speed and to improve the
package density by the microelectronics industry.
Electronic devices have brought, and will bring in the future, a far
increasing number of new functions to the basic computing systems such as fast data
computing, telecommunication, and several kinds of actuations which are collectively
fabricated on the same physical object named as the solid state circuit, the integrated
circuit or the chip. Electronic devices are so small, that billions of basic functions are
3

accessible in a hand held system. Moreover, their unit cost has been divided by more
than a factor of 100 million over the past 30 years! The collective fabrication of
electronic devices coupled with the increase of their speed has given a tremendous
success, which is unique in the history of mankind, to Micro and nano electronics by
continuously introducing innovations in the fabrication process. Linear scaling of the
device dimensions to a quasi-nanometres level allows building a complex system
integrated on a chip which reduces drastically their volume and power consumption
per function, whilst tremendously increasing their speed.At present, in highperformance processor technology, the physical gate length of a transistor is reaching
into the sub-100 nm regime with a gate oxide thinner than 20 . In research
laboratories, transistors are being fabricated which might be the prototypes of the last
generation of CMOS devices based on the conventional structures and the
materials. Conventional scaling based on the reduction of feature sizes obviously
cannot continue forever.
The aggressive scaling of the CMOS technology in the deep sub micrometer
regime gives rise to the short channel effects (SCEs). The various undesirable SCEs
are the threshold voltage roll-off, the channel length modulation, the drain induced
barrier lowering (DIBL), the punch through, the velocity saturation, the increased sub
threshold leakage, the transconductance degradation, the increased parasitic
capacitances etc. Analog performance parameters like the intrinsic gain,
transconductance generating factor, the early voltage, the output resistance etc. are
greatly affected by the SCEs. The undesirable mobility degradation and increased
parasitic capacitances drastically reduce the device transconductance, the voltage gain
and the noise performance. Another major concern with scaling is the increased offstate leakage current which in turn increases the power dissipation.

Importance for VLSI

Low fabrication cost, small size, low power consumption.

Applications
Microprocessors, memories, power devices.

Basic Properties
Unipolar device; Very high input impedance; Capable of power gain3/4 terminal
device, G, S, D, B; Two possible device types: enhancement mode; depletion mode;
Two possible channel types: n-channel; p-channel.

1.3

Justification of the work

Scaling means to preserve the magnitude of the internal electric field in the
MOSFET, while the dimensions or area of MOSFET are decreased by the factor of S.
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To get such scenario the most widely use approaches is Constant Field Scaling
proposed by Den nard at all. With the reducing size the circuit speeds also increased
by the factor of S and the circuit density also increased by S2. And the most sweets
result of scaling is that the power dissipation is reduced by S2. However, this
downscaling trend creates various second order effects and the fundamental physical
limitations. These effects arise due to the velocity saturation, the non-scaling of the
sub threshold slope and the built-in potential of the source/drain to body junctions, the
quantum effects, the poly depletion effects, and the high-field effects etc. For CMOS
digital applications, the transistor efficiency is mainly determined by the on-current
(Ion) i.e. the current after threshold voltage and the off-current(I off) i.e. the current
before threshold voltage requirements of the device. Under sub 100 nm regimes, the
scaling technology faces increasing Ioff due to drain induced barrier lowering (DIBL)
and the gate tunneling. In the other side, the Ion current not increases sufficiently due
to reduced carrier mobility. Hence the main objective for the device design in logic
circuit is to increase the value of Ion/Ioff.
The effects of miniaturization of the device degrade the factors like Saturation
Current, Trans conductance generation factor (gm/Id), Intrinsic Gain (gmr0) , these are
very important for analog circuit performance.
Apart from these, degradation in the cut-off frequency or unity current gain
fT

f max

frequency ( ), the unity power gain frequency (

) and the maximum available
power gain (MAG) is an additional concern while scaling the technology for RF
applications. With fast growth in the radio-frequency (RF) wireless communications
market, the demand for high-performance but the low-cost RF solutions is rising. This
advanced performance of MOSFETs is attractive for the High Frequency (HF) circuit
design in view of a system-on-a-chip realization, where the digital, the mixed-signal
base band, and the RF transceiver blocks would be integrated on a single chip. Thus
the current research is very much devoted in studying the performance of the scaled
MOS devices in case of analog and RF applications. Thanks to the aggressive feature
size reduction in the past few years, however, MOSFETs are now qualified as RF
devices.

1.4

Status of the existing work

It is really a challenge for the many microelectronics researchers to integrate

the analog function in the standard digital ICs. Some researchers suggested some
novel device structure to improve the performance of MOSFETs. Many of these
employ Gate Engineering, Channel Engineering, and Source Drain Engineering to
get some better performance.
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[M shur split gate] In 1999 Long et. al[2]give a novel structure, the dual
material single gate MOSFET. Here instead of using channel engineering like
introducing halo or pocket in the channel region the gate engineering is applied. In
this MOSFET structure gate consist of two different metals with different work
function. This technique creates step changes in the channel potential profile causes
reduced Drain Induced Barrier Lowering (DIBL). Here also the electric field pattern
gives a better carrier transport efficiency. Double gate MOSFET approaches have
some advantages like low do pant fluctuation, low noise, and good power gain. But
dual gate or double gate is not the solution for all transistor problems. Many paper
works have already been done for double material double gate MOSFET structure.
From these papers, we realize that DMDG MOSFET exhibits satisfactory
performance for DC analysis as well as analog and RF analysis. Recently Tiwary et.
al [3] proposed the triple material dual gate structure. This paper mainly compares
the threshold voltage for different gate length with different gate material length ratio
and for different silicon and oxide thickness. Rajiv et all compare the surface
potential, electric field between the single material gate (SMG), dual material gate
(DMG) and triple material gate (TMG) MOSFET. From these papers, we clearly see
the TMG have the better capability to reduced short channel effects (SCEs).

1.5 Scope of the Work

In this work, we have systematically investigated the sub threshold analog
performances as well as the RF parameters for high frequency applications of nchannel Triple Material Double Gate MOSFET under 100nm gate length. ComputerAided Design (CAD) has been used for the realization and the analysis of all the
devices used in this study. All the device parameters are set as per ITRS road map for
the under100nm gate length.
In the case of the DG MOSFET with the triple metal gate technology, the
optimization of the length of the metals gates is illustrated with the detailed
simulation results. Analog parameters like the Transconductance generation factor (
gm I D

/ ), the output resistance and the intrinsic gain of all the devices have been
investigated and compared with that of the conventional DG MOSFETs. For RF
applications, the cut-off frequency, maximum frequency and the gain bandwidth
product have been explored.

2
CHALLENGES AND SCALING ISSUES OF MOSFET IN
THE NANO REGIME
CMOS ICs have conquered the electronic market with devices for
computing, communication, entertainment, automotive, and other applications
simultaneously with improvements in cost, speed, and power consumption. It is
believed that this trend of rapid improvements will continue in the near future. Since
the 1960s the price of one bit of semiconductor memory has dropped to 100 million
times and the trend continues as we go for more and more advanced devices with
relatively less cost and better performance. CMOS technology went through a lot of
advancement following Moores Law to achieve higher packing density and
improved performance. Also, miniaturization of CMOS devices has improved its cutoff frequency in the gigahertz range that made it also attractive for analogue and
mixed-signal applications.
The primary engine that powered the ascent of electronics is miniaturization.
By making the transistors and the interconnects smaller, more circuits can be
fabricated on each silicon wafer and therefore each circuit becomes cheaper.
Miniaturization has also been instrumental in the improvements in speed and power
consumption.
This chapter begins with a description of several key device design parameters
and how they are influenced by device scaling as predicted by first order theory.
Several of the most important second order effects are then discussed. Importantly
short the channel effects, Doping concepts including halo, different technologies like
bulk, SOI and various engineering concepts are discussed in detail.

2.1 METAL GATE TECHNOLOGY-GATE ENGINEERING

The continuous downscaling of the devices opens the window for higher short
channel effects because of lesser control of gate over channel. To reduce the drain
control over the channel, the most widely technique is introducing hetero material in
gate. Actually this concept came from the split gate which is achieved by full nickelsolicitation of the polysilicon gate combined with NiSi gate work function tuning at
the drain side through tilt angle antimony implantations, The hetero material Gate
Engineering technique uses different material with different work function which
creates some different threshold voltage for different region in the same device.
These different materials creates some step potential profile in the channel region,
7

which have great advantage as if we increase the drain voltage, the maximum
potential absorbed by the drain nearest gate material. So there is screening effect
from drain to source for increasing drain voltage. But it is most important thing is
that the work function of the source side material must have higher than the drain
side for n-channel MOSFET. Now the double material double gate MOSFET is
widely taken structure by many researchers. This shows some superior ability to
reduce short channel effects.

Double gate MOSFET

The scaling of metaloxidesemiconductor field effect transistor (MOSFET)
devices has been successfully done by the advancement in the fabrication
technology .The scaling down of devices is strongly required to achieve high
integration density and better device performance. Due to reduction in the channel
length the short channel effects and leakage current become important issue that
degrades the device performance in terms of leakage current and short channel effects.
Because of having two gates in DG MOSFET both gates control the channel from
both side and provide additional gate length scaling by factor of 2. Due to better
control on short channel effects DG MOSFET is superior to the conventional
MOSFET and it have higher current density, higher sub threshold swing at low supply
voltage [8]. Thus we are able to maintain the device performance in terms of higher
current density and low leakage by using DG MOSFET. When the gate length become
the order of depletion region then short channel effect become important issue in case
of MOSFET the short channel effects degrading the device performance but in DG
MOSFET we are able to reduce these effects . The DG MOSFETs also suffer from
short channel effects in the sub 100 nm regime due to reduction in threshold voltage.
Due to scaling of MOSFET threshold voltage is also continuously decreasing; As a
result leakage current and short channel effects also increasing. A metal gate
technology can overcome these issues by providing the appropriate gate work
functions. Work function is the minimum energy (usually measured in electron volts)
needed to remove an electron from a solid to a point immediately outside the solid
surface. In order to maintain good short-channel performance and proper threshold
voltages, the gate work functions of the n-FETs and p-FETs must be close to those of
n and p doped poly-Si for bulk-Si CMOS devices and within 0.2 eV of Si mid-gap in
novel structures such as double-gate MOSFETs. By changing the work function of
metal gates of DG MOSFET we can set the appropriate threshold voltage at same
supply voltage and also able to reduce short cannel effects and leakage currents. Due
to the presence of the different materials with various work functions in the gates
leads to better control of the channel by gates and consequently reduces short channel
effects such as DIBL and hot electron effect. Also it can be observed that the DMG,
TMG and PMG structures leads to reduction of transconductance and improvement of
drain conductance.
8

Figure: 2.1: Double gate MOSFET

2.2 Doping technique

Doping technique consists of establishing the initial impregnation of the
aggregate with a high performance paste in order to improve its binding to the matrix.
A Scanning Electron Microscope (SEM) equipped with an energy dispersive X-ray
(EDX) analysis system is used to observe the results of the technique in the ITZ.

2.3

Lateral channel engineering-halo implants

Halo doping or non-uniform channel profile in a lateral direction was

introduced below 0.25-m technology node to provide another way to control the
dependence of the threshold voltage on the channel length. Halo implants increase
the doping near the source and the drain implant. For n-channel MOSFETs, more
highly p-type doped regions are introduced near the two ends of the channel as shown
in Fig. 2.2. The implants near the source or drain can be symmetrical or
asymmetrical. The halo implants can be vertical or can have a tilt. They are usually
added after the gate pattern is completed. The implants add more of a barrier between
the source drain junctions with the channel. During sidewall oxidation, point defects
are injected under the edges of the gate, in the vicinity of what will eventually
become the end of the channel. Doping impurities from the substrate are gathered by
this point defects, thereby increasing the doping concentration near the source and
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drain end of the channel. More highly doped p-type substrate near the edges of the
channel reduces the charge-sharing effects from the source and drain fields, thus
reducing the width of the depletion region in the drain-substrate and source-substrate
regions. These highly doped regions consume a larger fraction of the total channel as
the channel length is reduced. Reduction of charge-sharing effects reduces the
threshold voltage degradation due to channel length reduction. Thus, threshold
voltage dependence on channel length becomes more flat. Hence, the off-current
becomes less sensitive to channel length variation. The barrier lowering in the
channel is also reduced by the reduction in drain and source junction depletion region
width, thus reducing DIBL. Since the channel edges are more heavily doped and
junction depletion widths are smaller, the distance between source and drain
depletion regions is larger. This reduces the punch through possibility.

Figure: 2.2: A Schematic view of halo doped MOSFETs (a) Left: Symmetric Halo
(b)
Right: Asymmetric Halo i.e. heavy doping only on the source side

2.4

Source/drain engineering

By using the source drain extensions (SDE), we can reduce short channel
effects. An example of source drain extensions is the LDD structure. SDE can be
formed by first etching the gate followed by ion implantation forming the SDE. A
spacer will be attached to the gate after the SDE implant. The spacers purpose is to
block the higher dose source/drain (S/D) implants. The SDE should be relatively
shallow compared to the S/D implants. The deeper the SDE, the more will be short
channel effects. But on the other hand, the shallower the SDE, the higher will be the
external resistance. The external resistance can be divided into five resistors in series.

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The current in the channel flows first through the channel (accumulation
region) next to SDE (spreading resistance) then through the deep source implant
(shunt resistance) and finally through contact resistance. The main components of the
external resistance are the RACCUMULATION and the RSPREADING resistance which are
shown in Fig.2.3.
The channel length becomes smaller and the SDE depth becomes narrower
when the transistors are scaled. The channel resistance decreases but the SDE
resistance increases. Scaling of the depth is limited. It is proposed by Intel that SDE
depths below 30-40 nm will have little to no benefit for devices with gate lengths less
than 0.1 um. The reason for this is that any gain in short channel effect because of
reduced charge sharing will be balanced out because of the increase in external
resistance. Also if the SDE depth is very narrow it will not extend far enough under
the gate. The SDE must extend under the gate to increase drive current. If the SDE
does not extend enough under the gate the current will spread out more in the lower
doped part of the SDE. This will cause an increase in the R ACCUMULATION and RSPREADING
resistance. The increase in the overall external resistance will decrease the maximum
drive current.

Figure: 2.3: Components of external resistance

The SDE is created using an ion implantation as described earlier. Ion implantation
can cause implant channeling and also cause transient enhanced diffusion. Both of
these effects can cause the SDE to be deeper than intended, which will increase the
short channel effects. The effect can be controlled decreasing the implant energy, but
is unlikely for p-channel MOSFETs using boron as the implant.

2.5 Channel engineering

Besides the gate oxide thickness and junction scaling, another technique to
improve short-channel characteristics is the well engineering. The distribution of the
electric field and potential contours can be changed by changing the doping profile in
the channel region. The goal is to optimize the channel profile to minimize the OFF11

state leakage while maximizing the linear and saturated drive currents. Super steep
retrograde wells and halo implants have been used as a means to scale the channel
length and increase the transistor drive current without causing an increase in the
OFF-state leakage current.

Figure: 2.4: Local heavy substrate doping for punch-through control

leaving channel lightly doped for threshold control

2.6 Drain source engineering technique

In order to mitigate short channel effects, the gate-oxide thickness and
source/drain junction depth have been scaled along with the gate length. Recently,
however, gate-oxide thickness scaling has slowed, as evidenced by the fact that an
equivalent oxide thickness (EOT) of ~1 nm has been used for the past 2-3 generations
of CMOS technology. Although significant progress has been made in the
development of high-permittivity gate-dielectric materials and metal gate technology
in recent years, it will be difficult to scale EOT well below 1 nm. This makes
junction-depth scaling even more pressing for continued transistor scaling.
Furthermore, as the dimensions of MOSFETs are scaled down, the contact resistance
of suicide-to-source/drain regions increasingly limits transistor performance. This is
because the on-state resistance of a MOSFET drops with transistor scaling, where as
contact resistance increases with contact area scaling.

2.7

Physics of scaling
Moores law , which states that the number of transistors on a given chip can
be doubled every two years, has been the roadmap of the continuous reduction of
CMOS device dimensions since Gordon Moore, co-founder of Intel, first
predicted it in 1965 . Over a period of a few decades, CMOS devices have been
scaled down to the sub-100nm regime.
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Figure 2.5: Number of transistors/die & feature size vs. time

Although the basic device geometry has remained relatively unchanged, the

gate length has been reduced from 10 mm in the 1970s to less than 0.1 m in 2001,
and the gate oxide thickness from 1000 to less than 20 . The Moores Law is a
succinct description of the persistent periodic increase in the level of miniaturization .

Benefits of MOSFET scaling

Computing power has increased dramatically over the decades, enabled by
Significant advances in silicon integrated circuit (IC) technology led by the continued
miniaturization of the MOS transistor. The rapid progress in the semiconductor
industry has been driven by improved circuit performance and functionality together
with reduced manufacturing costs. Since the 1960s, MOS transistor dimensions have
been shrinking30% every 3 years, as predicted by Moores law depicted and scaling
has in fact accelerated recently.

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Figure 2.6: Moores law of scaling. The number of transistors on a chip has
been increasing exponentially

While Moores Law only describes the rate of increase in transistor density,
reduction of the physical MOS device dimensions has improved both circuit speed
and density in the following ways: a) Circuit operational frequency increases with a
reduction in gate length, LG, as ~ 1/LG; allowing for faster circuits, b) Chip area
decreases ~ LG2; enabling higher transistor density and cheaper ICs. c) Switching
power density ~constant; allows lower power per function or more circuits at the
same power. Device scaling has been a relatively straightforward affair thus far, but
physical limits are fast being approached, and new materials and device structures are
needed to continue scaling trends.

Issues in planar bulk-Si MOSFET scaling

The planar bulk-silicon MOSFET has been the workhorse of the
semiconductor industry over the last 40 years. However, the scaling of bulk
MOSFETs becomes increasingly difficult for gate lengths below ~20nm (sub-45 nm
half-pitch technology node) expected by the year 2009. As the gate length is reduced,
the capacitive coupling of the channel potential to the source and drain increases
relative to the gate, leading to significantly degraded short-channel effects (SCE).
This manifests itself as a) increased off-state leakage, b) threshold voltage (VTH)
roll-off, i.e. smaller VTH at shorter gate lengths, and c) reduction of VTH with
increasing drain bias due to a modulation of the Source-channel potential barrier by
the drain voltage, also called drain-induced barrier lowering (DIBL). In order to
maintain the relatively strong gate control of the channel potential in bulk devices,
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various technological improvements such as halo implants and advance channel do

pant profile engineering techniques such as super-steep retrograde wells have been
necessary. Each of these technologies is now approaching fundamental physical
limitations which may, in turn, limit further scaling of device dimensions.
In summary, from a device design point of view, in order to achieve good
electrostatic integrity or good control of short-channel effects (SCE), the gate
dielectric thickness, Tox, the source/drain junction depth, Xj, and the channel
depletion depth Xdep,need to be scaled down. The scale length for a bulk device, bulk,
is an indication of how short LG can be made before the SCE are excessive, and is
quantitatively expressed in equation. For good electrostatic control, the minimum LG
should be no less than ~ 5bulk.
bulk=0.1(ToxXj X2dep)1/3
For a bulk MOSFET, gate leakage limits T ox scaling, Xdep scaling is
limited to about 10 nm due to substrate-to-drain band-to-band tunneling current
limitations on body doping, and XJ is limited by process limits for forming ultrashallow junctions with abrupt doping profiles. Experimental bulk MOSFETs have
been demonstrated down to 5nm LG However, the performance did not meet industry
roadmap specifications especially for low power applications. Continued device
scaling will require new materials and/or alternative MOSFET structures. Therefore
bulk MOSFET scaling is becoming increasingly harder and new transistor designs
offering better scalability are needed. These are introduced in the next section.

Figure 2.7: Voltage Scaling

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Table: Scaling Results for Circuit Performance (from Dennard)

Device or Circuit Parameter
Scaling Factor
Surface dimension (L, W)
Impurity concentration
Voltage
Current
Current density
Capacitance (per unit area)
Circuit delay time
Power dissipation per circuit
Power density

2.8

1/k
k
1/k
1/k
k
k
1/k
1/k2
1

Effects of device scaling

Device design in the deep sub-micron regime is a challenging task. The basic,
first-order theories do not fully describe the device behaviour. Second-order effects,
such as threshold variations with channel length due to the charge sharing and the
doping effects, extrinsic resistances, and quantum mechanical effects, must be taken
into account. These second order effects combine to make it difficult for the device
designers to have an intuitive grasp of all the trade-offs inherent in the device design,
complicating the design process.

2.8.1 Short channel effects

A MOSFET device is considered to be short when the channel length is the same
order of magnitude as the depletion-layer widths (xdD, xdS) of the source and drain
junction. As the channel length L is reduced to increase both the operation speed and
the number of components per chip, the so-called short-channel effects arise [6].The
short-channel effects are attributed to two physical phenomena: 1.The limitation
imposed on electron drift characteristics in the channel, 2.The modification of the
threshold voltage due to the shortening channel length.
Short channel MOSFET is defined as devices with width and length short
enough such that the edge effects cannot be neglected. Channel length L is
comparable to the depletion widths associated with the drain and source.
The natural length gives a measure of the short-channel effect inherent to a
device structure. It represents the penetration distance of the electric field lines from
the drain in the body of the device or the amount of control the drain region has on
the depletion zone in the channel, as both the gate and the drain compete for that
control.
In particular five different short-channel effects can be distinguished:
A. Drain-induced barrier lowering and punch through
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B. Surface scattering
C. Velocity saturation
D. Impact ionization
E. Hot electrons

A. Drain induced barrier lowering and punch through

The expressions for the drain and source junction widths are:
x

xdD=

2 Si e
2 Sie
qNa
q Na
and
x
=
dS
(V ds + si +V sb )()
( si +V db )( )

Where

V sb

and

V db

are source-to-body and drain-to-body voltages.

When the depletion regions surrounding the drain extends to the source, so that the
two depletion layer merge (i.e., when xdS + xdD = L), punch trough occurs. Punch
through can be minimized with thinner oxides, larger substrate doping, shallower
junctions, and obviously with longer channels. The current flow in the channel
depends on creating and sustaining an inversion layer on the surface. If the gate bias
voltage is not sufficient to invert the surface (Vgs<VT0), the carriers (electrons) in the
channel face a potential barrier that blocks the flow. Increasing the gate voltage
reduces this potential barrier and, eventually, allows the flow of carriers under the
influence of the channel electric field. In small-geometry MOSFETs, the potential
barrier is controlled by both the gate-to-source voltage V gs and the drain-to-source
voltage Vds. If the drain voltage is increased, the potential barrier in the channel
decreases, leading to drain-induced barrier lowering (DIBL). The reduction of the
potential barrier eventually allows electron flow between the source and the drain,
even if the gate-to-source voltage is lower than the threshold voltage. The channel
current that flows under this conditions (Vgs<VT0) is called the sub-threshold current.

B. Surface scattering
As the channel length becomes smaller due to the lateral extension of the
depletion layer into the channel region, the longitudinal electric field component y
increases, and the surface mobility becomes field-dependent. Since the carrier
transport in a MOSFET is confined within the narrow inversion layer, and the surface
scattering (that is the collisions suffered by the electrons that are accelerated toward
the interface by x) causes reduction of the mobility, the electrons move with great
difficulty parallel to the interface, so that the average surface mobility, even for small
values of y, is about half as much as that of the bulk mobility.
17

Figure: 2.8: Surface scattering

C. Velocity saturation
The performance short-channel device is also affected by velocity saturation,
which reduces the transconductance in the saturation mode. At low y, the electron
drift velocity vde in the channel varies linearly with the electric field intensity.
However, as y increases above 104 V/cm, the drift velocity tends to increase more
slowly, and approaches a saturation value of vde(sat)=107 cm/s around y=105 V/cm at
300 K. Note that the drain current is limited by velocity saturation instead of pinch
off. This occurs in short channel devices when the dimensions are scaled without
lowering the bias voltages. Using vde(sat), the maximum gain possible for a MOSFET
can be defined as, gm=WCoxvde(sat )

D. Impact ionization
Another undesirable short-channel effect, especially in NMOS, occurs due to
the high velocity of electrons in presence of high longitudinal fields that can generate
electron-hole (e-h) pairs by impact ionization, that is, by impacting on silicon atoms
and ionizing them. It happens as follow: normally, most of the electrons are attracted
by the drain, while the holes enter the substrate to form part of the parasitic substrate
current. Moreover, the region between the source and the drain can act like the base
of an n p n transistor, with the source playing the role of the emitter and the drain that
of the collector. If the aforementioned holes are collected by the source, and the
corresponding hole current creates a voltage drop in the substrate material of the
order of .6V, the normally reversed-biased substrate-source p n junction will conduct
appreciably. Then electrons can be injected from the source to the substrate, similar to
the injection of electrons from the emitter to the base. They can gain enough energy
as they travel toward the drain to create new impairs. The situation can worsen if
18

some electrons generated due to high fields escape the drain field to travel into the
substrate, thereby affecting other devices on a chip.

E. Hot electrons
Another problem, related to high electric fields, is caused by so-called hot
electrons. These high energy electrons can enter the oxide, where they can be
trapped, giving rise to oxide charging that can accumulate with time and degrade the
device performance by increasing VT and affect adversely the gates control on the
drain current.

Figure: 2.9: Hot electrons

2.8.2 Threshold Voltage

The threshold voltage VT for a MOS transistor can be defined as the voltage
between the gate and the source terminals below which the drain to source current
effectively drops to zero.

19

Figure 2.10: Threshold voltage of an ideal switch (b) Maximum gm definition of

threshold voltage.

When a positive voltage is applied to the gate relative to the substrate, positive
charges are in effect deposited on the gate metal. In response, negative charges are
induced in the underlying silicon, by the formation of a depletion region and a thin
surface region containing mobile electrons. This induced electrons from the channel
of the FET, and allow current to flow from drain to source.
Threshold voltage,

VT

ms

Qi

- Ci

Qd

Ci + 2 f

Since electrons are electro statically induced in the p-type channel region, the
channel becomes less p-type, and thus the valence band moves down, further away
from the Fermi level. This obviously reduces the barrier for electrons between the
source, the channel and the drain. If the barrier is reduced sufficiently by applying a
gate voltage in excess of what is known as the threshold voltage, V T, there is
significant current flow from the source to drain. Thus, one view of a MOSFET is
that it is a gate controlled potential barrier.

FLAT BAND VOLTAGE

Figure 2.11: Flat band voltage

Flat-band voltage, Vfb refers to MOS devices, a voltage at which there is no

electrical charge in the semiconductor and, therefore, no voltage drop across it; in
band diagram the energy bands of the semiconductor are horizontal (flat).
20

2.8.3 Threshold voltage roll-off

A clear indicator of short channel effects is the decrease in the threshold
voltage Vt with decreasing channel length. Plotting Leff on the x-axis and threshold
voltage on the y-axis makes aVt roll-off chart. The minimum Leff that will be
acceptable is indicated in the chart. Vt Roll-off is one of the most serious
consequences of short channel effects. Figure demonstrates
channel MOSFETs.

Vt

roll-off for n- and p-

The threshold voltage (Vt) of MOSFETs cannot continue to be scaled down as

the gate length is decreased. The sub threshold current I off increases as Vt is decreased.
An increase in Ioff is a serious threat to the continued performance enhancements of
the MOSFET transistor. For transistors less than 0.25 m designers must consider the
tradeoff between the speed and the power consumption.

Figure 2.12: Vt versus Lef demonstrating (Vt roll-of)

As the gate length is reduced below 2 m, the long channel approximation

for the threshold voltage is not as accurate. The Vt generally decreases as gate length
is decreased. Also, the Vt decreases as the drain-source voltage (V ds) is increased. In
order to predict the

Vt

of a short channel device, the shift in the threshold voltage,

21

Vt

Vt must be approximated. The short channel effect (SCE) is given by the following
formula where Vib the long channel is Vt: (Vib)SCE =Vib (Vt)

2.8.4 Drain induced barrier lowering (DIBL)

In the weak inversion regime there is a potential barrier between the source
and the channel region. The height of this barrier is a result of the balance between
drift and diffusion current between these two regions. The barrier height for channel
carriers should ideally be controlled by the gate voltage to maximize
transconductance. As indicated in Fig. [2:13], drain-induced barrier lowering (DIBL)
effect occurs when the barrier height for channel carriers at the edge of the source

Figure: 2.13 Surface potential Vs. Lateral position

characteristics

reduces due to the influence of drain electric field, upon application of a high drain
voltage. This increases the number of carriers injected into the channel from the
source leading to an increased drain off current. Thus the drain current is controlled
not only by the gate voltage, but also by the drain voltage. For device modeling
purposes this parasitic effect can be accounted for by a threshold voltage reduction
depending on the drain voltage.

22

Figure: 2.14 Drain induced barrier lowering

In addition to the surface DIBL, there are two unique features determining
Scission thin-film SOI devices viz.(a) positive bias effect to the body due to the
accumulation of holes generated by impact ionization near the drain and (b) the DIBL
effect on the barrier height for holes at the edge of the source near the bottom of thinfilm, as illustrated in Fig. [2:14]

Figure: 2.15

23

Figure: 2.16

The DIBL effect on the barrier height for holes reduces the positive bias effect
to the body because the accumulated holes in the body can more easily surmount the
barrier and flow to the source. As a result fewer number of accumulated holes remain
which weakens the Vth lowering. The potential near the bottom in the body region
increases as gate length decreases due to the drain electric field. This leads to the
lowering of the barrier height for holes at the source edge near the bottom with
shorter gate lengths. Fig. [2:15] compares the schematic energy band diagrams at
threshold condition between short and long channels MOSFETs. The comparison is
done near the bottom of the thin-film from the source to the drain. With shorter gate
lengths, the barrier height for holes near the bottom is lowered by the influence of the
drain electric field, and holes accumulated in the body region can more easily flow
into the source.

2.8.5 Punch through

Punch through in a MOSFET is an extreme case of channel length modulation
where the depletion layers around the drain and source regions merge into a single
depletion region. The field underneath the gate then becomes strongly dependent on
the drain-source voltage, as is the drain current. Punch through causes a rapidly
increasing current with increasing drain-source voltage. This effect is undesirable as
it increases the output conductance and limits the maximum operating voltage of the
device.

24

Figure: 2.17: Punch through

2.8.6 Hot carrier

Todays ULSI MOSFET devices feature extremely short channel lengths and
high electric fields. In these high electric fields, carriers are accelerated to high
velocities, reaching a maximum kinetic energy (hot) near the device drain. If the
carrier energy is high enough, impact ionization can occur (Drain Avalanche Hot
Carrier Effect), creating electron-hole pairs fig [2:18]. These holes and electrons can
attain enough energy to surmount the carrier conditions; the recommended maximum
drain stress bias voltage is less than 90% of the devices drain-to-source breakdown
voltage. With decreased MOSFET gate length, hot carrier induced degradation has
become one of the most important reliability concerns. In the hot carrier effect,
carriers are accelerated by the channel electric fields and become trapped in the
oxide. These trapped charges cause time dependent shifts in measured device
parameters, such as the threshold voltage (V th), transconductance (gm), and linear
(Idlin) and saturation (Idsat) drain current. In time, substantial device parameter
degradation can occur, resulting in device failure.

25

Figure: 2.18: Drain avalanche hot carrier efect

2.9

Electrostatic characteristics
The device performance is controlled by their electrostatic characteristics;
hence to analyze the electrostatic parameter is essential. Electrostatic characteristics
like potential and electric field primarily point out the analogue performance as well
as frequency performance also. Here we describe two important electrostatic
characteristics surface potential and electric field for MOSFET.

2.9.1 Surface potential

Surface potential is an important figure of merit for MOSFET which define
the amount of charge accumulated beneath the surface and it indicate the amount
drain current availability. Surface potential profile also shows DIBL characteristics
for the MOSFET.

2.9.2 Electric field

Electric field in the channel is also an important figure of merit. From the
electric field profile we can predict the source and drain potential barrier and the
impact ionization probability.

3
DEVICE STRUCTURE
26

3.1 Structure for triple material double gate MOSFET

Figure 3.1: Structure for triple material double gate

MOSFET (TM-DG)

Here we take a TM-DG structure for analysis and the node is taken from
International Technology Roadmap for Semiconductors [1].
For the analysis we take the following parameters for the MOSFET, written belowL= Gate length=60 nm
D= Silicon thickness=25 nm
tox= oxide thickness=2 nm
Na= Acceptor Impurity Concentration=1014
Nd=Donor Impurity Concentration =1020
The performance of the triple material double gate MOSFET is compared to
that of SM-DG and DM-DG MOSFET. The gate is length of DM-DG and SM-DG is
identical to that of TM-DG. The work function of gate material near the source of
DM-DG is 5eV and the material work function near the drain is 4.4. For TM-DG
MOSFET the work functions from source end to drain end are in the sequence: 5 eV,
4.6 eV, and 4.4 eV. The two gates of the double gate MOSFET under consideration
are maintained at the same voltage, i.e. they are shorted.

4
27

ANALYTICAL MODEL FOR TM-DG

4.1 Symbols and descriptions

Symbol

Descriptions

L
s

Channel Length of MOSFET

Surface Potential
Permittivity of Silicon
Permittivity of Silicon Dioxide
Capacitance of Silicon Dioxide per unit area
Silicon Dioxide Layer Thickness
Diffusion constant of electrons
Charge of electrons

SI
ox
Cox
tox
D
Q
Nd
Na
Vgb
Vfb
Vbi
K
T
t

Donor Impurity Concentration

Acceptor Impurity Concentration
Gate to Bulk Voltage
Flat Band Voltage
Induced barrier potential
Boltzmanns Constant
Temperature in Kelvin
KT /q
The gate and the source/drain forms a
capacitor between two plates at an angle

4.2 Model equation

Figure: 4.1: The n-channel DG-MOSFET transistor structure

The n-channel DG-MOSFET structure shown in Fig.1 issued to develop and

implement the model. The channel region is lightly doped so that the channel is fully
28

depleted. In this model we have used a device with gate length L=25 nm, silicon
thickness D=12 nm, Oxide thickness tox=1.6 nm, and channel doping density Na
=1015to 1017 cm3 .n+ poly silicon gate material along with source and drain contact
doping of Nd=1020 cm3are used for testing the model predictions.
Applying Gausss law on the surface consisting of the entire silicon region in
the channel and shown in Fig 2 and neglecting mobile charge carriers, the following
equation can be derived.
V
( gbV fb )

2
d s s qN
=

dx

Where 2 = Dsi/(2Cox ),s(x) is the surface epotential with respect to the

interior of the bulk, Vgb is the gate to bulk voltage, Vfb= 0.56 tln(Na/ni) is the flat
band voltage, Cox =ox/tox is the oxide capacitance per unit area, t ox is the oxide
thickness, D is the channel depth, N a is the channel doping concentration, t=
kT /q is thethermal voltage, and are the permittivity of silicon and Sio ,
ox
si
2
respectively.
At the two edges of the gate in addition to the vertical field there will also be a field
responsible for the edge effect.
At the end points, the gate and the source/drain forms capacitor between two
plates at an angle of =ox(2Si) and length Xj. If the channel length is long enough
then the edge effect is negligible. In short channel device to predict the surface
potential accurately we must take this effect into consideration. From the gate, this
field is aligned vertically downwards with a magnitude of E =V/(l-x),where V =
(VgsVfbVbi ) and l=0 at the source end (0<x<X j),V=(VgdVfb Vbi) and l=L at the
drain end (LXj<x<L,and V=0 and l=0 in the middle region (Xj<x<LXj).
By including edge effect the surface potential,
d 2 s s qN (V gbV fb)
2 v
=

dx

(lx )i D

s ( x )=C e +C e +

qN V gbV fb
2 v
(2 )

2
i
( lx ) i D

s = s=C e +C e

qN 2
2 v
+ ( V gbV fb ) +
2
i
(lx ) i D
29

(1)

 s = s=C e

+C 2 e

qN 2
2 v
+ ( V gb V fb ) +
2
i
( lx ) i D

(2)

s =C e +C e M (A)

Where , M =

qN 2
2 v
+ ( V gb V fb )
i
( lx ) i D

By solving (1) & (2), we get

( e

C =

se

(e

( e
s

C =

2 x

)+ M ( e

2 x

)
(3)

2x

)+ M ( e
( e e )
e

)
(4)

2x

Now putting the value of (3) & (4) in equation (A) we get
s

( e
s

) + M ( e
( e e )
e

2x

{e

( x +x )

2 x

( s + M )e

(e

2 x

( x+ x )

}{

e +

2 x

( e

(e

( s+ M ) } {e

2 x

( x+ x )

)+ M (e
)
e
x

2 x

( s+ M ) e

(e

2 x

( x+x )

2 x

( s+ M ) }

( s+ M ) e

( x x )

( x+x 2 x )

}( + M ) {e

( x+ x 2 x )

2e

2 ( x x )

2( x x )

( x x )

} + ( + M ) {e
s

( x x )

( x+x 2 x )

2e
30

}( + M

2 ( x x )

2 ( x

Now, we assume that

xx =C

x+ x 2 x =C
x+ x 2 x =C

xx =C

s=

( + M ) {e

2e

s=

( + M )( e

s=

e +e

2 ( x x )

C
C
( s + M ) cosh cosh

2 ( x x )

( + M ) {e

2e

2 ( x x )

} ( + M ) {e

2 ( x x )

( s+ M ) ( e e + e

2 ( x x )

2e

2 ( x x )

s=

s
2 ( x x )

C
C
( s + M ) 2 cosh 2cosh

1cosh

s=

22 cosh

s=

}( M ) {e

2( x x )

2e

2 ( x x )

s
2( x x )

) ( + M )( 2cosh C 2 cosh C ) M
s

22 cosh

2 ( x x )

) ( + M )(cosh C cosh C ) M
s

1cosh

2 ( x x )

(C +C )
(C C )
(C + C )
( C C )
sin h
s + M ) sin h
sin h
(
2
2
2
2

M
( x x )
( x x )
sin h
sin h

( s + M ) sin h

( xx )
( x x )
( xx )
( x x )
sin h
s + M ) sin h
sin h
(

M
( x x )
( x x )
sin h
sin h

( s + M ) sin h

31

 s=

s=

s=

Now,

( xx )
( x x )
s+ M ) sin h
(

M
( x x )
( x x )
sinh
sinh

( s + M ) sin h

( xx )
( xx )
1
( s+ M ) sin h ( s + M ) sin h M
( x x )
sin h

( xx )
( xx )
1
( s + M ) sin h ( s + M ) sin h M
( x x )
sin h

d=

qN V gb V fb 4 V

i
D x j
2

) , which depends on the region.

The complete solution of the equation,

d s
=
dx

( x x )
( xx )
1
( +d ) cos h
( + d ) cos h

( x x )
sin h

(5)

The channel in general, is required to be divided into three regions at any point
over the channel; the surface potential and its derivative are continuous. The boundary
condition in the three regions are given by,

Region 1:
X = 0< x < x ,the corresponding values are

s =V =V

bi

+Vsb ,

s =V

32

and

bi
gbV fb V

qN V gbV fb 4

i
D
2
d =2

In this region, V2 is to be evaluated.

d s
=
dx x x

s=

( xx )
( xx )
1
( V + d ) cos h
( V + d ) cos h

( x x )
sin h

( xx )
( xx )
1
( V +d ) sin h
( V +d ) sin h
d

( x x )
sin h

Region 2:
X < x < X , the corresponding values are

s (x =X 2)=V

, s =V

33

V
( gbV fb)
2

and
qN

i
d =2

Figure: 4.2: Elementary Gaussian surface in the channel covering

the entire depletion layer depth.
d s
=
dx x x

s=

( xx )
( x x )
1
( V + d ) cos h
( V +d ) cos h

( x x )
sin h

( xx )
( xx )
1
( V +d ) sin h
( V + d ) sin h
d

( x x )

sin h

Both V2 and V3 are to be evaluated applying the continuity of the field at the
boundaries between two regions.
Region 3:
X x< X =V +V , the corresponding values are
bi
db
s =V

, s =V = Vbi+Vdb and

34

bi
gbV fb V
V
is to be evaluated .

qN V gbV fb 4

i
D
2
2
d =

d s
=
dx x x

s=

( xx )
( xx )
1
( V + d ) cos h
( V +d ) cos h

( x x )
sin h

( xx )
( xx )
1
( V + d ) sin h
(V + d ) sin h
d

( x x )
sin h

Using (5) and applying the continuity of derivative of the potentials at the interface
between the region-1 and the region-2 we get,
Where a

V2 + a

11

= coth

12

V3 = D1

] [

( x x )
( x x )
+coth

cosech

( x x )

D=(V+D)cosech
+dcosech

(6)

( x x )

and

( x x )

] -dcoth [

( x x )

] -dcoth [

( x x )

Similar application of the boundary conditions at the interface between the region 2
and the region 3 gives,
35

a V + a V = D
2
3
2

Where a = cosech

a = coth

( x x )

( x x )

] [

( x x )
( x x )
+coth

D=(V+D)cosech

(7)

] -dcoth [

( x x )

( x x )

] +dcosech [

( x x )

] -dcoth

Solving equations (6) and (7), we can easily solve for V2 and V3 to get

V 2=

|
|

| |
| |

D1 a12
D2 a22

a 11 a12
a21 a22

4.3

V 3=

|
|

a11 D1
a 21 D2
a 11 a12
a 21 a22

The MATLAB program

L=60*(10^-9);
D=25*(10^-9);
tox=2*(10^-9);
Na=10^14;
Nd=10^20;
ni=1.5*(10^10);
Esi=11.8*8.85*(10^-14);
36

Eox=3.9*8.85*(10^-14);
cox=Eox/tox;
k=1.38*(10^-23);
T=300;
q=1.6*(10^-19);
Wt=k*T/q;
xj=6*10^-9;
W1=4.8;
Xsi=4.05;
Eg=1.1;
Ws=Xsi+Eg/2+Wt;
Vfb=(W1-Ws);
Vbi=(Eg/2)+Wt*log((Na)/(ni));
Vgs=0.2;
Vgd=0;
Vds=0.1;
x1=0;
x2=L/3;
x3=2*L/3;
x4=L;
y=((D*Esi)/(2*cox))^0.5;
d=(y^2)*(((q*Na)/Esi)-((Vgs-Vfb)/(y^2)));
d1=d;
d2=d;
d3=d;
V1=Vbi;
V4=Vbi+Vds;
37

a11=coth((x2-x1)/y)+coth((x3-x2)/y);
a12=-csch((x3-x2)/y);
a21=a12;
a22=coth((x3-x2)/y)+coth((x4-x3)/y);
D1=((V1+d1)*csch((x2-x1)/y))-(d1*coth((x2-x1)/y))-(d2*coth((x3-x2)/y))+d2*csch((x3x2)/y);
D2=(V4+d3)*csch((x4-x3)/y)+d2*csch((x3-x2)/y)-d2*coth((x3-x2)/y)-d3*coth((x4-x3)/y);
C1=[D1 a12;D2 a22];
C2=[a11 a12;a21 a22];
V2=(det(C1))/(det(C2));
C3=[a11 D1;a21 D2];
C4=[a11 a12;a21 a22];
V3=(det(C3))/(det(C4));
x11=x1:1*10^-9:x2;
x22=(x2+1*10^-9):1*10^-9:x3;
x33=(x3+10^-9):1*10^-9:x4;
psi1=(csch((x2-x1)/y))*(((V2+d1)*sinh((x11-x1)/y)-(V1+d1)*sinh((x11-x2)/y)))-d1;
psi2=(csch((x3-x2)/y))*(((V3+d2)*sinh((x22-x2)/y)-(V2+d2)*sinh((x22-x3)/y)))-d2;
psi3=(csch((x4-x3)/y))*(((V4+d3)*sinh((x33-x3)/y)-(V3+d3)*sinh((x33-x4)/y)))-d3;
epsi1=(1/y)*((csch((x2-x1)/y))*(((V2+d1)*cosh((x11-x1)/y)-(V1+d1)*cosh((x11-x2)/y))));
epsi2=(1/y)*((csch((x3-x2)/y))*(((V3+d2)*cosh((x22-x2)/y)-(V2+d2)*cosh((x22-x3)/y))));
epsi3=(1/y)*((csch((x4-x3)/y))*(((V4+d3)*cosh((x33-x3)/y)-(V3+d3)*cosh((x33-x4)/y))));
x=[x11 x22 x33];
psi=[psi1 psi2 psi3];
epsi=[epsi1 epsi2 epsi3];

L=60*(10^-9);
38

D=25*(10^-9);
tox=2*(10^-9);
Na=10^14;
Nd=10^20;
ni=1.5*(10^10);
Esi=11.8*8.85*(10^-14);
Eox=3.9*8.85*(10^-14);
cox=Eox/tox;
k=1.38*(10^-23);
T=300;
q=1.6*(10^-19);
Wt=k*T/q;
xj=6*10^-9;
W1=4.8;
Xsi=4.05;
Eg=1.1;
Ws=Xsi+Eg/2+Wt;
Vfb=(W1-Ws);
Vbi=(Eg/2)+Wt*log((Na)/(ni));
Vgs=0.2;
Vgd=0;
Vds=0.9;
x1=0;
x2=L/3;
x3=2*L/3;
x4=L;
y=((D*Esi)/(2*cox))^0.5;
39

d=(y^2)*(((q*Na)/Esi)-((Vgs-Vfb)/(y^2)));
d1=d;
d2=d;
d3=d;
V1=Vbi;
V4=Vbi+Vds;
a11=coth((x2-x1)/y)+coth((x3-x2)/y);
a12=-csch((x3-x2)/y);
a21=a12;
a22=coth((x3-x2)/y)+coth((x4-x3)/y);
D1=((V1+d1)*csch((x2-x1)/y))-(d1*coth((x2-x1)/y))-(d2*coth((x3-x2)/y))+d2*csch((x3x2)/y);
D2=(V4+d3)*csch((x4-x3)/y)+d2*csch((x3-x2)/y)-d2*coth((x3-x2)/y)-d3*coth((x4-x3)/y);
C1=[D1 a12;D2 a22];
C2=[a11 a12;a21 a22];
V2=(det(C1))/(det(C2));
C3=[a11 D1;a21 D2];
C4=[a11 a12;a21 a22];
V3=(det(C3))/(det(C4));
x11=x1:1*10^-9:x2;
x22=(x2+1*10^-9):1*10^-9:x3;
x33=(x3+10^-9):1*10^-9:x4;
psi1=(csch((x2-x1)/y))*(((V2+d1)*sinh((x11-x1)/y)-(V1+d1)*sinh((x11-x2)/y)))-d1;
psi2=(csch((x3-x2)/y))*(((V3+d2)*sinh((x22-x2)/y)-(V2+d2)*sinh((x22-x3)/y)))-d2;
psi3=(csch((x4-x3)/y))*(((V4+d3)*sinh((x33-x3)/y)-(V3+d3)*sinh((x33-x4)/y)))-d3;
epsi1=(1/y)*((csch((x2-x1)/y))*(((V2+d1)*cosh((x11-x1)/y)-(V1+d1)*cosh((x11-x2)/y))));
epsi2=(1/y)*((csch((x3-x2)/y))*(((V3+d2)*cosh((x22-x2)/y)-(V2+d2)*cosh((x22-x3)/y))));
40

epsi3=(1/y)*((csch((x4-x3)/y))*(((V4+d3)*cosh((x33-x3)/y)-(V3+d3)*cosh((x33-x4)/y))));
x=[x11 x22 x33];
psid=[psi1 psi2 psi3];
epsid=[epsi1 epsi2 epsi3];
plot(x,psi,'r',x,psid,'b');

5
RESULTS AND DISCUSSIONS
Simulating the results derived for surface potential, electric field and drain
current obtained, using MATLAB and TCAD, we obtained the following plots.
A comparison has been made between the characteristics of our derived model
and that obtained from TCAD simulation.

5.1 Surface potential profile with the channel length for different
gate voltages

41

Figure: 5.1: Graph for diferent Vgs in single material double gate
MOSFET

From the graph it is seen that more the Vgs the minimum potential increases with
the increase in gate voltage.

5.2 Comparison on the basis of surface potential

From the plot between channel length and surface potential of a single
material double gate MOSFET it is observed that, as the drain to source voltage
(Vds) is shifted from 0.1V and 0.9V,[fig. : 5.3] there is a noticeable shift in the
point of minimum surface potential for all the structures. Thus, it implies that for
a small change in drain voltage or gate voltage there is a comparatively larger
surge of drain current which might damage the device. For a double material
MOSFET, there is a difference in the work functions of the two materials, which
causes peaks to appear in the plot. Similarly, for a triple material MOSFET too,
there are two junctions formed by three different work functions, resulting in step
changes in channel potential profile. Unlike for a single material MOSFET, its
42

double and triple material counterparts screening effect is observed between the
source and drain ends, brought about by the work function differences. Thus,
there is a much reduced DIBL (Drain Induced Barrier Lowering) effect and
increased carrier transport efficiency. Also, these properties can be better
explained in a triple material MOSFET than a double material one. As it is shown
in figure 5.2 there are three steps in potential profile for TM-DG structure which
implies that reduced DIBL effect and among the three TM-DG structures,
the1:2:3 gate length ratios has less minimum potential value. So we can consider
this structure is efficient candidate to suppress DIBL effect and threshold voltage
roll off effects.
In the figure 5.3, we describe the minimum potential shift for changing
drain voltage (0.1V to 0.9V). And from the figure it is clear to us that there is
insignificant shift for TM-DG (1:2:3) structure.
Here we also extract the surface potential value for SM-DG, DM-DG, and TMDG (1:2:3) structures from T-CAD (Silvaco) simulation. The result shows a
satisfactory match in between Model and T-CAD.

Figure: 5.2(a): Single material,

double material (1:1), triple material
[(1:2:3) (1:1:1) (3:2:1)] from Model

Figure: 5.2(b): Single material,

double material (1:1), triple
material (1:2:3) from TCAD

Figure: 5.2: Surface potential along channel length for diferent

structure
43

Figure: 5.3: Graph of surface potential profile for diferent

drain voltage

5.3

Comparison on the basis of electric field

From the plot between channel length and electric field of a single
material double gate MOSFET it is observed that, for a single material
MOSFET, the electric field rises quite rapidly initially, then steadily with
the channel length then again it change promptly in drain side. So, the
44

velocity of the carriers (here electrons) increases towards the drain end
and hits the drain end. If the electron penetrates the surface of SiO 2due to
its high velocity then the carriers get trapped in it. On the other hand, at
the drain side due high electric field, it may lead to impact ionization.
These issues are resolved by double and triple material MOSFETs
significantly.
A double material MOSFETs electric field profile consists of one
peak, which tends to reduce the carrier velocity and increase the carrier
transported. So, the carriers arrive at the drain end at a relatively lower
velocity causing less damage to the device.
Similarly, for a triple material MOSFET the electric field
characteristics show two peaks, thus further improving the average
electric field reducing the carrier velocity and at the same time increasing
the number of carriers transported.
Triple material MOSFET with the materials in the ratio 1:2:3 which
is under our consideration has the best foresaid characteristics as
observed.
Here we have considered a double gate MOSFET since it has the
advantages of low do pant fluctuation, low noise and good power gain.
Neglecting fringing effect, there is slight variation with the model.
Also there is high peak, less ionization, high electric field. From figure
1:2:3 structures are much better.

45

Figure: 5.4(a): Single material,

double material (1:1), triple
material [(1:2:3) (1:1:1) (3:2:1)]
from Model

Figure: 5.4(b): Single material,

double material (1:1), triple
material (1:2:3) from TCAD

Figure: 5.4: Electric field along the channel for diferent

structure

46

Figure: 5.5: Graph of electric field profile for diferent

drain voltage

5.4

Comparison on the basis of current

Figure: 5.6(a): single
material, double material
(1:1), triple material (1:2:3)
from Model

47

Figure: 5.6(b): single material, double

material (1:1), triple material (1:2:3)
from TCAD

48

Figure: 5.6: Comparison on the basis of

current
As observed from the surface potential and electric field characteristics, TMDG structure with the ratio of the three materials 1:2:3 shows satisfactory results. So,
we have considered this ratio of TM-DG for further study.
The plot obtained from our model for drain current, figure: 5.6(a) shows that the
drain current is the largest for TM-DG. Theoretically, drain current for DM-DG should
be greater than SM-DG. But we have neglected the fringing effects, so there is a
discrepancy.
The drain current as obtained from TCAD analysis, figure: 5.6(b) shows that
drain current is maximum (0.000843 A) for TM-DG, followed by DM-DG (0.000757
A) and SM-DG (0.000282 A).This result is satisfactory to prove that employing
different materials with different work functions improves the drain current
significantly.

6
OVERVIEW OF TCAD TOOL
6.1

Tony plot

ATLAS is a modular and extensible framework for one, two and three
dimensional semiconductor device simulation. It is implemented using modern
software engineering practices that promote reliability, maintainability, and
extensibility. Products that use the ATLAS Framework meet the device simulation
needs of all semiconductor application areas.

Comprehensive set of models

ATLAS provides a comprehensive set of physical models, including:
DC, AC small-signal, and full time-dependency.
Drift-diffusion transport models.

 Energy balance and Hydrodynamic transport models.

Lattice heating and heat sinks.
Graded and abrupt hetero junctions.
Optoelectronic interactions with general ray tracing.
Amorphous and polycrystalline materials.
General circuit environments.
Stimulated emission and radiation
Fermi-Dirac and Boltzmann statistics.
Advanced mobility models.
Heavy doping effects.
Full acceptor and donor trap dynamics
Ohmic, Schottky, and insulating contacts.
SRH, radioactive, Auger, and surface recombination.
Impact ionization (local and non-local).
Floating gates.
Band-to-band and Fowler-Nordheim tunneling.
Hot carrier injection.
Quantum transport models
Thermionic emission currents.

The nature of physically-based simulation

ATLAS is a physically-based device simulator. Physically-based device simulation
is not a familiar concept for all engineers. This section will briefly describe this type
of simulation. By applying a set of differential equations, derived from Maxwell
laws, onto this grid you can simulate the transport of carriers through a structure.
This means that the electrical performance of a device can now be modeled in DC,
AC or transient modes of operation.
There are three physically-based simulations. These are:
It is predictive.
It provides insight.
It conveniently captures and visualizes theoretical knowledge.
Those who use physically-based device simulation tools must specify the
problem to be simulated. In ATLAS, specify device simulation problems by
defining:
The physical structure to be simulated.
The physical models to be used.
The bias conditions for which electrical characteristics are to be simulated.
The subsequent chapters of this manual describe how to perform these steps.

Getting started with ATLAS

ATLAS is a physically-based two and three dimensional device simulator.
It predicts the electrical behaviour of specified semiconductor structures and
provides insight into the internal physical mechanisms associated with device
operation.

ATLAS Inputs and Outputs

Most ATLAS simulations use two input files. The first input file is a text
file that contains commands for ATLAS to execute. The second input file is a
structure file that defines the structure that will be simulated. ATLAS produces
three types of output files. The first type of output file is the run-time output,
which gives you the progress and the error and warning messages as the
simulation proceeds. The second type of output file is the log file, which stores all
terminal voltages and currents from the device analysis. The third type of output
file is the solution file, which stores 2D and 3D data relating to the values of
solution variables within the device at a given bias poi ATLAS.

Figure: 6.1: ATLAS inputs and outputs

The ATLAS syntax

An ATLAS command file is a list of commands for ATLAS to execute.
This list is stored as an ASCII text file that can be prepared in DECKBUILD or
using any text editor. Preparing an input file in DECKBUILD is preferred, which
can be made easier by using the Deck Build Commands menu in the Deck Build
Window

Defining a structure
A device structure can be defined in three different ways for use in ATLAS:
The first way is to read an existing structure from a file. The structure is created
either by an earlier ATLAS run or another program such as ATHENA or DEVEDIT.
A MESH statement loads in the mesh, geometry, electrode positions, and doping of
the structure. For example:
MESH INFILE=<filename>
The second way is to use the Automatic Inter face feature from
DECKBUILD to transfer the input structure from ATHENA or DEVEDIT. The third
way is create a structure by using the ATLAS command language. In this work, we
create all the structure by using ATLAS command language.

6.2 TCAD program (Deckbuild)

go atlas
% Mesh Initialization %
mesh
x.mloc=0.000 s=0.005
x.mloc=0.130 s=0.005
y.mloc=0.000 s=0.001
y.mloc=0.005 s=0.001
y.mloc=0.007 s=0.001
y.mloc=0.029 s=0.002
y.mloc=0.031 s=0.001
y.mloc=0.036 s=0.001
% REGION SPECIFICATION %
Regionnum=1 x.min=0.000 x.max=0.130 y.min=0.007 y.max=0.029 silicon
Region num=2 x.min=0.020 x.max=0.110 y.min=0.005 y.max=0.007 sio2
Region num=3 x.min=0.000 x.max=0.020 y.min=0.000 y.max=0.007 material=Air
Regionnum=4 x.min=0.110 x.max=0.130 y.min=0.000 y.max=0.007 material=Air
Regionnum=5 x.min=0.020 x.max=0.035 y.min=0.000 y.max=0.005 polysilicon
Regionnum=6 x.min=0.035 x.max=0.065 y.min=0.000 y.max=0.005 polysilicon
Regionnum=7 x.min=0.065 x.max=0.110 y.min=0.000 y.max=0.005 polysilicon
Regionnum=8 x.min=0.020 x.max=0.035 y.min=0.031 y.max=0.036 polysilicon
Regionnum=9 x.min=0.035 x.max=0.065 y.min=0.031 y.max=0.036 polysilicon
Regionnum=10 x.min=0.065 x.max=0.110 y.min=0.031 y.max=0.036 polysilicon
Regionnum=11 x.min=0.020 x.max=0.110 y.min=0.029 y.max=0.031 sio2

Regionnum=12 x.min=0.000 x.max=0.020 y.min=0.029 y.max=0.036 material=Air

Regionnum=13 x.min=0.110 x.max=0.130 y.min=0.029 y.max=0.036 material=Air
% ELECTRODE SPECIFICATION %
Electrodenum=1 name=gate top x.min=0.020 x.max=0.035
Electrodenum=2 name=gate2 top x.min=0.035 x.max=0.065
Electrodenum=3 name=gate3 top x.min=0.065 x.max=0.110
Electrodenum=4 name=gate4 bottom x.min=0.020 x.max=0.035
Electrodenum=5 name=gate5 bottom x.min=0.035 x.max=0.065
Electrodenum=6 name=gate6 bottom x.min=0.065 x.max=0.110
Electrodenum=7 name=source x.min=0.000 x.max=0.000 y.min=0.007 y.max=0.029
Electrodenum=8 name=drain x.min=0.130 x.max=0.130 y.min=0.007 y.max=0.029
% SPECIFICATION OF DOPING PROFILE %
doping region=1 p.type uniform conc=1.0E16
doping region=1 x.min=0.000 x.max=0.020 y.min=0.007 y.max=0.029 n.type
uniform conc=1.0E20
doping region=1 x.min=0.110 x.max=0.130 y.min=0.007 y.max=0.029 n.type
uniform conc=1.0E20
% SPECIFYING CONTACT CHARACTERISTIC %
% SHORTING THREE CONTACT TOGETHER %
contact name=gate n.polysiliconworkfunction=4.8
contact name=gate2 n.polysiliconworkfunction=4.6 common=gate
contact name=gate3 n.polysiliconworkfunction=4.4 common=gate
contact name=gate4 n.polysiliconworkfunction=4.8 common=gate
contact name=gate5 n.polysiliconworkfunction=4.6 common=gate
contact name=gate6 n.polysiliconworkfunction=4.4 common=gate
% STRUCTURE FILE %
Saveoutf=dgtm1_90_22.str
Tonyplot dgtm1_90_22.str
% SPECIFYING PHYSICAL MODEL %
models MOS
% METHOD DECLARATION %
Methodclimit=1.0E-4
Solveinit
% DC SOLUTION %
log outf=dgtm1_90_22.log

solvevgate=0.1
solvevdrain=0.0 vstep=0.05 vfinal=2.2 name=gate
tonyplot dgtm1_90_22.log
extract name="gm123" deriv(v."gate",i."drain") outf="gm123.dat"
tonyplot gm123.dat

Interface from ATHENA

When ATHENA and ATLAS are run under DECKBUILD, you can take
advantage of an automatic interface between the two programs. Perform the some
steps to load the complete mesh, geometry, and doping from ATHENA to ATLAS.

Specifying the initial mesh

The first statement must be:
MESH SPACE.MULT=<VALUE>
This is followed by a series of X.MESH and Y.MESH statements.
X.MESH LOCATION=<VALUE> SPACING=<VALUE>
Y.MESH LOCATION=<VALUE> SPACING=<VALUE>

Figure: 6.2: Tony plot of the triple material double gate MOSFET

7
CONCLUSION AND SCOPE OF THE
FUTURE WORK
7.1 Conclusion
From the result and discussions section, we can say that the TM-DG MOSFET
structure is very promising candidate to suppress short channel effects.
From the plots it is clear that TM-DG MOSFET with material ratio 1:2:3 have
the required characteristics since it has the least shift in the point of minimum
potential. There are mismatches between the characteristics of our model and TCAD
simulation as we have neglected the fringing effects.

7.2 Scope of the future work

The effect of the gate work-function implemented on the multi gate devices can
be extended to the realization of different analogue circuits like the operation
amplifiers. The other different analogue parameters like the linearity; noise
parameter etc. can be analysed for the gate engineering method in the sub

100nm regime. Different high frequency circuits can also be implemented with
these advanced DG MOS devices.
The effect of gate overlap capacitance and quantum mechanical effect is not
included in this paper. The study of this effect is also important.
The study of gate tunnelling and oxide trapped charge effect is very important
for device performance.
The gate engineering technique that shows increased electric
field along the channel may exhibit mobility degradation due
to the velocity saturation effects. This may lead to an
interesting modelling approach of the gate engineered DG
MOSFETs.

8
REFERENCE
[1] International Technology Roadmap for Semiconductors, 2007.[Online].
Available: http://public.itrs.net
[2]W. Long and K. K. Chin, Dual material gate field effect transistor
(DMGFET), in IEDM Tech. Dig., 1997, pp. 549552.
[3]S. Tiwari, J. J.Welser, A. Kumar, and S. Cohen, Straddle-gate transistors:
High Ion/Ioff transistors at short gate lengths, in Proc. DRC Dig., 1999,
pp. 2627.
[4] Y. S. Pang and J. R. Brews, "Analytical sub threshold surface
potential model for pocket n-MOSFETs," IEEE Trans. Electron Devices, vol. 49,
no. 12, pp. 2209-2216, Dec. 2002.
[5] B. Yu, C. H. Wann, E. D. Nowak, K. Noda, and C. Hu, "Short channel effect
improved by lateral channel-engineering in deep sub micrometer MOSFETs,"
IEEE Trans. Electron Devices, vol. 44,pp. 627-634, Apr. 1997.
[6]S.Baishya, A.Mallik and C.K.Sarkar,A sub threshold surface potential

model for short-channel MOSFET taking into account the varying depth of
channel depletion layer due to source and drain junctions, IEEE Trans. Electron
Devices, vol. 53,pp. 507-514, Mar. 2006.
[7] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nded.New
York: McGraw-Hill, 1999.
[8]S.Kolberg T. A.Fjeldly, 2D Modeling of nanoscale DGSOIMOSFETs in and
near the subthreshold regime, J. Comput.
Electron, vol. 5,pp. 217-222, 2006.
[9] C. S. Ho, J. J. Liou, K.-Y. Huang, and C. C. Cheng, "An analytical sub
threshold current model for pocket-implanted NMOSFETs," IEEE
Trans. Electron Devices, vol. 50, no. 6, pp. 1475-1479, Jun. 2003.
[10]SILVACO International 2000, ATLAS: 2-D Device Simulation Software.