About the Experiment

This experiment enables a student to learn:

How to realize the functionality of sequential circuits using basic flip-flops

How to verify the operation of a combinational circuit using flip-flop(D Flip-Flop)

Aim of the Experiment

The objective of part 1 of the experiment is to fully understand the functionality of S-R FlipFlop.
The objective of part 2 of the experiment is to fully understand the functionality of J-K FlipFlop.
The objective of part 3 of the experiment is to fully understand the functiponality of D FlipFlop.
The objective of part 4 of the experiment is to verufy the functiponality of i bit full
adder(Combinational Circuit) using D Flip-Flop.

Sequential Circuits: The logic circuits whose outputs at any instant of time depend not only
on the present input but also on the past outputs are called sequential circuits.
The simplest kind of sequential circuit which is capable of storing one bit of information is
called latch.The operation of basic latch can be modified, by providing an additional control
input that determines, when the state of the circuit is to be changed.
The latch with additional control input is called the Flip-Flop.The additional control input is
either the clock or enable input.
Different types of Flip-Flop: There are four basic types, namely, S-R, J-K, D and T FlipFlops.
S-R Flip-Flop

Figure 1: Clocked NOR-based S-R Flip-Flop

Figure 2: NAND-based S-R Flip-Flop

Figure 3: Typical wave-form in S-R Flip-Flop

Figure 4: S-R Flip-Flop characteristic Table

NOTE :: clk, S and R signals are input signals
Qand Q : Output signals
J-K Flip-Flop

Figure 1: J-K Flip-Flop using S-R Flip-Flop

Figure 2: NAND based J-K Flip-Flop

Figure 3: Typical wave-form in J-K Flip-Flop

Figure 4: J-K Flip-Flop characteristic Table

D Flip-Flop

Figure 1: D Flip-Flop

Figure 2: NAND-based D Flip-Flop

Figure 3: D Flip-Flop characteristic Table

Synthesis using Flip-Flop
As a simple exersise,students can verify the operation of a serial (sequential)adder(1 bit full
adder) Carry output of a one bit full adder can be fed back to the input of a D Flip-Flop.The
output of this Flip=Flop can be fed back to the carry input of that adder.

Figure 1: Verification of the functionality of a combinational circuit using seqential

element(Flip-Flop)

Figure 2: Gate diagram of combinational circuit(1 bit full adder)

Figure 3: Truth table of a 1 bit fulladder

Please follow these steps to do the experiment(Part-I)

1. At first apply high voltage to Vcc1 & Vcc2.So that the "Clock Start" button will be
enabled.

2. Next, start the clock pulse by clicking on the "Clock Start" button and after
generation of some clock pulses stop the clock pulse by clicking on the"clock Stop"
button .

3. Now apply high voltage to S input and low voltage to R input and set "No of clock
pulses" to 1.See the changes at output(Q and Q) at positive clock edge.

4. Now apply high voltage to R input and low voltage to S input and start the clock
pulse.See the changes at output(Q and Q) at positive clock edge.

5. Next,apply low voltage to both the inputs(S and R) and start the clock pulse
again.See the changes at output(Q and Q) at positive clock edge.

6. Next,apply high voltage to both the inputs(S and R) and start the clock pulse
again.See both the outputs(Q and Q) will be zero.It is "not allowed" condition.

Please follow these steps to do the experiment(Part-II)

1. At first apply high voltage to Vcc1 & Vcc2.So that the "Clock Start" button will be
enabled.

2. Next, start the clock pulse by clicking on the "Clock Start" button and after
generation of some clock pulses stop the clock pulse by clicking on the"clock Stop"
button .

3. Now apply high voltage to J input and low voltage to K input and set "No of clock
pulses" to 1.See the changes at output(Q and Q) at positive clock edge.

4. Now apply high voltage to K input and low voltage to J input and start the clock
pulse.See the changes at output(Q and Q) at positive clock edge.

5. Next,apply low voltage to both the inputs(J and K) and start the clock pulse
again.See the changes at output(Q and Q) at positive clock edge.

6. Next,apply high voltage to both the inputs(J and K) and start the clock pulse
again.See both the outputs(Q and Q) will toggle at positive clock edge.

Please follow these steps to do the experiment(Part-III)

1. At first apply high voltage to Vcc1 & Vcc2.So that the "Clock Start" button will be
enabled.

2. Next, start the clock pulse by clicking on the "Clock Start" button and after
generation of some clock pulses stop the clock pulse by clicking on the"clock Stop"
button .

3. Now apply high voltage to D input and set "No of clock pulses" to 1.See the
changes at output(Q and Q) at positive clock edge.

4. Now apply low voltage to D input and start the clock pulse.See the changes at
output(Q and Q) at positive clock edge.