UNIT 3

1.
2.
3.

Draw the stick diagram for 2 input NOR gate using CMOS design style?
Briefly explain resistance estimation?
With neat sketch, explain the three different regions in MOS device

capacitance?

4.

Derive the expression for sheet resistance and calculate the resistance

of a conducting slab if the Rs = 4/square and aspect ratio is 2.

5.

Explain various factors that influence the power dissipation in CMOS

VLSI circuits?

6.
7.
8.

Briefly explain CMOS Lambda based design rules?

Explain scaling of MOS circuits and its parameters which are affected?
With a neat step by step procedure draw the stick diagram of CMOS

inverter?

9.

With neat diagram explain different leakage currents in MOS circuits?

10. In terms of silicon area consumption, out of nMOS NAND and NOR
gates, which one would you prefer and why?
11. Draw the stick diagram of two input XOR gate using nMOS design
style?
12. Mention the basic construction rules for transistor?
13. Derive the expressions for rise time, fall time and delay time?
14. Give the rules for drawing stick diagram using NMOS design style

with an example?
15. Give the layout diagram for the function F= (A+B).C?
16. Why scaling is required and mention the types?
17. Design a layout diagram for the Y= (A+B+C) using nMOS logic?
18. Elaborate Inductance estimation with diagram?
19.Discuss analytic delay models?
20.Explain different types of design rules and give some examples?

UNIT 4
1. Construct XOR and XNOR gates using pass transistor logic with

explanation?
2. Explain CMOS domino logic circuit with an example?
3. Explain the terms: i) standard Cells ii) Gate of arrays with an
example?

4. Give the circuit for the following in CMOS design style i) [A.(B+C)]
5.
6.
7.
8.

ii) AB+C
With neat sketch explain CMOS complementary logic structure?
Briefly explain about dynamic MOS circuits?

Describe charge sharing and its solution in brief?

Draw nMOS and CMOS version of the circuit to realize the following
Boolean expression F = [A(D+E)+BC]
9. List various CMOS logic structures and mention their advantages and
disadvantages?
10.Draw the pseudo-nMOS logic structure for the given Boolean expression F
= [A(B+C)+DE].
11. Explain CMOS logic gate design in AOI style with an example?
12. With neat sketch explain Pseudo nMOS logic?
13. Explain the concept of charge sharing for a dynamic CMOS circuit?
14. Construct XOR and XNOR gates using transmission gates?
15.Give an overview of basic physical design in VLSI?
16. Draw and explain the pass transistor arrangement for the logic

X=ABC ?

17.Design a two-input OR gate in domino logic and pseudo nMOS logic?

18. Explain CMOS logic gate design in OAI style with an example?
19.Dynamic CMOS logic structure cannot be cascaded. Justify?
20.What is pass transistor? Construct AND and NAND gates using pass
transistor logic?

UNIT 5
1. Explain chip level test techniques?
2. Explain what is meant by a Stuck-At-1 fault and Stuck-At-0 fault?
3. Explain the terms controllability, observability and fault coverage?
4. What is the need for testing?
5. Explain short circuit and open circuit fault models?
6. Briefly explain the serial scan based test technique?
7. What is fault simulation? Explain briefly fault models.
8. Explain various categories of manufacturing tests?
9. Discuss about LSSD in scan based test techniques?
10.Write about IDDQ testing?