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PPC400/PPC440 .......................................................................................................................
Warning ..............................................................................................................................
General
Troubleshooting ................................................................................................................
10
SYStem.Up Errors
10
FAQ .....................................................................................................................................
11
PPC400
11
PPC440
15
RISC Trace
22
Configuration .....................................................................................................................
System Overview
23
23
24
24
24
24
25
26
General Restrictions
26
Breakpoints
26
Software Breakpoints
26
On-chip Breakpoints
27
Breakpoint Restrictions
27
Breakpoint in ROM
27
28
1989-2016 Lauterbach GmbH
Memory Classes
29
Memory Coherency
29
30
30
30
SYStem.CPU
SYStem.CpuAccess
SYStem.LOCK
31
31
32
33
SYStem.MemAccess
SYStem.Mode
SYStem.CONFIG
30
Daisy-chain Example
35
TapStates
36
SYStem.CONFIG.CORE
37
38
SYStem.Option CLOCKX2
SYStem.Option DCFREEZE
38
38
SYStem.Option DCREAD
39
SYStem.Option DMALOW
39
39
SYStem.Option FREEZERUN
SYStem.Option FREEZEBDM
39
SYStem.Option FLOWTRACE
40
40
40
SYStem.Option FOLDING
SYStem.Option HOOK
SYStem.Option ICFLUSH
42
SYStem.Option ICREAD
42
42
42
SYStem.Option MMUSPACES
SYStem.Option NoJtagHalt
43
SYStem.Option OVERLAY
SYStem.Option NOTRAP
44
SYStem.Option ResetMode
44
45
BenchMarkCounter ...........................................................................................................
46
47
SYStem.Option TURBO
TrOnchip.view
Setup window
47
48
TrOnchip.DISable
48
TrOnchip.ENable
48
49
Trigger sources
49
49
TrOnchip.TOFF
49
TrOnchip.TON
50
TrOnchip.CONVert
TrOnchip.RESet
TrOnchip.Set
TrOnchip.TEnable
TrOnchip.TTrigger
TrOnchip.VarCONVert
50
50
50
52
TrOnchip.SYNCHRONOUS
MMU.DUMP
52
53
MMU.SCAN
54
MMU.FORMAT
55
56
60
MMU.List
MMU.Set.TLB
Mechanical Description
60
60
60
61
61
62
62
63
63
Support ...............................................................................................................................
Available Tools
64
64
Compilers
66
67
68
Products .............................................................................................................................
69
Product Information
69
Order Information
71
B::Data.List
addr/line
code
P:FFF021C0 39400000
P:FFF021C4 915F0018
567
P:FFF021C8
P:FFF021CC
P:FFF021D0
P:FFF021D4
39200000
2C890012
40850008
4800001C
B::Register
R0
0
R1
0FFFFFFD8
R2
0
R3
0
R4
0
R5
0
R6
0
R7
0
SPRG0
0
SPRG1
0
SPRG2
0
label
mnemonic
li
stw
comment
r10,0
r10,18(r31)
R8
R9
R10
R11
R12
R13
R14
R15
SRR0
SRR1
SRR2
0
0
0
0
0
0
0
0
0
0
0
B::PER
EXISR 80000000 CIS pending
D0IS wait
E0IS wait
S
D
E
Input
Output Configuration
IOCR 00000000 E0T level E1T level E2T le
E0L negative E1L negative
RDM disabled TCS sysclk
S
Bank 0
BR0
FF183FFE BAS 0FF00000
SRIS wait
D1IS wait
E1IS wait
BS 1MB
BU rea
Debugger Basics - Training (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.
Architecture-specific information:
Processor Architecture Manuals: These manuals describe commands that are specific for the
processor architecture supported by your debug cable. To access the manual for your processor
architecture, proceed as follows:
-
RTOS Debugger (rtos_<x>.pdf): TRACE32 PowerView can be extended for operating systemaware debugging. The appropriate RTOS manual informs you how to enable the OS-aware
debugging.
Warning
ESD Protection
NOTE:
Disconnect the debug cable from the target while the target power is
off.
2.
Connect the host system, the TRACE32 hardware and the debug
cable.
3.
4.
5.
6.
7.
Power down:
1.
2.
3.
4.
Warning
General
Locate the JTAG connector as close as possible to the processor to minimize the capacitive influence of
the trace length and cross coupling of noise onto the BDM signals.
Select the device prompt B: for the ICD Debugger, if the device prompt is not active after starting
the TRACE32 software.
b:
2.
3.
4.
This command resets the CPU and enters debug mode. After this command is executed it is possible
to access memory and registers.
6.
7.
The option of the Data.LOAD command depends on the file format generated by the compiler. For
information on the compiler options refer to the section Compiler. A detailed description of the
Data.LOAD command is given in the General Commands Reference.
The start up can be automated using the programming language PRACTICE. A typical start sequence is
shown below:
b::
WinCLEAR
MAP.BOnchip 0x100000++0x0fffff
SYStem.CPU 403gcx
SYStem.Up
Data.LOAD.Elf GNU403
Register.Set PC main
Data.List
Register /SpotLight
PER.view
Break.Set sieve
;
;
;
;
*) These commands open windows on the screen. The window position can be specified with the WinPOS
command.
Troubleshooting
SYStem.Up Errors
The SYStem.Up command is the first command of a debug session where communication with the target is
required. If you receive error messages while executing this command this may have the following reasons.
All
All
The pull-up resistor between the JTAG/COP[VCCS] pin and the target VCC
is too large.
All
All
All
10
Troubleshooting
FAQ
PPC400
Debugging via
VPN
11
FAQ
Setting a
Software
Breakpoint fails
IOP480
Wrong Reset
Address
Why does the reset vector of the IOP480 not point to the reset vector of the
401 core?
In the default setting for the PPC400 family the option
SYStem.Option.ResetMode.SYSTEM is chosen. After SYStem.Up the PC
points to the address of the last session or to any other address. Use the
SYStem.Option.ResetMode.CHIP or SYStem.Option.ResetMode.CORE,
because the system reset is not implemented on the IOP480.
PPC400
Connection to
Target Fails
When connecting to XILINX targets be sure to use a recent version of the debug
cable (see picture).
With the old version of the debug cable target connection will fail or be
unreliable.
12
FAQ
PPC4XX
Emulation
Debug Port
Problem
PPC4XX
Software
Breakpoints
Problem
PPC4xx
Stepping over
TLBWE
instruction
Virtex-PPC400
Flow Errors
Virtex-PPC400
Flow Errors
while Tracing
works
13
FAQ
VIRTEXPPC405
ISOCM Access
in Xilinx
VirtexFX Chips
Virtex-PPC4XX
Debugging and
Tracing
Embedded
PPC Cores in
Xilinx FPGAs
14
FAQ
PPC440
Debugging via
VPN
15
FAQ
Setting a
Software
Breakpoint fails
APM86190
APM86x90
verus
APM86x90B
APM86190
Protected
Access Error
APM86190
SYS.Detect.CP
U
ApmPacketPro
Single/Dual
16
FAQ
APM86190
SYStem.Up/
InTargetReset
with APM86xxx
APM86190B
APM86x90
verus
APM86x90B
APM86290
APM86x90
verus
APM86x90B
APM86290
Protected
Access Error
APM86290
SYS.Detect.CP
U
ApmPacketPro
Single/Dual
Many devices of the APM86xxx family share common JtagIDs which do not
allow to distinguish between the single derivatives. As a solution a general
ApmPacketProSingle/Dual device is detected to allow general debugging.
APM86290
SYStem.Up/
InTargetReset
with APM86xxx
17
FAQ
APM86290B
APM86x90
verus
APM86x90B
APM86491
Protected
Access Error
APM86491
SYS.Detect.CP
U
ApmPacketPro
Single/Dual
Many devices of the APM86xxx family share common JtagIDs which do not
allow to distinguish between the single derivatives. As a solution a general
ApmPacketProSingle/Dual device is detected to allow general debugging.
APM86491
SYStem.Up/
InTargetReset
with APM86xxx
APM86692
Protected
Access Error
APM86692
SYS.Detect.CP
U
ApmPacketPro
Single/Dual
18
FAQ
APM86692
SYStem.Up/
InTargetReset
with APM86xxx
APM86791
Protected
Access Error
APM86791
SYS.Detect.CP
U
ApmPacketPro
Single/Dual
Many devices of the APM86xxx family share common JtagIDs which do not
allow to distinguish between the single derivatives. As a solution a general
ApmPacketProSingle/Dual device is detected to allow general debugging.
APM86791
SYStem.Up/
InTargetReset
with APM86xxx
MICROBLAZE
No Source
Code shown
on Xilinx
Targets
PPC440
Connection to
Target Fails
19
FAQ
PPC440
No Source
Code shown
on Xilinx
Targets
PPC440GX
Enable/
configure
mixed TRACE
Interface
20
FAQ
PPC4XX
Software
Breakpoints
Problem
PPC4xx
Stepping over
TLBWE
instruction
VIRTEXPPC440
ISOCM Access
in Xilinx
VirtexFX Chips
Virtex-PPC4XX
Debugging and
Tracing
Embedded
PPC Cores in
Xilinx FPGAs
21
FAQ
RISC Trace
No information available.
22
FAQ
Configuration
System Overview
PODBUS Cable
PODPC
PODPAR
PODETH
Debug
Interface
EPROM
Simulator
(optional)
...
Debug Cable
CPU CLK
Target Connector
EPROM
Target
RESET
INT
(600
only)
NOTE:
Together with the debug interface you get a small black wire to connect the CPU
clock to the plug on the debug module. This way you can use the divided CPU
clock as clock for the debug interface.
NOTE:
If you use the PPC400 family you get a second wire to connect the TS4 signal.
This is only necessary if you want to use the TrBus.Out command.
23
Configuration
Exceptions
9.
10.
11.
12.
Instruction address after a return from interrupt or return from critical interrupt(RFI,RFCI)
24
If a Trace Start events has occurred (depend on DBCR Register configuration) then the first RiscTrace
program flow synchronization take place after one of the five cases explained before are executed. This
means that the program should be traced, must consist one of the five special cases. Source code parts
which do not consist of one of the five cases, which start the FlowTrace broadcast, cannot be traced in the
fifo mode.
25
General Restrictions
PPC400
Make sure, that you don't increase the debug clock without decreasing the
internal waitstates, when the TURBO option is enabled. If external waitstates
are used it is recommended to switch TURBO mode off. The BDM driver may
not work with older PPC403GA-JA25 samples.
Breakpoints
There are two types of breakpoints available: Software breakpoints (SW-BP) and on-chip breakpoints (HWBP).
Software Breakpoints
Software breakpoints are the default breakpoints. They can only be used in RAM areas.There is no
restriction in the number of software breakpoints. Please consider that increasing the number of software
breakpoints will reduce the debug speed.
26
On-chip Breakpoints
The following list gives an overview of the usage of the on-chip breakpoints by
TRACE32-ICD:
CPU family
Instruction breakpoints: Number of on-chip breakpoints that can be used for program and spot
breakpoints
Read/Write breakpoints: Number of on-chip breakpoints that can be used as read or write
breakpoints.
Data breakpoints: Number of on-chip data breakpoints that can be used to stop the program
when a specific data value is written to an address or when a specific data value is read from an
address.
CPU Family
On-chip
Breakpoints
Instruction
Breakpoints
Read/Write
Breakpoints
Data
Breakpoints
PPC401/403
2 Instruction
2 Read/Write
PPC405
4 Instruction
2 Read/Write
Breakpoint Restrictions
You can check your currently set breakpoints with the command Break.List
Breakpoint in ROM
With the command MAP.BOnchip <range> it is possible to inform the debugger where you have ROM
(FLASH,EPROM) on the target. If a breakpoint is set within the specified address range the debugger uses
automatically the available on-chip breakpoints.
27
2.
Software breakpoints:
; Software Breakpoint 1
; Software Breakpoint 2
; Software Breakpoint 3
On-chip breakpoints:
Break.Set 0x100 /Program
; On-chip Breakpoint 1
; On-chip Breakpoint 2
28
Memory Classes
The following memory classes are available:
Memory Class
Description
Program
Data
SPR
DCR
IC
Instruction Cache
DC
Data Cache
NC
If caching is disabled via the appropriate hardware registers (DCCR/ICCR for PPC400 series, HID0 for
PPC603 series), memory accesses to the memory classes IC or DC are realized by TRACE32-ICD as
reads and writes to physical memory.
Memory Coherency
Memory coherency on access to the following memory classes. If data will be set to DC, IC, NC, D or P the
D-Cache, I-Cache or physical memory will be updated.
D-Cache
I-Cache
Physical Memory
DC:
Yes
No
Yes
IC:
No
Yes
Yes
NC:
No
No
Yes
D:
Yes
Yes
Yes
P:
Yes
Yes
Yes
29
SYStem.BdmClock
Format:
SYStem.BdmClock <rate>
<rate>:
2. | 4.
<fixed>:
SYStem.CPU
Format:
SYStem.CPU <cpu>
<cpu>:
SYStem.CpuAccess
Format:
Default: Denied.
Enable
30
Denied
Nonstop
Lock all features of the debugger, that affect the run-time behavior.
Nonstop reduces the functionality of the debugger to:
trace display
The debugger inhibits the following:
all features of the debugger that are intrusive (e.g. action Spot for breakpoints, performance analysis via StopAndGo mode, conditional breakpoints etc.)
SYStem.LOCK
Format:
Default: OFF.
If the system is locked, no access to the debug port will be performed by the debugger. While locked, the
debug connector of the debugger is tristated. The main intention of the lock command is to give debug
access to another tool.
SYStem.MemAccess
Format:
SYStem.MemAccess Denied<cpu_specific>
SYStem.ACCESS (deprecated)
Denied
31
SYStem.Mode
Format:
SYStem.Mode <mode>
<mode>:
Down
NoDebug
Go
Attach
Up
NoDebug
Resets the target with debug mode disabled (for the PPC400 family the same
as Go). In this mode no debugging is possible. The CPU state keeps in the
state of NoDebug.
Go
Resets the target with debug mode enabled and prepares the CPU for debug
mode entry. After this command the CPU is in the system.up mode and running.
Now, the processor can be stopped with the break command or until any break
condition occurs.
Up
Resets the target and sets the CPU to debug mode. After execution of this
command the CPU is stopped and prepared for debugging. All register are set
to the default value.
Attach
This command works similar to Up command. The difference is, that the target
CPU is not reset. The BDM/JTAG/COP interface will be synchronized and the
CPU state will be read out. After this command the CPU is in the SYStem.Up
mode and can be stopped for debugging.
StandBy
32
SYStem.CONFIG
Format:
<parameter>
(General):
state
CORE
(JTAG):
DRPRE <bits>
DRPOST <bits>
IRPRE
<bits>
IRPOST <bits>
TAPState <state>
TCKLevel <level>
TriState [ON | OFF]
Slave
[ON | OFF]
<core>
The four parameters IRPRE, IRPOST, DRPRE, DRPOST are required to inform the debugger about the
TAP controller position in the JTAG chain, if there is more than one core in the JTAG chain (e.g. ARM +
DSP). The information is required before the debugger can be activated e.g. by a SYStem.Up. See Daisychain Example.
For some CPU selections (SYStem.CPU) the above setting might be automatically included, since the
required system configuration of these CPUs is known.
TriState has to be used if several debuggers (via separate cables) are connected to a common JTAG port
at the same time in order to ensure that always only one debugger drives the signal lines. TAPState and
TCKLevel define the TAP state and TCK level which is selected when the debugger switches to tristate
mode. Please note: nTRST must have a pull-up resistor on the target, TCK can have a pull-up or pull-down
resistor, other trigger inputs needs to be kept in inactive state.
Multicore debugging is not supported for the DEBUG INTERFACE (LA-7701).
33
state
CORE
For multicore debugging one TRACE32 GUI has to be started per core.
To bundle several cores in one processor as required by the system this
command has to be used to define core and processor coordinates within
the system topology.
Further information can be found in SYStem.CONFIG.CORE.
DRPRE
DRPOST
(default: 0) <number> of TAPs in the JTAG chain between the TDI signal
of the debugger and the core of interest. If each core in the system
contributes only one TAP to the JTAG chain, DRPOST is the number of
cores between the TDI signal of the debugger and the core of interest.
IRPRE
IRPOST
TAPState
TCKLevel
TriState
(default: OFF) If several debuggers share the same debug port, this
option is required. The debugger switches to tristate mode after each
debug port access. Then other debuggers can access the port. JTAG:
This option must be used, if the JTAG line of multiple debug boxes are
connected by a JTAG joiner adapter to access a single JTAG chain.
Slave
(default: OFF) If more than one debugger share the same debug port, all
except one must have this option active.
JTAG: Only one debugger - the master - is allowed to control the signals
nTRST and nSRST (nRESET).
34
Daisy-chain Example
TDI
Core A
Core B
Core C
Chip 0
Core D
TDO
Chip 1
Core A: 3 bit
Core B: 5 bit
Core D: 6 bit
SYStem.CONFIG.IRPRE 6
; IR Core D
SYStem.CONFIG.IRPOST 8
; IR Core A + B
SYStem.CONFIG.DRPRE 1
; DR Core D
SYStem.CONFIG.DRPOST 2
; DR Core A + B
SYStem.CONFIG.CORE 0. 1.
35
TapStates
0
Exit2-DR
Exit1-DR
Shift-DR
Pause-DR
Select-IR-Scan
Update-DR
Capture-DR
Select-DR-Scan
Exit2-IR
Exit1-IR
10
Shift-IR
11
Pause-IR
12
Run-Test/Idle
13
Update-IR
14
Capture-IR
15
Test-Logic-Reset
36
SYStem.CONFIG.CORE
Format:
<chipindex>:
1i
<coreindex>:
1k
37
SYStem.Option CLOCKX2
Format:
This option select the clock for the Real-Time Trace. (Required for the TRACE32-ICD Risc Trace Modul).If
the 403GCX works with internal double clock (IOCR [2XC]), this option must be on before starting to record
with the trace.
If the source code being traced change the IOCR[2XC] register by its own
during the trace, the RiscTrace doesnt works properly.
SYStem.Option DCFREEZE
Format:
If this feature is enabled the status of the data caches is preserved while debugging. This feature should be
used in combination with SYStem.Option.DCREAD in order to read data as seen by the core. Otherwise all
memory accesses are as for access class NC.
If disabled, the debugger might modify the caches contents with each data access e.g. a Data.dump
window.
For caches that use hardware coherency (e.g. MESI protocol), the DCFREEZE feature is not supported.
This respects multicore architectures that use non-shared caches.
38
SYStem.Option DCREAD
Format:
Data.dump windows for memory class D: displays the memory value from the d-cache if valid. If d-cache is
not valid the physical memory will be read.
If caching is disabled via the appropriate hardware registers (DCCR/ICCR for
PPC400 Series) or cache is invalid, read and writes from/to memory will directly
reflect to contents of physical memory even if a cache memory class is
selected.
SYStem.Option DMALOW
Format:
All DMA transfers continue in debug mode. If DMALOW is enabled all DMA activities are switched to low
priority.
SYStem.Option FREEZERUN
Format:
Controls the internal CPU timer. If FREEZERUN is enabled, the timer will be stopped whenever the CPU
enters the user mode.
SYStem.Option FREEZEBDM
Format:
Controls the internal CPU timer. If FREEZEBDM is enabled, the timer will be stopped whenever the CPU
enters the debug mode.
39
SYStem.Option FLOWTRACE
Format:
Prepare the CPU for real-time trace. (Required for the TRACE32-ICD RISC Trace Module). If switched on,
on every step or go the DBCR[EDM,IDM] bits are switched off and the IOCR[RDM] bits are switched to
Trace Mode automatically.
SYStem.Option FOLDING
Format:
The PPC400 CPUs can execute more than one instruction per cycle. If FOLDING is disabled, exactly one
instruction is executed per cycle.
SYStem.Option HOOK
Format:
The command defines the hook address. After program break the hook address is compared against the
program counter value.
If the values are equal, it is supposed that a hook function was executed. This information is used to
determine the right break address by the debugger.
This option make it possible to use breakpoints in the Real-Time Trace Mode. (Required for the TRACE32ICD RISC Trace Module) This assume that the trap exception handler can be modified for the RiscTrace.
After any synchronize break (using breakpoints) the IP will be compared with the Hook value. If true than the
last exception of will be canceled.
For example. Do use breakpoints, the trap exception handler must be prepared with some instructions.
P:FFF00700 lis r3,0
40
If the CPU runs the instruction P:FFF0070C mtxxx, it stops. The IP will be compared to the Hook value. If the
Hook value is also 0xFFF0070C the exception will be canceled and the CPU register reconstructed to the
last breakpoint.
If you start again after a break with a breakpoint the IP is on the breakpoint.
This means that in the HLL mode a step are executed before the processor put
into run mode.
41
SYStem.Option ICFLUSH
Format:
Invalidates the instruction cache and flush the data cache before starting the target program (Step or Go).
This is required when the ICACHEs are enabled and software breakpoints are set to a cached location.
SYStem.Option ICREAD
Format:
Data.List window and Data.dump window for memory class P: displays the memory value from the I-cache if
valid. If I-cache is not valid the physical memory will be read.
SYStem.Option MMUSPACES
Format:
Default: OFF.
Enables the usage of the MMU to support multiple address spaces. The command should not be used if
only one translation table is used. Enabling the option will extend the address scheme of the debugger by a
16 bit memory space identifier. You should activate the option first, and then load the symbols.
SYStem.Option NoJtagHalt
Format:
Default: OFF.
The JTAG connection for an PowerPC 4xx type CPU features an HALT- signal which will stop the CPU. The
HALT- line enables to stop an core independently from the BDM/JTAG clock. As the HALT- line is a shared
signal for all cores & chips in a JTAG chain all cores & chips stop if the HALT- line is asserted.
1989-2016 Lauterbach GmbH
42
By disabling the HALT- line it is possible to debug only specific cores in the chain without interference with
other PowerPC 4xx cores/chips (AMP). A side effect of this option is that the SYStem.Up behavior will
change as the core will then not be prevented from executing code after an reset. Thus if this option is
enabled the CPU will have executed some code after SYStem.Up and the system might be no longer in
reset status.
SYStem.Option NOTRAP
Format:
If the user software uses the TRAP command, the CPU performs a BREAK in debug mode and does not
jump to the interrupt handler of the TRAP command.
Normally, the T32Fire uses the trap command as patch for the synchronous software breakpoints. With this
option, a illegal instruction is used instead. (MPC5xx/8xx) or no software breakpoints are possible
(MPC4xx).
43
SYStem.Option OVERLAY
Format:
Default: OFF.
ON
Activates the overlay extension and extends the address scheme of the
debugger with a 16 bit virtual overlay ID. Addresses therefore have the
format <overlay_id>:<address>. This enables the debugger to
handle overlaid program memory.
OFF
WithOVS
Like option ON, but also enables support for software breakpoints. This
means that TRACE32 writes software breakpoint opcodes both to the
execution area (for active overlays) and to the storage area. In this way, it is
possible to set breakpoints into inactive overlays. Upon activation of the
overlay, the target's runtime mechanisms copies the breakpoint opcodes to
execution area. For using this option, the storage area must be readable and
writable for the debugger.
SYStem.Option OVERLAY ON
Data.List 0x2:0x11c4
; Data.List <overlay_id>:<address>
SYStem.Option ResetMode
Format:
Use this option to select the type of reset at SYStem.Up. There are three types of resets:
CHIP
Note that a reset of the core does not reset the register tbd.
44
SYStem.Option TURBO
Format:
If there are buffers, additional loads or high capacities on the JTAG/COP lines,
reduce the debug speed.
Enables Turbo debugging. If Turbo is disabled, the CPU checks after each memory access in debug mode if
the CPU is ready. This check will decrease debug speed (30-40%).
If Turbo is enabled, the CPU will make no checks. The internal waitstates for a memory access must be
decremented before increasing the debug frequency. With the default debug frequency of 1 MHz Turbo can
always be enabled.
45
BenchMarkCounter
For information about the architecture-independent BMC commands, refer to BMC (general_ref_b.pdf).
46
BenchMarkCounter
The features supported by the TrOnchip command for TRACE32-ICD vary for
the different PowerPC families.
TrOnchip.view
Setup window
Format:
TrOnchip.view
A.Data
OFF
G
H
GORH
GANDH
A.CYcle
Read
Write
Access
A.Lbus
OFF
A
B
C
A.Ibus
OFF
A
B
C
B.Data
OFF
G
H
GORH
GANDH
B.CYcle
Read
Write
Access
A.Count
1.
B.Count
1.
B.Lbus
OFF
A
B
C
B.Ibus
OFF
A
B
C
G.Value
00000000
G.Size
Byte
Word
Long
G.Match
OFF
EQ
NE
LE
GE
LT
GT
SIGNED
47
TrOnchip.CONVert
Format:
The on-chip breakpoints can only cover specific ranges. If a range cannot be programmed into the
breakpoint it will automatically be converted into a single address breakpoint when this option is active. This
is the default. Otherwise an error message is generated.
TrOnchip.CONVert ON
Break.Set 0x1000--0x17ff /Write
Break.Set 0x1001--0x17ff /Write
TrOnchip.CONVert OFF
Break.Set 0x1000--0x17ff /Write
Break.Set 0x1001--0x17ff /Write
TrOnchip.DISable
Format:
TrOnchip.DISable
Disables NEXUS register control by the debugger. By executing this command, the debugger will not write or
modify any registers of the NEXUS block. This option can be used to manually set up the NEXUS trace
registers. The NEXUS memory access is not affected by this command. To re-enable NEXUS register
control, use command TrOnchip.ENable. Per default, NEXUS register control is enabled.
tbd.
TrOnchip.ENable
Format:
If TrOnchip.Enable is ON (by default) the CPU internal trigger/trace/debug feature like IACx (Instruction
Address Compare Register) and DACx (Data Address Compare Register) will be used by the debugger. If
TrOnchip.Enable is OFF, the registers can be manually programmed by user or application.
48
TrOnchip.RESet
Format:
TrOnchip.RESet
Sets the TrOnchip settings and trigger module to the default settings.
TrOnchip.Set
Trigger sources
Format:
<item>:
BRANCH
eXception
Enables various trigger events. Detailed description of the trigger events can be found in the processor
manuals.
eXeption
BRANCH
TrOnchip.TEnable
Format:
TrOnchip.TEnable <par>
TrOnchip.TOFF
Format:
TrOnchip.TOFF
49
TrOnchip.TON
Format:
TrOnchip.TTrigger
Format:
TrOnchip.TTrigger <par>
Obsolete command. Refer to the Break.Set command to set a trigger for the trace.
TrOnchip.VarCONVert
Format:
The on-chip breakpoints can only cover specific ranges. If you want to set a marker or breakpoint to a
complex variable, the on-chip break resources of the CPU may be not powerful enough to cover the whole
structure. If the option TrOnchip.VarCONVert is on the breakpoint will automatically be converted into a
single address breakpoint. This is the default setting. Otherwise an error message is generated.
TrOnchip.SYNCHRONOUS
Format:
Default: OFF.
Switches the mode of the DAC (Data Address Compare Register) for debug events on PPC44x/PPC46x
cores. This mode setting is only effective if read/write breakpoints are used.
If the DAC works in synchronous mode the processor enters the stop state when reaching load/store
instructions and ceases the processing of instructions. This means the CPU will stop on a load/store
instruction without executing the read/write cycle. The disadvantage is that the core performance for load/
store instructions will be reduced in synchronous mode. Switch the synchronous mode OFF in order to
maintain normal processor performance .
50
In asynchronous DAC mode the processor enters stop state on load/store instructions either before or after
the completion of the instruction. This means the CPU will execute the read/write cycle and stop some
instructions later for the most cases.
51
MMU.DUMP
Format:
<table>:
PageTable
KernelPageTable
TaskPageTable <task>
and CPU specific tables
If the command is called with either an address range or an explicit address, table entries will
only be displayed, if their logical address matches with the given parameter.
The optional <root> argument can be used to specify a page table base address deviating from the default
page table base address. This allows to display a page table located anywhere in memory.
PageTable
KernelPageTable
TaskPageTable
TLB
52
MMU.List
Format:
<table>:
PageTable
KernelPageTable
TaskPageTable <task>
Lists the address translation of the CPU specific MMU table. If called without address or range parameters,
the complete table will be displayed.
If called without a table specifier, this command shows the debugger internal translation table.
See TRANSlation.List.
If the command is called with either an address range or an explicit address, table entries will only be
displayed, if their logical address matches with the given parameter.
PageTable
KernelPageTable
TaskPageTable
TLB
53
MMU.SCAN
Format:
<table>:
PageTable
KernelPageTable
TaskPageTable <task>
ALL
and CPU specific tables
Loads the CPU specific MMU translation table from the CPU to the debugger internal translation table. If
called without parameters the complete page table will be loaded. The loaded address translation can be
viewed with TRANSlation.List.
If the command is called with either an address range or an explicit address, page table entries will only be
loaded if their logical address matches with the given parameter.
PageTable
KernelPageTable
TaskPageTable
ALL
54
ITLB
Loads the instruction translation table from the CPU to the debugger internal
translation table.
DTLB
Loads the data translation table from the CPU to the debugger internal
translation table.
TLB
Loads the translation table from the CPU to the debugger internal translation
table.
TLB0
Loads the translation table 0 from the CPU to the debugger internal
translation table.
TLB1
Loads the translation table 1from the CPU to the debugger internal
translation table.
TLB2
Loads the translation table 2 from the CPU to the debugger internal
translation table.
MMU.FORMAT
Format:
<format>:
LINUX
LINUX26
LINUXEXT
LINUXE5
LYNXOS
LYNXOSPHYS
QNX
QNXBIG
DEOS
DEOS64
Defines the structure of the MMU table and optionally the base for the kernel space table.
LINUX
LINUXEXT
If you require support for a particular operating system, please contact support@lauterbach.com.
See also MMU.FORMAT in general_ref_m.pdf.
1989-2016 Lauterbach GmbH
55
MMU.Set.TLB
Format 1:
PPC 40x
Format 2:
PPC 44x/46x
Format 3:
PPC 47x
Creates/modifies an TLB entry addressed by index (optional: way) in the target CPU. The provided settings
match the format of the tlbwe instruction of the target CPU and is thus CPU/Architecture specific. For the
exact meaning of the Bits provided below please refer to the CPUs/Architecture User-Guide.
Common arguments:
<index>
<way>
56
EPN
SIZ
U0
TID
Bit
[0:21]
[22:24]
[25]
[26]
[27]
[28:35]
<hi>
RPN
SXW
ZSEL
WIMG
Bit
[0:21]
[22:23]
[24:27]
[28:31]
Examples:
; Create TLB Entry, A:0x08800000++0x3FFFFF <-> SD:0x08800000++0x3FFFFF
; TID: 0x0, Permissions: eXecute, Write
MMU.TLBSET 0. 0x0880034000 0x08800300
; Create TLB Entry, A:0x90000000++0xFFF <-> SD:0x0++0xFFF
; TID: 0x0, Permissions: Write,
Cache: Inhibit, Guarded
MMU.TLBSET 1. 0x000000C000 0x90000105
EPN
TS
SIZE
TID
Bit
[0:21]
[22]
[23]
[24:27]
[28:31]
[32:39]
<ws1>
RPN
ERPN
Bit
[0:21]
[20:21]
[22:31]
57
<ws2>
Bit
[0:9]
FAR,WL1
IL1ID2ID
WIMGE
UXWRSXWR
[10:11]
[12:15]
[16:19]
[20:24]
[26:31]
Examples:
; Create TLB Entry, A:0xE:0x0xFFFF8000++0x3FFF <-> SD:0xE0000000++0x3FFF
; TID: 0x0, Permissions: User XWR, Supervisor XWR, Cache: Inhibit (L1&L2)
MMU.TLBSET 0. 0xE000022000 0xFFFF800E 0x000F043F
; Create TLB Entry, A:0x0:0x0++0x0FFFFFFF <-> SD:0xC0000000++0x0FFFFFFF
; TID: 0x0, Permissions: User ---, Supervisor XWR, Bolted: 0x1,
; Coherency: Enabled => WL1=1
MMU.TLBSET 1. 0xC000029000 0x00000000 0x00100207
EPN
TS
DSIZ
TID
Bit
[0:19]
[20]
[21]
[22:27]
[28:31]
[32:39]
<ws1>
RPN
ERPN
Bit
[0:19]
[20:21]
[22:31]
<ws2>
IL1ID
WIMGE
UXWRSXWR
Bit
[0:12]
[14:15]
[16:19]
[20:24]
[25]
[26:31]
58
Examples:
; Create TLB Entry, A:0x2F:0x2000++0xFFF <-> SD:0x80801000++0xFFF
; TID: 0x0, Permissions: User ---, Supervisor XWR, Cache: Inhibit
; EA=0x80801000, DSIZ=0x0 => Index=0x1
MMU.TLBSET 0x1 0x0 0x8080180000 0x0000202F 0x00004007
; Create TLB Entry, A:0x0:0x0++0x3FFFFFFF <-> SD:0x0++0x3FFFFFFF
; TID: 0x0, Permissions: User ---, Supervisor XWR, Bolted: 0x1,
; Coherency: Enabled
; EA=0x00000000, DSIZ=0x3F => Index=0xC0, Bolted => Way=0x0
MMU.TLBSET 0x0 0x0 0xC0000BF000 0x00000000 0x00002007 /Bolted 1.
59
Debug Connector
Mechanical Description
JTAG Connector PPC401/403/405 and IOP480
It is recommended to connect all N/C Pins to GND (if you work with LAUTERBACH tools only).
Signal
TDO
TDI
N/C
TCK
TMS
HALTN/C
N/C
Pin
1
3
5
7
9
11
13
15
Pin
2
4
6
8
10
12
16
Signal
N/C
TRST- (*)
VCCS
N/C
N/C
N/C
KEY
GND
This is a standard 16 pin double row (two rows of eight pins) connector (pin to pin spacing: 0.100 in.).
60
Debug Connector
Trace Connectors
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
Signal
N/C
N/C
TRACECLK
N/C
N/C
VTREF
N/C
N/C
N/C
N/C
N/C
ES4
TS0
TS1
TS2
TS3
TS4
TS5
TS6
61
Trace Connectors
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
Signal
N/C
N/C
TRACECLK
N/C
N/C
VTREF
N/C
N/C
N/C
N/C
N/C
TS1O
TS2O
TS1E
TS2E
TS3
TS4
TS5
TS6
Pin
1
3
5
7
9
11
13
15
17
19
Pin
2
4
6
8
10
12
14
16
18
20
Signal
N/C
N/C
N/C
N/C
N/C
TS1O
TS1E
TS3
TS5
GND
This is a standard 20 pin double row (two rows of eight pins) connector (pin to pin spacing: 0.100 in.).
62
Trace Connectors
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
Signal
N/C
N/C
TRACECLK
N/C
N/C
VTREF
N/C
N/C
N/C
N/C
N/C
GND
TS0
TS1
TS2
TS3
TS4
TS5
TS6
Pin
1
3
5
7
9
11
13
15
17
19
Pin
2
4
6
8
10
12
14
16
18
20
Signal
N/C
N/C
N/C
N/C
N/C
N/C
TS1
TS3
TS5
GND
This is a standard 20 pin double row (two rows of eight pins) connector (pin to pin spacing: 0.100 in.).
63
Trace Connectors
Support
IOP480
NPE405H
NPE405L
PPC401
PPC403GA
PPC403GB
PPC403GC
PPC403GCX
PPC405
PPC405Axx
PPC405Bxx
PPC405CR
PPC405Cxx
PPC405Dxx
PPC405EP
PPC405EX
PPC405Exx
PPC405Fxx
PPC405GP
PPC405GPR
PPC405LP
PPC405PM
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
ICD
DEBUG
FIRE
ICE
CPU
Available Tools
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
64
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
ICD
DEBUG
FIRE
ICE
CPU
ACP3448
APM86190
APM86190B
APM86290
APM86290B
APM86491
APM86692
PPC440
PPC440Axx
PPC440EP
PPC440EPX
PPC440GP
PPC440GR
PPC440GRX
PPC440GX
PPC440Gxx
PPC440SP
PPC440SPE
PPC460EX
PPC460GT
PPC460SX
PPC476FPE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
65
Support
Compilers
Language
Compiler
Company
Option
ADA
GNAT
ELF/DWARF
C
C
CXPPC
XCC-V
C
C
GREEN-HILLS-C
MCCPPC
C
C
C
C
C
C
C
C++
CC
ULTRA-C
HIGH-C
DCPPC
D-CC
D-CC
D-CC
GCC
C++
C++
GREEN-HILLSC++
CCCPPC
Free Software
Foundation, Inc.
Cosmic Software
GAIO Technology Co.,
Ltd.
Greenhills Software Inc.
Mentor Graphics
Corporation
NXP Semiconductors
Radisys Inc.
Synopsys, Inc
TASKING
Wind River Systems
Wind River Systems
Wind River Systems
Free Software
Foundation, Inc.
Greenhills Software Inc.
C++
C++
C++
C++
C/C++
MSVC
HIGH-C++
D-C++
GCCPPC
GCC
C/C++
GCC
CODEWARRIOR
GCC
JAVA
FASTJ
Mentor Graphics
Corporation
Microsoft Corporation
Synopsys, Inc
Wind River Systems
Wind River Systems
HighTec EDV-Systeme
GmbH
NXP Semiconductors
Free Software
Foundation, Inc.
Wind River Systems
Comment
ELF/DWARF
SAUF
ELF/DWARF
ELF/DWARF
XCOFF
ROF
ELF/DWARF
ELF/DWARF
IEEE
COFF
ELF/DWARF
ELF/DWARF
ELF/DWARF
ELF/DWARF
EXE/CV5
ELF/DWARF
ELF/DWARF
ELF/STABS
ELF/DWARF
WindowsCE
ELF/DWARF
ELF/DWARF
ELF/DWARF
66
Support
Company
Comment
AMX
ChorusOS
CMX-RTX
DEOS
ECOS
Elektrobit tresos
ERCOSEK
Erika
FreeRTOS
Linux
Linux
LynxOS
MQX
MQX
NetBSD
NORTi
Nucleus PLUS
OS-9
OSE Delta
OSEK
OSEKturbo
PikeOS
ProOSEK
pSOS+
QNX
RTEMS
RTXC 3.2
RTXC Quadros
Sciopta
SMX
ThreadX
uC/OS-II
uITRON
VRTXsa
VxWorks
KadakProducts Ltd.
Oracle Corporation
CMX Systems Inc.
DDC-I, Inc.
eCosCentric Limited
Elektrobit Automotive GmbH
ETAS GmbH
Evidence
Freeware I
MontaVista Software, LLC
LynuxWorks Inc.
NXP Semiconductors
Synopsys, Inc
MISPO Co. Ltd.
Mentor Graphics Corporation
Radisys Inc.
Enea OSE Systems
NXP Semiconductors
Sysgo AG
Elektrobit Automotive GmbH
Wind River Systems
QNX Software Systems
RTEMS
Quadros Systems Inc.
Quadros Systems Inc.
Sciopta
Micro Digital Inc.
Express Logic Inc.
Micrium Inc.
Mentor Graphics Corporation
Wind River Systems
implemented by DDC-I
1.3, 2.0 and 3.0
via ORTI
via ORTI
via ORTI
v7
Kernel Version 2.4 and 2.6, 3.x, 4.x
3.0, 3.1, 4.0, 5.0
3.1.0, 3.1.0a, 4.0
3.x and 4.x
2.40 and 2.50
3.4 to 4.0
3.0, 4.0, 5.0
2.0 to 2.92
HI7000, RX4000, NORTi,PrKernel
5.x to 7.x
67
Support
Tool
Company
ALL
ALL
ALL
ADENEO
X-TOOLS / X32
CODEWRIGHT
ALL
CODE CONFIDENCE
TOOLS
CODE CONFIDENCE
TOOLS
EASYCODE
ECLIPSE
RHAPSODY IN MICROC
RHAPSODY IN C++
CHRONVIEW
LDRA TOOL SUITE
UML DEBUGGER
Adeneo Embedded
blue river software GmbH
Borland Software
Corporation
Code Confidence Ltd
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
POWERPC
POWERPC
POWERPC
ATTOL TOOLS
VISUAL BASIC
INTERFACE
LABVIEW
CODE::BLOCKS
C++TEST
RAPITIME
DA-C
TRACEANALYZER
SIMULINK
TA INSPECTOR
UNDODB
VECTORCAST UNIT
TESTING
VECTORCAST CODE
COVERAGE
WINDOWS CE PLATF.
BUILDER
GR228X ICTESTSYSTEME
OSE ILLUMINATOR
DIAB RTA SUITE
Host
Windows
Windows
Windows
Linux
EASYCODE GmbH
Eclipse Foundation, Inc
IBM Corp.
IBM Corp.
Inchron GmbH
LDRA Technology, Inc.
LieberLieber Software
GmbH
MicroMax Inc.
Microsoft Corporation
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
NATIONAL
INSTRUMENTS
Corporation
Open Source
Parasoft
Rapita Systems Ltd.
RistanCASE
Symtavision GmbH
The MathWorks Inc.
Timing Architects GmbH
Undo Software
Vector Software
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Linux
Windows
Vector Software
Windows
Windows
Windows
Battefeld GmbH
Windows
Windows
Windows
68
Support
Products
Product Information
OrderNo Code
Text
LA-7723
DEBUG-PPC400
LA-7723A
DEBUG-PPC400-A
supports PPC40x
please add the serial number of the base debug
cable to your order
LA-7723X
DEBUG-PPC400-X
supports PPC40x
requires a valid software guaranty or a valid
software license key
please add the serial number of the base debug
cable to your order
LA-3731
JTAG-PPC-CON-XILINX
LA-7986
JTAG-PPC4XX-2X38
69
Products
OrderNo Code
Text
LA-7752
DEBUG-PPC44X
LA-7752A
DEBUG-PPC44X-A
supports PPC440
please add the serial number of the base debug
cable to your order
LA-7752X
DEBUG-PPC44X-X
supports PPC440
requires a valid software guaranty or a valid
software maintenance key
please add the serial number of the base debug
cable to your order
LA-3731
JTAG-PPC-CON-XILINX
LA-7986
JTAG-PPC4XX-2X38
OrderNo Code
Text
LA-3900
PP-PPC4XX-AF-2
LA-3900A
PP-PPC4XX-AF-2-ADD
LA-7929
PP-PPC4XX-F
LA-7983
PRE-PPC4XX-CON-20-38
70
Products
Order Information
Order No.
Code
Text
LA-7723
LA-7723A
LA-7723X
LA-3731
LA-7986
DEBUG-PPC400
DEBUG-PPC400-A
DEBUG-PPC400-X
JTAG-PPC-CON-XILINX
JTAG-PPC4XX-2X38
Additional Options
LA-7752X DEBUG-PPC44X-X
LA-3730A JTAG-MICROBLAZE-A
LA-7984
JTAG-PPC4XX-CON-38
LA-7960X MULTICORE-LICENSE
Order No.
Code
Text
LA-7752
LA-7752A
LA-7752X
LA-3731
LA-7986
DEBUG-PPC44X
DEBUG-PPC44X-A
DEBUG-PPC44X-X
JTAG-PPC-CON-XILINX
JTAG-PPC4XX-2X38
Additional Options
LA-7723X DEBUG-PPC400-X
LA-3730A JTAG-MICROBLAZE-A
LA-7960X MULTICORE-LICENSE
Order No.
Code
Text
LA-3900
LA-3900A
LA-7929
LA-7983
PP-PPC4XX-AF-2
PP-PPC4XX-AF-2-ADD
PP-PPC4XX-F
PRE-PPC4XX-CON-20-38
Additional Options
LA-7986
JTAG-PPC4XX-2X38
LA-7992A PP-ARM-ETM-AF-2-ADD
LA-7995A PP-C55X-AF-2-ADD
LA-3903A PP-C64XP-AF-2-ADD
71
Products
Order No.
Code
Text
LA-7996A
LA-3901A
LA-3902A
LA-7999A
LA-3904A
PP-CEVA-AF-2-ADD
PP-MICROBLA-AF-2-ADD
PP-SHX-AF-2-ADD
PP-STARCORE-AF-2-ADD
PP-TEAKLITE3-AF-2-AD
72
Products