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17 November 2016

Design Project #2:

Switch-mode Light Dimmer Using Multivibrators
Darl John Philip B. Mendoza, 2012-36048
Electrical and Electronics Engineering Institute
University of the Philippines Diliman
Abstract A switch-mode light dimmer is designed in this
project using multivibrator. The light intensity depends on the
average voltage across the bulb, that is why, the duty cycle is
varied in the multivibrator. Two kinds of multivibrator are
constructed in this project: astable, which has no stable state,
and monostable, which has single state. The first stage of the
project is an astable multivibrator connected to a high pass filter,
then to a monostable multivibrator, then to a common collector
amplifier, and lastly, a power transistor with the bulb connected
in its collector is in the last stage. Deviations in the theoretical,
simulated and actual values are also presented. Lastly, it can be
concluded that transistor switching has various uses in different
projects.

I. INTRODUCTION
A light dimmer is designed to control the intensity of the
light produced by the bulb. The voltage across the bulb,
which dictates the intensity of the light, can be varied
linearly or by switch-mode.

On the other hand, a switch-mode light dimmer, shown

in Figure 2, is designed by connecting the bulb in series
with a switch, periodically turned on and off, to a voltage
source. When the switch is turned on, the voltage across
the bulb will be equal to the voltage source while when it
is turned off, no current through it will flow. Because of
its periodical switching, the average voltage across the
bulb will be proportional to the time it is turned on. Thus
the duty cycle, which indicates how long the switch is on,
will then dictate the intensity of the light.
II. BACKGROUND OF THE CIRCUIT
The first stage of the circuit is an astable multivibrator.
This kind of multivibrator has no stable state, but has two
quasi-stable states. Two transistors in this circuit are
switched on and off. Q1 is on while Q2 is off sometimes
and vice versa on other times. Thus, the two quasi-stable
states are generated. Because of the switching states of
each transistor, a square wave is generated at both
collector terminals of each transistor.

FIGURE 1. Light Dimmer Varied by a Variable Resistance

Shown in the figure above is the schematic of a light

dimmer varied linearly. Since resistance is proportional to
the voltage across it, the light intensity can be varied using a
variable resistance connected in series with the bulb
powered by a voltage source. A higher resistance value gives
lower voltage to the bulb, which consequently produces a
lower light intensity. While decreasing the resistor value will
increase the voltage across the bulb. With this, the light
intensity is varied linearly.
FIGURE 3. Astable Multivibrator Circuit

FIGURE 2. Switch-mode Light Dimmer

The output of the astable multivibrator is then passed

through a high-pass filter which acts as the trigger to the
next stage used in this circuit.
The next stage in the circuit is another kind of
multivibrator which is a monostable multivibrator. This
multivibrator has a single state condition. In this circuit,
one transistor is normally on while the other is normally
off, which produces a single stable condition. However, a
triggering pulse will turn it into a quasi-stable condition

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for a certain period. Figure 4 shows a schematic of a
monostable multivibrator.

FIGURE 4. Monostable Multivibrator Circuit

Similar to a collector-coupled monostable, a

collectorcoupled astable multivibrator consists of two
transistors having a collector terminal that is coupled to
the base of the other transistor. However, the normally on
transistor, Q6 in this schematic, is coupled by a resistor,
not a capacitor. Q6 is the normally on transistor because
of the base current supplied by the voltage drop across R8.
A diode D2 is connected in series with the emitter voltage
to protect the transistor against excessive reverse baseemitter voltage. The voltage drop across R10 will produce
a current flowing through the collector terminal of Q6 and
base terminal of Q5. The base voltage of Q5 will then be
equal to the difference of the collector voltage of Q6 and
voltage drop in R9 ((VCE(sat)+Vd) VR9). Having a high
resistance, the voltage drop in R9 will be bigger than the
collector voltage of Q6 which results to a negative base
voltage in Q5. Thus, Q5 will be normally off.
Since Q5 is normally off, its collector voltage is equal
to the voltage source, then, the capacitor voltage across
C4 will be equal to the difference of the collector voltage
of Q5 and base voltage of Q6, which is equal to (V1
(VBE(on)+Vd)).
As mentioned above, a triggering pulse can turn a
single stable condition into a quasi-stable condition for a
certain period of time. If the transistor Q5 is triggered to
switch on, its collector voltage will drop to VCE(sat). Since
the capacitor voltage in C4 cannot change its voltage
instantaneously, the base voltage of Q6 will drop to the
difference of collector voltage of Q5 and capacitor voltage
of C4 which is equal to
[VCE(sat) - (V1 (VBE(on)+Vd))]. Since this is a value below
ground, the transistor Q6 will turn off. At this certain time,
the base voltage of Q6 will not remain constant because of
the capacitor C4 discharging through resistor R8. Because
of this, it can be observed that the pulse width of the
collector voltage of each transistor is dependent to C4 and
R8. Thus, a variable resistance in R8 can produce an
output with varying duty cycle.

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multivibrator. The astable part must produce an output
frequency of 5kHz. The output of the astable multivibrator
is the input of a trigger which is constructed as a high pass
filter. The trigger output will then be the connected to the
base voltage of the normally off transistor in the
monostable part. In this project, the trigger output is
connected to the base of a transistor, in parallel with the
normally off transistor. If this transistor is turned on, the
normally off transistor will also turn on. Having a
triggered normally off transistor, the monostable part will
now produce a quasi-stable output. The output should be a
constant frequency of 5kHz and a varying duty cycle from
10% to 60%. A buffer stage is connected at the output of
the monostable to avoid loading effect. This stage is
implemented as a common collector amplifier which has
high input impedance, low output impedance and unity
gain. Lastly, a power transistor will be at the last stage of
the circuit, having a collector terminal connected to the
bulb. Figure 5 illustrates the block diagram of the project
while Figure 6 shows its schematic.
Astable

5 kHzOutput

Trigger

HighPassFilter

Monostable

10 %to60%DutyCycle

Buffer

CommonCollector

Switch

PowerTransistor

Load

12 VLightBulb

FIGURE 5. Block Diagram of the Project

III. DESIGN PROJECT CIRCUIT SCHEMATIC

In this design project, the objective is to construct an
astable multivibrator cascaded to a monostable

FIGURE 6. Schematic of the Project

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IV. DESIGN CALCULATIONS
A. Astable Multivibrator
In designing the astable multivibrator, the resistors
(R2+R9) and (R3+R18) are the unknowns. To solve this, the
equation in finding the time a capacitor charges is used:

t
=
RC
ln ,
where VCC is the voltage source, E is the initial capacitor
voltage and E is the final capacitor voltage. In calculating
the unknown resistors, we can use time as the pulse width of
the collector output of both transistors, the time where both
transistors are off and the collector voltage is equal to the
voltage source. At this period, the initial voltage of the
capacitor is equal to V1 while the final voltage is zero.
1 1
=

1 0
=0.69
Since the output frequency of the astable part is given in the
specifications, the pulse width can be computed from the
target frequency at 50% duty cycle.
1
=
2
By manipulating the equations:
1
=0.69
2
=
By substituting the values f = 5kHz and C = 4.7nF:

3
: PQR = 2.7
PST =
PST = 17
391

: PST = 15
and
2.7k
To adjust the duty cycle by a potentiometer, a 1M is
attached in parallel with the 15k. At full turn, the
resistance will be equal to 15k which is needed to
acquire the highest target duty cycle. On the other hand, at
the other turn, the potentiometer will be short and the
resistance will be equal to 0. This will now give the
lowest target duty cycle.
V. COMPONENTS
Table 1 shows the list of components used in this
project. The theoretical values, simulated values and
actual values are also tabulated accordingly. Non idealities
and breadboard circuit created some discrepancies in the
resistor values. However, it can be seen that these
discrepancies are relatively low.
Label

Type

Theoretical
Value

Simulated
Value

Actual
Value

D1, D2
C1, C2
C3, C4
Q1, Q2, Q3, Q4,
Q5, Q6, Q7
Q8
R1, R5
(R2+R19),
(R3+R18)
R4, R11, R12
R6
R7, R10
(R8+R13)
(R14+R15)

Diode
Capacitor
Capacitor
Transistor

1n4148
4.7nF
10nF
2n4401

1n4148
4.7nF
10nF
2n4401

1n4148
4.7nF
10nF
2n4401

Transistor
Resistor
Resistor

TIP31c
1k
30 835

TIP31c
1k
31k

TIP31c
1k
29k

Resistor
Resistor
Resistor
Resistor
Resistor

100
6.8k
2.5k
2 898
14 493

100
6.8k
2.5k
2.7k
15k

100
6.8k
2.5k
2k
11.5k

TABLE 1. Component Values

=
=

30 835

:
30
1

B. Monostable Multivibrator
The resistors (R8+R13+R14+R15) are the unknowns in
the design of the monostable multivibrator. Computing for
the resistance is also similar to the astable multivibrator but
the duty cycle is will be different. (D is duty cycle in
decimal form)

=0.69

()(0.69)
PQR =
PQR = 2 898

VI. DATA AND RESULTS

A. Simulations

FIGURE 7. Simulated Collector Output and Monostable Output at

Minimum Duty Cycle

Figure 7 shows the simulations in the collector output

of the power transistor and the output of the monostable
stage at minimum duty cycle. Both output have the same

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frequencies (4.98kHz) but different duty cycles (90.3%
and 9.7%). The duty cycle of the monostable cannot be
measured properly because of the spikes but, apparently,
its TON is same as the TOFF of the collector output. It can
also be observed that they are inverted of each other, which
is the expected output.

FIGURE 10. Actual Collector Output and Monostable Output at Maximum

Duty Cycle

Again using the actual values, Figure 10 shows the

collector output of the power transistor and the output of
the monostable stage at maximum duty cycle. Similarly,
the yellow output is the monostable output (4.91kHz,
60.39%) while the blue output is the collector output
(4.91kHz, 32.85%). Similar to the minimum duty cycle,
there is a need for a speed up capacitor to avoid the delay
in the collector output.

FIGURE 8. Simulated Collector Output and Monostable Output at

Maximum Duty Cycle

On the other hand, Figure 8 shows the simulations in

the collector output of the power transistor and the output
of the monostable stage at maximum duty cycle. Similar to
the output at minimum duty cycle, both have same
frequencies but inverted duty cycle. At this time, the duty
cycle of the monostable output can be measured properly
because of the absence of spikes.

B. Actual

C. Data Comparison
Table 2 shows the comparison of the frequencies and
duty cycles acquired in the simulations and actual circuit.
It can be observed that most values in simulated and
actual are almost identical, except for the duty cycle of the
collector output. These discrepancies are evident because
of its delay while the power transistor is being turned off.
Note that the collector voltage of the power transistor is
very close to the voltage source when it is off.
Monostable
Output

Frequency

Duty
Cycle

Frequency

Duty
Cycle

Simulated

4.98kHz

9.7%

4.98kHz

59.95%

Actual

4.93kHz

9.7%

4.91kHz

60.39%

Collector
Output

Frequency

Duty
Cycle

Frequency

Duty
Cycle

Simulated
Actual

4.98kHz
4.95kHz

90.34%
82.42%

4.99kHz
4.91kHz

40.65%
32.85%

TABLE 2. Comparison of Frequencies and Duty Cycles

VII. DEVIATIONS AND RESULTS DISCUSSION

FIGURE 9. Actual Collector Output and Monostable Output at Minimum

Duty Cycle

Using the actual values in Table 1, the collector output

of the power transistor and monostable output in the actual
circuit is shown in Figure 9. The yellow output is the
monostable output having a frequency of 4.93kHz and a
duty cycle of 9.7%. On the other hand, the blue output is
the collector output having a frequency of 4.95kHz and a
duty cycle of 82.48%. It can be seen that the rise of the
collector output has a delay and adding a speed up
capacitor will remove this delay.

It can be seen from Table 1 that only the computed

values are varied from theoretical to simulated to actual
value. First of all, theoretical values differ from simulated
values, only by a very small amount. This is because
resistors only have limited standard values and only these
standard values are used in the simulations and actual
circuit.
As expected, actual values differ from simulated values
due to non-idealities. At first try, the output frequency is
smaller than the target frequency, that is why, a smaller
value for the base resistance in the astable stage was
chosen. This is because the base resistance is inversely
proportional to the frequency. When the target frequency
is reached, the duty cycle can be varied through the base
resistance of the normally on transistor in the monostable
stage. A higher resistance yields to a higher duty cycle.
When the potentiometer is turned to make it short, the
measured duty cycle is higher than the target minimum.
Choosing a slightly lower resistance for the base

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resistance, not in parallel with the potentiometer, will
acquire the desired target minimum duty cycle. Same
adjustment goes with the target maximum frequency.
Since the component values are already varied, the goal
is to acquire an output waveform and output values that is
equal to the simulated output. It can be seen that most values
are similar, except for the duty cycle in the power transistor
collector output. The monostable output and collector output
are inverse of each other. When the transistor from the
monostable is off, it will have an output voltage close to the
voltage source. This voltage will then be supplied to the
resistors connected to the power transistor, producing a base
current enough to turn on the power transistor. At this
instant, its collector voltage will produce an output close to
ground. On the other hand, if the monostable transistor is on,
an output voltage close to ground will be supplied to the
power transistor, turning it off and producing a collector
output voltage equal to the voltage source.
VIII. CONCLUSION
Transistor has various uses in constructing design
projects. It can be biased in the cutoff region, saturation
region, or forward active region, which have their own uses.

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For instance, transistor used as an amplifier is commonly
biased in the forward active region. When there is not
enough voltage produced in the base terminal, the transistor
will not turn on, producing a maximum possible collector
voltage. At this instant, the transistor is in cutoff region. On
the other hand, enough base voltage will result to a
significant base current and collector current, turning on the
transistor. This is now in saturation region, producing a
collector voltage almost equal to zero. In this project,
transistors are biased in the cutoff and saturation region
which are used as switches. Transistors are switched on and
off for a certain period to produce quasi-stable states needed
to have a square wave output. This square wave output can
then be connected to a light bulb with varying brightness.
This can also be used to drive a different load, like a motor.
REFERENCES
[1] Bell, D.A., Solid State Pulse Circuits, Fourth Edition
[2] http://uvle.upd.edu.ph/pluginfile.php/224937/mod_
resource/content/3/EEE%2054%20DP2%201s1617.pdf