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A Power Shaping Methodology for Supply

Noise and EMI Reduction
White paper based on a DAC 2010 User Track presentation in the category of Silicon-level Design

Fabio Campi
Davide Pandini

Tobias Bjerregaard
Mikkel Stensgaard

ST Microelectronics
Central Cad & Design Solutions
Agrate Brianza, Italy

Teklatech
Copenhagen, Denmark

INTRODUCTION
Digital power rail noise poses increasingly severe
challenges in the design of ICs using advanced submicron technologies. Dynamic voltage drops on power
supply lines may lead to insurgence of non-systematic
timing errors (soft failures), unpredictable performance
degradation, unexpected clock jittering phenomena and
excessive power consumption due to degradation of
slew rates. Moreover, Electro-Magnetic Compatibility
(EMC) is a growing concern, especially in the segments
of automotive, wireless and highly integrated mobile
applications, where the certification for a given ElectroMagnetic Interference (EMI) class may well determine
the success of a given IC product.
Current EDA design methodologies for ensuring power
integrity and EMI compliancy in digital designs tend to
focus on the sign-off phase, where detailed power rail

Synthesis
Placement
FloorDirector
CTS
Routing

Figure 1: Integration of FloorDirector

into mainstream backend flows.

analysis can be performed and dynamic voltage drop

and current signatures can be studied. State-of-the-art
tools offer very good dynamic sign-off accuracy power
rail voltage/current analysis capabilities, allowing
designers to iterate local mitigation actions on the
design database such as power grid optimization,
supply pads positioning, and insertion of decoupling
capacitance (de-caps). In particular de-caps, also
referred to as filler-caps when inserted in place of filler
cells in a standard cell region, are a largely popular
design option for power integrity-aware design. This
approach however may prove too conservative, and
drawbacks of the unconstrained use of de-caps include
increased leakage current and lowered power grid
resonance frequency. Furthermore, designs that are
inherently noisy or EMI-prone may remain so even
after applying de-caps, leaving designers with little
choice but to increase chip area to allow for even more
on-chip power grid decoupling. Finally, addressing
power integrity issues at the sign-off stage may
introduce long iterative loops in the design process,
with no guarantee of convergence. With the limitations
of current approaches, it appears advisable to
complement these methods, oriented around physical
power grid optimization, with other approaches. Also, it
is desirable to enable design methods that can address
the challenges earlier in the design flow.
Voltage drops and electro-magnetic noise emissions are
essentially caused by stimulation of the power grid
conductors by the IC current demand. A
complementary approach to optimizing the power grid
itself is to mitigate peaks in the current demand, as
generated by the digital logic.
THE PROPOSED FLOW
In this paper, a methodology for EMI reduction using
Teklatechs FloorDirector tool is described. The
proposed methodology makes use of FloorDirectors
Dynamic Power Shaping (DPS) capabilities, an

2010 ST Microelectronics / Teklatech A Power Shaping Methodology for Supply Noise and EMI Reduction

www.teklatech.com
maximum power shaping flexibility. FloorDirectors
front-end-level current profile analysis provides good
correlation with post-layout results, and as such
furthermore aids in bridging the front-end to back-end
design optimization gap.

Figure 2: Reference design layout.

optimization applied to the gate-level netlist. While it is
independent of the physical implementation reference
flow, we validate its integration into a Cadence
Encounter-based backend flow.
The FloorDirector tool enables early stage dynamic
current signature analysis, and uses this in an automated
optimization to reduce system-level current demand
peaks. The outcome of the optimization is used to guide
the clock tree synthesis (CTS) process. Figure 1
illustrates the integration into the backend flow used in
the present work.
As a fully integral part of the optimization engine, the
FloorDirector tool provides static timing analysis for
maintaining design timing margins while ensuring

REFERENCE DESIGN
The proposed methodology is applied to an automotiveoriented, multi-processor IC reference design. The
design is composed of two Leon processor cores, a
system bus, 64K internal SRAM and a set of IO
peripherals. The design was synthesized for CMOS090,
4 Metal STMicroelectronics technology, optimized
using FloorDirector, laid-out using a Cadence
Encounter P&R flow, and signed-off using a StartRC /
PrimeTime timing extraction and analysis, and Apache
Redhawk dynamic power grid analysis. Figure 2 shows
the layout of the reference design. The total chip area
was 3.12mm2 and the total power consumption was
45.9mW@100MHz in the baseline implementation.
Reference Vdd supply voltage is 1.2V.
In order to comparatively evaluate the impact of the
proposed design methodology on voltage drop and
EMI, several backend implementations were made. The
first implementation was a standard baseline approach,
without applying specific measures for noise reduction.
The second applied DPS using FloorDirector.
Conducted noise emissions of an IC are measured as
the harmonic content of the current signature at the
device supply pins or board-level EMI measurement
pins. After layout, dynamic current profiles and
dynamic voltage drop (DVD) were analyzed, and a
conducted EMI spectrum was extracted. Figure 3 shows
the full chip-package-board modeling environment used
to perform sign-off analysis.

Figure 3: Full chip-package-board modeling environment.

2010 ST Microelectronics / Teklatech A Power Shaping Methodology for Supply Noise and EMI Reduction

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Figure 4: Dynamic voltage drop analysis (wires).

RESULTS
Due to high package impedance, and small number of
supply pads, the power-ground (PG) grid is inadequate
in terms of DVD. In Figure 4, which shows dynamic
Vdd drop and Gnd bounce, it is seen how a DVD
hotspot occurs in the SW corner in the baseline
implementation (left side). Power shaping (right side)
allows local resolution of the issue during P&R, with no
impact on PG-grid, package and board design. The
critical margin for DVD was fixed at 500mV (37.8% of
reference value). After power shaping, the worst DVD
value was 478mV versus 630mV in the baseline case, a
25% gain. All criticalities were resolved. Table 1
summarizes the DVD results.
Figure 5 shows the current demand of the design, in the
baseline implementation compared with the power

Table 1: Key numbers for dynamic

voltage drop analysis.
shaped version. It is seen how the DPS optimization has
shaped the dynamic current signature of the design,
reducing both the peak and the slope of the current
waveform.
Figure 6 shows the voltage fluctuations at the boardlevel EMI measurement pin. Again, notice not only the
reduction in peak value but also the reduction in slope,
which indicates noise reduction at higher frequencies

Figure 5: Power shaping induces evident smoothing of the dynamic cell current demand,
leading to a 55% reduction of the current peak and a significant softening of the slope.
2010 ST Microelectronics / Teklatech A Power Shaping Methodology for Supply Noise and EMI Reduction

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Figure 6: Voltage fluctuations at EMI measurement pin.

and generally improved dynamic power integrity.
Figure 7 shows a frequency domain analysis of the
voltage at the EMI measurement pin, and lists the noise
levels at even harmonics of the clock frequency. This
full EMI simulation confirms the expected trend: EMI
behavior of the power shaped design shows advantages
that become significant at higher harmonics.
CONCLUSION
FloorDirector's Dynamic Power Shaping (DPS)
technique proved a valuable design option for limiting
digital core supply Dynamic Voltage Drop and ElectroMagnetic Interference. Critical dynamic power integrity
issues were resolved and EMI measures were improved.
Experiments on a reference design provided:
55% reduction of IC cell peak current demand.
25% reduction of max Dynamic Voltage Drop.
Up to 30dBV reduction of digital core conducted
EMI harmonics, measured at board-level.

From a flow integration perspective, DPS showed small

impact on the physical design quality, and no impact on
PG-grid, package and board design. It is shown that the
FloorDirector methodology can be applied as a nonintrusive optimization technique, augmenting a
mainstream
backend
flow.
This
establishes
FloorDirector as an enabler for an easily accessible and
non-intrusive optimization technique that can be readily
applied to existing commercially available mainstream
backend IC design flows.

2010 ST Microelectronics / Teklatech. This document contains

information that is proprietary to ST Microelectronics and to
Teklatech. All trademarks mentioned are trademarks of their
respective owners.

Figure 7: Frequency domain analysis of the voltage at the EMI measurement pin
and noise levels in dBV at even harmonics of the clock frequency.
2010 ST Microelectronics / Teklatech A Power Shaping Methodology for Supply Noise and EMI Reduction