Power IC Design

Chapter 8. Switched-Inductor Supplies

8.1. Integration
8.2. Useful Circuits
8.3. Current Sensing
8.4. Compact Implementations
8.5. Single-Inductor Multiple-Output Supplies

8.1. Integration
Typical Design Sequence:
Select process technology.
Select package.
Design system (i.e., architecture).
Determine block-level specifications.
Design die floor plan.
Design transistor-level circuits (i.e., blocks).
Design block layouts according to the floor plan.
Assemble top-level layout.
Extract top-level schematic from layout and simulate.
Submit IC design for fabrication (i.e., "tape-out" design).
Test and evaluate IC in the laboratory.
Iterate another design to fix possible bugs and complications.

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Power IC Design

A. Die: i. Substrate Noise - Generation

Welled MOSFETs:
vSW transitions and drainbulk capacitors CDBP inject current iCP into the well
that can activate and prompt parasitic vertical BJTs QP
to steer current iQP through the substrate.

Substrate MOSFETs:
Body diodes DN can steer dead-time current iDN through the substrate.
vSW transitions and drainbulk capacitors CDBN inject current iCN into the substrate.

Suppression

Reduce Injection:
Minimize dead time tDT and shunt body diode DN with off-chip Schottky diode.
Minimize drainbulk capacitances CDBN and CDBP.
N+ in P+ source and N+ in N well reduce QP's activating voltage vEB.
N+ in N well also recombines QP's base hole carriers to reduce QP current iQP.
Grounded P+ in N well is a QP collector that steers current away from the substrate.
Block and Steer Substrate Current iSUB:
P+ ring collects iSUB and N+N-well ring impedes and steers iSUB into P+ ring.
A shallow P+ ring can suppress substrate noise 10 dB.

Separate Noise Regions: 50 m can suppress substrate noise 50 dB.

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Power IC Design

ii. Floor Plan: For Noise

Categorize circuit blocks on die into
Sensitive blocks: Bias, vREF, feedback amplifier, etc.
Noisy (switching) sensitive blocks: Feedback comparator, PWM comparator.
Noise generators: High-current drivers, power switches, DSP, etc.
Quiet insensitive blocks: Protection, trim, state monitors, etc.
Separate sensitive, noisy sensitive, and noisy signals, blocks, pads, and pins.
Place quiet insensitive blocks between them as noise buffers.
Use ground and supply metal and diffusion planes and lines to shunt noise.
Star ("Kelvin")-connect supplies to their respective pins and pads when possible.
Sprinkle substrate contacts throughout the die to suppress ground bounce.
Separate analog from power grounds and supplies.

For Power and Matching

Use multiple pads, bond wires, and pins for high-current paths when possible.
Place power blocks near their corresponding high-current pads.
Shorten high-current and at-speed paths to lower ohmic R losses and RC delays.
Guard-ring ESD circuits to collect and block (rev.-bias junctions) stray ESD carriers.
Separate and star-connect low- and high-current paths to lower ohmic IR drops.
Sample Floor Plan

Avoid routing over matchsensitive devices to

reduce local stresses.
Place reference near the
center of die when possible
to reduce die-wide stresses.

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Power IC Design

Place electrostatic-discharge (ESD) protection circuits next to/underneath pads.

iv. Lead Frame: Bond-Wire Mapping

Design pad frame so bond wires do not short.
Select padpin combinations with short bond-wire lengths for high-current paths.

B. Package
Considerations
Number of pins: Consider application.
Package material: Consider package stress on die, ambient and
junction temperatures TA and TJ, etc. (e.g., ceramic, plastic, etc.).
Type: Consider space requirements (e.g., small-outline IC -SOIC-,
shrink small-outline package -SSOP-, quad-flat no leads -QFN-, etc.).
Size: Consider die area.
Heat transfer: Consider power dissipation and heat flow
(e.g., power-padded package, heat sinks, heat pipes,
fan on the printed-circuit board PCB, etc.).

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Power IC Design

i. Heat
Power switches and other circuits generate heat when they burn power.
Junction temperature TJ > Ambient temperature TA.
TJ rises with power consumption PIC TJ PIC.
A plastic package melts at roughly 170 C TJ should be less than 150 C.
Convention: TA refers to temperature at the edge of the package.
Typical Specification: TA(MAX) is 85 or 125 C TJ(MAX) is higher.
Simulations: Usually at TA(MAX) Assumption is TJ TA.
Thermogram
Heat Flow:

ii. Thermal Model

TAB TAB = Power PX Thermal Resistance AB VAB = IXRAB.

TJA = PICJA TJ = TA + TJA = TA + PICJA.

Typical thermal resistances and capacitances (i.e., thermal time constants):
JA 30300 C/W, CJ 1.2200 mJ/C, and CA 120 J/C.
Assuming TAIR TA in JA measurements is practical.
For widest temperature range, keep PIC and JA low.

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Power IC Design

Small Off-Chip Inductors

C. Off-Chip Components
Discrete inductors typically outperform
(with lower RL ESR and higher LO)
on-chip inductors by orders
of magnitude.
One in-package inductor achieves
SiP footprint objectives.

MEMS

Practicable nHH inductances

Inductors

are possible with MEMS devices

Flip-Chip Capacitors

that use magnetic cores.

One or two in-package flip-chip capacitors
achieve SiP footprint objectives.

8.2. Useful Circuits

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Power IC Design

A. Startup
Problem: vO starts at zero Feedback loop maxes iL to raise vO to target.
Sudden inrush of current can damage components in power path.
Option 1: Limit dL, raise switch resistance RSW, or reduce over-current limit.
Limits iL Limited iL slews CO until vO reaches target.
Peculiarity: vO rises with interruptions.
Option 2: Start the reference vREF at zero and raise slowly to its final state.
vO rises slowly with vREF to target.
Digital: DAC generates vREF and counter and clock raise vREF.
Generates switching noise and occupies substantial silicon area.
Analog: Buffer, ground, and slew vREF' to target.
Noise-free and compact.
Drawback: Requires dedicated or buffered (degraded) vREF.

Option 3:

Bypass feedback amplifier's or comparator's MREF with MSLOW.

Operation: vFB and vSLOW start at 0 V, so MREF is off.

MSLOWMFB regulates vFB to a rising vSLOW.
When vSLOW surpasses vREF, MREF sinks MSLOW's iSLOW to shut MSLOW.
MREFMFB regulates vFB to vREF.
Features: Fast, accurate, and small silicon area.
Design Notes:
MSLOW need not match MREFMFB well.
MSLOW can be small and off to side.
MSLOW's CD slows circuit
Feed iREF and iFB into current

vSLOW

buffers (i.e., into low-impedance nodes).

vREF
vO
!v $ C
If IS = KSvREF, t START = CS ## REF && = S f(v REF )
t
" IS % K S
Shift vREF without changing tSTART.

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Power IC Design

B. Load-Dump Compensation
Center each worst-case load-dump variation vLD(MAX) about vREF.
Add and tune load-induced shift iOREQ to vREF.
Can cut total variation in half: From 2vLD(MAX) to vLD(MAX).
vREF' = vREF + 0.5vLD(MAX) iOREQ

where

iO(MAX)REQ vLD(MAX)

Notes: Actual response to load-dump vLD(MAX) remains unchanged.

Amounts to intentional (and tuned) load-regulation effect: vO iOREQ.

Implementation
Raise target by 0.5vLD(MAX) to vREF + 0.5vLD(MAX).
Sense iO via iL.
Convert to voltage vI with RS and average with CS.
Subtract vI from target with a summing amplifier or comparator.

Note that sensing iL requires a circuit that dissipates power.

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Power IC Design

C. Comparators: i. Hysteresis
Noise produces uncertainty in transition and jitter at the output.
Comparator
threshold

vin

vout

VOH

Noise
Jitter

VOL

Hysteresis in the comparator suppresses noise jitter.

vin

VTRP+

vHYS > vN*

VTRPVOH
VOL

VTRIP+ VTH(RISE) > VTRIP VTH(FALL)

vout

No Jitter

ii. Current Induced

Comparator:

Compares analog inputs vP and vN.

Outputs a digital high when vP > vN and a digital low when vP < vN.
Is an amplifier without compensation.

Current-Induced Hysteresis: The state of output vO and iH produce an offset that

differential input vP vN must overcome to trip the comparator.
When vP rises towards vN:
Positive
Feedback

vO is initially low.
MFB is off and iH is 0.
vO rises when i2 overcomes M4's i1.
When vP falls towards vN:
vO is initially high.
MFB is on and iH > 0.
vO falls when M4's i1 overcomes i2 + iH.

Hysteresis is asymmetrical: VTH+ = 0 and VTH iH/gm12 when iH is low.

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Power IC Design

iii. Cross-Coupled Load

When vP rises towards vN:
vON is initially high.
M4M5 is off and vON falls

Positive
Feedback

when i2 overcomes i1(S6/S3).

When vP falls towards vN:
vOP is initially high.
M3M6 is off and vOP falls
when i1 overcomes i2(S5/S4).

i1 + i2 = IT
VTH = v GS1 v GS2 =

2i1
2i 2

K N'S1
K N'S2

At Trip Point

Since S56/S34 > 1 and i1 and i2 must overcome i12(S56/S34),

i1 and i2 must surpass 0.5IT by some margin to induce a transition.
S6/S3 and S5/S4 set the symmetry of thresholds.

iv. Voltage Induced

Voltage-Induced Hysteresis: Summing Comparator
MH1MH2 produces an offset that M1M2 must overcome to transition vO.
Switcher reverses offset after vO transitions.
vH produces +iOS when vO is low and iOS when vO is high.

MHT should match MT.

MH1MH2 should match M1M2.
Hysteresis can be symmetrical: VTH+ = VTH =
vH should be low to keep translation linear.

Page 10

iOS v Hg mH12
.
=
g m12
g m12

Power IC Design

D. Ramp Generators
Clock-Synchronized Ramp:
Clock fCLK starts ramp.
Diode DR offsets ramp.
Current source IR slews CR and ramps vR.

vD

Inverters INV12 and MN reset ramp.

vR
tCLK

tCLK t

Relaxation Oscillator

Ramp-Generating Clock:
DR offsets ramp and IR ramps vR.
Comparator CPR ends ramp and resets vR.
CPR restarts ramp after propagation delay tP.

vCLK

tP should be long enough for MN to reset vR.

vD

Design Note: Hysteresis removes jitter near transition.

vR
tP

E. Gate Drivers
Small inverters cannot drive very large gates quickly.
Build drive with chain of increasingly sized inverters:
S2 S1AX
INV3

vC INV1
INV2

S3 S2AX

vG

Minimum Size

Minimum propagation delay tP(MIN) results when

successive gain AX is "e", which in practice relaxes to 5.
Each inverter loses shoot-through power PST.
Power losses rise with more inverters in the link.
Balance tP and PST.
3 to 5 stages is a typical balance.

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Power IC Design

F. Dead Time
Risk: Adjacent switches can short inputs/outputs (I/O's) Short supplies.
Fix: Engage power switches only after adjacent switches shut.
Implementation:
Sense adjacent gate signals.
RC or inverter chain delay adjacent gate signals tDEAD.
NOR engages NFETs only when adjacent gate signals are low.
NAND engages PFETs only when adjacent gate signals are high.
Shut-off path and transitions are undelayed.

vG(ADJACENT)

tDEAD

vG

Driver

vG(C)

8.3. Current Sensing

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Power IC Design

A. Basic Concepts
Purpose:
Current-mode control.

Over-current protection.

Load-dump compensation.
Power modes: Adjust modes according to load current.
Current-mode capacitor and inductor multipliers.
Ideal Characteristics:
No additional conduction losses PR in the power path.
No additional quiescent power PQ (e.g., to sense small voltages).
Monitors iL continuously.
All on chip.
Linear.
Accurate.

B. Series Resistances: i. Series Sensor and ii. Switch Resistance

i. Sense Resistor RS: Monitor RS's voltage iLRS. + Simple.
+ Accurate when RS is off chip.
+ Senses iL continuously.
RS can vary 25%50% on chip.
vR is small Additional PQ.
Extra pin when RS is on chip.

RS dissipates PR.

ii. Switch's RDS: Monitor RDS's voltage iL(+)RDS.

+ No additional PR.
+ On chip.
+ Senses iL(AVG) and half of iL.
RDS varies 50%200% across process and temperature Inaccurate.
vDS is small and discontinuous Additional PQ.

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Power IC Design

iii. Inductor Resistance

Averaged (filtered) Difference: Monitor RL ESR's voltage iLRL ESR.
RFCF averages (low-pass-filters) vSW.
vS = vSW(AVG) vO vESR = iL(AVG)RL ESR.
But only when vCF 0 and vLO vESR near the sampling frequency.
ZCF << RF and RL ESR >> ZLO

R
1
<< fSW << L ESR .
2R F C F
2L O

+ Marginal additional RMS PR.

+ Senses iL(AVG) only.
+ RF and CF can be moderate and on chip,
but they occupy considerable die area.
RL ESR drifts with frequency (skin effect), temperature, and process 50%200%.
vESR is small Additional PQ.

Matched RFCF Filter: Monitor RL ESR's voltage iLRL ESR.

LO's iL low-pass filters vL like CF's vS does:
iL =

vL
=
sL O + R L ESR

vL
! sL O
$
R L ESR #
+1&
" R L ESR %

If time constants match, R F C F

vS =

! 1 $
vL
#
&=
1 " sC F % R F C Fs +1
RF +
sC F
vL

LO
and vS iLRL ESR = vESR.
R L ESR

+ Marginal additional RMS PR.

+ Accurate with tuned RFCF.
+ Senses iL continuously.
vESR is small Additional PQ.
Requires tuning or trimming.
+ RF and CF can be on chip, but they occupy considerable die area.
E.g.: If LO = 4.7 H, RL ESR = 250 m, and RF = 1 M CF = 18.8 pF.

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Power IC Design

Matched RFCF Filter:

RFCF also offers an
in-phase feed-forward path to vSW.
RFCF establishes an in-phase zero zF
when RFCF's current iF exceeds LORL ESR's iL.
zF appears when RF + 1/sCF sLO + RL ESR:
! LO $
#
& s +1
1
R C s +1 " R L ESR %
sL + R L ESR
RF +
= F F
=
= O
sC F
sC F
sC F
sR L ESR C F
R FCF

zF =

1
2R L.ESR C F

sL O + R L ESR

LO
Matched time constants.
R L ESR

Since LO's RL ESR 5 and an on-chip capacitor CF 50 pF,

zF 637 MHz Normally, well above fSW f0dB fSW << zF.

Matched GMCF Filter: Same as before, but with programmable gain.

iL =

vL
=
sL O + R L ESR

vL
! sL O
$
R L ESR #
+1&
" R L ESR %

If time constants match, R F C F

!
1 $ vLG M R F
v S = v L G M # R F ||
&=
sC F % R F C Fs +1
"

LO
and vS (iLRL ESR)GMRF = vESRGMRF.
R L ESR

Tune Phase: Inject iAC sinusoid into vSW and

adjust RF to match vS's phase to iAC's phase.
Calibrate Gain: Ground vO, inject IDC into vSW,
and adjust GM to desired gain.
+ Higher vS.
GM's ICMR spans vSW's range Additional PQ.
Tuning, calibration, and transconductor require considerable die area.
Tuning and calibration require test/startup time.

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Power IC Design

C. Mirroring Sense FET: i. Unregulated

vSG S = vSG I and QSQB ensures vSD S vSD I iS
MS samples iL(+), QS current-buffers iS, and

i L(+)
.
AI

! i L(+) $!
1 $ ! i L(AVG) $
&#
&# R S ||
& RS .
RSCS translates and holds average vS = #
sCS % " A I %
" A I %"

+ No additional PR.
+ On chip.
+ Marginal additional PQ.
+ Senses iL(AVG) with CS or
half of iL without CS.
vSD S vSD I when iS IB, but not precisely otherwise Nonlinear:
vEBS rises (so vSDS falls) when iO rises iS is a nonlinear reflection of iO.
Nonlinear, mirror mismatch, and resistor tolerance 50% Inaccurate.

ii. Regulated
Negative feedback keeps vD at vSW iS is an accurate mirror of iO:
MSSMSO generates an error (vSW vD)gmSO that adjusts vG to keep vD near vSW.
T connection generates an error iS iFB that adjusts vG to keep iFB near iS.
vSGS = vSGI and vSDS vSDI.
iS

i L(+)
AI

And iFB iS.

i FB iS

i L(+)
AI

vG is the only high-resistance node.

Loop is stable.
Same principle as unregulated sense FET,
but without nonlinearity and with feedback delay (i.e., slower).

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Power IC Design

D. Comparison
PR

PQ

Monitor

On Chip Accuracy

Cost

Yes

Small RS

1 Pin or
Off-Chip RS

Yes iL & iL(AVG)

Yes

RDS

No

Yes

iL(AVG)

Yes

RL.ESR

Area

RL.ESR Matched RC No

Yes

iL

Yes

Tuned

Area, Tune

Yes

iL

Yes

Tuned

Area, Tune

Yes

Nonlinear,
Mirror, RS

Yes

Mirror, RS

Delay

RS

Yes Yes

RDS

No

Averaged
Diff.

Matched
G MC

No

iL

Sense Unregulated No Low iL & iL(AVG)

FET
Mirror Regulated No Low i & i
L
L(AVG)

RDS and unregulated and regulated MOS mirrors are popular

because their accuracy-to-cost tradeoff is usually more favorable.

8.4. Compact Implementations

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Power IC Design

A. Hysteretic Buck
Premise: vESR >> vC and vESL vO rises and falls with iL.
Functionality: CPERR keeps vO within hysteresis window vHYS about vREF.
Operation: CPERR compares vO to vREF to generate an error that adjusts dE.
CPERR pulse-width modulates MP according to vO's error.
Features: vO is nearly constant at vHYS and loop responds within one cycle.
zESR recovers phase after pLC2.
RC ESR > RC ESR(MIN) > 0.
pLC2, zESR < f0dB fSW.
f0dB can be high.
! d $! v $
A LG = A ERR A BUCK = ## e &&## o &&
" v o %" d e %

AERR0
ABUCK0, pLC2, zESR

i. Hysteretic Comparator
Hysteretic comparator CPE compares vREF with the rippling vO.
Output vCPO rises until vO reaches upper threshold VTH+ to end tE.
Output vCPO falls until vO reaches lower threshold VTH to end tD.

When active high.

A ERR =

de
t
D
= e E
v o v o t SW VHYS

t e dt E
D T
T
=
E E SW
v o dv O v O
VHYS

Since vO rises and falls with iL, loop regulates iL current-mode fashion.

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Power IC Design

ii. Noise
Switching events produce noise.
If vHYS is low, switching noise can trip
comparator and produce glitches.
Reduce Sensitivity:
Filter: RFBCFB filters
high-frequency noise.
AC Hysteresis: CAC overdrives vFB
momentarily to raise noise margin.
If RFB >> ZCFB, overdrive vOD is:
" C AC %
v OD = v HYS(AC) v IN $
'
# C AC + C FB &

iii. Low ESR

Recall: RESR introduces zESR to recover phase lost to pLC2.
No RESR: Bypass LOCO with RFFCFF's gain AFF before loop gain ALG reaches f0dB.
This way, LOCO's effects disappear from feedback signal vFB.
LC-Bypassed Hysteretic Buck: Low-ESR Hysteretic Buck

pFF, pLC2 < zFF2 < pFB < f0dB.

AFF is low at low frequency LOCO's gain ALC dominates.

AFF rises as CFF shorts and flattens when ZCFF RFF at p FF

AFF bypasses ALC past zFF2 when ALC AFF.

1
.
2R FF C FF

AFF falls when parasitic capacitance CFB shunts RFF || RFB at p FB

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1
.
2 ( R FF || R FB ) C FB

Power IC Design

Operation:

vFB iL

vO vCO

RFBCFB filters high-frequency noise.

RFF overdrives vFB CAC is not needed.
Near f0dB, AFF > ALC vFB vHYS > vO.
vO is low and vFB is less sensitive to noise in vO.
pFF << pFB and RFF > (RFF || RFB) and vFF(AVG) = vSW(AVG) = vO(AVG).
CFF >> CFB when RFB RFF vCFF 0 and vFF vO(AVG):
dv FB
dt

Rise

di
i FF v IN v O(AVG)
vE

L(+)
C FB
R FF C FB
R FF C FB
dt

dv FB
dt

Fall

di
i FF v O(AVG)
vD

L(-)
C FB R FF C FB R FF C FB
dt

vFB rises and falls with iL without RC ESR Preserves dE information.

Loop responds quickly to vFB variations.
RFBCFB delays vO-to-vFB translations Delays load-dump response slightly.

iv. Design Notes

No component of a duty-cycled vO rises and falls with iL Hysteretic is not easy.
How fast vFB reaches thresholds sets tE and tD fSW = f(vHYS, diL/dt, RFF, CFB, tP).
CPERR's propagation delay tP extends
vO's and vFB's ripples vO and vFB.
vFB > vHYS vHYS' > vHYS.
Feature: Loop reacts within one cycle f0dB fSW.
Drawbacks: Sensitive to noise in vO and fSW Clock.
fSW is less systemic Less suppressible.
Bypassing LOCO with RFFCFF removes RC ESR, but delays response slightly.
Other names for hysteretic buck: Self-oscillating, free-running, bang-bang,
bi-stable, two-state, sliding-mode, and ripple dcdc converter.

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Power IC Design

B. Non-inverting BuckBoost
Reduce gate-drive losses PG:
Replace diodes with synchronized FETs.
Open MN when bucking and close MP when boosting.
Operation:
CPBCK and CPBST switches MP and MN in buckboost.
CPBST opens MN and CPBCK switches MP in buck.
CPBCK closes MP and CPBST switches MN in boost.

Switch Control

Pulse-Width Modulation Scheme:

fCLK resets vSAW and closes MP and MN to start energizing LO.
CPBST trips first to open MN Energize or drain LO into vO.
CPBCK trips later to open MP Drain LO from ground into vO.
BuckBoost Mode Example when vO > vIN:
LO energizes across vIN.
LO drains to vO first from vIN and then from 0 V.

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Power IC Design

8.5. Single-Inductor Multiple-Output Supplies

A. Market
Emerging applications are tiny and functionally dense Highly integrated.

Functions: DSP's Programmable 0.51.8-V supplies.

PA's Dynamic 3-V supplies.
ADC's and DAC's Noise-free 1.8-V supplies.
Diverse vOiO profiles require supplies with multiple outputs.
Battery-supplied systems cannot lose much power Switched inductor.
Except power inductors are bulky Use only one inductor.
Single switched-inductor multiple-output (SIMO) supplies.

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Power IC Design

B. Power Stages: i. Buck- and ii. Boost-Derived SIMO's

Switched inductor implements a current source.
Output switches SO1, SO2SON distribute current to outputs vO1, vO2vON.
Boost SIMO

Buck SIMO
N

v SWI(AVG) = d E v IN = v SWO(AVG) = d O(X)v O(X)

v SWI(AVG) = v IN = d O(X)v O(X)

DG can drain LO to high outputs if

DG can energize LO to low outputs if

X=1

X=1

SI energizes LO enough to low outputs.

DO drains LO enough to high outputs.

SIMO bucks can also boost.

SIMO boosts can also buck.

vO(X) can be higher than vIN.

vO(X) can be lower than vIN.

vIN must exceed at least one vO(X).

At least one vO(X) must exceed vIN.

iii. BuckBoost-Derived SIMO's

Switched inductor implements a positive or a negative current source.
Non-inverting SIMO

v SWI(AVG) = d E v IN = v SWO(AVG) = d O(X)v O(X)

X=1

All outputs are above ground.

vIN can always energize LO.
vO's can always drain LO.
vO(X) vIN.
Inverting SIMO

0 = v SWI(AVG) = d E v IN + d O(X)v O(X)

X=1

All outputs are below ground.

vIN can always energize LO.
vO's can always drain LO.
|vO(X)| vIN.

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Power IC Design

iv. Complementary Outputs

Non-inverting systems can also invert and vice versa.
How: Tap into LO's inverting terminal Duty-cycle vIN.
If SI energizes LO enough to ground or low outputs,
LO can drain from inverting outputs.
Buck SIMO: With SGI, not SGO.
Boost SIMO: With SGO, not SGI.
Non-inverting
buckboost SIMO:
With SGI and SGO.
Notes: SGI cannot be or incorporate a diode because vO1 < 0 V.
LO must have diode escape paths for iL across dead-time periods.
One for vSWI's lowest voltage (DO1) and one for vSWO's highest vO(X).

v. Charge-Pumped Outputs
How: A switching node vSW initializes a flying capacitor CF.
CF then "flies" with vSW where vSW transitions across vIN + vD.
A rectifier DO(X)CO(X) then detects and holds peak voltage.
Positive Voltage:
When vSW is low, DPDG recharges CFP to vIN.
When vSW rises, DOPCOP holds peak 2vIN.
Negative Voltage:
When vSW is high, SIDN recharges CFN to vIN vD.
When vSW falls, DONCON holds peak vIN + vD.
Replace diodes with MOSFETs to reduce losses.
Charge-pumped outputs are unregulated.
CF's and CO's occupy board or silicon area.

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Power IC Design

C. Feedback Control
Approach:

Use master current loop to turn LO into a current source.

Use individual voltage loops to regulate outputs.
One feedback mixer per output.

Design:

Use average, peak, or hysteretic current loop.

Bandwidth fI 0dB must exceed those of voltage loops.
pC(X) << f0dB(X) fI 0dB = pI BW fSW < zRHP.

Alternative:

Operate LO in discontinuous-conduction mode (DCM).

No pL and no zRHP pC(X) << f0dB(X) fSW.

i. Shared Sequence
Shared Energize/Drain Sequence:
One energize/drain sequence for all outputs across operating period tO.
Collective demand sets LO's energizing time tE.
Individual demands set what fraction of LO's iL that reaches each output.
Cross Regulation:
Individual loop reactions to
load dumps offset iL
for other outputs.
No time gaps help
diminish cross regulation.
Switching Events:
tE plus one transition per output 1 + N Low gate-drive power.

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Master Voltage Loop

Current loop's dE disconnects last vON and connects first vO1 Reset clock.
Feed iL to one output at a time until each error disappears.
LO's leftover energy after vO(N1) should satisfy vON.
vON's error reflects variation of collective need.
AERR compares vON and vRN to generate collective error vERR.
vO(X)'s load iLD(X) relative to collective requirement iLD(X) determines dO(X).

pC << f0dB pI BW < zRHP.

Independent Voltage Loops

Peak-Voltage Control:
Flip flop de-couples connect and disconnect commands.
End of previous output dO(X1) sets flip flop to connect LO to vO(X).
CPERR resets flip flop to adjust LO's connection time dO(X).
CPERR disconnects LO when vO(X) reaches vR(X) vO(X)(+PK) vR(X).

Design Notes:
CO(X) establishes dominant pole pC pC << f0dB pI BW < zRHP.
A higher load current iLD(X) pulls vO(X)(PK) lower Load regulation.
vO(X)(AVG) falls with a higher iLD(X) Inherent droop compensation.

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Power IC Design

Pulse-Width Modulation:
dO(X1)'s fall starts ramp vRAMP.
End of previous output dO(X1) into CPPWM connects LO to vO(X).
AERR compares vO(X) and vR(X) to generate and amplify an error vE(X)
that adjusts LO's connection time dO(X) vO(X)(AVG) vR(X).

Compact Implementation: Integrate amplifier into summing comparator.

pC << f0dB pI BW < zRHP.

ii. Dedicated Sequences

Multiple Dedicated Energize/Drain Sequences:
One energize/drain sequence per output across operating period tO.
Individual demands set individual duty-cycles dE's.
Cross Regulation:
Individual loop reactions to
load dumps offset iL
for other outputs.
DCM and PDCM time gaps
diminish cross regulation.
Switching Events:
tE and tD per output 2N transitions Higher gate-drive power.

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Power IC Design

Implementation
Use vCLK to
Time-multiplex individual error signals vERR(X) into the current source.
Time-multiplex current source into individual outputs vO(X).
Each error amplifier AERR(X) adjusts each tE(X)tD(X) sequence to regulate vO(X).

Design Notes: Buck stage cannot energize to high output Cannot boost.
Boost stage cannot drain to low output Cannot buck.
tCLK must include margin for iL's response time tI BW.
tO includes margin for NtI BW Refresh vO's less often Lower accuracy.

Final Notes on Design

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Power IC Design

Too many factors can spoil performance Risk only when necessary.
A bad layout or a poorly packaged die can spoil a good circuit.
Consider all vertical issues, from devices to application.
Good designers balance optimism with pragmatism.
Challenge convention, but subject to worst-case possibilities.
The simplest circuit is usually the fastest and most reliable solution.
The simulator is good for tweaking and validating a design,
not for conceptualizing circuits.
Simulate only when you believe you know what to expect.
Meaningful innovation normally results from
intuition and insight of related technologies.

The END
Thanks for your interest,
and best wishes.
Rincon-Mora.gatech.edu

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