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HIGH-SPEED

SIGNAL
PROPAGATION
ADVANCED BLACK MAGIC

Howard Johnson
Martin Graham

`\\\

PRENTICE
HALL

PTR

PRENTICE HALL PTR


UPPER SADDLE RIVER,
WWW.PHPTR.COM

NJ 07458

TABLE OF CONTENTS
Preface

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Glossary of Symbols

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1 Fundamentals

1.1
Impedance of Linear, Time-Invariant, Lumped-Element Circuits
1.2
Power Ratios
1.3
Rufes of Scaling
1.3.1
Scaling of Physical Size
1.3.1.1 Scaling Inductors
1.3.1.2 Scaling Transmission-Line Dimensions
1.3.2
Power Scaling
1.3.3
Time Scaling
1.3.4
Impedance Scaling with Constant Voltage
1.3.5
Dielectric-Constant Scaling
1.3.5.1 Partially Embedded Transmission Lines
1.3.6
Magnetic Permeability Scaling
1.4 The Concept of Resonance
1.5
Extra for Experts: Maximal Linear System Response to a Digital Input
2 Transmission Line Parameters

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2.1
Telegrapher's Equations
2.1.1
So Good II Works an Barbed Wire
2.1.2
The No-Storage Principle and Its Implications for
Returning Signal Current
2.2
Derivation of Telegrapher's Equations
2.2.1
Definition of Characteristic Impedance ZC
2.2.2
Changes in Characteristic Impedance
2.2.3
Calculation of Impedance Zc From Parameters R, L, G, And C
2.2.4
Defmition of Propagation Coefficient y
2.2.5
Calculation of Propagation Coefficient y from Parameters R, L, G, and C
Ideal Transmission Line
2.3
2.4
DC Resistance
DC Conductance
2.5

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2.6 Skin Effect


What Causes the Skin Effect, and What Does It Have to Do With Skin?
2.6.1
Eddy Currents within a Conductor
2.6.2
High and Low-Frequency Approximations for Series Resistance
2.6.3
Skin-Effect Inductance
2.7
2.8 Modeling Intemal Impedance
Practical Modeling of Intemal Impedance
2.8.1
Special Issues Concerning Rectangular Conductors
2.8.2
2.9 Concentric-Ring Skin-Effect Model
Modeling Skin Effect
2.9.1
Regarding Modeling Skin Effect
2.9.2
2.10 Proximity Effect
2.10.1 Proximity Factor
2.10.2 Proximity Effect for Coaxial Cables
2.10.3 Proximity Effect for Microstrip and Stripline Circuits
2.10.4 Last Words an Proximity Effect
Proximity Effect II
2.10.4.1
2.10.4.2
2-D Quasistatic Field Solvers
2.11 Surface Roughness
2.11.1 Severity of Surface Roughness
2.11.2 Onset of Roughness Effect
2.11.3 Roughness of Pcb Materials
2.11.4 Controlling Roughness
2.12 Dielectric Effects
2.12.1 Dielectric Loss Tangent
2.12.2 Rule of Mixtures
2.12.3 Calculating the Loss Tangent for a Uniform Dielectric Mixture
2.12.4 Calculating the Loss Tangent When You Don't Know q
2.12.5 Causality and the Network Function Relations
2.12.6 Finding lerl to Match a Measured Loss Tangent
2.12.7 Kramers-Kronig Relations
2.12.8 Complex Magnetic Permeability
2.13 Impedance in Series with the Return Path
2.14 Slow-Wave Mode On-Chip
3 Performance Regions
3.1
Signal Propagation Model
3.1.1
Extracting Parameters for RLGC Simulators
3.2 Hierarchy of Regions
3.2.1
A Transmission Line 1s Always a Transmission Line
3.3
Necessary Mathematics: Input Impedance and Transfer Function
3.4 Lumped-Element Region
3.4.1
Boundary of Lumped-Element Region
3.4.2
Pi Model

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3.4.3
Taylor-Series Approximation of H (Lumped-Element Region)
3.4.4
Input impedance (Lumped-Element Region)
3.4.5
Transfer Function (Lumped-Element Region)
3.4.6
Step Response (Lumped-Element Region)
3.5 RC Region
3.5.1
Boundary of RC Region
3.5.2
Input Impedance (RC Region)
3.5.3
Characteristic Impedance (RC Region)
3.5.4
General Behavior within RC Region
3.5.5
Propagation Coefficient (RC Region)
3.5.6
Transfer Function (RC Region)
3.5.6.1 Propagation Function of RC Line with Open-Circuited Load
3.5.6.2 Propagation Function of RC Line with Matched End Termination
3.5.6.3 Propagation Function of RC Line with Matched Source Termination
3.5.6.4 Propagation Function of RC Line with Resistive End Termination
3.5.7
Normalized Step Response (RC Region)
3.5.8
Tradeoffs Between Distance and Speed (RC Region)
3.5.9
Closed-Form Solution for Step Response (RC Region)
3.5.10 Elmore Delay Estimation (RC Region)
LC Region (Constant-Loss Region)
3.6
3.6.1
Boundary of LC Region
Characteristic Impedance (LC Region)
3.6.2
Influence of Series Resistance on TDR Measurements
3.6.3
Propagation Coefficient (LC Region)
3.6.4
Possibility of Severe Resonance within the LC Region
3.6.5
3.6.5.1 Alternate Interpretation of Equation [3.17]
3.6.5.2 Practical Effect of Resonance
Terminating an LC Transmission Line
3.6.6
3.6.6.1 End Termination
3.6.6.2 Source Termination
3.6.6.3 Both-Ends Termination
3.6.6.4 Subtle Differences Between Termination Styles
3.6.6.5 Application of Termination Equations to Other Regions
Tradeoffs Between Distance And Speed (LC Region)
3.6.7
Mixed-Mode Operation (LC and RC Regions)
3.6.8
Skin-Effect Region
3.7
Boundary of Skin-Effect Region
3.7.1
Characteristic Impedance (Skin-Effect Region)
3.7.2
Influence of Skin-Effect on TDR Measurement
3.7.3
Propagation Coefficient (Skin-Effect Region)
3.7.4
Possibility of Severe Resonance within Skin-Effect Region
3.7.5
3.7.5.1 Subtle Differences Between Termination Styles
3.7.5.2 Application of Termination Equations to Other Regions
Step Response (Skin-Effect Region)
3.7.6

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Tradeoffs Between Distance and Speed (Skin-Effect Region)


3.7.7
Dielectric Loss Region
3.8
Boundary of Dielectric-Loss-Limited Region
3.8.1
Characteristic Impedance (Dielectric-Loss-Limited Region)
3.8.2
Influence of Dielectric Loss an TDR Measurement
3.8.3
Propagation Coefficient (Dielectric-Loss-Limited Region)
3.8.4
Possibility of Severe Resonance within Dielectric-Loss Limited Region
3.8.5
3.8.5.1 Subtle Differences Between Termination Styles
3.8.5.2 Application of Termination Equations to Other Regions
Step Response (Dielectric-Loss-Limited Region)
3.8.6
Tradeoffs Between Distance and Speed (Dielectric-Loss Region)
3.8.7
3.9 Waveguide Dispersion Region
Boundary of Waveguide-Dispersion Region
3.9.1
3.10 Summary of Breakpoints Between Regions
3.11 Equivalence Principle for Transmission Media
3.12 Scaling Copper Transmission Media
3.13 Scaling Multimode Fiber-Optic Cables
3.14 Linear Equalization: Long Backplane Trace Example
3.15 Adaptive Equalization: Accelerant Networks Transceiver
4 Frequency-Domain Modeling
Going Nonlinear
4.1
4.2 Approximations to the Fourier Transform
Discrete Time Mapping
4.3
Other Limitations of the FFT
4.4
4.5 Normalizing the Output of an FFT Routine
Deriving the DFT Normalization Factors
4.5.1
Useful
Fourier Transform-Pairs
4.6
4.7 Effect of Inadequate Sampling Rate
4.8 Implementation of Frequency-Domain Simulation
Embellishments
4.9
What if a Large Bulk-Transport Delay Causes the Waveform to
4.9.1
Slide Off the end of the Time-Domain Window?
How Do I Transform an Arbitrary Data Sequence?
4.9.2
4.9.3
How Do I Shift the Time-Domain Waveforms?
4.9.4
What If I Want to Model a More Complicated System?
4.9.5
What About Differential Modeling?
4.10 Checking the Output of Your FFT Routine

5 Pcb (printed-circuit board) Traces


5.1
Pcb Signal Propagation
5.1.1
Characteristic Impedance and Delay
5.1.2
Resistive Effects
5.1.2.1 DC Resistance of Pcb Trace

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5.1.2.2 AC Resistance of Pcb Trace


5.1.2.3 Calculation of Perimeter of Pcb Trace
5.1.2.4 Very Low Impedance Pcb Trace
5.1.2.5 Calculation of Skin-Effect Loss Coefficient for Pcb trace
5.1.2.6 Popsicle-Stick Analysis
5.1.2.7 Nickel-Plated Traces
5.1.3
Dielectric Effects
5.1.3.1 Estimating the Effective Dielectric Constant for a Microstrip
5.1.3.2 Propagation Velocity
5.1.3.3 Calculating the Effective Loss Tangent for a Microstrip
5.1.3.4 Dielectric Properties of Laminate Materials (core and prepreg)
5.1.3.5 Variations in Dielectric Properties with Temperature
5.1.3.6 Passivation and Soldermask
5.1.3.7 Dielectric Properties of Soldermask Materials
5.1.3.8 Calculation of Dielectric Loss Coefficient for Pcb Trace
Mixtures of Skin Effect and Dielectric Loss
5.1.4
Non-TEM Modes
5.1.5
5.1.5.1 Strange Microstrip Modes
5.1.5.2 Simulation of Non-TEM Behavior
Limits to Attainable Distance
5.2
SONET Data Coding
5.2.1
Pcb Noise and Interference
5.3
Pcb: Reflections
5.3.1
5.3.1.1 Both Ends Termination
5.3.1.2 Pcb: Lumped-Element Reflections
5.3.1.3 Potholes
5.3.1.4 Inductive Potholes
5.3.1.5 FVho's Afraid of the Big, Bad Bend?
5.3.1.6 Stubs and Vias
5.3.1.7 Parasitic Pads
5.3.1.8 How Close ls Close Enough?
5.3.1.9 Placement of End Termination
Making an Accurate Series Termination
5.3.1.10
Matching Pads
5.3.1.11
Pcb Crosstalk
5.3.2
5.3.2.1 Purpose of Solid Plane Layers
5.3.2.2 Variations with Trace Geometry
5.3.2.3 Directionality
5.3.2.4 NEXT: Near-End or Reverse Crosstalk
5.3.2.5 FEXT: Far-End or Forward Crosstalk
5.3.2.6 Special Considerations
5.3.2.7 Directionality of Crosstalk
Pcb Connectors
5.4
Mutual Understanding
5.4.1

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Table of Contents

Through-Hole Clearances
5.4.2
Measuring Connectors
5.4.3
Tapered Transitions
5.4.4
Straddle-Mount Connectors
5.4.5
Cable Shield Grounding
5.4.6
Modeling
Vias
5.5
Incremental
Parameters of a Via
5.5.1
Three Models for a Via
5.5.2
Dangling Vias
5.5.3
Capacitance Data
5.5.4
5.5.4.1 Three-Layer Via Capacitance
5.5.4.2 Effect of Back-Drilling
5.5.4.3 Effect of Multiple Planes
Inductance Data
5.5.5
5.5.5.1 Through-Hole Via Inductance
5.5.5.2 Via Crosstalk
Tlw Future of On-Chip Interconnections
5.6
6 Differential Signaling

Single-Ended Circuits
6.1
Two-Wire Circuits
6.2
Differential Signaling
6.3
6.4 Differential and Common-Mode Voltages and Currents
Differential and Common-Mode velocity
6.5
6.6 Common-Mode Balance
6.7 Common-Mode Range
6.8 Differential to Common-Mode Conversion
Differential Impedance
6.9
6.9.1
Relation Between Odd-Mode and Uncoupled Impedance
6.9.2
Why the Odd-Mode Impedance Is Always Less Than the
Uncoupled Impedance
6.9.3
Differential Reflections
6.10 Pcb Configurations
6.10.1 Differential (Microstrip) Trace Impedance
6.10.2 Edge-Coupled Stripline
6.10.3 Breaking Up a Pair
6.10.4 Broadside-Coupled Stripline
6.11 Pcb Applications
6.11.1 Matching to an External, Balanced Differential Transmission Medium
6.11.2 Defeating ground bounce
6.11.3 Reducing EMI with Differential Signaling
6.11.4 Punching Through a Noisy Connector
6.11.4.1
Differential Signaling (Through Connectors)
6.11.5 Reducing Clock Skew

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6.11.6 Reducing Local Crosstalk


6.11.7 A Good Reference about Transmission Lines
6.11.8 Differential Clocks
6.11.9 Differential Termination
6.11.10
Differential U-Turn
6.11.11
Your Layout Is Skewed
6.11.12
Buying Time
6.12 Intercabinet Applications
6.12.1 Ribbon-Style Twisted-Pair Cables
6.12.2 Immunity to Large Ground Shifts
6.12.3 Rejection of External Radio-Frequency Interference (RFI)
6.12.4 Differential Receivers Have Superior Tolerance to Skin Effect and
Other High-Frequency Losses
6.13 LVDS Signaling
6.13.1
Output Levels
6.13.2 Common-Mode Output
6.13.3 Conunon-Mode Noise Tolerance
6.13.4 Differential-Mode Noise Tolerance
6.13.5 Hysteresis
6.13.6 Impedance Control
6.13.7 Trace Radiation
6.13.8 Risetime
6.13.9 Input Capacitance
6.13.10
Skew
6.13.11
Fail-Safe

7 Generic Building-Cabling Standards


7.1
Generic Cabling Architecture
7.2 SNR Budgeting
Glossary of Cabling Terms
7.3
Preferred Cable Combinations
7.4
FAQ: Building-Cabling Practices
7.5
7.6
Crossover Wiring
Plenum-Rated Cables
7.7
Laying cables in an Uncooled Attic Space
7.8
7.9 FAQ: Older Cable Types
8 100-Ohm Balanced Twisted-Pair Cabling
UTP Signal Propagation
8.1
8.1.1
UTP Modeling
Adapting the Metallic-Transmission Model
8.1.2
8.2 UTP Transmission Example: 10BASE-T
8.3
UTP Noise and Interference
UTP: Far-End Reflections
8.3.1

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Table of Contents

UTP: Near-End Reflections


8.3.2
8.3.2.1 UTP: (Structural) Return Loss
8.3.2.2 Modeling Structural Return Loss
UTP: Hybrid Circuits
8.3.3
UTP: Near-End Crosstalk
8.3.4
UTP: Allen crosstalk
8.3.5
UTP: Far-End Crosstalk
8.3.6
8.3.7 Power sum NEXT and ELNEXT
UTP: Radio-Frequency Interference
8.3.8
UTP: Radiation
8.3.9
8.4 UTP Connectors
Issues with Screening
8.5
Category-3 UTP at Elevated Temperature
8.6
9 150-Ohm STP-A Cabling
9.1
9.2
9.3
9.4
9.5
9.6
10

150-Q STP-A Signal Propagation


150-Q STP-A Noise and Interference
150-Q STP-A: Skew
150-Q STP-A: Radiation and Safety
150-Q STP-A: Comparison with UTP
150-Q STP-A Connectors
Coaxial Cabling

10.1 Coaxial Signal Propagation


Stranded Center-Conductors
10.1.1
10.1.2 Why 50 Ohms?
10.1.3 50-Ohm Mailbag
10.2 Coaxial Cable Noise and Interference
10.2.1 Coax: Far-End Reflected Noise
10.2.2 Coax: Radio Frequency Interference
10.2.3 Coax: Radiation
10.2.4 Coaxial Cable: Safety Issues
10.3 Coaxial Cable Connectors
11

Fiber-Optic Cabling
11.1 Making Glass Fiber
11.2 Finished Core Specifications
11.3 Cabling the Fiber
11.4 Wavelengths of Operation
11.5 Multimode Glass Fiber-Optic Cabling
11.5.1 Multimode Signal Propagation
11.5.2 Why Is Graded-Index Fiber Better than Step-Index?
11.5.3
Standards for Multimode Fiber
11.5.4 What Considerations Govern the Use of 50-micron Fiber?

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11.5.5 Multimode Optical Performance Budget


11.5.5.1
Multimode Dispersion Budget
11.5.5.2
Multimode Attenuation Budget
11.5.6 Jitter
11.5.7 Multimode Fiber-Optic Noise and Tnterference
11.5.8 Multimode Fiber Safety
11.5.9 Multimode Fiber with Laser Source
11.5.10
VC SEL Diodes
11.5.11
Multimode Fiber-Optic Connectors
11.6 Single-Mode Fiber-Optic Cabling
11.6.1
Single-Mode Signal Propagation
11.6.2 Single-Mode Fiber-Optic Noise and Interference
11.6.3 Single-Mode Fiber Safety
11.6.4 Single-Mode Fiber-Optic Connectors
12

Clock Distribution
12.1 Extra Fries, Please
12.2 Aritlunetic of Clock Skew
12.3 Clock Repeaters
12.3.1 Active Skew Correction
12.3.2 Zero-Delay Clock Repeaters
12.3.3 Compensating for Line Length
12.4 Stripline vs. Microstrip Delay
12.5 Importance of Tenninating Clock Lines
12.6 Effect of Clock Receiver Thresholds
12.7 Effect of Split Termination
12.8 Intentional Delay Adjustments
12.8.1 Fixed Delay
12.8.2 Adjustable Delays
12.8.3 Automatically Programmable Delays
12.8.4 Serpentine Delays
12.8.5 Switchback Coupling
12.9 Driving Multiple Loads with Source Termination
12.9.1 To Tee or Not To Tee
12.9.2 Driving Two Loads
Daisy-Chain Clock Distribution
12.10
Case Study of Daisy-Chained Clock
12.10.1
12.11
The Jitters
When Clock Jitter Matters
12.11.1
12.11.1.1 Clock Jitter Rarely Matters within the Boundaries of a
Synchronous State Machine
12.11.1.2 Clock Jitter Propagation
12.11.1.3 Variance of the Tracking Error
12.11.1.4 Clock Jitter in FIFO-Based Architectures

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12.11.1.5 What Causes Jitter


12.11.1.6 Random and Deterministic Jitter
12.11.2
Measuring Clock Jitter

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12.11.2.1 Jitter Measurement
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12.11.2.2 Jitter and Phase Noise
Power Supply Filtering for Clock Sources, Repeaters, and PLL Circuits 656
12.12
659
12.12.1
Healthy Power
661
12.12.2
Clean Power
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12.13
Intentional Clock Modulation
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12.13.1
Signal Integrity Mailbag
12.13.2
Jitter-Free Clocks
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Reduced-Voltage Signaling
12.14
Controlling Crosstalk an Clock Lines
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670
12.16
Reducing Emission
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Time-Domain Simulation Tools and Methods

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13.1 Ringing in a New Era


13.2 Signal Integrity Simulation Process
13.2.1 How Much Modeling Do You Need?
13.2.2 What Happens After Parameter Extraction?
13.2.3 A Word of Caution
13.3 The Underlying Simulation Engine
13.3.1 Evolving Forward
13.3.2 Pitfalls of SPICE-Like Algorithms
13.3.3 Transmission Lines
13.3.4 Interpreting Your Results
13.3.5 Using SPICE Intelligently
13.4 IBIS (VO Buffer Information Specification)
13.4.1 What Is IBIS?
13.4.2 Who Created IBIS?
13.4.3 What Is Good About IBIS?
13.4.4 What' s Wrong with IBIS?
13.4.5 What You Can Do to Help
13.5 IBIS: History and Future Direction
13.5.1 IBIS Historical Overview
13.5.2 Comparison to SPICE
13.5.3 Future Directions
13.6 IBIS: Issues with Interpolation
13.7 IBIS: Issues with SSO Noise
13.8 Nature of EMC Work
13.8.1 EMC Simulation
13.9 Power and Ground Resonance

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Collected References

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Table of Contents

xix

Points to Remember

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Appendix A - Building a Signal Integre Department

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Appendix B - Calculation of Loss Slope

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Appendix C - Two-Port Analysis

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Simple Cases Involving Transmission Lines


Fully Configured Transmission Line
Complicated Configurations
Appendix D - Accuracy of Pi Model
Pi-Model Operated in the LC Region

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Appendix E - erf( )

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Index

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