EE7605 Signal Integrity in HighSpeed Digital Systems

Lecture 8: The Power Distribution

Network (PDN)
System Level Design

PDN Can Mean a lot to the System

Gigabyte 965P-S3

Gigabyte 965P-DS3

The same chipset:

Northbridge: Intel P965
Express Chipset
Southbridge: Intel ICH8
Marvel 8056 Gigabit LAN
Controller
GIGABYTE SATAII
controller
Realtek ALC888 8 Channel
Audio Codec
Big difference in market price
(30 USD)?

IR Drop in PDN
To design a high speed system, the first and primary is to keep a
constant supply voltage on the pads of the chips, and keep it within
a narrow tolerance band. Voltage ripple typically on the order of 5%,
which leads to a limitation on impedance of PDN.

Target Impedance

Hierarchies of PDN
PCB

On-die

On-package
decoupling
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VRM

Successful PDN

When the impedance profile is

below the target impedance,
the worst case voltage noise is
below the ripple spec.
The square wave is the
current draw by the chip,
while the flat curve is the
voltage on the supply rail.

Target Impedance
Real PDN depends on current spectrum

If the target impedance were 1 Ohm, this board would work well
in all cases.
Even if the target value were as low as 0.2 Ohm, as long as the
current spectrum did not have any worst case amplitude spikes
in the 5 MHz to 20 MHz range, this board might work just fine.

Target Impedance
In the real world of practical product design, its very
hard to establish the target impedance without
accurate spectrum of current drawn by chips

Target Impedance
In practice, maximum transient current is estimated at
some ratio of the active peak current.
The maximum impedance for the PDN, the target
impedance, is established based on the highest
impedance that will create a voltage drop still below
the acceptable ripple spec.

Target Impedance

ome chip vendors, especially FPGA vendors, will
S
provide calculation tools that allow simple estimates of
the current draw of specific voltage rails depending on
the gate utilization. These can be used to estimate the
target impedance specs of the rails.

Example of the target impedance of different voltage rails for Altera FPGA.
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Engineering the PDN

The PDN interconnects can be partitioned in
the frequency domain into five regions

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1) The Voltage Regulation Module

Low quiescent current, low

dropout
Designed to operate from an
input voltage between 2.3 V
and 5.5 V and to provide up to
300 mA of output current.
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Real Capacitor Modeling

NO ideal capacitors
An ideal capacitor has an impedance that drops off
inversely with increasing frequency
A real capacitor reaches a lowest impedance and then
begins to increase in value. It can be approximated by
a RLC circuit model.
self resonant frequency (SRF)

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Real Capacitor Modeling

Changing a Capacitors C has no impact on its High Frequency
Impedance

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VRM + Bulk Decoupling Cap

When the regulator is turned on, its output impedance drops by orders of
magnitude at low frequency. A large change in current produces a small
change in voltage, the behavior of a low impedance and exactly what is
expected from a regulator. However, the actual behavior of the VRM, this
low impedance is maintained from DC only up to the kHz range.
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How to Determine the Cap?

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Multiple Capacitors in Parallel

When multiple, identical capacitors are connected in
parallel, the resulting impedance matches the
behavior of an RLC circuit, but the circuit elements
values are different.

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Multiple Capacitors in Parallel

When capacitors have a different value of capacitance
or ESL, the behavior is not so simple.
There is a new
feature
between the
self resonant
frequencies:
parallel
resonant peak.

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2) Multi-layer ceramic chip (MLCC)

capacitors

Multi-layer ceramic chip (MLCC) capacitors are used quite often

in dc-dc converter input and output filters. They have low
intrinsic ESL (equivalent series inductance), small footprint and
low cost.
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The Equivalent Series Inductance

The complete path of the power and return currents
from the pads of the BGA package to the capacitor is
shown below

The ESL of the capacitor can be divided into four

regions:
1) The loop inductance of the surface traces and top of the plane's
cavity
2) The loop inductance of the vias from the capacitor pads to the top
of the plane cavity
3) The spreading inductance from the capacitor vias to the vias of the
BGA
4) The loop inductance from the cavity under the package to the leads
or solder balls of the package
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The Equivalent Series Inductance

Accurate modeling can only be done by 3D simulation
tools.

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Engineering the parameters can leads to smaller

inductance.

General Guidelines
Reduce the impedances in the PDN:
Use power and ground planes on adjacent
layers, with as thin a dielectric as possible,
and bring them as close to the surface of the
board stack-up as possible.
Use as short and wide as possible surface
trace between the decoupling capacitor pads
and the vias to the buried power and ground
plane cavity and place the capacitors where
they will have the lowest loop inductance.
Use SPICE to help select the optimum number
of capacitors and their values.
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3) The Package Barrier

Between the pads on the chip and the pads on the
circuit board is typically the IC package.
The loop inductance of the package leads in the
power/ground distribution path is in series with the
pads of the chip to the pads on the circuit board. This
series inductance creates an impedance barrier.
Low-cost packages are often leaded. The loop
inductance of adjacent leads is about 20 nH/inch. For
package leads 0.25 inches long, the loop inductance can
be as much as 5 nH 0.3Ohm@100Mhz

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Package Types
Package functions
Electrical connection of signals and power, mechanical
connection of chip to board, heat sink, chip protection,
low cost

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Quad Flat Pack (QFP)

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Ball Grid Array (BGA)

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Ball Grid Array with Flip-Chip Bumping

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4) On-die Capacitance
The impedance at the highest frequency is established
by the on-die decoupling cap.
the capacitance between the power and ground rail
metallization, the gate capacitance from all the p and
n junctions and any added capacitance.
In a typical CMOS circuit, at anyone time, one of the
gates is on and the other is off.
This means that the gate capacitance of one of the
gates, either the p channel or the n channel is
connected between the power and ground rails.

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at 65 nm, total
cap 1000 nF

On-die Capacitance

The on-die capacitance provides an impedance below 1 mOhm,

at frequencies above 800 MHz. All high-frequency decoupling is
provided by this mechanism.
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On-die Cap + Package inductance

When the interactions of the on-die capacitance are added to the package
inductance, the behavior is complicated. The figure suggests that no matter
what the board level PDN does, it can never reduce the impedance the chip
sees below the package lead impedance. When the package equivalent lead
inductance is 0.1 nH, the board cannot influence the impedance the chip sees
to below 10 mOhms at frequencies above 10 MHz (for this simulation).
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On-die/package Cap + Package induct.

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