Programmable Processors

Reading: Chapter 8

ELE 206/COS 306:

Contemporary Logic Design
Fall 2016
Sharad Malik

Copyright Frank Vahid and Sharad Malik

Derived from presentation slides for Digital Design, 2nd edition, Frank Vahid, 2010

Introduction

Programmable (general-purpose) processor

Mass-produced, then programmed to implement different processing tasks

Well-known common programmable processors: Pentium, ARM, Sparc, PowerPC

Lesser-known but still common: MIPS, 8051, PIC
Low-cost embedded processors found in appliances, toys, etc.

Instructive to design a very simple programmable processor

Real processors can be much more complex

Seatbelt
3-tap FIR filter
warning light
program
program

e 3
2
1
0
2x4

Instruction
memory I

x(t)
xt0

Seatbelt warning
light single-purpose
processor

x(t-1)
c0

xt1

c1

xt2

c2

PC

IR

reg

3-tap FIR filter

single-purpose processor

n-bit
2x1
Register file
RF

Controller
Control unit

Data memory D

x(t-2)

Other
programs

ALU
Datapath

General-purpose processor

Basic Architecture

Processing generally consists of:

Loading some data

Transforming that data
Storing that data

Basic datapath: Useful circuit in a

programmable processor

Can read/write data memory, where main

data exists
Has register file to hold data locally
Has ALU to transform local data

Data memory D

n-bit
2x1

Register file RF

ALU

Datapath
3

connected
to the
outside
world

Basic Datapath Operations

Load operation: Load data from data memory to RF

ALU operation: Transforms data by passing one or two RF register values through ALU, performing

operation (ADD, SUB, AND, OR, etc.), and writing back into RF.
Store operation: Stores RF register value back into data memory
Each operation can be done in one clock cycle

Data memory D

Data memory D

Data memory D

n-bit
2x1

n-bit
2x1

n-bit
2x1
a

Register file RF

Register file RF

Register file RF

ALU

ALU

ALU

ALU operation

Store operation

Load operation

Basic Datapath Operations

Q: Which

are valid single-cycle operations for given datapath?

Move D[1] to RF[1] (i.e., RF[1] = D[1])

Store RF[1] to D[9] and store RF[2] to D[10]

a

Add D[0] plus D[1], store result in D[9]

Data memory D

Data memory D

Data memory D

n-bit
2x1

n-bit
2x1

n-bit
2x1

Register file RF

Register file RF

Register file RF

ALU

ALU

ALU

ALU operation

Store operation

Load operation

Basic Architecture Control Unit

D[9] = D[0] + D[1] requires a sequence

of four datapath operations:
0: RF[0] = D[0]
1: RF[1] = D[1]
2: RF[2] = RF[0] + RF[1]
3: D[9] = RF[2]

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

Data memory D

n-bit
2x 1

Each operation is an instruction

Sequence of instructions program
Looks cumbersome, but that's the world of
programmable processors Decomposing
desired computations into processorsupported operations
Store program in Instruction memory
Control unit reads each instruction and
executes it on the datapath

PC: Program counter address of current

instruction
IR: Instruction register current instruction

PC

IR
Register file RF

Controller
ALU
Control unit

Datapath

signals to control the datapath

Basic Architecture Control Unit

To carry out each instruction, the control unit must:

Fetch Read instruction from inst. mem.

Decode Determine the operation and operands of the instruction
Execute Carry out the instruction's operation using the datapath
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

PC
01

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

IR
RF[0]=D[0]
PC

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

Data memory D
D[0]: 99

IR
RF[0]=D[0]

PC
1

Controller

n-bit
2x 1

IR
RF[0]=D[0]

Register file RF
R[0]: ?? 99

Controller
Control unit

(a)

Fetch
7

"load"

Controller

Control unit
(b)

Decode

ALU
Datapath

Control unit

Execute

(c)

Basic Architecture Control Unit

To carry out each instruction, the control unit must:

Fetch Read instruction from inst. mem.

Decode Determine the operation and operands of the instruction
Execute Carry out the instruction's operation using the datapath
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

PC
12

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

IR
RF[1]=D[1]
PC

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

Data memory D
D[1]: 102

IR
RF[1]=D[1]

PC
2

Controller

n-bit
2x 1

IR
RF[1]=D[1]

Register file RF
R[1]: ?? 102

Controller
Control unit

(a)

Fetch
8

"load"

Controller

Control unit
(b)

Decode

ALU
Datapath

Control unit

Execute

(c)

Basic Architecture Control Unit

To carry out each instruction, the control unit must:

Fetch Read instruction from inst. mem.

Decode Determine the operation and operands of the instruction
Execute Carry out the instruction's operation using the datapath
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

PC
23

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

IR
RF[2]=RF[0]+RF[1]
PC

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

Data memory D

IR
RF[2]=RF[0]+RF[1]

PC
3

Controller

IR
RF[2]=RF[0]+RF[1]

Register file RF
R[2]: ?? 201

Controller
Control unit

(a)

Fetch
9

"ALU (add)"

99

Controller

Decode

ALU
Datapath

Control unit

Execute

102
201

Control unit
(b)

n-bit
2x 1

(c)

Basic Architecture Control Unit

To carry out each instruction, the control unit must:

Fetch Read instruction from inst. mem.

Decode Determine the operation and operands of the instruction
Execute Carry out the instruction's operation using the datapath
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

PC
34

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

IR
D[9]=RF[2]
PC

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

Data memory D
D[9]=?? 201

IR
D[9]=RF[2]

PC
4

Controller

n-bit
2x 1

IR
D[9]=RF[2]

Register file RF
R[2]: 201

Controller
Control unit

(a)

Fetch
10

"store"

Controller

Control unit
(b)

Decode

ALU
Datapath

Control unit

Execute

(c)

Basic Architecture Control Unit

Init
PC=0

Fetch

Decode

Execute

IR=I[PC]
PC=PC+1

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

Data memory D

n-bit
2x1

Controller
PC

IR
Register file RF

Controller
ALU

11

Control unit

Datapath