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An Overview of LTE PRACH Detection for the PC20x

Date: 04-01-2008
Version: v0.50
Status: Preliminary
Type: CTO Office Technical Note
ID: CTO-TN-0009

picoChip (Beijing) Technology Co. Ltd.


Room 108, Bldg 10,
ZGC Software Park, Haidian District,
Beijing, 100094
P.R. China
www.picochip.com

Proprietary & Confidential


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An Overview of LTE PRACH Detection for the PC20x

Table of Contents
Table of Contents............................................................................................................................................. 2
Version History ................................................................................................................................................ 2
1 Introduction to picoArray ......................................................................................................................... 3
2 Introduction to PRACH ............................................................................................................................. 5
3 Generation of RACH Preamble ................................................................................................................ 6
4 Detection of RACH Preamble ................................................................................................................... 7
4.1 RACH Preamble Receiver structure.................................................................................................... 7
4.2 Complexity Analysis............................................................................................................................. 8
4.3 Consideration of one antenna ............................................................................................................. 9
4.4 Implementation on PC20x ................................................................................................................. 10
4.4.1 Detection Method ....................................................................................................................... 10
4.4.2 Throughput calculations............................................................................................................. 10
4.4.3 Resource Estimation.................................................................................................................. 11
References ..................................................................................................................................................... 11
5 Glossary ................................................................................................................................................... 12

Version History
Version

Date

Author(s)

Reason for Change

v0.10

25-Oct-2007

Yu Huai

Created

v0.20

03-Jan-2008

Yu Huai

Re-write

v0.30

10-Jan-2008

Yu Huai

Re-construct after Sams


Review

V0.40

20-Jan-2008

Yu Huai

Re-construct after
general review

v0.50

01-Apr-2008

Yu Huai

Updated new algorithm


for prach detection

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An Overview of LTE PRACH Detection for the PC20x

1 Introduction to picoArray
The picoArray is a multi-processor IC which integrates hundreds of processing elements into a single array.
The individual elements have been optimized for signal processing and wireless algorithm computation and
control. The result is a general purpose wireless communications processor, capable of executing all
contemporary wireless standards, which combines the computational density of a dedicated ASIC with the
programmability of a traditional high-end Digital Signal Processor (DSP). Details of picoArray can be found in
[3]. For the time being there are two main picoArray DSP products: PC102 and PC20x (PC202, PC203 and
PC205).
The PC102[6] contains four different types of array elements (AEs) which are detailed in Table 1, three of
which are programmable and the fourth is a configurable hardware accelerator unit. Minor differences exist
between the three programmable AE types (STAN2, MEM2 and CTRL2). These differences include the size
of instruction/data memory, additional processing units and instructions supported (e.g. multiply-accumulate,
multiply). Each AE can issue a long instruction word (LIW) of up to 64 bits into up to 3 execution units in a
single cycle (at 160 MHz). Each AE communicates with other AEs within the array over a bus which is
connected to by several ports.
In addition to the STAN2, MEM2 and CTRL2 AE types specified in Table 1, software for the PC102 can also
be targeted at the ANY2 AE type implying that: (1) the function does not use any AE-specific instructions and
(2) the code and data memory requirements can be met by all AE types.
Software, written in C or ASM, is targeted at an AE type depending on the processing units used and
memory required.

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Table 1: PC102 processor variants and memory distribution.


Type

Description

Number

Memory
(bytes)

STAN2

Standard.

240

768

64

8,704

14

n/a

65,536

322

1,003,520

A standard AE type includes multiply-accumulate peripheral


as well as special instructions optimized for CDMA spread
and de-spread. Memory is divided between 512 bytes code
and 256 bytes data.
MEM2

Memory
An AE having multiply unit and additional memory.
Memory division between code and data is configurable.

FAU

Function Accelerator Unit


A co-processor optimized for specific signal processing
tasks (FEC, preamble detect, FHT, etc). Includes dedicated
hardware for trellis operations.

CTRL2

Control
An AE type with a multiply unit and larger amounts of data
and instruction memory optimized for the implementation of
base station control functionality.
Memory division between code and data is configurable.
Totals per PC102 device:

The picoBus is the name given to the switching fabric running vertically and horizontally between the
processing elements in the array. AEs are assigned 32-bit slots on the picoBus at compile time thereby
removing the need for arbitration and making performance completely deterministic. Each AE communicates
over the picoBus via its ports. These are defined using picoVHDL. Each AE has a number of ports which can
be configured to be read (incoming) or write (outgoing). Data sent between AEs is:
1. Written to a write port FIFO by the sending AE.
2. Sent over the picoBus on the next available slot.
3. Read from the read port FIFO by the receiving AE.
By default, communication between AEs is data blocking. On an attempt to read data from the picoBus, an
AE will block until data becomes available in the read port FIFO. Similarly, when attempting to write data to
the picoBus, the sending AE will block if its write port FIFO is full. A full write port FIFO infers that the
receiving AEs read port is not taking data (i.e., is full itself).
Bandwidth on the picoBus between communicating AEs is assigned via @-rates. A signal is assigned an @rate which is a positive integer power of 2, e.g., @8, @16. The @-rate is defined in the port declarations in
both the sending and receiving AEs. This @-rate is relative to the system clock (160 MHz for the PC102 and

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PC20x) and indicates how often data may be sent. For example, @8 means that a 32-bit data value can be
sent every 8 cycles (of the 160 MHz bus). The receiving AEs must therefore issue a read (against the
associated port) once every 8 cycles in order to prevent the sending AE from blocking.
PC20x and PC102 are similar except that they have different number of AEs and different accelerators. In
Table 2 we give a brief overview of PC202, PC203 and PC205[7].
Table 2: Brief overview of PC202, PC203 and PC205
AE Type

PC20x

Number

Memory

of AEs

(bytes)

STAN

196

768

FFT/IFFT

MEM

50

8,704

Viterbi

CTRL

65,536

Turbo decoder,

Total*

248

716,800

Reed-Solomon decoder,

FAU

Cryptography accelerator
PC202 & PC205 only: ARM9 host & peripherals
* FAU AEs not included

2 Introduction to PRACH
This document discusses the structure, complexity, resource estimation of the LTE random access preamble
correlator implemented on a picoArray.
The main purpose of the random access procedure is to obtain uplink time synchronization and to obtain
access to the network.
The physical layer random access preamble, illustrated in Figure 1, consists of a cyclic prefix of length TCP
and a sequence part of length

TPRE .
CP

Sequence

TCP

TPRE

Figure 1 Random access preamble format.


The following preamble sequence and parameters have been agreed so far[1]:
-

Preamble sequence: Zadoff-Chu(ZC) sequence with zeros correlation zone

Zadoff-Chu sequence length

Preamble duration in the table below:

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Table 3 Random access preamble parameters.


Preamble format

TCP

TSEQ

3168 Ts

24576 Ts

21024 Ts

24576 Ts

6240 Ts

2 24576 Ts

21024 Ts

2 24576 Ts

448 Ts

4096 Ts

4
(frame structure type 2 only)

Bandwidth : 1.08 MHz

Number of preamble sequences in a cell : 64

The details of parameters and configuration of the RACH preamble can be found in [1]. In this document, we
focus on transmission bandwidth to 5MHz, 10MHz and 20MHz.

3 Generation of RACH Preamble


The random access preambles are generated from Zadoff-Chu sequences with zeros correlation zone,
generated from one or several root Zadoff-Chu sequences. The network configures the set of preambles
sequences the UE is allowed to use.
The

u th root Zadoff-Chu sequence is defined by


xu (n ) = e

un ( n +1)
N ZC

, 0 n N ZC 1

where N ZC is the length of the Zadoff-Chu sequence. From the u th root Zadoff-Chu sequence, random
access preambles with zero correlation zones of length N CS 1 are defined by cyclic shifts according to

xu ,v (n) = xu ((n + Cv ) mod N ZC )


where

Cv is the cyclic shift.

The signatures are generated by cyclic shifts of a ZC sequence as shown in Figure 2.


Signature 0

Guard Interval

Signature 1
CP

ZC sequence
Signatures are generated
by Cyclic Shift

Signature 2

Signature 3

Figure 2 RACH Preamble Sequence


The RACH preamble generation can be done either in time domain or frequency domain.
Given that the sampling rate for a 20 MHz system is 30.72MHz and given that the RACH preamble spans
0.8ms, the number of samples equals 24576. Further, the RACH sub-carrier spacing is 1.25 KHz while the
sub-carrier for PUSCH and PUCCH is 15 KHz. In order to maintain the same sampling rate, 2048*12 point
DFT is needed for the signal generation at transmitter if they are done in frequency domain.
The alternative approach is to have time domain signal generation and extraction which involves upsampling and filtering at transmitter. With time domain implementation, the up-sampling from 1.08 MHz to
system sampling rate 30.72 MHz is difficult to implementation.
One typical method is illustrated in Figure 3. It is similar to the usual TX signal generation for DFT spread
OFDM signal.

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The frequency domain scheme used to generate the RACH preamble is explained as follows.
1. ZC sequence is generated in Time Domain.
2. N ZC -point DFT is used for time to frequency domain conversion, where N ZC is the ZC sequence length
with prime number, for FDD it is 839.
3. The output of N ZC -point DFT is mapped to the assigned sub-carrier.
4.

N IDFT point IDFT is used for frequency to time domain conversion, where IDFT is used instead of IFFT
N

since the number of the samples after IDFT is not 2 in order to maintain the same system sampling rate.
5. If preamble time duration is larger than 0.8 ms, it needs repeat the output of IDFT.
6. CP insertion

DFT

Sub-carrier
Mapping

IDFT

Repeat

CP
insertion

Preamble segment

Size: N IDFT

Size: N zc

Figure 3 Generation of RACH preamble

4 Detection of RACH Preamble


4.1 RACH Preamble Receiver structure
In order to reduce the complexity especially for the number of multiplications of the detector at eNodeB,
frequency domain processing has been accepted for the preamble detection (i.e. correlation operation). This
is one reason to introduce cyclic prefix for random access.
The received signal is first pre-processed in time domain, then transformed to frequency domain by FFT and
multiplied with the Fourier transformed RACH sequence. Then the cross correlation is obtained by
transforming back to time domain by IFFT followed zero insertion operation.
Figure 4 describes the principle components of the RACH preamble receiver, using DFT-based (frequency
domain) SC-FDMA receiver. The following notations are used:

Figure 4 RACH preamble DFT-SOFDM receiver structure


For the receiver, the first block is Down-conversion by using NCO, which shifts the location band of PRACH
to lowest frequency band. After the Down-converion block, the Linear filter filters the sampling signal, which
avoid to aliasing after Decimation. and the result of Decimation is fed into CP-removing block. After the CPremoving block, the FFT engines transform the SC-FDMA symbols from time domain to frequency domain.
Then the sub-carrier de-mapping block extracts the RACH preamble sequence from the output of the FFT
engines. The result of sub-carrier de-mapping multiplied by each signatures is fed into zero insertion block.

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Then IFFT engines transform the cross correlation from frequency domain to time domain. The energy
detection block estimates noise power, sets the detection threshold, and makes a decision.

4.2 Complexity Analysis


In this section, the complexity is evaluated as the required number of multiplication for detection of RACH
preamble. The chosen method to detection the RACH preamble uses a FFT and IFFT, illustrated in Figure 5.
The received signal is first transformed to the frequency domain by a FFT and multiplied with the Fourier
transformed RACH sequence. Then the cross correlation is obtained by transforming back to time domain
using an IFFT.
With this scheme, the delay profile for the cyclic delay whose range is up to the preamble length is obtained.
Therefore, since the signatures are equivalent to the propagation delay, every signatures generated by cyclic
shifts of the same ZC sequence can be detected simultaneously as illustrated in Figure 5.

FFT

IFFT
RACH sequence

Signature0

( Freq. Domain)

Signature3

Signature1 Signature2

Figure 5 Detection of RACH preamble


Therere 64 preamble sequences in one cell [1]. These preamble sequences can be generated by using one
same root sequence or different root sequence. The number of root sequence used to generate preamble
sequence depends on cell radius. For example, if Ncs equal to 13, it means that cell radius less than 1 km,
the 64 preamble sequences are generated cyclic shifts of the same ZC sequence. While Ncs equal to 839,
the 64 preamble sequences are generated by 64 different ZC sequences. The worst case of complexity is
the case that Ncs equal to 839. The following complexity analysis based 64 preamble sequences generated
by cyclic shifts of the same ZC sequence. In the worst case, the computation of IFFT and time energy
detection are need to perform 64 times.
Polyphase filters are used for Linear filter and Decimation. For general, we use cascade filters to implement
the polyphase filters for different transmission bandwidth as illustrated in Table 4. The 3x decimation filter
has large taps (about 48 taps) to guarantee enough stopband attenuation, the cascaded 2x decimation filter
has small taps (7 taps enough).
In [1] the RACH sub-carrier spacing is 1.25 KHz while the sub-carrier for PUSCH and PUCCH is 15 KHz. In
order to maintain the same sampling rate, 12*FFT point DFT is needed for the signal receive at receiver if
they are done in frequency domain. In Figure 4, Decimation is used to decrease the needed FFT size as
illustrated in Table 4.
Table 4: RACH receiver DFT size
Transmission
PUSCH and
PUCCH receiver
FFT size
System Sampling
Rate
RACH Sampling
point

1.25MHz
128

2.5MHz
256

5MHz
512

10MHz
1024

15MHz
1536

20MHz
2048

1.92MHz

3.84MHz

7.68MHz

15.36MHz

23.04MHz

30.72MHz

128*12
=1536

256*12
=1536*2

512*12
=2048*2

1024*12
=2048*2*3

1536*12
=1536*2*2*
3
1536

2048*12
=2048*2*2*
3
2048

RACH receiver
1536
1536
2048
2048
DFT size
Polyphase Filter
1
2
3
3*2
3*2*2
Deceimation rate
From the Figure 4, the number of complex multiplications, N CML is calculated as follows.
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N CML = N Filters + N FFT + N IDFT _ N ZC + N ZC


N Filters is the number of complex multiplication required for polyphase filters.

Here

N Filters = tap _ number / decimation _ rate


Using the polyphase filters decimation approach, the needed FFT size is reduced to 2048-point, the number
of multiplications can be reduced to:
N FFT = M / 2 log 2 M ,
where M is 2048 FFT size
The N IDFT _ N ZC is the number of complex multiplications required for prime 839 point IFFT. Zeros are
appended after cross correlation sequences to construc 1024 point then IFFT can be used to transform
sequence from frequency domain to time domain. The zeros insertion change the PRACH time resolution
from 839/1ms to 1024/1ms.
N IDFT _ N ZC = N / 2 log 2 N ,
Given that the sampling rate for a 20 MHz system is 30.72MHz and given that the RACH preamble spans
0.8ms, N CML = 16480
From above analysis, the complexity of algorithm for prach detection can be accepted if its implemented in
PC20x, and it doesnt need additional memory to store sampling signal.

4.3 Consideration of one antenna


For the system to function correctly, RACH must be able to operate as the same received C/I as UL-SCH ,
sync RACH and any associated UL control signalling.
As the C/I for UL-SCH is a function of the transmission data rate, we therefore need to establish a
reasonable minimum data rate for UL-SCH.
Using the following, we consider that a minimum transmission rate of 96 bits per 1ms TTI (96kbps) is a
reasonable assumption:
-

The RB size for UL is 12 sub-carriers (180kHz)

6 long blocks per UL sub-frame, 2 sub-frames per 1ms TTI, and QPSK modulation results in 288
channel bits per TTI

Excessive use of repetition after channel coding is to be avoided as this consumes valuable
time/frequency resources in the cell and suggests an alternative multiple access scheme or
resource block size should be considered

The base turbo code rate is assumed to be 1/3

288 channel bits /3 = 96 information bits per 1ms TTI

Assuming time-separated transmission of RACH and UL-SCH, the transmit power available at the UE for
non-sync RACH and UL-SCH are equal.
For balance transmit power conditions between RACH and PUSCH, and similar noise-limited situations,
required RACH preamble length is obtained as [2],

Tp =
where

E p / N0

RPUSCH Eb / N 0

RPUSCH is the bit rate of PUSCH during active transmission.

There seems to be some consensus that the required

E p / N 0 is of the order of 17 or 18dB in TU 6-ray

channel for a probability of false alarm of 1% or 0.1% respectively and for a probability of missed detection of
1e-2(see e.g. [2],[3]).
Comparing various results for the performance of the SC-FDMA uplink (e.g. [4]), it would appear that it is
st
reasonable to expect 20% BLER (a probable HARQ operating point for 1 time transmissions) at around 1dB
Es / N 0 per receive antenna in a TU channel using a 1/3 rate turbo code with realistic channel estimation.

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This translates into an approximate

Eb / N 0 for the UL-SCH of around 3dB per antenna (0 dB with two

antennas).
Given

RPUSCH =96kbps, the preamble length of Tp =800s,


E p / N 0 = Eb / N 0 + 10*log10 ( Tp * RPUSCH ) = 18.8 dB

this result in a 18.8dB, its larger than the required 18dB, so we can use one antenna for RACH receiver in
2x2 MIMO systems.
For lower data rate, the longer RACH preamble sequence is used for RACH detector, its also satisfied with
above discussion.

4.4 Implementation on PC20x


4.4.1 Detection Method
The received signal on each antenna is pre-processed in time-domain (down-conversion, filters and
decimation), transformed in frequency domain, de-mapped, multiplied by each signature, and then
transformed back in time domain (See Figure 4). The energy detector estimates noise power, sets the
detection threshold, and makes a decision.
To estimate noise power, the samples after the IFFT are compared to Threshold A. For each root sequence
used, noise power is estimated over the samples lower than Threshold A. Threshold B (the detection
threshold) is set by the estimated noise power plus an offset value (this offset is chosen to achieve a 1%
global false alarm probability).
For each sample, the energy received on each antenna is added and compared to Threshold B. If the energy
of one sample exceeds Threshold B, the corresponding preamble is detected.

4.4.2 Throughput calculations


With the system parameters presented in [1], here we give out some throughput, illustrated in Table 3.
Table 5: RACH receiver Throughput
System
Transmission
Bandwidth
System
Sampling Rate
Number of
cycle per input
sample(Note 1)
Downconversion
Polyphase
filters
(Note 2)
CP removing
(Note 3)
RACH receiver
FFT
De-mapping
(Note 4)
Multiplication
IFFT

1.28MHz

2.56MHz

5MHz

10MHz

15MHz

20MHz

1.92MHz

3.84MHz

7.68MHz

15.36MHz

23.04MHz

30.72MHz

@83.33

@41.67

@20.83

@10.42

@6.94

@5.20

@83.33

@41.67

@20.83

@10.42

@6.94

@5.20

@83.33
@83.33

@41.67
@83.33

@20.83
@62.50

@10.42
@62.50

@6.94
@83.33

@5.20
@62.50

@83.33
@94.07
@94.07
@94.07
@94.07
@172.0
@172.0
@172.0
@172.0
@172.0

@83.33
@94.07
@94.07
@94.07
@94.07
@172.0
@172.0
@172.0
@172.0
@172.0

@62.50
@70.50
@70.50
@70.50
@70.50
@172.0
@172.0
@172.0
@172.0
@172.0

@62.50
@70.50
@70.50
@70.50
@70.50
@172.0
@172.0
@172.0
@172.0
@172.0

@83.33
@94.07
@94.07
@94.07
@70.50
@172.0
@172.0
@172.0
@172.0
@172.0

@62.50
@70.50
@70.50
@70.50
@70.50
@172.0
@172.0
@172.0
@172.0
@172.0

Note 1: number of cycle per input sample is 160/(system sampling rate), where 160 is core clock rate of the
pA.

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Note 2: Polyphase filters are used to as filters and decimation. The result of decimation is constant length
2048 point, for different transmission bandwidth, the decimation rate is different. For 1.28MHz, theres not
polyphase filters.
Note 3: Due to decimation operation, the throughput of FFT engine is same as 2.56MHz, the CP ratio is
3168/24576, so the throughput of the FFT engine is 2.56*(24576)/(24576+3168) = 2.267MHz. So the
number of cycles per sample is 160/2.267 = 70.50 cycles. The top slot rate is input data rate, the bottom slot
rate is output data rate.
Note 4: The number of used data sub-carrier of RACH preamble is 839, after 2048-point FFT, extracting
sub-carriers from frequency domain, the throughput of the input of the multiplied by each signature block is
2.267*839/2048=0.929MHz, the number of cycles per sample is 160/0.929 = 172.0 cycles. The latecy of
RACH receiver is computed as following: the 2048 point FFTs latency is about 140 us, 1024 point IFFTs
latency is about 70 us, the latency of other block is about 300 us. For 64 preamble sequences generated by
cyclic shifts of the same ZC sequence, the latency is 140us+70us+300us = ~510us. For the worst case, the
latency is 140us+(70us)*64+300us=~5ms.

4.4.3 Resource Estimation


As shown in Figure 4, the RACH preamble receiver need Down-conversion, Linear filters, CP remover, DFT,
mother Zadoff-Chu sequence generation, sub-carrier de-mapping, IDFT and Energy detection blocks. The
resource estimation is illustrated in Table 7.
Table 6: Resource Estimation
System
Transmission
Bandwidth
Downconversion
Polyphase
filters
(Note 1)
CP removing
DFT
(Note 2)

Sub-carrier
de-mapping
Zadoff-Chu
mother
sequence
Cross corelator
839 point IDFT
Energy
Detection

1.28MHz

2.56MHz

5MHz

10MHz

15MHz

20MHz

1 Mems

1 Mems

1 Mems

1 Mems

1 Mems

1 Mems

6 STANs

5 STANs

6 STANs

7 STANs

7 STANs

1 STANs
1 STANs
2 ANYs
3 MEMs
512-point
accelerator
1 STANs

1 STANs
1 STANs
2 ANYs
3 MEMs
512-point
accelerator
1 STANs

1 STANs
1 STANs
2 ANYs
3 MEMs
1024-point
accelerator
1 STANs

1 STANs
1 STANs
2 ANYs
3 MEMs
1024-point
accelerator
1 STANs

1 STANs
1 STANs
2 ANYs
3 MEMs
512-point
accelerator
1 STANs

1 STANs
1 STANs
2 ANYs
3 MEMs
1024-point
accelerator
1 STANs

1 MEMs
1 STANs

1 MEMs
1 STANs

1 MEMs
1 STANs

1 MEMs
1 STANs

1 MEMs
1 STANs

1 MEMs
1 STANs

1 STANs
1024-point
accelerator
1 MEMs

1 STANs
1024-point
accelerator
1 MEMs

1 STANs
1024-point
accelerator
1 MEMs

1 STANs
1024-point
accelerator
1 MEMs

1 STANs
1024-point
accelerator
1 MEMs

1 STANs
1024-point
accelerator
1 MEMs

Note 1: Linear filters resource reference to wimax PC8530 decimation filters implementation.
Note 2: For 2048 point FFT, theres not directly accelerator, 3MEMs 1 STANs and 2 ANYs and 1024 point
HW accelerator are need. For 1536 point FFT, 3MEMs 1 STANs and 2 ANYs and 512 point HW accelerator
are need.

References
1.

TS 36.211 v8.2.0 2007-11

2.

R1-060998 E-UTRA Random Access Preamble Design, Ericsson, RAN WG1 #44bis, Athens, Greece,
27-31 March 2006

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3.

R1-062306 RACH Sequence Extension Methods for Large Cell deployment, LGE, RAN WG1 #46,
th
st
Tallinn, Estonia, 28 Auguest-1 September 2006

4.

R1-051073 Performance Comparison of Distributed FDMA and Localised FDMA with Frequency
th
th
Hopping for EUTRA Uplink, NEC Group, RAN WG1 #42bis, San Diego, USA, 10 -14 October 2005

5.

Digital Signal Processing Principles, Algorithms, and Applications, Fourth Edition, Jhon G. Proakis

6.

PC102 datasheet

7.

PC20x datasheet

5 Glossary
CP
DFT/IDFT
Es
Eb
FFT/IFF
LTE
No
RACH
OFDM

picoArray
PUCCH
PUSCH
QPSK
TU channel
Ts
ZC

Cyclic prefix
Fourier transform
energy per symbol
energy per bit
Fast Fourier transform/Inverse Fast Fourier transform
Long Term Evolution
Noise power spectral density
Random Access channel
Orthogonal Frequency Division Multiplexing
picoChip Designs Limited proprietary array processing architecture
Physical Uplink Control channel
Physical Uplink Shared channel
Quadrature Phase Shift Keying
Typical Urban channel
A number of time units Ts=1/(15000x2048) seconds
ZadChu

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