FinFET Current Mirror Design and Evaluation

Andrew Marshall (1), Mak Kulkarni (1), Mark Campise (3), Rinn Cleavelin (1),
Charvaka Duvvury (1), Harald Gossner (2), Michael Gostkowski (2,3),
Gerhard Knoblinger (2), Christian Pacha (2), Christian Russ (2), Klaus Schruefer (2),
Thomas Schulz (2,3), Klaus VonArnim (2), Bruce Wilks (3), Wade Xiong (1,3)
(1) Texas Instruments Inc., Dallas, TX, USA a-marshall jti.corn
(2) Infineon Technologies AG, Balanstrasse 73, D-81541 Munich, Germany
(3) ATDF Advanced Technology Development Facility, International SEMATECH, Austin, TX, USA

sidewalls and top of the silicon channel region, and

are usually constructed on thinner SOI. FinFETs
use the active region of the sidewalls. The top has
thicker oxide. FinFETs are usually narrower than
Tri-gate FETs. In this work, we have evaluated the
FinFET version of the MuGFET.
The starting material for making MuGFETs
and SOI MOS devices are silicon-on-insulator
(SOI) wafers. The thin silicon film is etched away,
while narrow fin(s) of silicon are remaining on top
of the isolation layer (buried oxide, BOx). Thin
gate oxides are either grown on both sidewalls of
the silicon fin creating a dual gate FinFET, or
additionally on the top of the fin to make a Tri-gate
FET device. A gate material (e.g. poly silicon or
metal) is deposited and structured by lithography so
that a narrow stripe is quasi 'wrapped' around the
silicon fin (figure 2). The gate material covers the
sidewalls and the top of the silicon fin thus
defining the total MOS channel width.

Abstract - With trends toward smaller geometries

and improved circuit performance continuing, an
option being investigated is multigate FETs on SOI
substrates. SOI lends itself to SOC systems due to
its inherently lower noise and ease of integration of
analog, digital, RF and power circuits. A critical
analog circuit requirement is accurate current
mirroring. Here characteristics of Fully Depleted
FinFET current mirrors are presented. Silicon
FinFET current mirrors and their bulk planar
counterparts have similar performance and
matching; a vital requirement for analog circuitry
on this type of material.

I. Introduction
Multigate FET (MuGFET) is a highly
promising emerging technology for the 32nm
process node range and below [l]. MuGFET
devices on SOI are particularly appropriate for
system on a chip applications, as the oxide provides
good electrical isolation between circuit modules.
In addition, MuGFET provide continued favorable
MOS drive current scaling trends as compared to
bulk silicon. MuGFET devices allow suppression
of short channel effects (SCE) by use of advanced
fin-like device geometry (figure 1). SCE are
normally seen in bulk CMOS, planar devices or in
partially depleted SOI devices. The suppression of
SCE becomes possible in MuGFETs due to the
fully depleted body where the depletion region
entirely fills the body region with the consequence
that no free charge carriers are available. We have
observed 90nm gate length MuGFET transistors
with very high MOS drive currents of typically 600
to 800uA/um for Vd=1.2V at significantly reduced
loff (-I OOX a similar performing planar device).
MuGFET is a general term for Triple-gate
FET (Tri-gate FETs) and Double-gate FET
(FinFETs). Tri-gate FETs make use of the

0-7803-9516-6/05/$20.00 2005 IEEE

Si3N,
sio2

uSi

Figure 1: 3-D visualization of a multigate device.

top gate
eIef_troJe

H1-~FIN ~

~ ~

WFIN
_

BOX
side gate electrodes

Figure 2: Visualization and TEM of a MuGFETfin.

187

Figures 3 and 4 show SEMs of the Fins,

from a plan view and angle.

1 um and Sum length NMOS and PMOS

FinFET current mirrors were made (figure 5). Each
device is 50 fins wide, and these each occupy I Oum
linear width. These are adjacent with dummy
transistors at each end of the array [3].

Figure 3: SEM of FinFET, showing fins and poly

gate.
Figure 6: Layout of the lum FinFETs. Gates are
brought out at the top, sources to the right and
drains to the left. Dummy devices flank the active.

The layout is shown in figure 6, indicating

the dummy structures to the left and right of the
array, and showing the fin placement. This is a
typical semi-precision layout for current mirrors,
where accuracy between stages of a few percentage
points is acceptable. Higher precision structures
may include cross coupling of structures.

Figure 4: SEM plan views of FinFET.

Current Mirrors - lum

Good NMOS matching (better than 2.5%)
is observed for most of the current range, for all
supply voltages, except at higher currents, where
the mirror operates outside the linear region. Figure
7 shows measured NMOS matching and figure 8
shows extracted spice simulations of I um devices.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

I~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Figure 5: Schematic of the FinFET current mirror

showing input or reference transistor and five
adjacent output or mirror devices.

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aU

In the past the various forms of SOI have

been shown to be useful for digital and some
analog applications. However, FinFETs offer some
new challenges and questions. Recent work has
validated the effectiveness of FinFETs for digital
circuits. Analog circuits have been built using
FinFETs also [2], and here we here investigate
current mirror matching.

Mirror

Current Mirrors

Voltages

Current Mirrors

1.2
i.0 0.8-

00 2,v
U1 0.4v

Iua)
U
4.

o30, 8v

0.2-0.0

1 2 345
AuA

12 3 45
SuA

12 3 45
lOuA

12 3 45

1OOuA

Site
U/P Current

Figure 7: J um length NMOS Current mirror ratios,

varying input current and output voltages, as a
function of the site distancefrom the reference.

188

Mirror
Volages

Current Mirrors

1.2

I O02vI

1.0
0

08
0.6

0.86v

:0

0.4

0.2
0.0

Ov

1 2 3 45
SuA

1 2 3 45
luA

1 2 3 4 5 Site
lOOuA UP Current

1 2 345

1kuA

Figure 8: Spice simulation of lum length NMOS

Current mirror ratios, varying input current.

Figure

Figures 7 and 8 match for moderate mirror

conditions, but diverge at high current, indicating
saturation current mismatch between silicon and
model. Similar performance is seen for PMOS
devices (figure 9). Matching and leakage are also
shown for the l um current mirrors in figures 10-13.

1: l um length PMOS current mirror

matching (Vds=0.5, Id= IOuA)

Current Mirrors - leakage - NMOS

21. OQE2
C

co.

5-

1.5.OE4-23
1O.OOE42-

s...

,..s...,..........

SSSS

O.OOE+00

._ S S.S-SS'SSS''.s
_.-..ss s.S -s o _ s

..s..ss

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ssss.''
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S 'S'

.....~~~~~~~~.......

3
ste

Figure 12: lum NMOS leakage matching

Current Mirrors - leakage - PMOS
7. OOE40O
6. OOE4O

Figure 9: lum length, PMOS current mirror ratios,

varying input current and output voltages, as a
function of the site distance from the reference.

3 WOOE
D

Current Mirrors - nmtching - NMOS

i:- :->> . ... .... ...

s.Ss,s,s s,,,s,.,s....~~~~~~~........... .: s

_>-.:

:>

> :::- : :S . . : i

...............................................

OOE+OOfS:

............:..''S:S
_
-.::::..S':

:,.::S.:S':_

S S..f-:f': .'S S_

site

1.04E+00

o1O02E+00
1:>:S:>0. L .. .>:..... .....-:i:>>:::>.>...
> >:

:-

:.>e:

.-.;:....>X :. .

>.

>

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>

Figure 13: lum PMOS leakage matching

9.80E-01

By contrast to figure 11, where PMOS

matching in silicon depends on reference device
proximity, simulation does not show variability
(figure 14). However, it has an average current
ratio from reference to output of 99%, the
difference attributed to gate leakage. This is similar
to the closest proximity PMOS (site 1, figure 11).

9.60E-.Ol

9.40E-01

7oOEq
s,:,.,s,,s.sS.

u~~~~~~~~~~~~~~~~~~~~~~~~~~
_..i:i: _:

3
site

Figure 10: lum length NMOS current mirror

matching (Vds=0.5, Id=1OuA)

189

Current Mirrors - matching: PMOS -1 um

Current Mirrors - PMOS

UXP

1 .00

1.20E+00
1.OOE+00nO2

.20.99

8.ODE-OlmO4
'R' SSRSRSS
4.0-1[Im
6.EDDE-Ol

0.98-

0.97
1

Site

4 OOE-01
O.OOE+00OO

Figure 14: lum PMOS leakage matching from

Spice simulations. As would be expected, there is
no variation in input to output current ratio in this

v.

g"

..

,,.,

00.6v

1O 10u

l uA

5 uA

lO uA

lOOuA

Figure 16: Sum length PMOS Current mirror

ratios, varying input current and output voltages,
as a function of the site distance from the
reference.

case

Current Mirrors - 5um

Surprisingly, matching for the Sum gate
length structures was inferior to that observed for
the lum gate lengths, at approximately 8%. This
was traced to fin loss due to the longer channel
length. Process modifications are aimed at fixing
this problem. As with the shorter current mirrors,
matching is retained over all the supply voltages,
except for higher currents (figures 15 and 16).

Conclusions
We have demonstrated that current
capabilities on semi-precision current mirrors built
on FinFET technology are in line with those of
bulk material, despite the added complexity of the
MuGFET process. Correlation with spice models
has been shown in the linear region of operation.

References
[1] X. Huang, et-al, "Sub-50nm FinFET:PMOS," IEDM
Tech Digest, Dec 1999
[2] G. Knoblinger et.al., "Design and Evaluation of Basic
Analog Circuit in an Emerging MuGFET Technology",
IEEE SOI Conference, Oct 4-6, 2005

[3] A. Marshall, "Circuit Design Techniques in SOI",

Tutorial, presented at Custom Integrated Circuits
Conference, September 2005, San Jose, CA
Figure 15: Sum length NMOS Current mirror
ratios, varying input current and output voltages,
as afunction of the site distance from the
reference.

190