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Microprocessor Design

Project One Report for ECE 480


Digital Systems Design

Submitted by
Taylor Wilson
11279131
Domicia Herring
11411483
JLen Dowdy
11385824

Department of Electrical and Computer Engineering


The University of Alabama
Tuscaloosa, Alabama 35487

November 3, 2016

ABSTRACT

The purpose of this project was to design, simulate, and test a simple
microprocessor design that could perform several instructions using the Quartus II VHDL
software. The design was programmed using VHDL and Verilog on the provided Altera
Cyclone II FPGA boards. There were complications with instantiating the memory needed
to store the ram and establishing the signals needed to display the range of the project and
fully understanding the errors in order to debug. Despite that, the project was able to
execute the basic functions involving the register and address demonstrations.

Introduction
The purpose of this project was to design, simulate, and test a simple microprocessor
design. The microprocessor, also known as the Central Processing Unit (CPU), is the brain of all
computers and many household and electronic devices. The microprocessor is a clock
driven, register based, programmable electronic device. It accepts digital/binary data as inputs
and processes it accordingly to instructions stored in its memory and provides results as an
output. The design was programmed using VHDL and Verilog on the provided Altera Cyclone II
FPGA boards.
Microprocessor Design
For this project, a microprocessor was designed using the instructions specified in
Appendix A. The memory for the microprocessor in this project, including the instructions and
data, is 1024 X 16. In total, the microprocessor contains 32 instructions, 16 of them being
predefined and 16 instructions of our choice. For the clock signal, if SW[9] is equal to 0, then
the clock source for the microprocessor is set to 12.5 MHz, created by a clock divider
component. If SW[9] is equal to 1, then the clock source is set to the KEY[0] pushbutton. The
KEY[0] pushbutton act as a single step clock source. KEY[1] is set to reset the microprocessor.
To verify our design, we used a SignalTap II Logic Analyzer. Using as 50 MHz clock
source as the sampling clock, a sufficient signal was produced to verify the design. The signals
displayed are the program counter, instruction register, data to/from memory, active clock, and,
registers R[0] and R[1] which can be found in Appendix G.
Next, we created an assembly language program that used a bubble sort algorithm to sort
a list of data values in memory. To verify the result, we used the in-System Memory Content
Editor. The second assembly language program was created to delay loop and the LEDS

LEDR[7..0] to implement a rotating lights that rotate at a rate of 10 Hz. The state of SW[0]
affects the direction of the light. If SW[0] is equal to 0 the lights rotate left and if SW[0] is equal
to 1 the lights rotate right. While LEDs are rotating, the microprocessor can also be executing
any assembly language program that is provided.
The code implemented for this design can be found in Appendix B. The simulation via
Model Sim can be found in Appendix C. The RTL viewer, Technology Map Viewer, Fitter
Report, SignalTap II Logic Analyzer Simulation, MIF bubble Sort, and MIF Rotating Light can
be found in Appendix D, E, F, G, H, and I respectively.

The Fitter Report


The fitter report details device usage parameters and utilization. For the designated code
presented in this project, ALMs were used which compromised of the total. There was a low
packing difficulty . logic registers were used compromising completely of the primary
registers.

% of the I/O pins were making up .

memory bits and

RAM blocks were used.

Results
There were several issues we ran into while trying to implement the micro-computer. One
major issue was trying to correctly instantiate the memory needed to store the ram. Our original
approach was to implement a bi-directional dual port ram. However, the In-System Memory
Content Editor only allows for mega function instantiations for single-port rams.
The next issue was trying to adequately establish the signals needed to display the range
of the project and fully understand the errors in order to debug. This was very time-consuming
and impacted the overall quality of the project. The machine language programs were also a

challenge in attempt to convert them to MIF files. In conclusion, the project was able to execute
the basic functions involving the register and address demonstrations.
Conclusion
This project allowed us to use our knowledge acquired from the lectures to design and
simulate a simple microprocessor design. Overall, the project was able to execute the basic
functions involving the register and address demonstrations.

Appendix A Instructions

Instruction
ADD R[REG], ADDRESS
STR R[REG], ADDRESS
LDR R[REG], ADDRESS
JMP ADDRESS
JN R[REG], ADDRESS
SUB R[REG], ADDRESS
INC R[REG]
OR R[REG], ADDRESS
AND R[REG], ADDRESS
NOT R[REG]
JP R[REG], ADDRESS
JZ R[REG], ADDRESS
SHL R[REG]
SHR R[REG]
IN R[REG]
OUT R[REG]

Function
R[REG] R[REG] + contents of ADDRESS
ADDRESS R[REG]
R[REG] contents of ADDRESS
PC <- ADDRESS
IF R[REG]<0 THEN PC ADDRESS
R[REG] R[REG] - contents of ADDRESS
R[REG] R[REG] + 1
R[REG] R[REG] OR contents of ADDRESS
R[REG] R[REG] AND contents of ADDRESS
R[REG] R[REG]
IF R[REG]>0 THEN PC ADDRESS
IF R[REG]=0 THEN PC ADDRESS
R[REG] R[REG] shifted left by one
R[REG] R[REG] shifted right by one
R[REG][7..0] SW[7..0]
LEDR[7..0] R[REG][7..0]

Opcode
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

Appendix B Microprocessor Code

Appendix C ModelSim simulation

Appendix D RTL viewer

Appendix E - Technology Map Viewer

Appendix F- Fitter Report

10

Appendix G - SignalTap II Logic Analyzer

11

Appendix H - MIF bubble Sort

12

Appendix I - MIF Rotating Light

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