Analog and Digital Electronics (Ade) Lab Manual by Prof. Kavya M. P. (SGBIT, BELAGAVI)

S. S.
Education Trusts
S.G. BALEKUNDRI INSTITUTE OF TECHNOLOGY

Shivabasavanagar, Belagavi.
Analog and Digital Electronics

Laboratory Manual
(15CSL37)
Staff-in-charge
Prof. Kavya M. P.
HoD , Dept. of CSE
List of Experiments
Sl. No.
Laboratory Experiments
Page No.
Laboratory session-1: Write-upon analog components; functional

block diagram, Pin diagram (if any), waveforms and description.
Laboratory session-2: Write-upon Logic design components, pin

diagram (if any), Timing diagrams, etc.
a) Design and construct a Schmitt trigger using Op-Amp for given

UTP and LTP values and demonstrate its working.
12
b) Design and implement a Schmitt trigger using Op-Amp using a

simulation package for two sets of UTP and LTP values and
demonstrate its working.
15
a) Design and construct a rectangular waveform generator (Op-Amp

relaxation oscillator) for given frequency and demonstrate its
working.
17
b) Design and implement a rectangular waveform generator (OpAmp relaxation oscillator) using a simulation package and
demonstrate the change in frequency when all resistor values are
doubled.
19
3.
Design and implement an Astable multivibrator circuit using 555

timer for a given frequency and duty cycle.
21
4.
Design and implement Half adder, Full Adder, Half Subtractor, Full
Subtractor using basic gates.
24
5.
a) Given a 4-variable logic expression, simplify it using Entered

Variable Map and realize the simplified logic expression using 8:1
multiplexer IC.
31
b) Design and develop the Verilog /VHDL code for an 8:1

multiplexer. Simulate and verify its working.
34
1.
2.
6.
Design and implement code converter I) Binary to Gray II) Gray to

Binary Code using basic gates.
36
7.
Design and verify the Truth Table of 3-bit Parity Generator and 4-bit
Parity Checker using basic Logic Gates with an even parity bit.
41
8.
a) Realize a J-K Master / Slave Flip-Flop using NAND gates and verify
its truth table.
45
b) Design and develop the Verilog / VHDL code for D Flip-Flop with
positive-edge triggering. Simulate and verify its working.
48
a) Design and implement a mod-n (n<8) synchronous up counter

using J-K Flip-Flop ICs and demonstrate its working.
50
b) Design and develop the Verilog / VHDL code for mod-8 up

counter. Simulate and verify its working.
55
10.
Design and implement an asynchronous counter using decade

counter IC to count up from 0 to n (n<=9) and demonstrate on 7segment display (using IC-7447).
57
11.
Study experiment
To study 4-bitALU using IC-74181.
61
Appendix
63
9.
List of Figures
Sl No.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
Figures
Basic analog components
Resistors of different value
Resistor
Different types of Inductors
Different types of capacitors
Types of Diode
Different types of Transistor
Op-Amp IC
555 Timer IC
Circuit Diagram of Schmitt Trigger Circuit
CRO in DUAL mode
CRO in X-Y mode showing the Hysteresis curve
Snapshot of Schmitt trigger in Multisim for UTP=4V and LTP= 2V
Simulation waveform of Schmitt trigger Circuit when UTP=4V and
LTP= 2V.
Snapshot of Schmitt trigger in Multisim for UTP=+2V and LTP= -2V
Simulation waveform of Schmitt trigger Circuit when UTP=+2V and
LTP= -2V
Circuit Diagram of Relaxation Oscillator
Output waveform of Relaxation oscillator
Snapshot of Relaxation Oscillator Circuit in Multisim
Simulation of Relaxation Oscillator in Multisim
Snapshot of Relaxation Oscillator Circuit in Multisim
Simulation of Relaxation Oscillator in Multisim
Circuit Diagram of Astable Multivibrator
Waveform of Astable multivibrator
IC diagram of 74151
Implementation of expression using 8:1 Mux
8:1 Mux
Snapshot of 8:1 Mux Simulation Input
Snapshot of 8:1 Mux Simulation Output
Logic Circuit of J/K Master-Slave flip-flop with Preset and Clear
Logic Symbol
Page
No.
1
2
3
4
5
6
7
7
8
13
13
14
15
15
16
16
18
18
19
19
20
20
22
23
31
33
34
35
25
45
45
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
Circuit diagram of J/K Flip-Flop

D Flip-Flop
Snapshot of D-Flip Flop Simulation Input
Snapshot of D-Flip Flop Simulation Output
IC 7476
IC 7408
MOD 8 Counter
Snapshot of Mod 8 Counter Simulation Input
Snapshot of Mod 8 Counter Simulation Output
IC 7490
IC 7447
Circuit Diagram of Asynchronous Mod- 10 Counter with 7-Segment
display
Timing diagram of Mod 10 counter
Circuit Diagram of Asynchronous Mod- 5 Counter with 7-Segment
display
Timing diagram of Mod 5 counter
Functional representation of IC-74181
46
48
48
49
50
51
55
56
56
57
57
58
59
59
60
61
List of tables
Sl No.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
Figures
4 band color code for resistor
Details of Logic ICs
Truth Table for Half Adder
Truth Table for Full Adder
Truth Table for Half subtractor
Truth Table for Full subtractor
Rules for entering values in a MEV K-map
MEV map entry
Truth Table for 8:1 MUX
Truth Table for Binary to Gray Converter
Truth Table for gray to binary Converter
Truth table of Parity Generator
Truth table of Parity Error Checker
Function Table for JK-FF
Function table of JK flip flop
State Table of Modulo-5 counter
Truth table of Mod 8 counter
Function Table of Decade counter
Function Table of Decade counter
Truth table of 75181
Page
No.
2
10
25
26
28
29
31
32
34
37
39
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51
52
55
58
59
61
Analog and Digital Electronics Laboratory Manual
Laboratory Session 1
Write-upon analog components; functional block diagram, Pin diagram (if
any), waveforms and description.
Analog components are electronic components with a continuously variable
signal, in contrast to digital components where signals usually take only two levels. The
term "analog" describes the proportional relationship between a signal and a voltage or
current that represents the signal. The word analog is derived from the Greek word
(analogos) meaning "proportional".
Basic analog components are,
Resistor
Inductor
Capacitor
Diode (PN Junction)
Bipolar Junction Transistor(BJT)
Operational Amplifier (Op-Amp)
555 Timer IC
Figure 1: Basic analog components
Prof. Kavya M. P., SGBIT, Belagavi
Page 1
Resistor
A resistor is a passive two-terminal electrical component that implements electrical
resistance as a circuit element. In electronic circuits, resistors are used to reduce
current flow, adjust signal levels, to divide voltages, bias active elements, and terminate
transmission lines, among other uses.
Figure 2: Resistors of different value
Components are coded are with colors to identify their value

Table 1: 4 band color code for resistor
Page 2
Figure 3: Resistor
Example 1:
A resistor colored Yellow-Violet-Orange-Gold would be 47 k with a tolerance of +/5%.

Example 2:
A resistor colored Green-Red-Gold-Silver would be 5.2 with a tolerance of +/- 10%.

Applications of Resistor: Resistors may be used to reduce current flow, and, at the
same time, may act to lower voltage levels within circuits. They are used in devices
like,
Lightbulb
Fuse
Voltmeter
Inductor
An inductor is a passive electronic component that stores energy in the form of a
magnetic field. In its simplest form, an inductor consists of a wire loop or coil. The
inductance is directly proportional to the number of turns in the coil. Inductance also
depends on the radius of the coil and on the type of material around which the coil is
wound.
Page 3
Figure 4: Different types of Inductors
For a given coil radius and number of turns, air cores result in the least inductance.
Materials such as wood, glass, and plastic - known as dielectric materials - are
essentially the same as air for the purposes of inductor winding. Ferromagnetic
substances such as iron, laminated iron, and powdered iron increase the inductance
obtainable with a coil having a given number of turns. In some cases, this increase is on
the order of thousands of times. The shape of the core is also significant. To roidal
(donut-shaped) cores provide more inductance, for a given core material and number of
turns, than solenoidal (rod-shaped) cores.
The standard unit of inductance is the henry, abbreviated H. This is a large unit. More
common units are the microhenry, abbreviated H (1 H =10-6H) and the millihenry,
abbreviated mH (1 mH =10-3 H). Occasionally, the nanohenry (nH) is used (1 nH = 10-9
H).
It is difficult to fabricate inductors onto integrated circuit (IC) chips. Fortunately,
resistors can be substituted for inductors in most microcircuit applications. In some
cases, inductance can be simulated by simple electronic circuits using transistors,
resistors, and capacitors fabricated onto IC chips.
Inductors are used with capacitors in various wireless communications applications. An
inductor connected in series or parallel with a capacitor can provide discrimination
against unwanted signals. Large inductors are used in the power supplies of electronic
equipment of all types, including computers and their peripherals. In these systems, the
inductors help to smooth out the rectified utility AC, providing pure, battery-like DC.
Capacitor
The capacitor is a component which has the ability or capacity to store energy in the
form of an electrical charge producing a potential difference (Static Voltage) across its
plates, much like a small rechargeable battery.
Page 4
Figure 5: Different types of capacitors
There are many different kinds of capacitors available from very small capacitor beads
used in resonance circuits to large power factor correction capacitors, but they all do
the same thing, they store charge.
In its basic form, a capacitor consists of two or more parallel conductive (metal) plates
which are not connected or touching each other, but is electrically separated either by
air or by some form of a good insulating material such as waxed paper, mica, ceramic,
plastic or some form of a liquid gel as used in electrolytic capacitors. The insulating
layer between capacitors plates is commonly called the Dielectric.
Due to this insulating layer, DC current can not flow through the capacitor as it blocks it
allowing instead a voltage to be present across the plates in the form of an electrical
charge.
The conductive metal plates of a capacitor can be square, circular or rectangular, or they
can be of a cylindrical or spherical shape with the general shape, size and construction
of a parallel plate capacitor depending on its application and voltage rating.
Diode
A diode is a specialized electronic component with two electrodes called the
anode and the cathode. Most diodes are made with semiconductor materials such as
silicon, germanium, or selenium. Some diodes are comprised of metal electrodes in a
chamber evacuated or filled with a pure elemental gas at low pressure. Diodes can be
Page 5
used as rectifiers, signal limiters, voltage regulators, switches, signal modulators, signal
mixers, signal demodulators, and oscillators.
Figure 6: Types of Diode
The fundamental property of a diode is its tendency to conduct electric current in

only one direction. When the cathode is negatively charged relative to the anode at a
voltage greater than a certain minimum called forward breakover, then current flows
through the diode. If the cathode is positive with respect to the anode, is at the same
voltage as the anode, or is negative by an amount less than the forward breakover
voltage, then the diode does not conduct current. This is a simplistic view, but is true for
diodes operating as rectifiers, switches, and limiters. The forward breakover voltage is
approximately six tenths of a volt (0.6 V) for silicon devices, 0.3 V for germanium
devices, and 1 V for selenium devices.
Transistor
A transistor is a device that regulates current or voltage flow and acts as a switch
or gate for electronic signals. Transistors consist of three layers of a semiconductor
material, each capable of carrying a current.
Page 6
Figure 7: Different types of Transistor
The transistor was invented by three scientists at the Bell Laboratories in 1947,
and it rapidly replaced the vacuum tube as an electronic signal regulator. A transistor
regulates current or voltage flow and acts as a switch or gate for electronic signals. A
transistor consists of three layers of a semiconductor material, each capable of carrying
a current. A semiconductor is a material such as germanium and silicon that conducts
electricity in a "semi-enthusiastic" way. It's somewhere between a real conductor such
as copper and an insulator (like the plastic wrapped around wires).
The semiconductor material is given special properties by a chemical process
called doping. The doping results in a material that either adds extra electrons to the
material (which is then called N-type for the extra negative charge carriers) or creates
"holes" in the material's crystal structure (which is then called P-type because it results
in more positive charge carriers). The transistor's three-layer structure contains an Ntype semiconductor layer sandwiched between P-type layers (a PNP configuration) or a
P-type layer between N-type layers (an NPN configuration).
Operational Amplifier(Op-Amp)
Operational amplifiers are linear devices that have all the properties required for
nearly ideal DC amplification and are therefore used extensively in signal conditioning,
filtering or to perform mathematical operations such as add, subtract, integration and
differentiation.
Figure 8: Op-Amp IC
Page 7
An Operational Amplifier, or op-amp for short, is fundamentally a voltage

amplifying device designed to be used with external feedback components such as
resistors and capacitors between its output and input terminals. These feedback
components determine the resulting function or operation of the amplifier and by
virtue of the different feedback configurations whether resistive, capacitive or both, the
amplifier can perform a variety of different operations, giving rise to its name of
Operational Amplifier.
An Operational Amplifier is basically a three-terminal device which consists of
two high impedance inputs, one called the Inverting Input, marked with a negative or
minus sign, ( ) and the other one called the Non-inverting Input, marked with a
positive or plus sign ( + ).
The third terminal represents the operational amplifiers output port which can
both sink and source either a voltage or a current. In a linear operational amplifier, the
output signal is the amplification factor, known as the amplifiers gain ( A ) multiplied by
the value of the input signal and depending on the nature of these input and output
signals, there can be four different classifications of operational amplifier gain.
555 Timer IC
The 555 timer IC was introduced in the year 1970 by Signetic Corporation and
gave the name SE/NE 555 timer. It is basically a monolithic timing circuit that
produces accurate and highly stable time delays or oscillation. When compared to the
applications of an op-amp in the same areas, the 555IC is also equally reliable and is
cheap in cost. Apart from its applications as a monostable multivibrator and astable
multivibrator, a 555 timer can also be used in dc-dc converters, digital logic probes,
waveform generators, analog frequency meters and tachometers, temperature
measurement and control devices, voltage regulators etc.
Figure 9: 555 Timer IC
Page 8
Laboratory Session 2
Write-upon Logic design components, pin diagram (if any), Timing
diagrams, etc.
A digital component is an electronic component which uses discrete, numerable
data and processes for all its operations. The alternative type of device is analog, which
uses continuous data and processes for any operations. Any device which uses a
computer of any sort in its operations is at least partially digital.
Logic gate
A logic gate is an elementary building block of a digital circuit. Most logic gates
have two inputs and one output. At any given moment, every terminal is in one of the
two binary conditions low (0) or high (1), represented by different voltage levels.
Different Types of gates are,
Basic gates- AND, OR and NOT
Universal Gates- NAND and NOR
Special Gates- XOR and XNOR
Page 9
Table 2: Details of Logic ICs
Sl
No
Logic
Gate
Logic
Function
Symbol of
each Gate
IC
Nam
e
quad 2input
AND gate
Y=A.B
7408
quad 2input OR
gate
Y=A+B
7432
hex
inverter
If A is
input, Y=A
7404
Pin Diagram
Truth table
1.
2.
3.
Page 10
4.
quad 2input
NAND
gate
Y=(A.B)
7400
quad 2input
NOR gate
Y=(A+B)
7402
quad 2input
XOR gate
Y=AB
7486
Y=(AB)
7426
6
5.
6.
7.
quad 2input
XNOR
gate
Page 11
Experiment 1
(a) Design and construct a Schmitt trigger using Op-Amp for given UTP and
LTP values and demonstrate its working.
(b) Design and implement a Schmitt trigger using Op-Amp using a
simulation package for two sets of UTP and LTP values and demonstrate its
working.
(a) Aim: To design and implement a Schmitt trigger circuit using op-amp for the given
UTP and LTP values.
Components Required: IC A 741, Resistors of 10K 100K, DC regulated power
supply, Signal generator, CRO.
Theory:
Schmitt Trigger converts an irregular shaped waveform to a square wave or
pulse. Here, the input voltage triggers the output voltage every time it exceeds certain
voltage levels called the upper threshold voltage VUTP and lower threshold voltage VLTP.
The input voltage is applied to the inverting input. Because the feedback voltage is
aiding the input voltage, the feedback is positive. A comparator using positive feedback
is usually called a Schmitt Trigger. Schmitt Trigger is used as a squaring circuit, in digital
circuitry, amplitude comparator, etc.
Design:
From theory of Schmitt trigger circuit using op-amp, we have the trip points,
R1Vref
RV
UTP
+ 2 sat whereVsat is the positive saturation of the opamp 90% of Vcc
R1 + R2 R1 + R2
& LTP
R1Vref
R1 + R2
R2Vsat
R1 + R2
Hence given the LTP & UTP values to find the R1 , R2 & Vref values, the following design is used.
UTP + LTP
UTP - LTP
Let Vsat
Let R2
2 R1Vref
R1 + R2
- - - - - -(1)
2 R1Vsat
- - - - - -(2)
R1 + R2
10V, UTP 4V & LTP 2V, then equation (2) yields R1

10 KW, then R1
9 R2
90 KW
From equation (1) we have Vref
(UTP + LTP)(R1 + R2 )
2 R1
3.33V
Page 12
Values
R1 =90K choose 100k, R2 =10k, Vref=3.33V
Example2: Vsat=10V, UTP=+2V and LTP=-2V

Procedure:
1. Before doing the connections, check all the components using millimeter.
2. Make the connection as shown in circuit diagram.
3. Using a signal generator apply the sinusoidal input waveform of peak-to-peak
amplitude of 10V, frequency 1 kHz.
4. Keep the CRO in dual mode; apply input (Vin) signal to the channel 1 and observe
the output (Vo) on channel 2 which is as shown in the waveform below. Note the
amplitude levels from the waveforms.
5. Now keep CRO in X-Y mode and observe the hysteresis curve.
Circuit Diagram:
Figure 10: Circuit Diagram of Schmitt Trigger Circuit
Waveforms:
Figure 11: CRO in DUAL mode
Page 13
Figure 12: CRO in X-Y mode showing the Hysteresis curve
Result:
Sinusoidal waveform is converted into square waveform using UTP and LTP values.
Page 14
(b) Aim: To design and implement a Schmitt trigger using Op-Amp using a
simulation package for two sets of UTP and LTP values and demonstrate its
working.
Components Required: Computer with Multisim Software.
i)
Vsat=10V, UTP=+4V and LTP=+2V
Figure 13: Snapshot of Schmitt trigger in Multisim for UTP=4V and LTP= 2V
Figure 14: Simulation waveform of Schmitt trigger Circuit when UTP=4V and LTP= 2V.
Page 15
ii)
Vsat=10V, UTP=+2V and LTP=-2V
Figure 15: Snapshot of Schmitt trigger in Multisim for UTP=+2V and LTP= -2V
Figure 16: Simulation waveform of Schmitt trigger Circuit when UTP=+2V and LTP= -2V
Result: Designed and implemented Schmitt trigger using Op-Amp using a simulation
package for two sets of UTP and LTP values and demonstrated its working.
Page 16
Experiment 2
a) Design and construct a rectangular waveform generator (Op-Amp
relaxation oscillator) for given frequency and demonstrate its working.
b) Design and implement a rectangular waveform generator (Op-Amp
relaxation oscillator) using a simulation package and demonstrate the
change in frequency when all resistor values are doubled.
(a) Aim: To design and implement a rectangular waveform generator for a given
frequency.
Components Required: Op-amp A 741, Resistors of 10k, 12 k, 4.7k/5.1k,
Capacitor of 0.1 F, Regulated DC power supply, CRO.
Theory:
Op-Amp Relaxation Oscillator is a simple Square wave generator which is also
called as a Free running oscillator or Astable multivibrator or Relaxation oscillator. In
this figure the op-amp operates in the saturation region. Here, a fraction (R2/(R1+R2))
of output is fed back to the noninverting input terminal. Thus reference voltage is
(R2/(R1+R2)) Vo. And may take values as +(R2/(R1+R2)) Vsat or - (R2/(R1+R2)) Vsat.
The output is also fed back to the inverting input terminal after integrating by means of
a low-pass RC combination. Thus whenever the voltage at inverting input terminal just
exceeds reference voltage, switching takes place resulting in a square wave output.
Design:
1+ b
The period of the output rectangular wave is given as T 2RC ln
------- (1)
1- b
R1
is the feedback fraction
Where, b
R1 + R2
If R2=1.16 R1, then T = 2RC ---------- (2)
Design for a frequency of 1 kHz
1
1
T
10 -3 1ms )
3
f
10
Let R1 = 10k, then R2 = 11.6k

Choose next a value of C and then calculate value of R from equation (2).
T
10 -3
5 KW
Let C=0.1F, then R
2C 2 10 -7
The voltage across the capacitor has a peak voltage of Vc
R1
V sat
R1 + R2
Page 17
Values
C=0.1F, R1 = 10k, R2 = 11.6 k choose 12K, R = 5k choose 4.7k/5.1k
Procedure:
1. Before making the connections check all the components using multimeter.
2. Make the connections as shown in figure and switch on the power supply.
3. Observe the voltage waveform across the capacitor on CRO.
4. Also observe the output waveform on CRO. Measure its amplitude and frequency.
Circuit Diagram:
Figure 17: Circuit Diagram of Relaxation Oscillator
Waveforms:
Figure 18: Output waveform of Relaxation oscillator
Result:
The Amplitude of the Oscillations= _________ V
The frequency of the oscillations = ___________ Hz.
Page 18
(b) Aim: Design and implement a rectangular waveform generator (Op-Amp

relaxation oscillator) using a simulation package and demonstrate the change in
frequency when all resistor values are doubled.
Components Required: Computer with Multisim Software.
Figure 19: Snapshot of Relaxation Oscillator Circuit in Multisim
Figure 20: Simulation of Relaxation Oscillator in Multisim
Time Period= 2 * 500 * 10-6 s

Frequency= (1/ Time Period)= (1/2 * 500 * 10-6 s) = 1KHz
Page 19
When resistor values are doubled,
Figure 21: Snapshot of Relaxation Oscillator Circuit in Multisim
Figure 22: Simulation of Relaxation Oscillator in Multisim
Time Period= 2 * 1*10-3 s

Frequency= (1/ Time Period)= (1/2 * 1*10-3 s) = 500 Hz.
Result: Designed and implemented rectangular waveform generator using a simulation
package and frequency reduces half the time when all resistor values are doubled.
Page 20
Experiment 3
Design and implement an Astable multivibrator circuit using 555 timer for a
given frequency and duty cycle.
Aim: To design and implement an astable multivibrator using 555 Timer for a given
frequency and duty cycle.
Components Required: 555 Timer IC, Resistors of 3.3K, 6.8K, Capacitors of 0.1 F,
0.01 F, Regulated power supply,CRO.
Theory:
Multivibrator is a form of oscillator, which has a non-sinusoidal output. The
output waveform is rectangular. The multivibrators are classified as: Astable or free
running multivibrator: It alternates automatically between two states (low and high for
a rectangular output) and remains in each state for a time dependent upon the circuit
constants. It is just an oscillator as it requires no external pulse for its operation.
Monostable or one shot multivibrator: It has one stable state and one quasi stable. The
application of an input pulse triggers the circuit time constants. After a period of time
determined by the time constant, the circuit returns to its initial stable state. The
process is repeated upon the application of each trigger pulse. Bistable Multivibrators: It
has both stable states. It requires the application of an external triggering pulse to
change the output from one state to other. After the output has changed its state, it
remains in that state until the application of next trigger pulse. Flip flop is an example.
Design:
Example 1: Frequency (f) = 1 KHz and Duty cycle = 60% (0.6)
The time period , T =1/f = 1ms = tH + tL
Where, tH is the time the output is high and
tL is the time the output is low.
From the theory of astable multivibrator using 555 Timer, we have
tL = 0.693 RB C
------(1)
tH = 0.693 (RA + RB)C
------(2)
T = tH + tL = 0.693 (RA +2 RB) C
Duty cycle = tH / T = 0.6.
Hence tH = 0.6T = 0.6ms and
tL = T tH = 0.4ms.
Let C=0.1F and substituting in the above equations,
RB = 5.8K (from equation 1) and RA = 2.9K (from equation 2 & RB values).
Page 21
The Vcc determines the upper and lower threshold voltages (observed from the
capacitor voltage waveform) as VUT 2 VCC & VLT 1 VCC .
3
Note: The duty cycle determined by RA & RB can vary only between 50 & 100%. If RA is
much smaller than RB, the duty cycle approaches 50%.
Values
C=0.1F, RA =2.9K choose 3.3K, RB = 5.8k choose 6.8K
Example 2: Frequency = 1 kHz and Duty cycle =75%

Circuit Diagram:
Figure 23: Circuit Diagram of Astable Multivibrator
Procedure:
1. Before making the connections, check the components using multimeter.
2. Make the connections as shown in figure and switch on the power supply.
3. Observe the capacitor voltage waveform at 6th pin of 555 timer on CRO.
4. Observe the output waveform at 3rd pin of 555 timer on CRO (shown below).
5. Note down the amplitude levels, time period and hence calculate duty cycle.
Page 22
Waveforms
Figure 24: Waveform of Astable multivibrator
Result:
The amplitude of the oscillations = _________________V
The Time Period of the oscillations = _______________s.
The frequency of the oscillations = _________________ Hz.
The Duty Cycle of the oscillations = ___________________
Page 23
Experiment 4
Design and implement Half adder, Full Adder, Half Subtractor, Full
Subtractor using basic gates.
Aim: To design and implement Half adder, Full Adder, Half Subtractor, Full Subtractor
using basic gates.
Components required: 7408, 7404, 7432, 7486, connecting wires and digital IC trainer
kit.
Theory:
Adders
An Adder is a device that can add two binary digits. There are two types of Adder.
One is Half Adder, and another one is known as Full Adder. There are two types of
Adders.
Half Adder
Full Adder
There are two inputs and two outputs in a Half Adder. Inputs are named as A and
B, and the outputs are named as Sum (S) and Carry (C). The Sum is X-OR of the input A,
and B. Carry is AND of the input A and B. With the help of half adder, one can design a
circuit that is capable of performing simple addition with the help of logic gates. The
main disadvantage of this circuit is that it can only add two inputs and if there is any
carry it is neglected. Thus, the process is incomplete. To overcome this difficulty Full
Adder is designed. While performing complex addition, there may be cases when you
have to add two 8 bit bytes together. This can be done with the help of Full Adder
The full adder is a little more difficult to implement than a half adder. The main
difference between a half adder and a full adder is that the full adder has three inputs
and two outputs. The two inputs are A B, and the third input is a carry input Cin. The
output carry is designated as Cout, and the normal output is designated as S.
Subtractors
Subtractor circuits take two binary numbers as input and subtract one binary
number input from the other binary number input. Similar to adders, it gives out two
outputs, difference and borrow (carry-in the case of Adder). There are two types of
subtractors.
Half Subtractor
Full Subtractor
Page 24
Half Subtractor is a combinational circuit that performs subtraction of two bits

and has two inputs and two outputs. The two inputs denoted by A and B represents
minuend and subtrahend. The two outputs are the difference D and the borrow bit B.
Full Subtractor is a combinational circuit capable of performing subtraction on
two bits namely minuend and subtrahend. It accepts three inputs: minuend, subtrahend
and a borrow bit. It produces two outputs: difference and borrow. The borrow output
tells whether the minuend bit needs to borrow a binary bit 1 from the next higher
minuend bit or not.
Design:
a) Half Adder:
Step 1: Write truth table of Half Adder.
Table 3: Truth Table for Half Adder
Inputs
A
0
0
1
1
B
0
1
0
1
Outputs
S
Cout
0
0
1
0
1
0
0
1
Step 2: Write logic equation for each output and simplify if possible.
Sum= AB+AB = AB
Cout= AB
Step 3: Implement the above logic equations using basic gates
Page 25
Step 4: Implement the above logic equations using special gates
b) Full Adder:
Step 1: Write truth table of Full Adder.
Table 4: Truth Table for Full Adder
Inputs
A
B
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Cin
0
1
0
1
0
1
0
1
Outputs
S
Cout
0
0
1
0
1
0
0
1
1
0
0
1
0
1
1
1
S = AB Cin +AB Cin+AB Cin+AB Cin
= Cin(AB+AB)+ Cin(AB+AB)
= Cin(AB)+ Cin(AB)
S = AB Cin
Cout = AB Cin+AB Cin+AB Cin+AB Cin
= Cin(AB+AB)+ AB(Cin+ Cin)
= Cin(AB) + AB (1)
Cout = Cin(AB) + AB
Page 26
Step 3: Implement the above logic equations using basic gates.
Step 4: Implement the above logic equations using special gates.
Page 27
c) Half Subtractor:
Step 1: Write truth table of Half Adder.
Table 5 : Truth Table for Half subtractor
Inputs
A
0
0
1
1
Outputs
B
0
1
0
1
D
0
1
1
0
B
0
1
0
0
D = AB+AB = AB
B = AB
Page 28
d) Full Subtractor:
Step 1: Write truth table of Full Adder.
Table 6 : Truth Table for Full subtractor
Inputs
A
B
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
B1
0
1
0
1
0
1
0
1
Outputs
D B2
0
0
1
1
1
1
0
1
1
0
0
0
0
0
1
1
D = AB B1 +AB B1+AB B1+AB B1
= B1 (AB+AB)+ B1(AB+AB)
= B1 (AB)+ B1(AB)
D = AB B1
B2 = AB B1+AB B1+AB B1+AB B1
= B1 (AB+AB)+ AB(B1+ B1)
= B1 (AB) + AB (1)
B2 = B1 (AB) + AB
Page 29
Step 3: Implement the above logic equations using basic gates.
Step 4: Implement the above logic equations using special gates.
Result: Adders and Subtractors are designed and verified using truth table.
Page 30
Experiment 5
a) Given a four variable expression, simplify using Entered Variable Map
(EVM) and realize the simplified logic using 8:1 MUX.
b) Design and develop the Verilog /VHDL code for an 8:1 multiplexer.
Simulate and verify its working.
(a) Aim: To simplify four variable expression using Entered Variable Map (EVM) and
realize the simplified logic using 8:1 MUX.
Components required: IC 74LS151, Patch chords, trainer kit.
Theory: The term multiplex means Many to one. A multiplexer (MUX) has n inputs.
Each line is used to shift digital data serially. The single output line.
Pin Diagram of IC 74LS151 :
Figure 25: IC diagram of 74151

Table 7: Rules for entering values in a MEV K-map
Rule No
1
2
MEV
Entry in MEV
Map
0
1
0
0
0
1
1
1
Comments
If function equals 0 for both values
of MEV, enter 0 in appropriate cell
of MEV Map
If function equals 1 for both values
of MEV, enter 1.
Page 31
3
4
5
6
7
8
9
0
1
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
1
x
x
x
0
0
x
x
1
1
x
If function equals MEV enter MEV

MEV
-----MEV
X
0
0
1
1
If the function is compliment of

MEV then enter complement of
MEV.
If function equals don't care for
both values of MEV, enter X
If f=X for MEV=0 and f=0 for
MEV=1, Enter 0.
If f=0 for MEV=0 and f= X for
MEV=l, Enter 0.
If f = X for MEV=0 and f = 1 for
MEV=1, Enter 1.
If f = 1 for MEV=0 and f = X for
MEV=X, Enter 1.
Design:
Example 1: f(a,b,c,d)=m(2,3,4,5,13,15)+d(8,9,10,11)
Table 8: MEV map entry
Decimal Values
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Binary Values
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
f
0
0
1
1
1
1
0
0
X
X
X
X
0
1
0
1
MEV map entry

0------Do
1------D1
1-----D2
0-----D3
X-----D4
X-----D5
d----D6
d----D7
Page 32
Circuit diagram:
Figure 26: Implementation of expression using 8:1 Mux
Example 2: f(a,b,c,d)=m(1,7,9,10,14)+d(0,4,5,6)(Solve and implement using 8:1 MUX)

Procedure:
1. Verify all components and patch chords whether they are in good condition or
not.
2. Make connection as shown in the circuit diagram.
3. Give supply to the trainer kit.
4. Provide input data to circuit via switches.
5. Verify truth table sequence and observe outputs.
Result:
Verified result according to Entered Variable Map for the given equation.
Page 33
(b)Aim: To design and develop the Verilog /VHDL code for an 8:1 multiplexer.
Components Required: Computer with Xilinx Software.
8 to 1 Multiplexer
Figure 27: 8:1 Mux

Table 9: Truth Table for 8:1 MUX
a
0
0
0
0
1
1
0
1
Inputs
b
0
0
1
1
0
0
1
1
c
0
1
0
1
0
1
1
1
Outputs
y
d0
d1
d2
d3
d4
d5
d6
d7
Page 34
-- Verilog code for 8 to 1 mux (Dataflow modeling).

module multiplexer(d0,d1,d2,d3,d4,d5,d6,d7,a,b,c,y );
input d0,d1,d2,d3,d4,d5,d6,d7 ;
input a,b,c;
output y;
assign y= ((~a&~b&~c&d0) |(~a&~b&c&d1) |(~a&b&~c&d2) |(~a&b&c&d3)
|(a&~b&~c&d4)|(a&~b&c&d5) |(a&b&~c&d6) |(a&b&c&d7 ));
endmodule
8:1 Mux Simulation Input
Figure 28: Snapshot of 8:1 Mux Simulation Input
8:1 Mux Simulation Output
Figure 29: Snapshot of 8:1 Mux Simulation Output
Result: Designed and developed VHDL code for an 8:1 multiplexer. Simulated and
verified its working.
Page 35
Experiment 6
Design and implement code converter
a)
Binary to Gray Code
b)
Gray to Binary Code
Using basic gates
Aim: To design and implement code converter a) Binary to Gray b) Gray to Binary
Code using basic gates
Components Required: 7408, 7404, 7432, 7486, Patch chords and digital IC trainer
kit.
Theory:
Binary Numbers is default way to store numbers, but in many applications binary
numbers are difficult to use and a variation of binary numbers is needed. This is
where
Gray
codes
are
very
useful.
Gray code has property that two successive numbers differ in only one bit because of
this property gray code does the cycling through various states with minimal effort
and used in K-maps, error correction, communication etc.
Binary to Gray conversion:
1. The Most Significant Bit (MSB) of the gray code is always equal to the MSB of the
given binary code.
2. Other bits of the output gray code can be obtained by XORing binary code bit at
that index and previous index.
Gray to binary conversion:
1. The Most Significant Bit (MSB) of the binary code is always equal to the MSB of
the given binary number.
2. Other bits of the output binary code can be obtained by checking gray code bit at
that index. If current gray code bit is 0, then copy previous binary code bit, else
copy invert of previous binary code bit
Page 36
Design:
a) Binary to Gray Converter
Step 1: Write truth table of Binary to Gray Converter
Table 10: Truth Table for Binary to Gray Converter
Inputs
B2 B1 B0
0
0 0
0
0 1
0
1 0
0
1 1
1
0 0
1
0 1
Outputs
G2 G1 G0
0 0 0
0 0 1
0 1 1
0 1 0
1 1 0
1 1 1
1
1
1
1
1
1
0
1
0
0
1
0
Logic Equation of G2
G2 =B2
G1 = B2B1+ B2 B1
G1 = B 2 B1
Page 37
G0 = B1B0 +B1B0
G0 = B 1 B0
Page 38
b) Gray to Binary Converter

Step 1: Write truth table of Binary to gray Converter
Table 11: Truth Table for gray to binary Converter
G2
0
0
0
0
1
1
1
1
Inputs
G1 G0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Outputs
B2 B1 B0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
1
0
1
0
0
1
0
1
Logic Equation of B2
B2 = G2
Logic Equation of B1
B1 = G2G1+ G2 G1
B1 = G2 G1
Page 39
B0 = G2 G1G0 +G2 G1 G0+ G2 G1G0 +G2 G1 G0

B0 = G2(G1G0+ G1G0)+ G2(G1 G0+ G1 G0)
B0 = G2(G1+ G0) + G2 (G1+ G0)
B0 = G2G1 G0
Result: Binary to Gray and Gray to Binary converters are designed and verified using
truth table
Page 40
Experiment 7
Design and verify the Truth Table of 3-bit Parity Generator and 4-bit
Parity Checker using basic Logic Gates with an even parity bit.
Aim: To design and verify the Truth Table of 3-bit Parity Generator and 4-bit Parity
Checker using basic Logic Gates with an even parity bit.
Components required: 7408, 7404, 7432, 7486, connecting wires and digital IC
trainer kit.
Theory:
A parity bit is used for the purpose of detecting errors during transmission of
binary information. A parity bit is an extra bit included with a binary message to
make the number of 1s either odd or even. The message including the parity bit is
transmitted and then checked at the receiving end for errors. An error is detected if
the checked parity does not correspond with the one transmitted. The circuit that
generates the parity bit in the transmitter is called a parity generator and the circuit
that checks the parity in the receiver is called a parity checker.
In even parity the added parity bit will make the total number of 1s an even
amount and in odd parity the added parity bit will make the total number of 1s an
odd amount. In a three bit odd parity generator the three bits in the message
together with the parity bit are transmitted to their destination, where they are
applied to the parity checker circuit. The parity checker circuit checks for possible
errors in the transmission.
Since the information was transmitted with odd parity the four bits received
must have an odd number of 1s. An error occurs during the transmission if the four
bits received have an even number of 1s, indicating that one bit has changed during
transmission. The output of the parity checker is denoted by PEC (parity error
check) and it will be equal to 1 if an error occurs, i.e., if the four bits received has an
even number of 1s
Page 41
Design:
a) 3-bit Parity Generator
Step 1: Write truth table of Parity Generator
Table 12: Truth table of Parity Generator
B2
0
0
0
0
1
1
1
1
Inputs
B1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
Output
P
0
1
1
0
1
0
0
1
Step 2: Write logic equation for output and simplify if possible.
P=B2B1 B0 +B2B1 B0+B2B1B0+ B2 B1B0

P= B2 (B1 B0+ B1B0) + B2 (B1 B0+ B1B0)
P= B2 B1 B0
Page 42
b) 4-bit Parity checker

Step 1: Write truth table of 4-bit Parity checker
Table13: Truth table of Parity Error Checker
B2
Inputs
B1 B0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Output
Parity Error
Check (PEC)
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
Page 43
Step 2: Write logic equation for output and simplify if possible.
PEC=B2B1B0P
Result: 3-bit Parity Generator and 4-bit Parity Checker are designed using basic
gates and also using special gates and verified using truth table.
Page 44
Experiment 8
a) Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its
truth table.
b) Design and develop the Verilog / VHDL code for D Flip-Flop with positiveedge triggering. Simulate and verify its working.
(a) Aim: To realize a J-K Master / Slave Flip-Flop using NAND gates and to verify its
truth table
Components used: 7400, 7410, 7420, Patch chords and trainer kit.
Theory:
A cascade of two S-R FLIP-FLOPS is a master-slave J-K FLIP-FLOP. One of them is
termed as Master and the other one is slave. Figure 30 demonstrates the logic circuit. The
master is positively clocked. Because of the presence of inverter, here the slave is negatively
clocked. It means that when clock is high, the slave is inactive and the master is active.
Figure 30: Logic Circuit of J/K Master-Slave flip-flop with Preset and Clear
Figure 31: Logic Symbol
Page 45
While the clock is low, the slave is active and the master is inactive. Figure 31 demonstrates
the symbol. It is a level clocked Flip-Flop. As clock is high, any changes there in J and K
inputs can influence S and R outputs. Thus, J and K are kept constant throughout positive half
of clock. As clock is low, the master is inactive and also J and K inputs can be permitted to
be changed. The dissimilar conditions are Set, Reset and Toggle. The race condition is
ignored due to feedback from slave to master and the slave being inactive throughout positive
half of clock.
(i) SET State: Suppose that Q is low and Q is high. For high J, low K and high CLK, the
Master goes to SET state providing High S and Low R. As Slave is inactive, Q and Q do not
change. While CLK is Low, the Slave becomes to Set state providing High Q and low Q.
(ii) RESET State: At the ending of Set State Q is High and Q low. Here if J is low, K is high
and CLK is high, the Master Resets providing Low S and High R. Q and Q do not change
since Slave is inactive. While CLK becomes Low, the Slave changes active and resets
providing Low Q and High Q.
(iii) Toggle State: The Slave copies the Master, if both J and K are high. While CLK is High,
the Master toggles once. After that the Slave toggles once when CLK is low. If the Master
toggles in Set state, the slave copies the Master and toggles in Set state. If the Master toggles
in Reset state, the slave again copies the Master and toggles in Reset state. Because the
second FLIP-FLOP only follows the first one, this is termed to as the slave and the first one
as the master. Therefore, this configuration is termed to as master- slave (M-S) FLIP-FLOP.
JK Master Slave Flip-Flop Truth Table shows that a Low PR and Low CLR can cause race
condition. Therefore, PR and CLR are kept High when inactive. To clear, we make CLR Low
and to preset we make PR Low. In both cases we change them to High while the system is to
be run. Low J and Low K make inactive state irrespective of clock input. the next clock pulse
resets the Flip-Flop, if K goes High. If J goes High through itself, the subsequent clock pulse
sets the Flip-Flop. While both J and K are High, all clock pulse generates one toggle.
Circuit Diagram:
Figure 32: Circuit diagram of J/K Flip-Flop

Page 46
Pin Details of the ICs:

7400
7410
Table 14: Function Table for JK-FF
Procedure:
1. Verify all components and patch chords whether they are in good condition or not.
2. Make connection s shown in the circuit diagram.
4. Provide input data to circuit via switches.
5. Verify truth table sequence and observe outputs.
Result: J-K Master/Slave Flip-Flop is realized using NAND gates and verified using truth
table.
Page 47
(b) Aim: To design and develop the Verilog / VHDL code for D Flip-Flop with positiveedge triggering and to Simulate and verify its working.
Circuit diagram
Figure 33: D Flip-Flop
--Verilog code for D Flip Flop

module dflipflop(d,clk,q, qbar);
input d;
input clk;
output q,qbar;
reg q,qbar;
always @(posedge clk)
begin
q<=d;
qbar<=~d;
end
endmodule
D-Flip Flop Simulation Input
Figure 34: Snapshot of D-Flip Flop Simulation Input

Page 48
D-Flip Flop Simulation Output
Figure 35: Snapshot of D-Flip Flop Simulation Output
Result: Designed and developed the VHDL code for D Flip-Flop with positive-edge
triggering. Simulated and verified its working.
Page 49
Experiment 9
a) Design and implement a mod-n (n<8) synchronous up counter using J-K
Flip-Flop ICs and demonstrate its working.
b) Design and develop the Verilog / VHDL code for mod-8 up counter.
(a)Aim: To design and implement a mod-n (n<8) synchronous up counter using J-K
Flip-Flop ICs and to demonstrate its working.
Components used: 7476-2, 7408, connecting wires and trainer kit.
Theory:
The counters which use clock signal to change their transition are called Synchronous
counters. This means the synchronous counters depends on their clock input to change state
values. In synchronous counters, all flip flops are connected to the same clock signal and all
flip flops will trigger at the same time.
The 4 bit up counter is designed by using JK flip flop. External clock pulse is connected to all
the flip flops in parallel. For designing the counters JK flip flop is preferred .The significance
of using JK flip flop is that it can toggle its state if both the inputs are high, depending on the
clock pulse. The inputs of first flip flop are connected to HIGH (logic 1), which makes the
flip flop to toggle, for every clock pulse entered into it. So the synchronous counter will work
with single clock signal and changes its state with each pulse.
Pin diagram of 7476 and 7408:
Figure 36: IC 7476
Page 50
Figure 37: IC 7408
Table 14: Function table of JK flip flop
Table 15: Excitation Table of JK flip-flop
Qn
Qn+1
0
0
1
1
0
1
0
1
0
1
X
X
X
X
1
0
Page 51
Design of mod-n (n<8) synchronous up counter

1. Synchronous Modulo-5 Counter
Step1: To write State Table of Modulo-5 counter
Table 16: State Table of Modulo-5 counter
Present
State
Nert State
Qc Qb Qa
Qc+1 Qb+1 Qa+1
Jc Kc
Jb Kb
Ja Ka
Step 2: To draw K-map and derive characteristic equation for each inputs of JK flip flop.
Jc :
Jc= Qb.Qa
Page 52
Kc:
Kc= 1
Jb:
Jb= Qa
Kb:
Kb= Qa
Ja:
Ja= Qc
Ka:
Ka= 1
Page 53
Step 3: Circuit diagram of Synchronous Mod-5 Counter
Step 4: Timing diagram
2. Synchronous Modulo-7 Counter (Assignment)

Procedure:
1. Verify all components and patch chords whether they are in good condition or
not.
2. Make connection as shown in the circuit diagram.
4. Provide positive edge triggered clock.
5. Verify the count.
Result:
Mod-5 and Mod-7 synchronous up counters are designed and implemented using J-K
Flip-Flop ICs and demonstrated its working.
Page 54
(b)Aim: To write a verilog/VHDL code for Mod 8 Synchronous Counter and to

simulate and verify its working.
Circuit Diagram:
Mod 8 Counter
Figure 38: MOD 8 Counter

Table 17: Truth table of Mod 8 counter
Clock
Reset
Q2
Q1
Q0
0
1
2
3
4
5
6
7
8
9
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
Verilog code for Mod-8 Counter.

module mod( clk, reset, q);
input clk;
input reset;
output [2:0] q;
reg [2:0]q;
always @(posedge clk or posedge reset)
if(reset) q= 3'b0;
else q= q+1;
endmodule
Page 55
Mod 8 Counter Simulation Input
Figure 39: Snapshot of Mod 8 Counter Simulation Input
Mod 8 Counter Simulation Output
Figure 40: Snapshot of Mod 8 Counter Simulation Output
Result:
Designed verilog code for Mod 8 Synchronous Counter and simulated using Xilinx.
Page 56
Experiment 10
Design and implement an asynchronous counter using decade counter IC to
count up from 0 to n (n<=9) and demonstrate on 7-segment display (using
IC-7447).
Aim: Design and implement an asynchronous counter using decade counter IC to count
up from 0 to n (n<=9) and demonstrate on 7-segment display (using IC-7447).
Components used: 7490 IC, 7447, Connecting wires and trainer kit.
Theory:
Asynchronous counter is a counter in which the clock signal is connected to the clock
input of only first stage flip flop. The clock input of the second stage flip flop is triggered
by the output of the first stage flip flop and so on. This introduces an inherent
propagation delay time through a flip flop. A transition of input clock pulse and a
transition of the output of a flip flop can never occur exactly at the same time. Therefore,
the two flip flops are never simultaneously triggered, which results in asynchronous
counter operation.
Pin Diagram of 7490 and 7447:
Figure 41: IC 7490
Figure 42: IC 7447

Page 57
Design of asynchronous counter using decade counter IC to count up from 0

to n (n<=9):
1. Asynchronous Mod-10 Counter (counts from 0 to 9)
Figure 43: Circuit Diagram of Asynchronous Mod- 10 Counter with 7-Segment display
Table 18 : Function Table of Decade counter
Clock
0
1
2
3
4
5
6
7
8
9
10
Qd
0
0
0
0
0
0
0
0
1
1
Qc
0
0
0
0
1
1
1
1
0
0
Qb
0
0
1
1
0
0
1
1
0
0
Resets
Qa
o
1
0
1
0
1
0
1
0
1
Page 58
Timing Diagram:
Figure 44: Timing diagram of Mod 10 counter
2. Asynchronous Mod-5 Counter (counts from 0 to 4)
Figure 45: Circuit Diagram of Asynchronous Mod- 5 Counter with 7-Segment display
Table 19 : Function Table of Decade counter
Clock
0
1
2
3
4
5
Qd
0
0
0
0
0
Qc
0
0
0
0
1
Qb
0
0
1
1
0
Resets
Qa
o
1
0
1
0
Page 59
Timing Diagram:
Figure 46: Timing diagram of Mod 5 counter
Procedure:
1.
2.
3.
4.
5.
6.
7.
Check whether all components are working or not.

Make connections of 7490 IC as shown in the circuit.
Provide power supply to the trainer kit.
Check binary count at logic output side.
Make further connection of 7447 and 7 segment display.
Give negative clock.
Verify the count on 7 segment display.
Result: Asynchronous Mod-10 and Mod-5 counters are designed and implemented
using decade counter IC and demonstrated on 7-segment display.
Page 60
11. Study Experiment: To study 4-bit ALU using IC-74181.

Aim: To study and understand 4-bit ALU using IC-74181.
Components required: IC-74181
Figure 47: Functional representation of IC-74181

Table 20: Truth table of 75181
Page 61

This applet demonstrates the TTL-series 4-bit 74181 arithmetic-logical unit. It takes 4-bit
operands and a carry input and calculates one of 16 logical or 16 arithmetic functions. Two additional
active-low outputs X (/propagate) and Y (/generate) allow to interface to the 74182 carry-lookahead
generator IC for fast addition.
The M input selects whether the ALU should calculate logical functions (M=1) or arithmetic
functions (M=0). In each mode, the four S3...S0 opcode inputs select one of the available operations;
check the table in the applet schematics for the specific funtions selected by each opcode. For
example, M=0 and S= (1001) select the normal binary addition including carry, Z= (A+B+Cin)
The circuit of the TTL-series 4-bit 74181 ALU is integrated circuit. The input signals for the
A and B data inputs pass through three main stages of logic. The first stage consists of four identical
blocks of logic connected to one pair of the (A, B) inputs and the four function selection inputs. Each
block calculates the logical function selected by the S inputs and generates two output signals which
are then passed to the next stage of logic. Note that the outputs generated by the first stage of logic
are directly passed through to the F outputs (via the XOR gates) when the M input is high. The next
stage of logic realizes the carry-look-ahead calculation for the arithmetic adder functions (when M is
low), while the XOR gates calculate the summation (Ai+Bi) of each pair of data inputs. The final
stage of logic consists of the output XOR gates and calculates the final sum by adding the carry bits
and the (Ai+Bi) bits
Page 62
Appendix
I. Multisim:
Multisim is an industry-standard, best-in-class SPICE simulation environment. It
is the cornerstone of the NI circuits teaching solution to build expertise through
practical application in designing, prototyping, and testing electrical circuits. The
Multisim design approach helps you save prototype iterations and optimize printed
circuit board (PCB) designs earlier in the process.
Steps for schematic design:

1. Start
Click on Start
Suite 10.0
All Programs
Multisim
National Instruments
Circuit Design
2. Open/Create Schematic
A blank schematic Circuit 1 is automatically created. To create a neschematic click on
File New Schematic Capture. To save the schematic click on File /Save As. To open
an existing file click on File/ Open in the toolbar.
3. Place Components
To Place Components click on Place/Components. On the Select Component Window
click on Group to select the components needed for the circuit. Click OK to place the
component on the schematic.
4. Rotate Components
To rotate the components right click on the Resistor to flip the component on 90
Clockwise (Ctrl +R) and 90 Counter Clockwise (Ctrl+Shift+R).
5. Place Wire/Connect Components
To connect resistors click on Place/Wire drag and place the wire. Components can
also be connected by clicking the mouse over the terminal edge of one component
and dragging to the edge of another component
6. Change Component Values
To change component values double click on the component this brings up a window
that display the properties of the component. Reference Figure 7. Change R1 from 1k
Ohm to 10 Ohms, R2 to 20 Ohms, R3 to 30 Ohms, and R4 to 40 Ohms. Also change the
DV source from 0 V to 20 V. Figure 8 shows the completed circuit
Page 63
7. Grounding:
All circuits must be grounded before the circuit can be simulated. Click on Ground in the
toolbar to ground the circuit. If the circuit is not grounded Multisim will not run the
simulation.
8. Simulation:
To simulate the completed circuit Click on Simulate/Run or F5. This feature can also be
accessed from the toolbar
II. Xilinx:
The ISE 10.1 Quick Start Tutorial is a hands-on learning tool for new users of the
ISE software and for users who wish to refresh their knowledge of the software. The
tutorial demonstrates basic set-up and design methods available in the PC version of
the ISE software. By the end of the tutorial, you will have a greater understanding of
how to implement your own design flow using the ISE 10.1 software.
Steps to simulate a digital system:

Create a new ISE project which will target the FPGA device on the Spartan-3 Startup
Kit demo board.
1. To create a new project:

1. Select File > New Project... The New Project Wizard appears.
2. Type tutorial in the Project Name field.
3. Enter or browse to a location (directory path) for the new project. A
tutorial subdirectory is created automatically.
4. Verify that HDL is selected from the Top-Level Source Type list.
5. Click Next to move to the device properties page.
6. Fill in the properties in the table as shown below:
Product Category: All
Family: Spartan2
Device: XC3S200
Package: PQ208
Speed Grade: -6
Top-Level Source Type: HDL
Page 64
Synthesis Tool: XST (VHDL/Verilog)

Simulator: ISE Simulator (VHDL/Verilog)
Preferred Language: Verilog (or VHDL)
Verify that Enable Enhanced Design Summary is selected.
Leave the default values in the remaining fields.
When the table is complete, your project properties will look like the following:
7. Click Next to proceed to the Create New Source window in the New Project
Wizard. At the end of the next section, your new project will be complete
2. Creating a Verilog Source

Create the top-level Verilog source file for the project as follows:
1. Click New Source in the New Project dialog box.
2. Select Verilog Module as the source type in the New Source dialog box.
3. Type in the file name counter.
4. Verify that the Add to Project checkbox is selected.
5. Click Next.
6. Declare the ports for the counter design by filling in the port information as
shown below:
7. Click Next, then Finish in the New Source Information dialog box to complete the
new source file template.
8. Click Next, then Next, then Finish.
3. Checking the Syntax of the New Counter Module

When the source files are complete, check the syntax of the design to find errors
1. Verify that Implementation is selected from the drop-down list in the
Sources window.
2. Select the counter design source in the Sources window to display the
related processes in the Processes window.
3. Click the + next to the Synthesize-XST process to expand the process group.
4. Double-click the Check Syntax process.
Note: You must correct any errors found in your source files. You can check for
errors in the Console tab of the Transcript window. If you continue without valid
syntax, you will not be able to simulate or synthesize your design.
5. Close the HDL file.
Page 65
4. Design Simulation
Verifying Functionality using Behavioral Simulation
Create a test bench waveform containing input stimulus you can use to verify the
functionality of the counter module. The test bench waveform is a graphical view
of a test bench.
Create the test bench waveform as follows:
1. Select the counter HDL file in the Sources window.
2. Create a new test bench source by selecting Project New Source.
3. In the New Source Wizard, select Test Bench WaveForm as the source type,
and type counter_tbw in the File Name field.
4. Click Next.
5. The Associated Source page shows that you are associating the test bench
waveform with the source file counter. Click Next.
6. The Summary page shows that the source will be added to the project, and it
displays the source directory, type, and name. Click Finish.
7. Click Finish to complete the timing initialization.
8. The blue shaded areas that precede the rising edge of the CLOCK correspond to
the Input Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION
port to define the input stimulus for the counter design as follows:
9. Save the waveform.
10.In the Sources window, select the Behavioral Simulation view to see that
the test bench waveform file is automatically added to your project.
5. Simulating Design Functionality

Verify that the counter design functions as you expect by performing behavior
simulation as follows:
1. Verify that Behavioral Simulation and counter_tbw are selected in the
Sources window.
2. In the Processes tab, click the + to expand the Xilinx ISE Simulator process
and double-click the Simulate Behavioral Model process.
The ISE Simulator opens and runs the simulation to the end of the test bench.
Page 66
Page 67
S. S. Education Trusts
S.G. BALEKUNDRI INSTITUTE OF TECHNOLOGY,

SHIVABASAVANAGAR, BELGAUM
ADE Lab Viva Questions

1. What are resistors, capacitors, inductors, function generator, CRO, regulated power
supply?
2. What are ICs?
3. Truth table of all gates.
4. What is the function of Schmitt trigger?
5. What are UTP and LTP values?
6. How relaxation oscillator is different from Schmitt trigger?
7. What are multivibrators? Type? Explain.
8. Mention differences between analog and digital electronics
9. What is the significance of Full adder over half adder?
10.What is the significance of Full subtractor over half subtractor?
11.What are multiplexer, decoder, encoder, priority encoder, code converters, parity
generator and checker?
12.What are combinational and sequential circuits? Difference between them.
13.What are flip flops? Types
14.Difference between synchronous and asynchronous counter.
15.What are shift registers? Types? Function?
16.What is significance of parity generator and checker?
17.What is the advantage of JK flip flop over RS flip flop?
18.What is ALU?
19.Positive and negative logic
20.What is dont care condition?
21.What is HDL? Types? Models?
22.What is test bench in HDL?
23.What is LED? Function?
24.Explain about 7 segment display.
25.What are PLA and PAL?
26.What is clock?
27.What are applications of counter, parity generator, flip flops, multivibrators, shift
registers, adders, relaxation oscillator?
28.What is universal shift register?
29.What is decade counter?
30.Study and memorize about all ICs which are used in lab.

Analog and Digital Electronics (Ade) Lab Manual by Prof. Kavya M. P. (SGBIT, BELAGAVI)

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S. S.

S.G. BALEKUNDRI INSTITUTE OF TECHNOLOGY

Analog and Digital Electronics

HoD , Dept. of CSE

Laboratory session-1: Write-upon analog components; functional

Laboratory session-2: Write-upon Logic design components, pin

a) Design and construct a Schmitt trigger using Op-Amp for given

b) Design and implement a Schmitt trigger using Op-Amp using a

a) Design and construct a rectangular waveform generator (Op-Amp

Design and implement an Astable multivibrator circuit using 555

a) Given a 4-variable logic expression, simplify it using Entered

b) Design and develop the Verilog /VHDL code for an 8:1

Design and implement code converter I) Binary to Gray II) Gray to

a) Design and implement a mod-n (n<8) synchronous up counter

b) Design and develop the Verilog / VHDL code for mod-8 up

Design and implement an asynchronous counter using decade

Circuit diagram of J/K Flip-Flop

Analog and Digital Electronics Laboratory Manual

Figure 1: Basic analog components

Prof. Kavya M. P., SGBIT, Belagavi

Analog and Digital Electronics Laboratory Manual

Figure 2: Resistors of different value

Components are coded are with colors to identify their value

Prof. Kavya M. P., SGBIT, Belagavi

Analog and Digital Electronics Laboratory Manual

A resistor colored Yellow-Violet-Orange-Gold would be 47 k with a tolerance of +/5%.

A resistor colored Green-Red-Gold-Silver would be 5.2 with a tolerance of +/- 10%.

Analog and Digital Electronics Laboratory Manual

Figure 4: Different types of Inductors

Prof. Kavya M. P., SGBIT, Belagavi

Analog and Digital Electronics Laboratory Manual

Figure 5: Different types of capacitors

Analog and Digital Electronics Laboratory Manual

Figure 6: Types of Diode

The fundamental property of a diode is its tendency to conduct electric current in

Prof. Kavya M. P., SGBIT, Belagavi

Analog and Digital Electronics Laboratory Manual

Figure 7: Different types of Transistor

Prof. Kavya M. P., SGBIT, Belagavi

Analog and Digital Electronics Laboratory Manual

An Operational Amplifier, or op-amp for short, is fundamentally a voltage

Figure 9: 555 Timer IC

Prof. Kavya M. P., SGBIT, Belagavi

Analog and Digital Electronics Laboratory Manual

Prof. Kavya M. P., SGBIT, Belagavi

Analog and Digital Electronics Laboratory Manual

Table 2: Details of Logic ICs

Prof. Kavya M. P., SGBIT, Belagavi

Analog and Digital Electronics Laboratory Manual

Prof. Kavya M. P., SGBIT, Belagavi

Analog and Digital Electronics Laboratory Manual

10V, UTP 4V & LTP 2V, then equation (2) yields R1

From equation (1) we have Vref

Prof. Kavya M. P., SGBIT, Belagavi

Analog and Digital Electronics Laboratory Manual

Example2: Vsat=10V, UTP=+2V and LTP=-2V

Figure 10: Circuit Diagram of Schmitt Trigger Circuit

Figure 11: CRO in DUAL mode

Prof. Kavya M. P., SGBIT, Belagavi

Analog and Digital Electronics Laboratory Manual

Figure 12: CRO in X-Y mode showing the Hysteresis curve

Prof. Kavya M. P., SGBIT, Belagavi

Analog and Digital Electronics Laboratory Manual