1.

What's the best place to find details on how to perform ECOs

in EDI System?
The EDI System User Guide has a chapter dedicated to ECO
Flows (Cadence Online Support access required). It describes several
flows depending on whether it is a pre-mask or post-mask ECO,
whether the changes are coming from a new Verilog netlist, DEF or
ECO file, and whether gate array cells are being used or not. If you are
new to ECO flows in EDI System then the ECO Flows chapter is the
place to start!
It's worth mentioning here ECOs can be implemented using the supercommand ecoDesign or by running each command individually
(init_design, ecoDefin, ecoPlace, ...). Both methods are
described in the User Guide.
2. What's the difference between a pre-mask and post-mask
ECO flow?
A pre-mask ECO is when you are making changes to the design before
any masks have been made. With a pre-mask ECO you are free to
make changse to any layer thus providing you more freedom to
implement the ECO.
A post-mask ECO is when you are making changes to a design after
masks have been made. Therefore, you want to limit the changes to
specific layers so you do not need to re-make all the masks. In a postmask ECO flow you can utilize existing spare cells which where placed
in the design to avoid changes to layers Metal1 and below. You can also
instruct the router to which layers it can use to perform ECO routing
and which must remain frozen.
3. How do I apply changes made in my RTL to the physical
design through ECO?
Encounter Conformal ECO Designer is recommended for performing

complex ECOs originating from RTL. It interfaces with RTL Compiler and
EDI System to perform the logical and physical ECOs while leveraging
Conformal's logical equivalency abilities to ensure the ECO was
successful for both the front-end and back-end signoff.
4. How does EDI System identify spare cells in a post-mask
ECO flow?
Spare cells should have a unique string in their instance name to
identify them. Then the command specifySpareGate or ecoDesign
-useSpareCells patternName is run to identify the spare instances.
For example, if all spare cells have _spare_ in their name then they are
identified using:
specifySpareGate -inst *_spare_*
OR
ecoDesign -spareCells *_spare_* ...
Note if you are making manual ECO changes to a netlist and
converting a spare cell to a logical instance, it's important to change
the instance name. Otherwise, the instance may be identified as a
spare cell if a future ECO is performed because it still has the spare cell
instance name.
5. How does EDI System identify the changes in the design?
During the ecoDefin step the existing netlist (new netlist) is compared
against the original placed and routed design. A summary of
differences is output to the log file and a detailed report file is output
to the local directory. You can review the report file to see a list of all
the differences.
6. How do I use spare cells or gate array cells during

placement?
Spare cells are identified using specifySpareGate. Then use the useSpareCells true option when running ecoPlace to instruct it to
swap the unplaced cells with spare cells of the same cell type:
specifySpareGate -inst *_spare_*
ecoPlace -useSpareCells true
Gate array style filler cells can be programmed with metal layers so
the poly/diffusion and lower layers are not changed, and only the metal
and via layer masks need to be modified. If you are using gate array
spare cells the flow depends on the SITE type used by the gate array
cells.
If your design has GA Cells which utilize a SITE type (i.e. GACORE)
different from normal standard cells (i.e. CORE) then use:
ecoPlace -useGACells GACORE
If your design has GA cells which utilize the same SITE type as
standard cells: ecoPlace -useGAFillerCells {List of
GAFillerCells}
Reference the User Guide for the complete flow.
7. Is ecoPlace -useSpareCells true timing driven?
ecoPlace will choose the spare cells to minimize wire length but is not
timing driven. After ecoPlace you can run ecoSwapSpareCell to
relocate an instance to the location of another spare cell of the same
type. Alternatively, you can run ecoRemap in place
of ecoPlace. ecoRemap is timing driven and automatically analyzes the
functionality of the newly added cells and remaps them to available

spare cells. The software analyzes the logic and performs changes to
improve timing and minimize DRVs.
8. How do I freeze certain metal layers during routing?
In a post-mask ECO Flow run ecoRoute with the modifyOnlyLayers option to specify which layers it is allowed to
modify. For example, to route using only Metal1 through Metal3:
ecoRoute -modifyOnlyLayers 1:3
9. How does ECO routing deal with metal fill?
When performing a post-mask ECO flow, ecoRoute will ignore the metal
fill while routing. This will likely cause DRC violations between the ECO
routes and metal fill. To fix these violations,
run verifyGeometry followed by the the trimMetalFill command.
This will cut back the metal fill from the ECO routing to fix the
violations.
10. Does EDI System support interactive (maual) ECOs?
Yes, EDI System provides a number of interactive commands to both
evaluate and commit ECO changes. See the Interactive ECO chapter of
the EDI System User Guide for details.
When performing interactive ECOs make sure setEcoMode is set as
desired. Here are some specific options to pay attention to and tips to
speed up run time when implementing a series of ECOs:
setEcoMode -updateTiming - Default is false allowing you to wait
until all ECOs are performed to run timing analysis. If set to true, timing
analysis is run after each ECO command.
setEcoMode -honorDontTouch, -honorDontUse,
-honorFixedStatus - The default for all of these is true. So if you find
you cannot make a change, check if any of these apply.

setEcoMode -batchMode - Sets this to true to improve runtime if you

are performing many ECOs.
- See more at: https://community.cadence.com/cadence_blogs_8/b/di/archive/2013/04/17/answersto-frequently-asked-questions-when-performing-ecos-in-edi-system#sthash.48Fox42L.dpuf

Noise Analysis of a Transmission gate in cadence

I have made a simple transmission gate with one input (for signal with sinusiodal voltage
input V0), a control (logic 0/1 to make switch On /OFF, with dc voltgae) and an output
across a resistor.
I want to do the noise analysis of this circuit.
1) Since it is not a differential circuit, how can i have positive and negative output nodes, for
output noise? Can I use ground as one output node?
2) For input noise, Input voltage source should be the the input sin voltage V0. But software
is neither selecting the vsin as source or any of its ports.
Thanks

1. How is IR drop analysis done?

How is IR drop analysis done? What are various statistics available in reports?
21st March 2010, 17:00

2.

21st March 2010, 17:52#2

ljxpjpjljx

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Re: IR drop analysis

is your company's backend flow belong to yourself?
21st March 2010, 17:52

3.

22nd March 2010, 05:08#3

useless_skew

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Re: IR drop analysis

Blastrail/Quartzrail can do the IR drop analysis. We are usually interested in the % of
vdd/vss drop. Also there are other tools available from Synopsys and Cadence to do the IR
drop analysis.
o

22nd March 2010, 05:08

4.

22nd March 2010, 05:49#4

itsmeteja

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Re: IR drop analysis

IR drop analysis is done using any of the following Power Analysis CAD tools ::
Sequence - Cooltime
Apache - Redhawk
Magma - Blastrail/Quartz rail
Synopsys - Prime rail

For this analysis you need to have certain inputs depending on the design stage you are in.
General inputs are techfile (Avanti flow) itf (synopsys flow) tech lef (cadence/magma flow)
standard cell /hard macros gdsii
.libs for std cells and sub blocks
timing constraints
design def
design verilog netlist
power budget if its estimates are known else provide activity factor of 0.3 which is definitely
pessimistic number
saif or some simulation file for running dynamic analysis.
Signal spefs
and some other optional inputs like sub ckts for decap's and wellcap subckts for standard
cells
After providing all these info you can perform static (resistive drop) or dynamic
(instantaneous drop) analysis. Then you can analyze the drop numbers either in gui or in
textual report.
If you are doing IR drop analysis for the first time, then you will be much more interested in
the grid connectivity.A tool from sequence called coolcheck which can be used to analyze
grid connectivity even you can invoke the cooltime tool if you have cool check licence. As in
some places even the grid connectivity is not proper it might be masked by IR product, for
such cases coolcheck tool will be much more useful.
If you are using magma quartz rail you need not provide all the inputs I had provided, you
can just provide the volcano DB with constraints as it has inbuit extractor.
Thanks
Teja
1 members found this post helpful.

1. The 10% IR drop we talk about represents VDD

drop+VSS drop?
I often read that 10% IR drop may cause 7% performance degrade..
Does the 10% mentioned here represents VDD drop+VSS drop? If so, what is the deffernt
between 2%VDD/8%VSS and 5%VDD/5%VSS?
I'm not sure about the impact of VSS drop to output high voltage(CMOS, voltage pull up by
VDD, seems irrelevant with VSS ).
o

4th September 2006, 04:50

2.

5th September 2006, 05:19#2

nitu

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Re: The 10% IR drop we talk about represents VDD drop+VSS dr

Originally Posted by albred

I often read that 10% IR drop may cause 7% performance degrade..

Does the 10% mentioned here represents VDD drop+VSS drop? If so, what is the deffernt
between 2%VDD/8%VSS and 5%VDD/5%VSS?
I'm not sure about the impact of VSS drop to output high voltage(CMOS, voltage pull up by
VDD, seems irrelevant with VSS ).
It does not make difference whether it is 2%vdd 8%vss or 10%vdd 0%vss etc because we
would be looking at vdd - vss (difference) only. so, 10% IR drop means that vdd-vss has
been decreased by 10%.
The high output is defined with respect to some reference in this case it is VSS. So, in case
VSS gets increased due to IR drop then in that case output high though seems unaffected
with respect to ground i.e. 0 volts, but has actually got decreased with respect to VSS.
2 members found this post helpful.

5th September 2006, 05:19

3.

5th September 2006, 06:28#3

albred

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Re: The 10% IR drop we talk about represents VDD drop+VSS dr

Thanks nitu.
I think you're righy.
o

5th September 2006, 06:28

4.

9th September 2006, 06:12#4

funster

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Re: The 10% IR drop we talk about represents VDD drop+VSS dr

10% IR DROP means (VDD(drop) - VSS(drop)) = 90 * (VDD(ldeal) - VSS
(ideal)), that's all.
best regards

Originally Posted by albred

I often read that 10% IR drop may cause 7% performance degrade..

Does the 10% mentioned here represents VDD drop+VSS drop? If so, what is the deffernt
between 2%VDD/8%VSS and 5%VDD/5%VSS?
I'm not sure about the impact of VSS drop to output high voltage(CMOS, voltage pull up by
VDD, seems irrelevant with VSS ).
5.

27th September 2006, 10:45#5

aravind.b

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Re: The 10% IR drop we talk about represents VDD drop+VSS dr

IR drop is fall in VDD and rise VSS that means diference between fall in VDD and rise in VSS
EX : - 10%fall in VDD - 10%rise in VSS.
1.

2. How to calculate the IR

drops ?
hi guys
hw can i calculate the IR drops
assume I=100uA metal width=5um length=20um
can anybody help me
regards
analayout
o

3.

29th March 2007, 11:15

29th March 2007, 12:10#2

rajkumaru

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Re: IR drop
Hi,
In my view, Voltage Drop V=IR
Here given thatI= 100uA, So, we need to know the value of R. For that we check in design
manual/foundary_provided_document that what is the value of metal resistance for unit
area. Then we can use formula R_metal = metal length*metal width*metal per unit area
resistance.
Suppose it is given that R=5uohm/um*um then R_metal=5um*20um*5= 500uohm
So, Now V=IR=100uA*500ohm= 50000uV=0.05V
If, I am wrong then please viewers let me correct. Thanks in advance!
Raj
o

4.

29th March 2007, 12:10

29th March 2007, 12:28#3

MSSN

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Re: IR drop
So, we need to know the value of R. For that we check in design
manual/foundary_provided_document that what is the value of metal resistance for unit
area. Then we can use formula R_metal = metal length*metal width*metal per unit area
resistance.
I think the more common in the foundaries' documents is the resistance per square(square
resistance) and what u do then is that u simply divide the length by the width to get the
number of squares and then calculate the total resistance by multiplying the number of
squares by the square resistance.
o

5.

29th March 2007, 12:28

29th March 2007, 12:33#4

srieda

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Re: IR drop
I agree. You will usually find the Rs (Sheet Resistance) given in terms of ohms/square.
So R = Rs * L / W
6.

30th March 2007, 05:23#5

pvnk

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Re: IR drop
Originally Posted by rajkumaru

Hi,
In my view, Voltage Drop V=IR
Here given thatI= 100uA, So, we need to know the value of R. For that we check in design
manual/foundary_provided_document that what is the value of metal resistance for unit
area. Then we can use formula R_metal = metal length*metal width*metal per unit area
resistance.
Suppose it is given that R=5uohm/um*um then R_metal=5um*20um*5= 500uohm
So, Now V=IR=100uA*500ohm= 50000uV=0.05V
If, I am wrong then please viewers let me correct. Thanks in advance!
Raj
Here is the calculation,
suppose R is the ohm/square for your metal layer ( refer FAB electrical specs.)
L is the length if your rout
W is the width of your rout,
I is the current flowing ( take slightle higher than your avg I )
Now to calculate no. of sqrs, N = L/W
total resistance Rtot = N * R
IR dorp = Rtot*I volts ( if I is in amps )
Hop it's clear. it's ok if you have a 10mV drop for digital lines and 1mV for analog generally.
for analog, always ensure that your disigner knows what is the drop on important nets.

thanks
if you are working on a Cadence platform, you can get this ohms/square by dumping your
technology file ( provided your tech file contains this info) go to icfb > tools > technology
file manager ( something similar ) > dump > select electrical rules and give file path to
dump > click ok.
i
or mail your FAB and they will be happy to give you this info.