Electromagnetic Interference Mitigation in Switched

Mode Power Converters Using Digital Sampling

Techniques

by

Djilali Hamza

A thesis submitted to the Graduate Program in Department of Electrical and Computer

Engineering in conformity with the requirements for
the Degree of Doctor of Philosophy

Queens University
Kingston, Ontario, Canada
(November, 2011)

Copyright Djilali Hamza, 2011

Abstract
Increasing power density of switch mode power supplies, by increasing their switching frequency
has becoming a challenging obstacle for EMI mitigation. The passive EMI suppression technique
has always been the primary solution to fulfill the EMC requirement in terms of conducted
emission limits. However, the call for stringent power supplies specifications renders the passive
techniques less desirable, due to their increasing size and power losses. In other words, the greater
the power density of the converter, the bigger the passive filter. Other suppression techniques
such as the spread spectrum frequency modulation (SSFM), and soft switching, prove to have less
performance and much complex to implement. The active analog EMI filters provide the basic
noise suppression technique; however, their performance is dramatically impeded at higher
frequency. This solution requires an additional small size passive filter to complete the EMC
spectrum for conducted emissions.
Digital active filtering techniques offer advantages of flexibility, fewer external components and
reduced overall size and power losses as compared to conventional passive filtering techniques.
In this thesis DSP-based and FPGA-based EMI control techniques to mitigate the conducted
emissions of switch mode power converters are proposed. These techniques are implemented inlieu of the passive filtering techniques, by keeping equal or better performance. Moreover, these
solutions can be configured as a stand-alone or integrated into the converter digital controller
algorithm.
Finally, the proposed solutions are implemented into three types of power converters, namely, a
AC-DC power factor corrected converter, DC-AC micro-inverter for Photovoltaic application,
and DC-DC for Electric Vehicle (EV) battery charger. Analytical, simulation and experimental
results are provided to verify the proposed solutions.

ii

Acknowledgements
I would like to express my sincere gratitude and many thanks to Dr. Praveen Jain, the director of
ePOWER centre, for his support and confidence during the course of this work. Dr. jain's
extensive research vision has been a source of inspiration and an example for me to overcome all
the hurdles encountered in this research work.
I also thank my committee members, in particular, Dr. John E. Quaicoe of Memorial University
of Newfoundland, for their insights and valuable observations. In addition, I would like to extend
my thanks to my past and present colleagues, as well as, all the graduate students of Queen's
ePOWER centre for their cooperation and understanding.
Financial support in the form of tuition waver award under Queen's University Employee Tuition
Assistant Program, is gratefully acknowledged.
Finally, my heartfelt appreciation goes to my parents, my wife, my daughter and my son for their
love, support and patience.

iii

To my Parents,
My wife Mei
My daughter Myriam
& My son Yusuf

iv

Statement of Originality
(Required only for Division IV Ph.D.)
I hereby certify that all of the work described within this thesis is the original work of the author.
Any published (or unpublished) ideas and/or techniques from the work of others are fully
acknowledged in accordance with the standard referencing practices.

(Djilali Hamza)

(November, 2011)

Table of Contents
Abstract ............................................................................................................................................ ii
Acknowledgements ......................................................................................................................... iii
Statement of Originality................................................................................................................... v
Table of Contents ............................................................................................................................ vi
List of Figures .................................................................................................................................. x
Acronyms: ................................................................................................................................ xvii
Symbols: ..................................................................................................................................... xx
Chapter 1 Introduction ..................................................................................................................... 1
1.1

Background ...................................................................................................................... 1

1.2

EMI Generation in Power Converters .............................................................................. 3

1.2.1

Conducted Emissions in Power converters .............................................................. 6

1.2.2

Radiated Emissions in Power Converters ................................................................ 9

1.3

EMC Regulations and Standards ................................................................................... 10

1.4

Thesis Objectives ........................................................................................................... 14

1.5

Thesis Outline ................................................................................................................ 15

Chapter 2 Review of EMI Control techniques in Power converters .............................................. 17

2.1 Introduction .......................................................................................................................... 17
2.2 Basic EMI Suppression Techniques .................................................................................... 17
2.2.1 Reducing Heat-sink Stray Capacitance ......................................................................... 18
2.2.2 Reducing Transformer Stray Capacitance .................................................................... 21
2.2.3 Reducing Transformer Stray Inductance ...................................................................... 23
2.3 Passive Analog Filtering Technique in Switch Mode Power Converter.............................. 25
2.3.1 Passive Input EMI Filter ............................................................................................... 26
vi

2.3.2 Basic Circuit Configurations......................................................................................... 27

2.3.3 Source and Load Impedance Variations ....................................................................... 30
2.3.4 Passive EMI Filter Design Procedures.......................................................................... 31
2.3.5 Performance and Limitations of the Passive EMI Filter ............................................... 34
2.4 Zero Voltage/Soft Switching (ZVS) Techniques ................................................................. 35
2.4.1 Simulation Results ........................................................................................................ 36
2.5 Spread Spectrum Frequency modulation techniques (SSFMT) ........................................... 39
2.5.1 SSFM techniques limitation .......................................................................................... 44
2.6 Active Analog Filtering Technique in Switch Mode Power Converters ............................. 45
2.6.1 Principle of Operation ................................................................................................... 45
2.6.2 Circuit Analysis ............................................................................................................ 46
2.6.3 Transformer Based Injector .......................................................................................... 50
2.6.4 Design Example ............................................................................................................ 52
2.7 Summary .............................................................................................................................. 55
Chapter 3 Proposed DSP-Based EMI Suppression Technique ...................................................... 56
3.1 Introduction .......................................................................................................................... 56
3.2 Principle of Operation .......................................................................................................... 58
3.3 Sampling Theory.................................................................................................................. 59
3.4 Circuit Building Blocks ....................................................................................................... 62
3.5 Analysis and Design Approach ............................................................................................ 67
3.6 Simulation Results Waveforms ............................................................................................ 71
3.7 Experimental Results of the Proposed Techniques in a Stand-alone Configuration............ 76
3.8 Summary .............................................................................................................................. 81
Chapter 4 Proposed FPGA-Based EMI Suppression Technique (FPGABEST) ........................... 82
4.1 Introduction .......................................................................................................................... 82
vii

4.2 Principle of operation........................................................................................................... 83

4.3 Analysis and Design Approach ............................................................................................ 84
4.3.1 The sensor discretization............................................................................................... 86
4.3.2 The Injector discretization ............................................................................................ 87
4.3.3 The DAC discretization ................................................................................................ 88
4.3.4 Discrete-time Closed Loop Transfer Function.............................................................. 88
4.4 Summary .............................................................................................................................. 91
Chapter 5 Integration of the Proposed DAEF in a Digital Controller of a grid-tied Photovoltaic
Micro-inverter ................................................................................................................................ 93
5.1 Introduction .......................................................................................................................... 93
5.2 Description and Principle of Operation of the Grid-tied Inverters ...................................... 93
5.2.1 Centralized Inverters architecture ................................................................................. 94
5.2.2 String Inverters architecture .......................................................................................... 95
5.2.3 Multi-strings inverter architecture ................................................................................ 96
5.2.4 Micro-inverters architecture .......................................................................................... 98
5.3 Micro-Inverter Circuit Description and Controller Design Techniques ............................ 100
5.3.1 Output current control in D-Q frame .......................................................................... 103
5.4 Controller design for micro-inverter and stability verification .......................................... 106
5.4.1 Compensator design .................................................................................................... 109
5.5 Experimental results........................................................................................................... 115
5.6 Summary ............................................................................................................................ 118
Chapter 6 Proposed DAEF Integration in a DSP-Based DC-DC Digital Controller Used in
Electric Vehicle (EV) Battery Charger ........................................................................................ 119
6.1 Introduction ........................................................................................................................ 119
6.2 EV Power Conversion System Description ....................................................................... 119
viii

6.3 Circuit Analysis ................................................................................................................. 123

6.3.1 Circuit Description ...................................................................................................... 123
6.3.2 Controller Design Strategies and Stability Assessment .............................................. 125
6.3.3 Digital Controller Design ............................................................................................ 126
6.4 Experimental Results and Validations ............................................................................... 133
6.5 Summary ............................................................................................................................ 138
Chapter 7 Conclusions & Future Work........................................................................................ 139
7.1 Conclusions ........................................................................................................................ 139
7.2 Future Work ....................................................................................................................... 141
References .................................................................................................................................... 143
Appendix A Simulation Schematics ............................................................................................ 160
A.1

DC-DC Converter Operating in Continuous Mode, including the Line Impedance

Stabilization Circuit ................................................................................................................. 160

A.2

Digital Active EMI Filter Module ............................................................................... 161

Appendix B Circuit Layout & Selected Components List ........................................................... 162

B.1

Circuit Layout .............................................................................................................. 162

B.2

Selected Components ................................................................................................... 164

Appendix C Matlab Analysis file ................................................................................................ 165

C.1

Transfer Functions Evaluation ..................................................................................... 165

Appendix D MathCAD Analysis File .......................................................................................... 168

D.1

Attenuation Plot of the DAEF...................................................................................... 168

D.2

Compensator Design .................................................................................................... 171

Appendix E DSP Program ........................................................................................................... 185

ix

List of Figures
Fig. 1.1 Cost of EMC solution during the Design Lifecycle [2] ...................................................... 2
Fig. 1.2 EMI coupling mechanism block diagram ........................................................................... 3
Fig. 1.3 Inductive Coupling ............................................................................................................. 4
Fig. 1.4 Capacitive Coupling ........................................................................................................... 5
Fig. 1.5 CM and DM paths in power converter ............................................................................... 6
Fig. 1.6 Differential Mode currents is generated by the normal switching action of the MOSFET 7
Fig. 1.7Common Mode currents coupled to chassis through stray capacitance .............................. 8
Fig. 1.8 CM noise due to the Drain heat-sink stray capacitance ................................................... 9
Fig. 1.9 Possible loop areas for radiated emission in SMPS .......................................................... 10
Fig. 1.10 Fields of EMC ................................................................................................................ 12
Fig. 2.1 MOSFET Drain to Heat-sink stray capacitance, the CM current returns through the LISN
impedance (large return path) ........................................................................................................ 19
Fig. 2.2 Reducing the CM current by floating the heat-sink.......................................................... 20
Fig. 2.3 Reducing the CM current by screening/shielding the MOSFET ...................................... 20
Fig. 2.4 Reducing the CM noise current by using LC circuit ........................................................ 21
Fig. 2.5 CM current generation through core and primary-to-secondary stray capacitance .......... 22
Fig. 2.6 Transformer core is referenced to the DC-link, shorter current path................................ 22
Fig. 2.7 shield connection between the primary and the transformer core .................................... 23
Fig. 2.8 shielding primary and secondary winding ........................................................................ 23
Fig. 2.9 Transformer windings configuration; (a) single windings, fringing fields; (b) split
windings creates leakage fields that tend to cancel........................................................................ 25
Fig. 2.10 Schematic diagram of an input EMI filter for SMPS ..................................................... 26

Fig. 2.11 Basic passive EMI filter circuit configurations: (a) single stage LC-circuit, (b) -circuit,
(c) T-circuit, (d) Multistage LC-circuit

...................................................................................... 28

Fig. 2.12 Basic EMI filter Configuration for CM and DM attenuation ........................................ 28
Fig. 2.13 Insertion loss (IL) measurement: (a) Reference circuit, (b) Filter under test inserted ... 30
Fig. 2.14 Single ended CM equivalent circuit diagram ................................................................ 31
Fig. 2.15 Interface impedances of the passive EMI filter .............................................................. 33
Fig. 2.16 zero voltage transition (ZVS) circuit implemented in a DC/DC converter .................... 36
Fig. 2.17 ZVS Transition in main switch S1.................................................................................. 37
Fig. 2.18 HS Transition in main switch S1 .................................................................................... 37
Fig. 2.19 EMI profile with Soft Switching circuit ......................................................................... 37
Fig. 2.20 EMI Profile with Hard Switching ................................................................................... 38
Fig. 2.21 EMI Profile with ZVS and HS [38] ................................................................................ 39
Fig. 2.22 Effect of SSFM technique on an nth harmonic of a clock signal; (a) un-modulated clock;
(b) modulated clock ....................................................................................................................... 40
Fig. 2.23 Resulting spectrum of different modulating signal waveforms; (a) sine wave; (b) square
wave; (c) ramp ............................................................................................................................... 41
Fig. 2.24 Spectral content of the modulated signal ........................................................................ 43
Fig. 2.25 The configuration of the active input EMI filter............................................................. 46
Fig. 2.26: Equivalent harmonic circuit of the converter: (a) Equivalent circuit with passive filter
only, (b) Equivalent circuit with hybrid active and passive filters ................................................ 47
Fig. 2.27: Noise attenuation of the active circuit (Zin=50//50H, Rs=50, Cs=5F, Cin=20F,
k1=6106, k2 =100, N=15) .............................................................................................................. 49
Fig. 2.28: Injection transformer ..................................................................................................... 51
Fig. 2.29: Experimental circuit diagram ........................................................................................ 52
Fig. 2.30: Conducted EMI noise spectrum result with the input passive filter only ...................... 53
xi

Fig. 2.31: Conducted EMI noise spectrum result with the combination of passive and active input
EMI filters. ..................................................................................................................................... 54
Fig. 3.1 Application of DAEF versus PEF in power converters ................................................... 57
Fig. 3.2 General Scheme of the Digital Input EMI filter ............................................................... 59
Fig. 3.3 Impulse Sampling Model.................................................................................................. 60
Fig. 3.4 Circuit example of a Sampling time-domain analog signal .............................................. 62
Fig. 3.5 Simulation waveforms showing the sampling process using impulse function and the
recovered signal ............................................................................................................................. 62
Fig. 3.6 Block Diagram of an Analog-to-Digital Converter (ADC) .............................................. 63
Fig. 3.7 Block Diagram of a Digital-to-Analog Converter (DAC) ................................................ 64
Fig. 3.8 Feedback Diagram of the DSP-Based Digital EMI filter ................................................. 68
Fig. 3.9 Frequency response - magnitude of the DSP-based EMI filter ........................................ 70
Fig. 3.10 Frequency response - phase of the DSP-based EMI filter ............................................. 70
Fig. 3.11 Schematic block diagram of the simulation circuit ....................................................... 71
Fig. 3.12 Conducted Noise measurement without Input EMI Filter ............................................. 74
Fig. 3.13 Conducted Noise measurement with Passive Input EMI Filter ...................................... 74
Fig. 3.14 Conducted Noise measurement with Proposed Digital Input EMI Filter ....................... 75
Fig. 3.15 Output of the ADC and the DAC in time domain ......................................................... 76
Fig. 3.16 Conducted emissions testing experimental setup ........................................................... 77
Fig. 3.17 Input and output voltage signal of the proposed DAE Filter .......................................... 78
Fig. 3.18 Conducted emission spectrum of EUT without filters.................................................... 79
Fig. 3.19 Conducted emission spectrum of EUT with PEF ........................................................... 79
Fig. 3.20 Conducted emission spectrum of EUT with DAEF........................................................ 80
Fig. 3.21 Comparative attenuation between PEF and DAEF........................................................ 81
Fig. 4.1 Proposed FPGABEST block diagram connected to a buck converter.............................. 84
xii

Fig. 4.2 Feedback loop diagram of the proposed FPGA-Based EST............................................. 84

Fig. 4.3 two-port network model ................................................................................................... 85
Fig. 4.4 Noise attenuation performance of the discrete-time transfer function.............................. 91
Fig. 5.1 Centralized PV system Architecture ................................................................................. 95
Fig. 5.2 String Inverters Architecture ........................................................................................... 96
Fig. 5.3 Multi-strings Inverter Architecture ................................................................................... 97
Fig. 5.4 Multi-strings Architecture with distributed MPPT ........................................................... 98
Fig. 5.5 Micro-inverter Architecture .............................................................................................. 99
Fig. 5.6 Cost of PV inverter as a function of the rated power...................................................... 100
Fig. 5.7 Schematic diagram of a micro-inverter including the digital controller ......................... 101
Fig. 5.8 Block diagram micro-inverter controller architecture in rotating D-Q frame ............... 103
Fig. 5.9 Average circuit model in R-I stationary frame .............................................................. 105
Fig. 5.10 Equivalent circuit model in D-Q rotating frame .......................................................... 106
Fig. 5.11 Current Control Loop in Continuous time ................................................................... 107
Fig. 5.12 Corresponding discrete model of the current control loop .......................................... 107
Fig. 5.13 Bode plot of the open loop un-compensated control system ....................................... 109
Fig. 5.14 Schematic Diagram of Type III Compensator ............................................................. 110
Fig. 5.15 Compensator gain plot: Gain boost of 104dB ............................................................. 112
Fig. 5.16 Compensator Phase plot: Phase boost of 46 deg. ........................................................ 112
Fig. 5.17 Bode plot of the compensated micro-inverter control system ..................................... 113
Fig. 5.18 Nyquist Plot of the micro-inverter closed loop control system ................................... 114
Fig. 5.19 Conducted emissions test setup ................................................................................... 115
Fig. 5.20 Conducted emissions spectrum of the micro-inverter with passive EMI filter ........... 116
Fig. 5.21 Conducted emissions spectrum of the micro-inverter without EMI filters.................. 117
Fig. 5.22 Conducted emissions spectrum of the micro-inverter with DAEF installed ............... 117
xiii

Fig. 6.1 Hybrid Parallel Traction System .................................................................................... 121

Fig. 6.2 Plug-in Hybrid Vehicle Configuration .......................................................................... 122
Fig. 6.3 Full-bridge ZVS resonant converter .............................................................................. 124
Fig. 6.4 closed loop block diagram of the EV auxiliary battery charger .................................... 127
Fig. 6.5 Bode Plot of soft complex digital zero-pair used for the system compensation ............ 128
Fig. 6.6 Frequency response of the current loop gain (Magnitude) ............................................ 131
Fig. 6.7 Frequency response of the current loop gain (Phase) .................................................... 131
Fig. 6.8 Frequency response of the outer voltage loop gain (Magnitude) .................................. 132
Fig. 6.9 Frequency response of the outer voltage loop gain (Phase) .......................................... 132
Fig. 6.10 DC-DC converter conducted emissions test setup....................................................... 134
Fig. 6.11 Transient response to a step up change in the load current ......................................... 135
Fig. 6.12 Transient response to a step down change in the load current..................................... 135
Fig. 6.13 Conducted emission spectrum with the passive EMI filter ......................................... 136
Fig. 6.14 Conducted emissions spectrum with no EMI filter installed ....................................... 137
Fig. 6.15 Conducted emissions spectrum with DSP-Based DAEF installed .............................. 137

Fig. A.1 OrCAD Simulation Schematic of the DC-DC power converter .................................... 160
Fig. A. 2 OrCAD Simulation Schematic of the DAEF Module.................................................. 161

Fig. B.1 PCB Top Layer of the DAEF........................................................................................ 162

Fig. B.2 PCB Bottom Layer of the DAEF ................................................................................... 162
Fig. B.3 Unpopulated PCB prototype of the DAEF .................................................................... 163
Fig. B.4 Populated PCB Prototype of the DAEF ........................................................................ 163

Fig. D.1 Frequency response of the DAEF - Magnitude ............................................................ 169

xiv

Fig. D.2 Frequency response of the DAEF - Phase .................................................................... 169

Fig. D.3 Magnitude plot of the ZOH .......................................................................................... 170
Fig. D.4 Phase plot of the ZOH .................................................................................................. 171
Fig. D.5 Gain plot of the plant transfer function ......................................................................... 173
Fig. D.6 Phase plot of the plant transfer function ....................................................................... 173
Fig. D.7 Type 3 compensator magnitude plot ............................................................................. 176
Fig. D.8 DC-DC Converter Digital Controller Design ............................................................... 176
Fig. D.9 Digital compensator gain for different values of b and c.............................................. 180
Fig. D.10 Phase of the digital compensator for different values of b and c ................................ 180
Fig. D.11 Bode plot of the Gain Transfer function of the inner current loop .............................. 182
Fig. D.12 Phase response of the open loop transfer function for the current inner loop ........... 183
Fig. D.13 Bode plot of the open loop gain transfer function for the outer voltage loop ............. 183
Fig. D.14 Phase response of the open loop transfer function for the outer voltage loop ............ 184

xv

List of Tables
Table 2-1: Performance comparisons of the passive and the hybrid filters ................................... 54
Table 3-1 Simulated Converter Parameters for DSP-based EMI filter .......................................... 72
Table 3-2 Comparison of attenuation performance between PEF and DAEF using simulation
results ............................................................................................................................................. 75
Table 3-3 Comparison between experimental and simulation results ........................................... 80
Table 5-1 Characteristics Evaluation of different PV systems architectures ............................... 100
Table 6-1 Converter parameters.................................................................................................. 133

Table B. 1 Main Components List ............................................................................................... 164

xvi

List of Acronyms & Symbols

Acronyms:
AC

Alternative Current

ADC

Analog-to-Digital Converter

AEM

Active EMI Filter

AM

Amplitude Modulation

ASIC

Application Specific Integrated Circuit

CFL

Compact Fluorescent Lamp

CISPR

Comit International Spcial Pour Radio

ITC

International Telecommunication Convention

CM

Common Mode

DAC

Digital-to-Analog Converter

DAEF

Digital Active EMI Filter

DC

Direct Current

DM

Differential Mode

DOD

Department of Defense

D-Q

Direct Quadrature

DSP

Digital Signal Processor

DSPBEST

DSP-Based EMI Suppression Technique

EEC

European Economic Consortium

EM

Electromagnetic

EMC

Electromagnetic Compatibility

EMI

Electromagnetic Interferences
xvii

ESR

Equivalent Series Resistance

EST

EMI Suppression Technique

EV

Electrical Vehicle

FCC

Federal Communications Commission

FCHEV

Fuel Cell Hybrid Electric Vehicle

FCV

Fuel Cell Vehicle

FM

Frequency Modulation

FPGA

Field Programmable Gate Array

FPGABEST

FPGA-Based EMI Suppression Technique

HPF

High-Pass Filter

HS

Hard Switching

HV

Hybrid (gas/electrical) Vehicle

HV

High Voltage (Battery)

ICEV

Internal Combustion Engine Vehicle

IEC

International Electro-technical Commission

IL

Insertion Loss

IPEM

Input Power Electronic Module

LISN

Line Impedance Stabilization Network

LSB

Least Significant Bit

LV

Low Voltage (Battery)

MOSFET

Metal-Oxide-Semiconductor Field Effect Transistor

MPP

Maximum Power Point

MPPT

Maximum Power Point Tracking

MSB

Most Significant Bit

PCB

Printed Circuit Board

xviii

PFC

Power Factor Correction

PHEV

Plug-in Hybrid Electric Vehicle

PI

Proportional and Integral

PSD

Power Spectrum Density

PV

Photovoltaic

PWM

Pulse-Width-Modulation

RHP

Right Half-Plane

SMPS

Switch Mode Power supply

SSCG

Spread Spectrum Clock Generation

SSFMT

Spread Spectrum Frequency Modulation Techniques

TF

Transfer Function

VHDL

Very high speed integrated circuit Hardware Description Language

ZOH

Zero-Order-Hold

ZCS

Zero-Current Switching

ZVS

Zero Voltage Switching

xix

Symbols:
U0

Voltage of the generator

Um

Measuring instrument Voltage

R1

Source impedance of the generator

R2

Input impedance of the measuring instrument

Rin

Input impedance of the DC/DC converter

Lf and Rf

Filter inductance and its series resistance

Cf and ESRcf

Filter capacitance and its equivalent internal series resistance

Rd and Cd

Damping resistance and damping capacitance across the DC bus

Zeq

Equivalent impedance of the EMI filter at the input of DC/DC converter

ZIF

Input Impedance of the passive EMI filter loaded with the DC/DC converter with
the output port open

ZOF

Output Impedance of the passive EMI filter connected to an input DC bus with
the input port shorted

ZDC

Output impedance of the input DC source

Zin

Input impedance of the DC/DC converter

s(t) and (t)

Instantaneous amplitude and phase angle of the modulated signal

Frequency of the carrier signal
Frequency of the modulated signal
Peak frequency deviation

Modulation index

Rate of modulation, %

Lin and Cin

Input passive filter inductance and capacitance

Cs and Rs

Sensing branch (capacitance and resistance) of the active filter

Rb, Rb1 and Cb Bias circuit (resistance and capacitance) of the OPAmp
xx

Vref

Reference voltage to set the bias voltage of the OPAmp

in

Ripple current generated by the switching MOSFET

iinj

Injected current noise

Iin

Current fed back into the utility mains with the passive filter only

I'in

Current fed back into the utility mains with the hybrid filter

Gain of the injection transformer

Av

Closed-loop voltage gain for the current feedback amplifier with unity gain

A(s)

Frequency-dependant open-loop trans-conductance gain function

k1 and k2

DC gain (typically 105 to 107) and the cutoff frequency of the OPAmp

vit _1 and vit _2

Voltages at the primary and secondary windings of the injection transformer

vop

Output voltage of the OPAmp

sw

Switching frequency

fs and Ts(or T) Sampling frequency and clock period

i(t)

Infinite impulse train

m(t)

Band-limited low-pass signal

s(t)

Sampled signal
Maximum frequency of the band-limited signal
Sensed analog signal
Sampled signal of the
Piece-wise linear function of the sampled signal

Gzoh(s) and D(s) Laplace transform transfer function of ZOH

Y(s)

EMI source function (noise current) at the quite port, utility side

X(s)

EMI source function (noise current) at noisy port, the converter side

X(s)

Injected EMI noise function, after processing

K1

Injector gain
xxi

K2

Bits inversion algorithm implemented in the DSP device

Laplace transform transfer function of the high-pass filter

G(s)

Laplace transform transfer function of the RC low-pass filter

(f1)

Corner frequency of the high-pass filter

(f2)

Corner frequency of the low-pass filter

XD

Inductor current in the rotating frame

XQ

Capacitor voltage in the rotating frame

XR

Real circuit variable

XI

Imaginary circuit variable

Xm

Peak value of the sinusoidal waveform

Initial phase
Fundamental frequency

PM

Phase margin

Km

Modulator gain

Vs

Peak value of the oscillator ramp signal

Kb

Plant DC gain

Gp(s)

Plant TF

Gd(s)

D-Q transformation TF

Gc(s)

Type-III compensator TF

Laux1 and Laux2 Auxiliary circuit inductors

C1, C2, C3, and C4 Auxiliary circuit capacitors
Tcl_v

Closed loop control-to-output voltage transfer function

Tcl_i

Closed loop control-to-inductor current transfer function

Delay transfer function
Analog to digital converter gain
xxii

Number of bits
Output voltage sensor transfer function

Ksense

Sensing gain
Gain of the PWM

Gi(s)

Transfer function of the control to output current of the converter

Gv(s)

Transfer function of the control to output voltage of the converter

Transfer function of the digital active EMI filter
Gain of the Error amplifier

xxiii

Chapter 1
Introduction

1.1

Background

The principle of electromagnetic compatibility (EMC) is to allow a correct and optimum

functioning of any electrical or electronic devices in the presence of each other. In other words, it
is the right of electrical/electronic equipment to co-exist in an electromagnetic environment
without disturbing each other. This definition draws three poles of interest: the study of sources of
interference, the study of the coupling paths and, finally, the study of the impact of disturbances
on the "victim" circuit, susceptibility. The absence of one of these conditions will breach the EMI
manifestation. In this research work, we apply this principle in the field of power electronics,
specifically the field of switching power converters. These converters are referred in most
literature as switched mode power supplies (SMPS). They have become one of the most popular
types of electrical supply compared to their counterpart linear power supplies, due to their power
quality preservation, their voltage regulation, and their energy efficiency. Their use ranges from
the feeding of integrated electronic devices to the feeding of power drive systems. According to
the definitions given in the IEC Draft 22G-WG4-11 [1], an SMPS consists of two parts: the socalled converter section and the control section. The former is composed of the switching
elements, the auxiliary devices, and the conductors to the load. The switching elements are
usually semiconductor devices with switching frequency extending from tens to hundreds of
kilohertz to a few Megahertz. During turn-on and turn-off operations they give rise to very fast
voltage and current transients (di/dt and dv/dt). Those transients are sources of most conducted
and radiated electromagnetic interferences (EMI) pollution that can disturb not only other utilities
indirectly connected to the polluting device, but also the device itself.
1

From the very beginning, there was an obvious trade-off between efficiency or functional
characteristics of the power electronic system and the EMC performances. One of the major
challenges is to predict, with reasonable accuracy, the noise levels for a given device early in the
design phase. In order to accomplish this task, the designer must deal with more or less empirical
models for the component behavior in various frequency ranges and handle different and specific
simulation methods. EMI should be considered early in design cycle of a product, in order to
decrease expensive post-development modifications for EMI compliance. On the other hand, as
shown in Fig. 1.1, the more the EMI problems are left at the end of the design cycle of the
product, the more the cost and time to market increases. Hence, it is necessary to resolve all the
issues pertaining to EMI at the design stage of the product.

Degree of Freedom

Design

Solution Cost

Prototyping

Production

Fig. 1.1 Cost of EMC solution during the Design Lifecycle [2]

1.2

EMI Generation in Power Converters

Electromagnetic Interference requires three elements to manifest:

A generator of electromagnetic energy (the source of EMI, the culprit circuit);

A transmission of that energy between equipments (the coupling path);

A receptor circuit whose operation is negatively impacted by the transmitted energy (the
victim circuit).

All three elements must be present for EMI to take place remove any one and there can be no
interference. This is illustrated in Fig. 1.2 below.

Fig. 1.2 EMI coupling mechanism block diagram

Fundamentally, EMI requires recognition of the fields caused by rapidly changing currents and
voltages. While these characteristics are quantitatively described by Maxwells equations, we
need only to know that electronic noise may be induced by coupling between circuit elements
through the action of either a magnetic or an electric field. A magnetic field will cause a changing
current in a conductor to induce a voltage in another according to:

Where, M is the mutual inductance between the source and the victim circuit. Fig. 1.3 illustrates
the concept of inductive coupling.

Radiated EM

Near-Field
Magnetic Energy

Far-Field
Magnetic Energy

Fig. 1.3 Inductive Coupling

Similarly, an electric field will cause a changing voltage on a surface to induce a current to flow
in another conductor according to:
Where, C is the capacitance coupling the source to the victim. Fig. 1.4 illustrates the concept of
capacitive coupling.

E-field

Near-field
Conducted Energy

Far-field
Radiated Energy

Fig. 1.4 Capacitive Coupling

These equations tell us that where we have rapidly changing currents (high di/dt) as in the
conductors in series with power switching devices we can expect to see an induced voltage
across other conductors coupled by a mutual inductance. And where there is a high dv/dt as on
the drain contacts of the power switching FETs any parasitic capacitance can couple an induced
current into another path in the vicinity circuits.
More specifically, the switch mode power converter is based on a non-linear action of the
switching devices, such as MOSFETs which are controlled by the pulse modulated signal with
variable or fixed frequency, to step-down or to step-up the input voltage to a desired level. These
switching waveforms contain significant energy levels at the fundamental switching frequency
and its multiple harmonics and therefore generate EMI problems. The EMI is transmitted in two

forms: radiated and conducted. Usually conducted noise is several orders of magnitude higher
than the radiated noise into free space.

1.2.1 Conducted Emissions in Power converters

The conducted noise consists of two categories commonly known as the differential mode (DM)
and the common mode (CM). The differential-mode noise is a current or a voltage noise
measured between the lines of the source. The common-mode noise is a current or a voltage noise
measured between the power lines and the ground. Both the differential-mode and common-mode
noises are taken into account in the EMI filter design and noise diagnosis, with the CM noise
being the dominant factor [3]-[7]. Fig. 1.5 illustrates an example of Common mode and
Differential Mode paths in a power converter.
50 /50 H LISN

CM

1 to 10uF
Decoupling Cap

0.1uF
50

DM

EUT
(SMPS, DC/DC
Converter)

GND
50
1 to 10uF
Decoupling Cap
0.1uF
Neutral

CM
CM
50
CM and DM add vectorially
EMI (Line) = CM + DM
EMI (Neutral) = CM - DM

Spectrum Analyzer

Fig. 1.5 CM and DM paths in power converter

R_load

The contributions of these two modes are inherent to the basic operation of the switching power
supply. The action of the internal power switches causes fast di/dt rates in the differential current
at both the input and the output of the power supply. As illustrated in Fig. 1.6, the input filter
ideally would decouple any high frequency noise which is external to the power supply.
However, residual ripples and switching spikes exist as a differential mode noise source with
bidirectional current flowing into input port and exiting from the output port. On a Printed Circuit
Board (PCB) the DM noise resides in the trace routing, parts placement, current paths that can be
translated into radiated emissions in free space once the current paths meets the criteria of a loop
antenna.

R_load

I_DM
I_DM
I_DM
DC

I_DM

Main Switch

I_DM
I_DM

Pulse Control
signal

Fig. 1.6 Differential Mode currents is generated by the normal switching action of the MOSFET

There are also sources of rapidly changing voltage within the power supply which can couple
noise through parasitic capacitance to earth ground, some of which are shown in Fig. 1.7. This
type of noise in the ground path, which can be seen as common mode noise on all power supply
terminals, is measured with respect to ground.

DM_filter

CR1

T1

C_out

R_load

D1
C_bulk
DC

Main Switch

Pulse Control
signal

Stray Capacitance Induce

Currents to Chassis

Chassis Ground

I_CM

I_CM

Chassis Ground

Fig. 1.7Common Mode currents coupled to chassis through stray capacitance

So far we have mentioned the sources of EMI in the SMPS that can be generated through
capacitive and inductive coupling to the ground chassis, in the form of differential and common
mode. However, this is not the only locations of the EMI source where high dv/dt signals might
introduce ground noise. Heat sinks are also potential problem area, as safety requirements
typically do not allow heat-sinks to be charged to a high voltage potential when fault condition
occur. Hence, they must be grounded to chassis.
Another potential induced noise source is the transformer primary to secondary coupling. This is
a CM noise that can be returned back to the line impedance stabilization network (LISN) through
the chassis, creating a large current loop. The additional sources of CM noise that can be found in
DC/DC converters are noise coupled through the stray capacitance of the output rectifier to the
heat-sink and the output rectifier to the transformer core.
A noise path through the heat-sink stray capacitance is illustrated in Fig. 1.8.

50 LISN

CM noise path

CR1

T1

C_out

R_load

D1
CD_HS

C_bulk
DC

Main Switch

Pulse Control
signal

Heat Sink

Chassis Ground

Chassis Ground

Fig. 1.8 CM noise due to the Drain heat-sink stray capacitance

1.2.2

Radiated Emissions in Power Converters

In an electronic apparatus or circuit such as found in switch mode power supplies, EMI energy
can be mutually interchanged between radiated and conducted form. For example, EMI is initially
generated in a conducted form through an interconnecting wire or PCB trace. This conducted
energy creates an electromagnetic field around the conductor according to Faradays law. If there
is then mutual inductance or capacitive coupling to another conductor, then the radiated energy is
transformed back to conducted noise in the adjacent conductor. However, the RF energy which
propagates along the trace at specific length could become a radiating loop antenna. Thus, the
circuit becomes susceptible to external EMI, according to the antenna reciprocity theorem.
Typical radiated emission scenario is illustrated in
Fig. 1.9.
As for the radiated emission in the power converters, it depends on the switching frequency
employed in the circuit. Power converters, operating below 500 KHz switching frequency, tend to
have their noise bandwidth up to 16 MHz which is not a concern in terms of EMC standards

compliance (30 MHz to 1GHz). However, it is a problem for the internal circuit operation of the
power converter [8]-[10].

T1
Clamp/Reset

CR1
C_out
R_load
D1

C_bulk
Main Switch

DC

Naux
Rg

in
Fr
gi
ng
fie

To PWM VCC

Fr
in

gi

ng

fie

ld

ld

Fig. 1.9 Possible loop areas for radiated emission in SMPS

From the schematic diagram of
Fig. 1.9, there are several current loops that can be a source of radiated emissions. These are
namely:
1. Main switch power loop
2. Transformer reset/Clamp loop
3. Output rectifier loop
4. Gate drive loop
5. Auxiliary Vcc loop
6. Output coupled inductor loop

1.3 EMC Regulations and Standards

Interference problems are not new. Since the beginning, radio engineers have perceived the
difficulties encountered when trying to make ground connections to the chassis of different

10

systems. All these are manifestations of EMI and demonstrate the need to design systems which
are compatible with their electromagnetic environment. There are two aspects to EMC. First,
systems must be designed so that they do not emit significant amounts of unintended
electromagnetic (EM) radiation into their environment. This aspect is described as emission and
may be divided in turn into conducted and radiated emission. Second, systems must be capable of
operating without malfunction in their intended environment. This aspect is described as
immunity, or alternatively, as susceptibility. Hence, all EMC analyses and design techniques aim
to address these two aspects using circuit-based and field-based experimental, analytical, and
numerical techniques.
It is important to realize why EMC has become so important in recent years. As is usual in such
cases, there are several reasons: Modern design relies increasingly on the processing of digital
signals, i.e., signals of a trapezoidal shape with very short rise and fall times. This gives them a
very broad frequency spectrum and thus they are more likely to interfere with other systems.
Most modern designs rely on clocked circuits with clock frequencies exceeding 2 GHz. This
implies very short transition times and also the presence of several harmonics well into the
microwave region. Such a broad spectrum makes it inevitable that some system resonances will
be excited forming efficient antennas for radiating EM energy into the environment and coupling
to other systems. Voltage levels for switching operations have steadily decreased over the years
from hundreds of volts (vacuum tubes) to a few volts in modern solid-state devices. This makes
systems more susceptible to even small levels of interference. We make a much greater use of the
EM spectrum as, for instance, with mobile phones and other communication services. Equipment
is increasingly constructed using small cabinets made out of various plastics and composites in
contrast to traditional design, which used metal (a good conductor) as the primary constructional
material. This trend meets the need for lighter, cheaper, and more aesthetically pleasing products.
11

However, poor conductors are not good shields for EM signals, thus exacerbating emission and
susceptibility problems. Miniaturization has become a trade option, as smaller and lighter mobile
systems are required. This means close proximity between circuits and thus greater risk of intrasystem interference (cross talk). We rely increasingly on electronics to implement safety critical
functions. Examples are airbags systems for cars, automatic flight controls in aircraft, etc... It is,
therefore, imperative that such circuits be substantially immune to EMI. In addition, military
electronic systems are continuously exposed to very hostile EM environments.
These points illustrate the engineering need to design electromagnetically compatible systems. To
ensure that this compatibility exists, a relatively new engineering discipline, namely
electromagnetic compatibility (EMC), has evolved. EMC is defined as the study and analysis to
resolve electromagnetic interaction problems in the field of electrical engineering. EMC is
branched into two distinct categories: EM emissions and EM susceptibility with alternating
medium of propagation. The two categories are fundamentally reciprocal.
Fig. 1.10 illustrates the areas of EMC fields.

Fig. 1.10 Fields of EMC

12

It is important to mention that EMC is a system level consideration. However, all electronic subcomponents must undergo compliance testing. This does not imply that compliant subcomponents mean that the system is EMC compliance. So it is common to test for
electromagnetic noise generation from a power supply as a stand-alone box, and also the ultimate
standards that have to be met apply to the system as a whole with the power supply as an internal
component or subsystem.
International standardization bodies have recognized for many years the need to define standards
and procedures for the certification of systems meeting EMC requirements. These are the
responsibility of various national standard bodies and are overseen by the International Electrotechnical Commission (IEC).
Furthermore, various regulations have been imposed by government authorities to limit the level
of the EMI emissions. These regulations have been developed as EMC standards and are a
condition to product marketing and circulation. A product is considered to be compliant when the
limits applying to that product are not exceeded. There are many ways of achieving EMC
compliance, using different suppression techniques. These techniques have their own advantages
and limitations. These advantages are measured based on their EMI attenuation and their
drawbacks are evaluated based on their impact on the power converter overall size , efficiency,
and cost. Conducted Interference filtering technique, either passive or active is the most used
technique due to its attenuation performance, regardless of the size and the cost factors. However,
stringent power converters specification and cost requirements, make these EMI solutions less
desirable or the performance is compromised with the cost and size. A combined active and
passive filtering technique (hybrid) seems to be the solution for size and performance to a certain
extent. The main purpose of the hybrid EMI filter is to reduce the size of the passive filter, by
splitting the EMC frequency spectrum for the conducted emissions in two allocations. The low
13

frequency allocation is targeted by the active filter whereas the high frequency allocation is
assigned for the passive filter. The combination of these filters covers the whole EMC spectrum,
from 150 KHz to 30 MHz, achieving a significant overall attenuation in the conducted emissions,
while reducing the passive filter size and increasing the performance.

However, there are

limitations pertaining to hybrid technique. This can be translated in an increase in components

counts and losses in the filter inductor. The active device is limited in terms of frequency
bandwidth at unity gain. The active device or the OPAmp exhibits an inherent phase error in the
sensed signal at higher frequency which has a direct impact on the performance degradation of
the EMI filter. In the hybrid EMI filter, the size reduction is achieved by reducing the capacitive
component only, the inductive element can not be reduced since it is part of the power path and
must carry the rated current of the converter. More details concerning the passive and the active
EMI reduction techniques are provided in the next chapter.

1.4 Thesis Objectives

The scope of this research deals with the subject of satisfying the EMC requirements in terms of
conducted EMI noise emissions at the input leads of a power converter. The research is focused
on the design analysis and implementation of a Digital EMI filter as a novel solution for
conducted EMI mitigation using a Digital Signal Processor (DSP) and/or a Field Programmable
Gate Array (FPGA) based circuitry to overcome the issues associated with the analog active EMI
filtering technique and to replace the conventional passive EMI filter. The proposed techniques
reduce significantly the size and the cost as well as improve the overall performance of the input
EMI suppression.
The following are the objectives of this thesis:

1. Development of a digital active EMI filter with DSP-Based implementation as a stand-alone

EMI solution
14

2. Development of a digital active EMI filter using concurrent FPGA based implementation.
3. Integration of the proposed EMI solution in a digital controller of a grid-tied PV inverter as
an industrial application.
i. Analysis and modeling of the micro-inverter
ii. Verification of the micro-inverter control loop stability

4. Development of a DC-DC converter prototype for electric vehicle battery charger that
consists of the proposed EMI solution integrated into the digital controller of the power
converter.
i. Design of a digital control compensator including the proposed EMI solution
ii. Verification of the control loop stability of the converter

5. Experimentations and simulations to validate the proof-of-concept on three converters types,

namely a DC-DC, AC-DC, and DC-AC converter.

1.5 Thesis Outline

This thesis is partitioned as follows: Chapter 1 starts by stating the EMC background and
definitions, a complete section showing the different sources of EMI generation in power
converters and their coupling paths. Another section provides an introduction to EMC regulations
and standards pertaining to power converters. Chapter 2 presents a review of different existing
EMI suppression techniques for conducted emissions, using analog active and passive circuits.
Most of these techniques employ passive components such as inductors and capacitors to divert
the invading interference noise from polluting auxiliary equipment attached to the power
converter or in close proximity. Other techniques such as soft switching and spread spectrum
frequency modulation techniques are converter-specific techniques and they can only be
considered as add-on techniques besides the filtering techniques. In Chapter 3, a novel sequential
15

EMI suppression technology, based on Digital Signal Processing (DSP) approach is introduced.
This method extracts the interference noise from the input leads of the power converter using a
sensing circuit, the noise is then fed to an Analog-to-Digital Converter (ADC) to digitize the
noise signal. The digital form of the noise signal is then fed to the DSP core for further
processing. The output of the Digital-to-Analog Converter (DAC) is an image representation of
the original noise signal which is used to suppress the incident noise in the power converter. This
method of suppression does not employ any passive components as compared to the passive
filtering method which requires both bulky capacitors and choke inductors. In chapter 4, a new
FPGA-based approach to suppress conducted EMI emission has been presented. This method
uses a Very high speed integrated circuit Hardware Description Language (VHDL) algorithm to
process the noise signal with a negligible delay in the phase. Both approaches have been
compared in terms of their EMI attenuation performance. The analysis and modeling of the
proposed methods are presented. The simulation and experimental verification to validate the
proof-of-concept have been laid down. In addition, two industrial applications have been selected
as a test bed. These are namely, the solar micro-inverter application in Chapter 5 and Electrical
vehicle (EV) DC/DC power converter in Chapter 6. Finally, Chapter 7 summarizes the
contribution of the achieved milestones and provides guidance for future research directions.

16

Chapter 2
Review of EMI Control techniques in Power converters

2.1 Introduction
For cost-effective design approach, EMC should be considered at early stage of the power
converter design. Hence, designing to achieve EMC involves a series of measures to reduce
emissions at the source. This can be done by identifying and minimizing the coupling paths and
diverting CM noise away from ground. As product development progresses from the design stage
to testing the prototype and mass production, the range of available noise suppression techniques
decreases steadily. As the first step, the power converter should be analyzed for its EMI
generation to determine the required measures of suppressions that can be implemented at the
design stage without the need for passive EMI filters. The later, are not cheap and have a direct
impact on the stability characteristics of the power converter, adding the cost and the PCB real
estate.

2.2 Basic EMI Suppression Techniques

As already mentioned in previous sections, fast rise and fall times of the switching pulse,
introduce a very wide spectrum of frequencies. Hence the slowest logic family used should be
compatible with design requirements. This can be translated into lower switching frequency with
slower switching device. Another aspect of CM noise reduction that needs to be addressed at the
design stage of the power converter is the PCB layout. A well designed PCB results in cost
saving, weight and size. For example, the first step in designing an SMPS circuit layout is careful
selection of the EMI-sensitive components such as the PWM controller chip or FPGA devices, if
digital signal is part of the control circuit. The primary goal is to prevent electromagnetic
coupling between these circuits, and also coupling of switching current carrying conductors to
17

ground. These components should be placed as close to each other as possible. The PCB should
be laid out in such a way to minimize loop area of return current paths. A DM coupling via a loop
antenna leads to unwanted noise radiation and will jeopardize the circuit immunity to external
noise. Hence, grid grounds and ground planes should be always added as additional layers to the
PCB design. With the ground plane the return current flows directly underneath the PCB tracks at
higher frequencies. Power converters are not sealed box products. They need to be supplied by a
source power so that they can convert power to the specific load. This is done through a power
cable. This cable at specific length becomes an antenna radiating CM noise. This CM noise can
be prevented by cable filtering and by additional ground planes during PCB design. Shielding is
another technique to suppress radiating magnetic fields. This technique can be applied to
magnetic components such as transformers and power inductors to contain the fringing fields.
However, this method is very expensive when used for this purpose and magnetic fields are very
difficult to shield. Thus it is better to combat the problem at its source by minimizing current
loops and containing magnetic fields. This leads to the discussion of the two major circuit
elements that are responsible for most CM EMI generation namely the heat-sink and the
transformer.

2.2.1 Reducing Heat-sink Stray Capacitance

In switch mode power supplies, the main switch MOSFET is generally mounted on a heat-sink
for thermal dissipation. A significant capacitance can be formed between the heat-sink and the
drain leg of the MOSFET switch. This stray capacitance plays a major role in CM noise
generation. As shown in Fig. 2.1 the insulation material between the heat-sink and the drain pin
of the MOSFET, can be as high as 100pF, which is enough to couple most of the harmonics of
the switching waveform into the ground plane as a CM noise current (

18

). This CM noise

current can be converted into CM voltage noise in the artificial line impedance (LISN) and part of
this current can produce a radiating E-field due to the large return path that acts as a loop antenna.
Cr1

LISN

Cout

Rload

50
GND
MOSFET
N

50

Icm

Ground

Fig. 2.1 MOSFET Drain to Heat-sink stray capacitance, the CM current returns through the LISN
impedance (large return path)

One of the most efficient solutions for suppressing the CM noise voltage is achieved by reducing
the value of the stray capacitance built between the MOSFET and the heat-sink. Three methods
are known; the first one is to float the heat-sink from ground and alternatively to tied it to source
pin of the MOSFET as shown in
Fig. 2.2. This ensures that the CM noise current flowing through the stray capacitance C d_HS, is
kept confined within the primary circuit rather than returning through the LISN. However, this
type of referencing is not acceptable by safety standards, should the heat-sink become live after a
short circuit condition.

19

Cr1

LISN
Icm

Cout

Rload

50
GND

CD_HS
MOSFET

50

Fig. 2.2 Reducing the CM current by floating the heat-sink

The second method for reducing the stray capacitance formed between the Drain of the power
MOSFET and the heat-sink is to apply a screen (shield) between the drain and the grounded heatsink. The shield is to be insulated both from the MOSFET drain and the heat-sink and it should be
made from good thermal conductivity material. One end of the shield is connected to the
MOSFET source pin as illustrated in Fig. 2.3. This method has similar effect as the one in

Fig. 2.2 except that in this method the heat-sink is grounded as per safety standards requirements.
The CM current return path is confined in the primary circuit, because the impedance between the
shield and the source of the MOSFET is very low compared to the impedance between the heatsink and the ground.
Cr1

LISN
Icm

Cout

50
GND

Cstr1

Cstr2

MOSFET
N

50

Zs <<

GND

Fig. 2.3 Reducing the CM current by screening/shielding the MOSFET

20

Rload

The third method of reducing the CM current path and bypassing the LISN is using LC circuit.
This method uses an inductor between the heat-sink and ground and connects a capacitor between
the heat-sink and the source pin of the power MOSFET. This circuit operates as follows: at high
frequency the inductor acts as an open circuit and the capacitor as a short circuit. At DC level, the
inductor acts as a short circuit and the capacitor as an open circuit. In this way the high frequency
CM noise current takes the path of least impedance while the heat-sink is kept referenced to
ground.
Fig. 2.4 illustrates the concept.
Cr1

LISN
Icm

Cout

Rload

50
GND

Cstr1
MOSFET

50
ZL=2fL
Zc=1/2fC
GND

Fig. 2.4 Reducing the CM noise current by using LC circuit

2.2.2 Reducing Transformer Stray Capacitance
In switched mode power converters, the power transformer parasitic capacitance is the main
culprit for CM EMI generation. Most of the power converters are designed with the transformer
core and the secondary circuit referenced to ground as an added safety feature. However, this
configuration will aggravate the conducted EMI problem at high dv/dt, creating a CM noise
current that finds their path through the LISN. This can be seen in Fig. 2.5.

21

Cr1

LISN

Cout

Rload

50
GND
Ccore
MOSFET
N

Cp-s

50

ICM

ICM

GND

Fig. 2.5 CM current generation through core and primary-to-secondary stray capacitance

To reduce the inter-winding and the transformer core stray capacitances, two methods can be
applied; first referencing the core to the DC-link of the power circuit, will provide a shorter path
to the CM current and keep it confined in the primary circuit. The layout of this configuration is
shown in Fig. 2.6.
Cr1

LISN

Cout

Rload

ICM
50
GND
Ccore
MOSFET

50

GND

Fig. 2.6 Transformer core is referenced to the DC-link, shorter current path

As for reducing the unwanted inter-winding stray capacitance, an electrostatic shield can be
placed between the primary and the secondary windings and referenced to the DC-link, as
illustrated in Fig. 2.7. This approach will divert the CM noise away from the ground and provide a
shorter return path. This is adequate solution for low output voltage converters.
22

Electrostatic shield

Cr1

LISN

Cout

Rload

50
GND
MOSFET
N

50

Stray capacitance

GND

Fig. 2.7 shield connection between the primary and the transformer core

For higher output voltages, the stray capacitance between the shield and the secondary winding
becomes significant and may couple CM noise currents into the secondary side of the power
converter. To circumvent this current path, a secondary shield is required. This configuration is
shown in Fig. 2.8.
Electrostatic shield
Cr1

LISN

Cout

Rload

50
GND
MOSFET
N

50

Stray capacitance

GND

Fig. 2.8 shielding primary and secondary winding

2.2.3 Reducing Transformer Stray Inductance

In designing the power transformers of the SMPS, the leakage inductance between primary and
secondary windings can be factor degrading the power converter overall efficiency. Furthermore,
23

the leakage inductance generates a transverse magnetic field between windings. Depending on the
coupling factor of the magnetic transformer, some of this field may be coupled to the transformer
core, and the rest acts as a magnetic dipole antenna fringing out into surrounding space with an
intensity which decays as the cube of the distance as derived from Maxells field equations. To
suppress the fringing field, a change in the winding procedure to interleave the primary as shown
in Fig. 2.9, will produce two leakage fields with opposite polarities which ultimately cancel each
other. Due to the skin effect at high frequency, it is preferable to use different types of magnet
wire such as Litz wire, or bifilar windings. This will result in significant attenuation of radiated
emissions.
Another method of reducing the fringing magnetic fields from a transformer is the use of a
conductive copper foil strapped around the transformer. The copper foil provides a path for the
eddy currents that result from the leakage inductance magnetic dipole. The current flowing in the
flux strap creates an opposing magnetic dipole which tends to cancel the original field in the
vicinity of the power transformer.
Inductors are also potential generators of stray magnetic fields caused by the side gaps of the core
which are outside the coil winding. By changing the core geometry so that the gap is in the center
leg, the flux will be fully contained within the winding, hence, reducing the source of EMI
radiation.

24

Fringing Fields

Primary

Secondary

Core

Primary

Coupled Fields

Primary

Secondary

Primary

Secondar
y

Primary

Primary

Secondar
y

Core

Coupled Fields

(a)

(b)

Fig. 2.9 Transformer windings configuration; (a) single windings, fringing fields; (b) split windings
creates leakage fields that tend to cancel

2.3 Passive Analog Filtering Technique in Switch Mode Power Converter

Passive EMI filters were first introduced in 1950s to respond to the EMC legislation set forth by
the International Telecommunication Convention (ITC) to suppress EMI caused by electronic
equipment. This legislation was reflected into EMC standards which limit the level of EMI
emissions from the electronic equipment. Since then passive EMI filters have evolved into
different sizes and shapes to comply with the continuously changing and challenging limits of the
EMC standards [11],[12].
The idea of an EMI filter is to block, or bypass the interference noise, which can be achieved by
introducing high impedance (inductor) into the path of the interfering currents and bypassing
them to ground through a low impedance (capacitor) path. This technique is called passive
filtering, since it uses only passive components in the circuit. This type of filters is simple and
cost effective in some applications; however, in application where stringent noise reduction is
required, the size, weight, temperature and reliability can present a significant design challenge.
25

In this section, the conventional passive EMI filters are introduced. The circuit configuration and
design considerations in terms of mismatch impedances are discussed.

2.3.1 Passive Input EMI Filter

In order to comply with International EMC standards, switch mode power converter circuits using
high-frequency switching devices, such as MOSFET, must carry a proper EMI filter to avoid the
injection of excessive conducted noise towards the power utility network, in the frequency range
of 150 KHz 30 MHz The desired noise attenuation is achieved by means of suitable passive
EMI filter connected in the supply section of the switch mode power converter, as shown in Fig.
2.10.
Mains

EMI FIlter

Power Converter
L

Zs
T1

CR1

R_load
C_out

C_bulk
Cx

D1

AC

Main Switch
Zg

Pulse Control
signal

L
Cy

Cy

Chassis Ground

Fig. 2.10 Schematic diagram of an input EMI filter for SMPS

A passive EMI filter is essentially an inductor-capacitor (LC) network designed to attenuate high
frequency conducted interference while at the same time allow the low frequency operating
current to pass through unaffected. The filtering action comes from the impedance characteristics
of the inductor and capacitor. The impedance of an inductor increases with frequency; while the
impedance of a capacitor decreases as frequency increases. This can be expressed by equations
(2.1) and (2.2) respectively.

26

X L 2fL
XC

(2.1)

1
2fC

(2.2)

It is important to note that the basic approach to EMI filtering is to use a set of series inductors
and parallel capacitors to divert the flow of EMI currents away from the auxiliary circuit. This is
done by using the high inductor impedance to prevent the flow of the EMI noise from flowing in
the circuit and the low capacitor impedance to divert the EMI noise towards the ground. The EMI
current flows through the path of the least impedance.
Hence, filtering common-mode EMI requires capacitors connected to ground. These capacitors
are referred as Y capacitors and safety regulations limit these capacitors to relatively low values.
Consequently, high values of inductance are essential for effective filtering. However,
differential-mode filtering requires capacitors across the input lines. These capacitors are referred
as X capacitors.

2.3.2 Basic Circuit Configurations

The basic passive EMI filter circuit configurations are shown in Fig. 2.11. The -circuit
configuration is the most common one. However, in high performance applications, multistage
circuit configurations are also used. Configurations with more than three stages are not
recommended due to their excessive space and power losses.
To suppress the EMI noise in both positive and negative lead, one of the selected filter circuits of
Fig. 2.11 must be inserted in each input lead of the power converter. Therefore, the two-port
network EMI filter becomes three-port network with the ground lead added to the filter circuit, as
shown in Fig. 2.12. In this configuration, both common-mode (CM) and differential-mode (DM)
noises can be attenuated.
27

L1

C1

L1

C2

L2

L2

L3

C2

C1

C3

Fig. 2.11 Basic passive EMI filter circuit configurations: (a) single stage LC-circuit, (b) circuit, (c) T-circuit, (d) Multistage LC-circuit

Phase

Y
LOAD

Neutral

Earth GND

Fig. 2.12 Basic EMI filter Configuration for CM and DM attenuation

28

The passive EMI filter can be evaluated by its insertion loss which can be defined as the ratio of
the generator voltage and the measured voltage when the filter is inserted between the generator
and the measuring instrument as shown in Fig. 2.13.
The insertion loss (IL) can be generally expressed in terms of voltages as:

U
R2
IL 20 log 0

U m R1 R2

(2.3)

Where: U0 is the generator voltage and Um is the measuring instrument voltage when the filter
under test is inserted in the circuit. R1 is the generator source impedance, and R2 is the measuring
instrument input impedance.
In practice, R1 and R2 should be equal; in this case equation (2.3) can be simplified as follows:

U0
IL 20 log
2 U m

(2.4)

The attenuation is a transfer function that reflects the performance of the filter at each frequency
with the real circuit impedance, rather than assumed impedance as in the case of the insertion loss
measurements. To respond to the challenges of low profile DC/DC converters and their fast
growing switching frequency (>1MHz), it is important to consider the following parameters: the
size (small footprint), performance (at least 30 dB attenuation across the frequency spectrum) and
cost. The first two parameters are circuit related and provide a lot of room for research on the
combination of the passive and the active EMI filters as an integral part in an open frame
configuration of DC/DC type converter.

29

Measuring Instrument
(R1=R2=R)

Signal Generator
R1

R2

U0

U0
2

(a)
Measuring Instrument

Signal Generator
R1

Filter Under Test

U0

R2

Um

(b)

Fig. 2.13 Insertion loss (IL) measurement: (a) Reference circuit, (b) Filter under test
inserted
2.3.3 Source and Load Impedance Variations
One of the main problems in designing passive EMI filters for power converters is caused by the
arbitrary selection of the source and the load impedance values. This means that there is no
guarantee that the arbitrary selected values that are supposed to reflect the source and the load
impedances are valid values, given the fact that a typical EMI filter is to be installed in power
converters which can be used in variety of applications and supply networks. The high frequency
impedance of the DC/DC converter which represents the noise source varies widely, depending
on the converter circuit topology, circuit layout, types of MOSFET and the switching frequency.
Furthermore, the load impedance which is the supply impedance of the passive EMI filter is even
less predictable than the source impedance, because the load impedance depends on the facility
network from which the power converter would be supplied and varies with the number of
30

electrical equipment connected to the supply network [13]-[19]. Nonetheless, modeling the power
converter in terms of its EMI noise, as shown in [20], is an essential step in designing the proper
EMI filter.

2.3.4 Passive EMI Filter Design Procedures

The basic procedures of designing and selecting the components of the passive EMI filter have
been reported in [21]-[25]. Depending on the equivalent circuit of the passive filter, one can
consider the following important parameters such as the circuit impedance, the switching
frequency of the converter, the fundamental ripple current and the rise time, the fall time of the
fundamental pulse of the MOSFET switch and finally the cut-off frequency of the filter.
Fig. 2.14 shows the equivalent circuit of a typical passive EMI filter; the purpose of the damping
resistor Rd is to reduce the output impedance of the filter at the cut-off frequency. The damping
capacitor Cd across the DC bus prevents the problem of voltage overshoots and ringing at the
input of DC/DC converter. The input of the DC/DC converter is represented by impedance Rin.
The impedance of the passive EMI filter is defined as follows:

Rf

Z2

Lf
Z1

Cf

Input
DC
Voltage

Z3
Rd

ESRcf
Cd

ESRcd

Fig. 2.14 Single ended CM equivalent circuit diagram

31

Rin
(DC/DC
converter
input side)

Z1 R f sL f

(2.5)

Where: Rf and Cf are series resistance and filter inductance respectively

Z 2 ESRC f

1
sC f

(2.6)

Where: ESRc is the equivalent internal series resistance of the filter capacitor

Z3

1
ESRCd Rd
sCd

(2.7)

Then the equivalent impedance of the EMI filter at the input of DC/DC converter is given by:

Z eq Z1

Z 3 Z 2 Rin
Rin Z 3 Rin Z 2 Z 2 Z 3

(2.8)

The values of damping resistor and energy-storage capacitor can be selected according to:

Rd

Lf

(2.9)

Cf

Cd 2 C f

(2.10)

The input and the output impedances of the passive EMI filter are important parameters that must
be known when connecting the filter to the input side of the DC/DC converter. This condition sets
a boundary requirement between the EMI filter and the DC/DC converter in terms of input/output
impedances [25]. The input EMI filter can adversely affect the performance of the DC/DC
converter which can be driven into continuous oscillations and instability. Thus, the input passive
EMI filter should be designed with the issue of the impedance compatibility in mind. Fig. 2.15

32

shows the interface impedance of the input passive EMI filter with the input DC voltage bus and
the DC/DC converter.

Input Interface

Input DC Bus

Output Interface

Passive EMI Filter

ZDC

ZIF

DC/DC Converter

ZOF

Zin

Fig. 2.15 Interface impedances of the passive EMI filter

To ovoid the issue of interaction of the EMI filter with its load converter, the following
input/output impedance compatibility requirements must be satisfied:
1. At the interface between the DC source and the input filter:

Z DC Z ' IF

(2.11)

Where, ZDC is the output impedance of the input DC source, and ZIF is the input impedance of the
filter with the output port open
2. At the interface between the input filter and the DC/DC converter:

Z 'OF Z in

(2.12)

Where, ZOF is the output impedance of the filter with the input port shorted, and Zin is the input
impedance of the DC/DC converter.

33

Since impedances ZDC and Zin are system dependant and can not be known, the two impedances
ZIF and ZOF can be considered as design parameters and can be calculated or measured.
The input impedance can be selected as high as possible to minimize interactions with the input
DC bus, and the output impedance can be selected as low as possible to minimize interactions
with the loop gain of DC/DC converter.

2.3.5 Performance and Limitations of the Passive EMI Filter

Passive filtering can be considered as the most economical solution in many applications, in
particular where space and weight do not constitute a prime obstacle in the design specifications.
The availability of the components and the design simplicity permit the manufacturers to
integrate passive filters in almost all switch mode power converters. However, their performance
is strongly dependent on the source and the load impedances which are most of the time assumed
quantities in the case of the Off-the-Shelf products and they are measured quantities in the case of
integrated design. In addition, to prevent resonance of the LC filter, a damping resistor must be
introduced in the circuit. This will reduce the efficiency of the power converter and result in a
permanent current circulation at no-load condition. One of the features that makes the passive
EMI filter a desirable solution is their performance at higher frequencies (> 10MHz). This is due
to the series inductive impedance which is directly proportional to the frequency. Furthermore,
for safety and shock hazards, the total capacitance is limited to a maximum value so that the
capacitor leakage current finds its way to the chassis ground.
These limitations are usually very strict, and it can be very difficult to meet them while achieving
the insertion loss objectives. Therefore, in certain application where the size, weight, thermal
dissipation and efficiency are crucial design requirements, the passive filter simply can not be an
appropriate contingent.

34

2.4 Zero Voltage/Soft Switching (ZVS) Techniques

It has been reported [27]-[37] that converters employing the Zero Voltage Switching (ZVS)
techniques can achieve high power density, high efficiency, and low switching losses in Switch
mode Power supplies (SMPS) while operating at a constant frequency. In addition, this topology
can contribute to less conducted EMI emissions to a certain extent.
To quantify the effect of the ZVS technique on the conducted EMI attenuation, a simulation
comparison of the EMI profiles of two buck converters, employing the ZVS switching technique
and the Hard Switching (HS) method respectively, is carried out in [38]. It is concluded that the
difference in EMI emissions between the two is insignificant. In fact, the ZVS circuit may be
detrimental in terms of EMI emissions, if the auxiliary circuit providing the ZVS is not properly
laid out on the printed circuit board (PCB).
The ZVS mechanism is achieved by the lagging current produced by the resonance circuit shown
in Fig. 2.16 to make the switching device transition at zero voltage [39]. This is also known as
soft switching mechanism. This helps reduce the amount of high frequency ringing generated in
the circuit since both fast voltage transition dv/dt across the main switches S1&S2 and fast
current change di/dt in the diode D1&D2 in Fig. 2.16 are avoided. A direct comparison between a
ZVS circuit and a HS circuit is suggestive because both circuits share the same power, circuit
topology and both are operated at a constant frequency.

35

CS1
D1
S1

Series resonant Circuit

(Soft switching)

vS1 -

Ls

Cs

iS2

gS1

Vin

SR1

ir

iS1

S2
gS2

Tx

gSR1

iSR1
Co

CS2 +
vS2
-

+
R L Vo
-

D2
SR2

gSR2

iSR2

Fig. 2.16 zero voltage transition (ZVS) circuit implemented in a DC/DC converter

2.4.1 Simulation Results

In order to carry out the above mentioned comparison, the circuit of Fig. 2.16 was simulated
using OrCAD PSPICE simulation software. The circuit is a series resonant buck converter with
single output. The rectification is done using synchronous rectifiers to decrease the losses and
improve the efficiency. The input voltage is kept constant at 48Vdc and the switching frequency
is selected to be 500 KHz. The resonant circuit is designed to provide a ZVS of the main
MOSFETs switches.
First, the circuit was simulated at nominal load condition including the ZVS circuit. A second
simulation was conducted on the same circuit conditions, without the ZVS circuit. The resulting
waveforms for the ZVS and HS are shown in Fig. 2.17 and Fig. 2.18 respectively. The EMI
spectrum of each circuit is shown in Fig. 2.19 and Fig. 2.20.

36

60

40

Vds1
20

Vgs1
0

-20
475 . 6us

475 .8 us

476 .0 us

476 .2 us

476 .4 us

476 .6 us

476 .8 us

477 .0us

Tim e

Fig. 2.17 ZVS Transition in main switch S1

54.7

40.0

Vds1
20.0

Vgs1
0

- 18.5
475.900us

476.000us

476.100us

476.200us

476.300us

476.400us

476.500us

476.600us

476.700us

476.800us

Time

Fig. 2.18 HS Transition in main switch S1

100mV

10mV

100uV

1.0uV

150KHz

300KHz

1.0MHz

3.0MHz

10MHz

Frequency

Fig. 2.19 EMI profile with Soft Switching circuit

37

30MHz

100mV

10mV

100uV

150KHz

300KHz

1.0MHz

3.0MHz

10MHz

30MHz

Frequency

Fig. 2.20 EMI Profile with Hard Switching

The simulation results reveal the difference between the HS and ZVS converters with respect to
their EMI conducted profiles. It is found that the advantage of using the ZVS circuit as an EMI
solution is not significant. It slightly contributes to the EMI attenuation especially at higher
frequency where the CM noise dominates. However, at lower frequency, it exhibits an increase in
the fundamental peak and the first few harmonics, up to 3MHz.
To support what has been claimed in the section above, a comparison between two boost
converters, one employing ZVS technique whereas the other one uses hard switching method, is
provided. It is concluded that the figure of merit in terms of EMI conducted emissions is
insignificant and can be quantified to few dB only and can be even negligible at low frequencies.
This is illustrated in the experimental waveform shown in Fig. 2.21 below. Hence, the ZVS
method cannot be regarded as an EMI solution but rather as an option to slightly improve the
conducted emissions, if and only if the resonant converter topology is sought to be suitable for a
specific application. In fact, under EMC standards, 2 or 3dB is considered an uncertainty margin
for measurements; hence it is not worth it to implement a ZVS circuit just to accomplish the EMI
attenuation of a couple of dB, especially at lower frequencies.
38

Fig. 2.21 EMI Profile with ZVS and HS [38]

2.5 Spread Spectrum Frequency modulation techniques (SSFMT)
As weve seen in the previous sections, the major contributor to the EMI issue in an electronic
device is the fast pulsating rate of the switching voltages or currents. This is in the case of the
power converters, where the high frequency pulse is generated in the controller to drive the gate
of the MOSFET switches of the converters. On the other hand, in digital circuits, the high
frequency pulse signal is the reference clock of the entire circuit. The clock frequency can range
from few Megahertz to hundreds of Megahertz, depending on the circuit application. Having said
that, the SSFMT is used in both digital and power applications to mitigate the conducted EMI and
radiated EMI respectively.
The concept of spectrum spreading is not new, it has been used in communication systems for
broadcasting FM radio signals. However, the application of this concept in the field of digital
circuits goes back to K.B. Hardin who established in 1994 the principle known as spread
39

spectrum clock generation (SSCG) method [40]-[43] to reduce the radiated emission. This
method is based on frequency modulating (FM) the system clock signal which results in power
spectrum density (PSD) with uniform sideband harmonic amplitudes. The energy of each discrete
frequency harmonic is spread over a wider bandwidth, thus reducing the amplitude of the
harmonic contents of the pulse signal.
Fig. 2.22 illustrates the effect of the SSCG technique on a single harmonic of a clock signal.

Amplitude

Frequency

Frequency

(a)

(b)

Fig. 2.22 Effect of SSFM technique on an nth harmonic of a clock signal; (a) un-modulated
clock; (b) modulated clock
As an example of signal modulation, consider a modulated signal

which can be written as:

(2.13)

Where:

is the instantaneous amplitude of the signal and

is the instantaneous phase

angle which is varied as a result of the modulation. In terms of frequency, this can be expressed
as:
(2.14)
Where:

is the frequency of the carrier signal,

is the modulating signal with the frequency

and K is the modulation index. The peak frequency deviation

the sideband harmonic centered at

and it is given by:

40

represents the variation of

(2.15)
The key to maximizing the attenuation of a clock signal fundamental and its harmonics is the type
of the modulating waveform, either being a sine wave, triangular or saw tooth as illustrated in
Fig. 2.23. Optimum attenuation can be achieved using triangular modulating waveform
Fig.2.23(c), compared to sinusoidal waveform Fig.2.23(a).

(a)

(b)

(c)

Fig. 2.23 Resulting spectrum of different modulating signal waveforms; (a) sine wave; (b)
square wave; (c) ramp
Two useful parameters to describe the characteristics of the modulated signal are the modulation
index K and the rate of modulation, % given by:

41

(2.16)
(2.17)
The parameter , gives an idea on how wide the energy of a single harmonic will be spread
relative to

. According to Carsons rule, 98% of the energy of the fundamental component of

the modulated signal is spread within the bandwidth. This can be expressed as:
(2.18)
Since the modulated clock signal is periodic in nature with a period of

and a phase of
(2.19)

The Fourier coefficient of the modulated signal can be derived as:

(2.20)
(2.21)
Where: =0, 1, 2 and

is either 5V or 0V
(2.22)

Therefore the amplitude of the

sideband harmonic can be represented by:

(2.23)

The frequency spectrum of the modulated clock signal is represented by delta functions at integer
multiples of

, with amplitudes given by (2.23). As the modulation index K increases, the

number of sidebands increases, resulting in signal energy that is more evenly distributed in the
bandwidth. An even distribution of signal energy provides a greater overall attenuation of the
fundamental harmonic amplitude of the modulated signal. This can be seen in Fig. 2.24.
42

Fig. 2.24 Spectral content of the modulated signal

In power electronics, the Spread spectrum technique is used to FM modulate the gating signal of
the MOSFET switch in such a way as to spread the harmonic energy contained in the pulse,
equally within the specific bandwidth. One important point pertaining to the application of the
SSFMT is that this techniques is valid only when the switching frequency of the converter is
within the EMC standards frequency spectrum of the conducted emissions, which is between
150KHz to 30MHz, except the MIL-STD461 that starts at 10KHz. Whereas, in digital circuits,
the SSFMT is mostly beneficial to the radiated emission attenuation, since this technique is
applied to the reference clock and other clock derived signals to spread the harmonic power of the
pulse signal. Most of the clock frequency harmonics are within the EMC standards frequency
spectrum of the radiated emission, which stretch between 30MHz to 1GHz.
The application of SSFM techniques in DC/DC converters [44]-[51] can provide a substantial
level of conducted EMI attenuation. However, comparative measurements show the advantage of
random carrier FM over periodic sinusoidal carrier FM modulation. An attenuation of 18dB was
achieved at frequency above 2MHz and only 5dB reduction at low frequency with a randomness
index of R>0.06. As R increases, further attenuation is achieved up to 11dB at fundamental
frequency with R=0.2. No improvement was observed at high frequency.
43

It is demonstrated in [52], [53] that using SSCG to modulate the system clock with triangular
waveform at 1% frequency deviation, have resulted maximum of 16.7dB in the radiated emission
attenuation. Also it is found that the level of reduction in the radiated emissions depends on the
amount of the frequency deviation or the modulation index.
Similarly, it is shown in [54],[55] that the application of the SSFM techniques in a resonant
inverter based compact fluorescent lamp (CFL) can help to reduce the output lamp current power
spectral density (PSD) to an EMC compliant level. An optimum attenuation of 12db was
achieved using multi-slope ramp or triangular modulation while controlling the effect of
amplitude modulation (AM) affect to keep the output current ripples within the desired level.

2.5.1 SSFM techniques limitation

The following bullets list the performance limitation of the spread spectrum modulation method;

This technique has been proven to have low attenuation at lower frequency harmonics
with a maximum attenuation around 10dB at optimum modulation index and triangular
waveform. However good performance is observed at higher harmonics.

The technique is useful in power converters only when the switching frequency falls
within the EMC spectrum of the conducted emissions.

Increasing the modulation index beyond a certain value may impact the output current
ripple.

The modulating frequency may interact with the feedback loop bandwidth of the power
converter and may results in continuous oscillations.

Higher frequency performance of this technique makes it more suitable in digital circuit
design application, by modulating the system clock to mitigate the radiated emissions.

44

2.6 Active Analog Filtering Technique in Switch Mode Power Converters

The mitigation of EMI noise in the power converters using active analog techniques has been
demonstrated in [56]-[72]. This method is based on the phase reversal and injection of the output
voltage ripple or output current ripple back to the output DC rail, using combined active and
passive circuit. Some applications of the active EMI Filter (AEM) [73] have been reported as an
add-on circuit to minimize the input passive EMI filter size. However, this solution uses a
transformer as the sensor element which is designed to carry the primary current of the input
power electronic module (IPEM). Similar method has been used at the input side of the DC/DC
converter [74].
This technique aims to attenuate the EMI noise appearing on the ground line which is referred
to as common mode noise. The main highlights of this method are described in the following
sections.

2.6.1 Principle of Operation

The hybrid EMI filter consists of an active filter and one-stage passive filter as shown in Fig.
2.25. Lin and Cin form the input passive filter. The active filter consists of the sensing branch Cs
and Rs, the active device, and the transformer based current injector. Rb, Rb1 and Cb are the bias
circuit of the OPAmp. Vref is the reference voltage to set the bias voltage of the OPAmp. Vo is the
output voltage of the OPAmp which is injected to the DC-bus through the wide bandwidth
transformer.
The input noise current is sensed through a RC branch circuit which converts the noise current
into noise voltage. This type of sensor is simple and efficient for sensing only the ac-signal while
rejecting the DC component. There are other methods of sensing the input current noise using a
wide-band transformer as detailed in [75]; however, this method requires a larger magnetic core
45

to avoid saturation, in particular when it is placed at the output of the power converter. The ripple
voltage which is in the phase of the input ripple current is fed into an inverting feedback amplifier
to inverse the phase of the sensed noise signal. The output signal of the amplifier is injected back
into the converter through a transformer with the desired gain. This injected voltage is converted
into current through the shunt inductor which is part of the passive filter elements.

Fig. 2.25 The configuration of the active input EMI filter

2.6.2 Circuit Analysis

Consider a power converter with Zin being the input impedance and In being the ripple current
that is generated by the switching MOSFET. The equivalent circuit model of harmonic noise of
the power converter showing both configuration of passive and combined active/passive, are
depicted in Fig. 2.26(a) and Fig. 2.26(b) respectively. For maximum attenuation, the magnitude
of the generated noise current In should be equal to the magnitude of the injected current Iinj:
(2.24)
(2.25)
(2.26)
Therefore:
46

(2.27)
Where:
(2.28)
Assume that the current that is fed into the utility mains in Fig. 2.26(a) and Fig. 2.26(b) is Iin and
I'in respectively, the performance of the active filter can be evaluated by its insertion loss defined
as:

IL

I in
I in

(2.29)

In the frequency domain, the current Iin and I'in can be derived according to Fig. 2.26:

Iinj

Fig. 2.26: Equivalent harmonic circuit of the converter: (a) Equivalent circuit with passive filter only,
(b) Equivalent circuit with hybrid active and passive filters

47

The noise current can be derived as:

I in I n
1

1
Z in sLin R ESR _ Lin

(2.30)

1
R ESR _ Cin
sC in

The noise current in circuit Fig. 2.26 (b) can be expressed as:

I in I n

Z1
B Z 2 E Z3 Z 4

(2.31)

Where, Lin and Cin are inductor and capacitor components of the input passive filter. Resr_Lin and
Resr_Cin are the equivalent series resistances for the inductor and the capacitor components
respectively. Rs and Cs are the resistive and capacitive components of the sense circuit. N is the
gain of the injection transformer.
B 1

E 1

Z1

Z in

(2.32)

Rs
1

sCs 1 Av N Rs
Z in
1 Av N Rs
Rs
sC s

(2.33)

1
R ESR _ Cin
sCin

(2.34)
1
sC s

(2.35)

Z3

1
RESR _ Cin Rs
sCin

(2.36)

Z4

1
Rs
sC s

(2.37)

Z 2 sLin RESR _ Lin

Av is the closed-loop voltage gain for the current feedback amplifier with unity gain that includes
the frequency-dependent open-loop trans-conductance gain function A(s):
48

Av

A( s)
1 A( s)

A( s)

(2.38)

k1
1 s k2

(2.39)

Where k1 is the DC open-loop voltage gain (typically 105 to 107), and k2 reflects the cutoff
frequency. These two parameters describe the frequency-dependent open loop characteristics of
the chosen OPAmp.
Therefore, the noise attenuation of the hybrid circuit can be found by substituting Iin and I'in in
equation (2.29) by equations (2.30) and (2.31) respectively, and Fig. 2.27 shows the noise
attenuation in frequency domain.

Fig. 2.27: Noise attenuation of the active circuit (Zin=50//50H, Rs=50, Cs=5F, Cin=20F,
k1=6106, k2 =100, N=15)

It can be seen that in the frequency range of interest (150 kHz-3 MHz), the active filter has
substantial noise attenuation, also referred as insertion loss of 30 dB at the fundamental switching
frequency of the DC converter, and around 20 dB at the first several harmonics. It is also found
that the noise attenuation is not only dependent on the characteristics of the OPAmp (k1 and k2),
49

but also highly dependent on the value of the shunt inductor Lin. In Fig. 2.27, the smaller value of
Lin results in better noise attenuation. However the minimum value of Lin should be limited by the
cut-off frequency of the input passive filter, which should be set at a decade lower than the
resonant frequency of the output filter of the DC/DC converter to avoid interaction.

2.6.3 Transformer Based Injector

A transformer based injector is used in the circuit. This could be accomplished by using a high
frequency transformer with parallel inductor on the secondary windings. The injection
transformer should be selected to have a wide bandwidth of several MHzs with a 1: n ratio, and
the secondary carrying the input current of the converter. The one turn of the secondary can be
the trace of the PCB, whereas the primary can be more than 10 turns, depending on the required
gain. The passive filter element Lin is used as the shunt inductor to handle the DC current flowing
through the secondary power circuit, and meanwhile, convert the injected voltage noise into a
current form. Both, the injection transformer and the shunt inductor, should provide sufficient
impedance to avoid loading the active device. It is important that the injection transformer
replicates the injected signal with high precision.
Fig. 2.28 shows the implementation of the injector that uses the passive filter inductor as a
bypass inductor, in parallel with high frequency transformer. The voltage at the primary winding
of the injection transformer is equal to the voltage noise at the output of the active filter. The
voltage noise at the primary winding induces a current noise at the secondary winding which is
injected at the node of Lin.

50

Fig. 2.28: Injection transformer

Accordingly three basic equations can be established:

(2.40)
(2.41)
(2.42)
(2.43)
Where vit

_1

and vit

_2

are the voltages at the primary and secondary windings of the injection

transformer; vop is the output voltage of the OPAmp; Rs is the resistance of the sensing element;

s is the switching frequency; in is the input ripple current; iinj is the injected current noise.
Ideally, the injected current noise should cancel the input ripple current:
(2.44)
From (2.43), the ratio of the injection current and the ripple current should be close to 1;

(2.45)
Or

(2.46)
51

From (2.46) above, the turns ratio of the injection transformer must match the impedance of the
bypass inductor in order to achieve maximum noise attenuation.

2.6.4 Design Example

A 30W DC/DC isolated forward step-down converter operating at 700 kHz switching
frequency is taken as a design example for the filter implementation. The input nominal DC
voltage is 48V, and the output voltage is regulated at 5V. The active filter is placed between the
input voltage source and the input passive filter as shown in Fig. 2.25. The circuit parameters of
the active and passive filters are selected according to the analysis given in sections 2.6.2. The
experimental circuit diagram is shown in Fig. 2.29.

Fig. 2.29: Experimental circuit diagram

The result of the EMI noise voltage is shown in Fig. 2.30. Dominant peaks can be seen at the
fundamental switching frequency (700 kHz) and at other harmonics. However, good harmonics
attenuation is achieved at higher frequencies. This is due to the contribution of the passive filter
since this latter provides up to 40dB attenuation beyond its cut-off frequency.

52

Fig. 2.30: Conducted EMI noise spectrum result with the input passive filter only
Another set of measurements were taken with the active EMI filter inserted between the LISN
and the passive filter. The corresponding result of the EMI noise spectrum, as per EN55022
standards, is shown in Fig. 2.31. As can be seen, significant noise attenuation is achieved at the
fundamental switching frequency and at the first harmonic. This is due to the contribution of the
active filter. Table 2-1, compares the peak attenuation accomplished by the passive and the hybrid
filters.

53

Fig. 2.31: Conducted EMI noise spectrum result with the combination of passive and active
input EMI filters.
An attenuation exceeding 30dBV is observed at the switching frequency and at the first higher
harmonic. These attenuation magnitudes make a significant difference in the EMC compliance in
terms of conducted emissions.
Table 2-1: Performance comparisons of the passive and the hybrid filters
Peak attenuation

Peak attenuation

Delta

With passive input filter

With hybrid input filter

attenuation

(dBV)

(dBV)

(dBV)

0.7

88.9

57.9

31

1.4

79.9

43.4

36.5

2.1

57.2

27.4

29.8

2.8

70.6

35.3

35.3

3.6

67.7

30.3

37.4

Harmonic Frequency
(MHz)

54

2.7 Summary
In this chapter, a review of the existing EMI suppression techniques in power converters, have
been presented. There are several techniques, namely the basic technique, the zero-voltage
crossing technique, the SSFM technique, the passive filtering technique and the active analog
filtering technique. Each of these techniques are evaluated according to their attenuation
performance. It has been shown that the passive and the active analog filtering techniques are the
most desirable EMI solutions. Furthermore, the limitations of each technique have been
discussed.
Finally, the simulation results have been shown and have demonstrated that the passive filtering
technique outperformed the other techniques, in particular at high frequency, in terms of noise
attenuation, design simplicity and cost. However, the size is a major drawback in the passive
filtering technique.

55

Chapter 3
Proposed DSP-Based EMI Suppression Technique
3.1 Introduction
The active analog EMI filters provide the basic noise suppression technique and their main
advantages are low cost and ease of use. However, their limitations call for a requirement of
additional passive elements to complete the EMC spectrum, in terms of noise attenuation. Also,
the issue of the negative impedance seen by the converter can have a great impact on its stability.
This is mainly due to the components selection of the passive elements of the EMI filter and the
final installation of the converter. In addition, the size of the passive filter is product specific and
varies with the input parameters of the converter, such as rated current and voltage.
The performance versus cost reduction trends of digital circuits has made possible their
application for power converters digital controller techniques [76]-[83]. They are usually based
on digital signal processor (DSP) that exploits their mathematical oriented resources. The main
limitation of using DSPs in high switching power converters is their sequential operation, that is,
instructions are executed one after the other resulting in a delayed signal. However, this issue can
be neglected if the number of instruction that needs to be executed is very small. Other limitation
in the digital control, is the issue of the limit-cycle oscillation. This is due to the small change in
the output voltage that can cause a further change in the duty cycle.
In this chapter DSP-based EMI suppression technique (DSPBEST) is proposed. It can also be
referred to as digital active EMI filter (DAEF). The proposed DSP-based filtering method
overcomes the drawbacks of the analog suppression techniques. Meanwhile, the DSP execution
time delay does not impact the DAEF performance, since it requires only a few instructions to

56

inverse the phase of the sensed signal. The following are two examples of the comparison
between active/passive analog EMI filter and the proposed DAEF.
Fig. 3.1 shows a simplified diagram comparing the DAEF and the passive EMI filter (PEF) in
terms of their size variation versus converter power rating. The DAEF presents stronger
competitive application in medium to high power converters. In low power applications, the
DAEF presents a less desirable option. This is due to the constant size of the DAEF as compared
to the PEF. However, this statement holds only when the DAEF is configured as a stand-alone
solution. In an integrated version, the DAEF is still the best solution in terms of size and
performance.

Filter size

PEF

DAEF

Co
nv
e
po rgenc
int
e

Low Power

50w

High power

Converter Power Ratings

Fig. 3.1 Application of DAEF versus PEF in power converters

Since the digital EMI filter (DAEF) can be modeled using sequential DSP codes in the discrete
domain, it is not frequency dependent. Hence no phase distortion within the digital block is
apparent compared to the active analog EMI filters. However, a non-significant delay will be
introduced due to the capacitive injection which in turn prevents the complete nullification of the
conducted noise of the converter.
57

This chapter is partitioned as follows. In section 2, the principle of operation of the proposed
DSPBEST which is also referred to as DAEF, is described. The sampling theory on which the
proposed technique is based on is briefly revisited and the building blocks of the proposed
technique are illustrated. Section 3 presents the circuit analysis and the derivation of the transfer
function of the proposed technique and the key design waveforms are given. Sections 4 and 5
validate the proposed technique through simulation and experimental results respectively. Finally,
section 6 summarizes the key elements of the proposed technique.

3.2 Principle of Operation

The objective of the Digital Active EMI Filter is to remove or to minimize the unwanted
interference signal generated by the DC/DC converter circuitry. This interference noise signal
tends to flow towards the utility grid, via the input rails of the power distribution system. The
active filtering technique is done by the emulation of the incident noise signal in terms of
amplitude and frequency. The emulated signal is digitally inverted then reconstructed using
digital to analog converter (DAC). The output DAC signal is then electrically injected at input
leads of the power converter. In this process, only one parameter is required by the digital
processor in order to replicate the original sensed signal.
As shown in Fig. 3.2, the input parameter to the digital EMI filter is the noise voltage that is
sensed through an RC High-pass circuit. The noise voltage is sampled using high speed analogto-digital converter (ADC), the noise signal is then inverted using a binary inverter, the output of
which is converted back to analog signal using digital-to-analog converter (DAC). The
reconstructed signal is fed back to the input lead of the power converter. The injection capacitor
Cinj is used to prevent the ADC from being loaded by the power converter.

58

Z>>>

AC

Vin

Cinj

PFC Converter

Rinj

Rs

Cbulk

Vout

LOAD

Cs

LPF

HPF

Iin

ADC

DAC

PFC Controller

Control Algorithm

Fig. 3.2 General Scheme of the Digital Input EMI filter

3.3 Sampling Theory

It is important to explain the sampling theory since it represents the backbone of the proposed
technique. In general, sampling is the process of converting a continuous analog signal into a
discrete time signal or a sequence of numbers. Depending on the characteristics of the sampling
circuit, sampling can be modeled differently, resulting in different frequency spectra for the
sampled signal. In this section, we consider three sampling models as shown in Fig. 3.3. The most
used sampling model is the impulse sampling also known as instantaneous sampling [84].

59

m(t)

S(t)

i(t)
(a)

Ts

(b)

Fig. 3.3 Impulse Sampling Model

Consider a band-limited low-pass signal m(t) as shown in Fig. 3.3 (a).
Assume that M(f) is the frequency domain representation of that signal. Suppose that we want to
sample this signal every second, this is achieved by multiplying the continuous input signal by an
infinite impulse train i(t) having a period as shown in Fig. 3.3 (b), and

is given by:
(3.1)

The frequency domain transformation of i(t) is also an impulse train given by:
(3.2)

Where:

is the sampling frequency

The sampled signal is given by:

(3.3)
Substituting (3.1) in (3.3), the expression for the sampled signal can be given as:

60

(3.4)
Multiplication in the time domain corresponds to convolution in the frequency domain. Hence,
the frequency domain transformation of the sampled signal is given by:

(3.5)
To recover the continuous band-limited signal the sampled signal s(t) is passed through an ideal
low-pass filter having a frequency response:

(3.6)
Where,

is the maximum frequency of the band-limited signal.

, from the sampled signal s(t), the maximum

To restore the continuous band-limited signal

frequency

of the band-limited signal must be less than or equal half the sampling frequency

i.e.:
(3.7)
Inequality (3.7) is known as the Nyquist condition for perfect reconstruction of a band-limited
signal. The minimum sampling frequency that satisfies inequality (3.7) is known as the Nyquist
rate. If the Nyquist condition of (3.7) is not satisfied, the spectra of the images overlap and will
cant be recovered from the sampled signal.

cause aliasing. When this occurs the signal

Fig. 3.4 shows a simulation circuit for sampling a time domain signal, with the delay introduced
by the low-pass filter.

61

mt

sampledsignal
IN2
V

V1

100

IN

OUT
V

IN1

OUT

recov eredsignal

0.1dB
60dB
Impulse
V

VOFF = 0
VAMPL = 1
FREQ = 1000

V2
V1 = 0
V2 = 1

Fig. 3.4 Circuit example of a Sampling time-domain analog signal

2.0V

Analog Input Signal

0V
-2.0V
V(mt)
2.0V

Impulse function

0V
V(Impulse)
1.0V

Amplified sampled signal

0V
-1.0V

V(sampledsignal)

1.0V
0V
-1.0V
0s

Recovered Signal
Filter delay
0.5ms 1.0ms
V(recoveredsignal)

1.5ms

2.0ms

2.5ms

3.0ms

3.5ms

4.0ms

4.5ms

5.0ms

5.5ms

6.0ms

6.5ms

7.0ms

7.5ms 8.0ms

Time

Fig. 3.5 Simulation waveforms showing the sampling process using impulse function and the
recovered signal

3.4 Circuit Building Blocks

Compared with analog signal processors, DSPs have numerous advantages. In digital systems, the
signal is quantized into discrete levels, and a finite number of digital code-words are transmitted,
most of the noise and interference added to the digital signal during processing or transmission
can be removed. Whereas, in analog systems any noise added to the signal is embedded into it
and hence cannot be removed. Therefore, analog signal processing requires accurate components
62

with precise tolerance. However, digital signal processing can tolerate less precise components
making digital signal processors less susceptible to temperature, aging and manufacturing
tolerances. Furthermore, digital systems offer more extensive programmability than analog
systems. However, all naturally occurring signals that are encountered in the real world are
analog signals. This requires the transformation of such signals from the analog domain to the
digital domain to make use of the powerful computational processing power of the digital signal
processors. The digital signal then has to be transformed back to the analog domain. This
transformation is done by using analog-to-digital and digital-to-analog converters. Fig. 3.6 shows
the block diagram of an analog-to-digital converter (ADC).
The sampler provide the discrete signal in the time domain then it is followed by the quantizer,
which is a many-to-one transformer that maps a range of the continuous signal into a discrete
level. The quantizer performs approximation to the analog signal by approximating it to one of a
finite number of discrete levels. After being quantized, the coder maps each quantized level into a
binary code-word.

Analog Input
(EMI source)

N-Bits Digital
Output
In

S/H

010...

X*(t)

x(t)
Sample
and Hold

Quantizer

Uniform
Encoder

Fig. 3.6 Block Diagram of an Analog-to-Digital Converter (ADC)

In the digital-to-analog converter (DAC), the reverse operations to those of the analog-to-digital
converter occur as shown in Fig. 3.7. The decoder transforms the binary code into a quantized
signal level. Because the quantizer is a many to one transformer, i.e. it maps a range of the
continuous signal into a discrete level, hence, it has no inverse equivalent in the digital-to-analog
63

converter. Thus, any quantization noise added to the signal is stuck to it and cant be removed by
the digital-to-analog converter. Finally, a low-pass filter converts the time-discrete (sampled)
signal into a continuous analog signal.

Analog Output
(Inverted EMI signal)

N-Bits Digital
Input
010...

Y(t)

X*(t)
Uniform
Decoder

Lowpass RF Filter

Fig. 3.7 Block Diagram of a Digital-to-Analog Converter (DAC)

In this case, the input signal to the ADC is the EMI source voltage generated in the power
converter and it is assumed to be periodic noise signal. This signal is converted into a discrete
form using high speed ADC. The discrete signal with specific bit resolution is then fed into a DSP
for bit inversion processing. The inverted bits are fed into the DAC to recover the original signal
with a 180 degrees phase inversion.
The conversion process of the EMI signal from the input-to-output is described by the transfer
function of the ADC and the DAC respectively as shown below.
According to Fig. 3.6 and Fig. 3.7, the output function
input function

in Fig. 3.6 is a sampled signal of the

in a bits pattern format. Whereas the output function

piece-wise linear function of the sampled signal

in Fig. 3.7 is a

The output function, before the low-pass filter, is a piece-wise linear constant or ramp function in
the nth T period and can be represented by:
(3.8)
So that
64

(3.9)
where:
(3.10)
And,
(3.11)
Where a1,2 and b1,2 are constants determined by the particular sample-and-hold. In the case of the
zero-order-hold (ZOH), the output has a constant value equal to x(nT) throughout the interval .
The Laplace transform, of the function

is as follows:
(3.12)

Replacing

, the above equation becomes

(3.13)
Where,
(3.14)
And,
(3.15)
Using the shifting properties of the transform for (3.13), S1 can be determined as,

65

(3.16)
Similarly, for S2, we have
(3.17)
Substituting (3.16), (3.17), (3.14) and (3.15) into (3.13) the general transfer function can be
written as follows.
(3.18)

For a ZOH based DAC, the time function

is constant for a period T. In other words,

, For

(3.19)

Thus, comparing (3.19) with (3.9), yields a1=a2=b1=0 and b2=1. Substituting these values into
(3.18), the general transfer function for the ZOH-based DAC can be simplified as follows:
(3.20)
The relation between the sensed analog signal x(t) to the sampled signal variable x*(t) in the Sdomain is:
(3.21)
The Input-to-Output transfer function for the ZOH DAC may then be written as:
(3.22)
While the transfer function from Input x(t) to Output y(t) is complicated by the repeating
spectrum, the effective frequency response is the continuous Laplace transform transfer function
of the impulse response which can be expressed as,

66

(3.23)
Thus, by substituting

, in (3.23), the magnitude and phase of the transfer function in the

frequency domain can be obtained.

(3.24)
Where

is normalized sinc function equal to

The gain is:

(3.25)
The phase is:
(3.26)
Thus the effect of the ZOH on the feedback loop is to increase the gain by a magnitude of
and introduce a phase shift of

, which is a negligible time delay.

3.5 Analysis and Design Approach

The feedback system diagram of the DSP-based EMI filter is illustrated in Fig. 3.8.

67

+
-

Y(s)

X(s)

Interference Noise
X(s)

Discrete
System

K1

ZOH+DAC

Injector
G(s)

D(s)

K2

Sensor
H(s)

Fig. 3.8 Feedback Diagram of the DSP-Based Digital EMI filter

The closed loop system transfer function can be written as.

(3.27)
Where,
is the EMI source function at the quite port, utility side;
is the EMI source function at noisy port, the converter side;
is the injected EMI noise function, after processing;
In theory,

should be equal in magnitude to the source function

, in order to achieve full

nullification of the EMI noise. However, in reality, this cannot be realized due to the parasitic
capacitance inherent in the circuit. Therefore,
K1 is the injector gain;
K2 is the bits inversion algorithm implemented in the DSP device;
is the Laplace transform transfer function of the high-pass filter and it is given by:
(3.28)
Where,

is equal to
68

D(s) is the Laplace transform transfer function of the ZOH as derived in the previous section.
(3.29)
Where, T is the ADC clock/sampling period.
G(s) is the Laplace transform transfer function of the RC low-pass filter given by:
(3.30)
Where,

is equal to

. This is the corner frequency of the filter

Substituting H(s), D(s), and G(s) in (3.27), the closed-loop transfer function of the feedback
diagram of Fig. 3.8 can be expressed as:
(3.31)

The frequency response of (3.31) in terms of magnitude and phase are illustrated in Fig. 3.9 and
Fig. 3.10 respectively.
For higher noise attenuation, the gain of the feedback transfer function of (3.31) should be as
large as possible. This can be done by increasing the injector gain K 1. To achieve an attenuation
of at least 50dB within the bandwidth of 10 KHz to 30MHz, a gain of 100 is required.
In Fig. 3.10, the effect of the ZOH frequency properties on the overall attenuation transfer
function is apparent. It is a shift of 1800 where the sine function changes sign.

69

Magnitude (dB)

15

30

45

60
10

100

1 10

1 10

1 10

1 10

1 10

1 10

1 10

Frequency (Hz)

Fig. 3.9 Frequency response - magnitude of the DSP-based EMI filter

200

Phase (Deg.)

100

100

200
10

100

1 10

1 10

1 10

1 10

1 10

1 10

1 10

Frequency (Hz)

Fig. 3.10 Frequency response - phase of the DSP-based EMI filter

70

3.6 Simulation Results Waveforms

Preliminary simulation results using mixed Analog and Digital PSPICE software are presented in
this section.
An entire DC/DC converter including an LC passive EMI filter circuit was simulated in PSPICE
software [85], in order to investigate the contribution of the proposed EMI suppression technique.
The simplified schematic diagram of the simulated circuit is illustrated in Fig. 3.11, and the
detailed one is given in Appendix A.

Lo
SW1

SW2

Resr
Co

Vdc

Ro
Resr

Rsense

CCVS
PWM Module

Type-3 Error Amplifier

Rpar
Rseries

Controller

Injected noise signal

Lf

Digital EMI Filter

Module

Cf

LISN
Sensed noise signal

Fig. 3.11 Schematic block diagram of the simulation circuit

Most of the components models exist in the software library, except the LISN which was
modeled to represent 50 utility source impedance. The primary (input) current signature
is simulated by the current controlled voltage source (CCVS) which flows through the LISN
sense branch (RC high-pass filter) to generate the corresponding noise voltage. The digital EMI
filter circuit is constructed using existing library models for ADC and DAC devices. The
71

resolution of these devices was selected to be 14 bits and the sampling frequency of the ADC was
set at 200 Mbps which reflects around 10 times the upper frequency of the EMC standards for
conducted emissions (30MHz). In this case Shannons theory for sampling, mentioned in the
previous chapter, is not sufficient, considering the sensed signal amplitude and frequency
variations. Thus, oversampling is required to achieve adequate and complete signal discretization.
Normally, for accurate comparisons between simulated and real plots, the simulation time should
be adjusted in order to match the normalized filter bandwidth at -6dB (200Hz and 9 kHz) as per
CISPR16 standards [86]. However, to simplify the various timing values and limit the number of
simulated data points, 500Hz and 10 kHz will be used as analysis bandwidths. The converter
parameters are given in Table 3.1.
Table 3.1 Simulated Converter Parameters for DSP-based EMI filter
Parameters

Values

Input voltage

12Vdc non-isolated

Output voltage

5Vdc

Output current

4 Amps

Switches S1 & S2

IRF640

Switching Frequency

500KHz

Output filter

Lout= 1uH; Cout=100uF

Input Passive filter components

Lf=1.5mH; Cf=0.2uF
14bits DAC, 14bits ADC, RC-low-pass

Digital EMI filter components

filter 10nF/30, RC-high pass filter

0.1uF/1k
50/50H

LISN components
72

First, the simulation run without the EMI filter connected to the power converter. Then the
passive analog EMI filter was added to the converter circuit in order to observe the overall
contribution in terms of input noise attenuation. The third case, the digital EMI filter was added to
the circuit but without the Passive EMI filter. In all simulation cases, Fast Fourier Transform
(FFT) was performed on the sensed voltage at the LISN sense port in order to represent the noise
voltage in terms of its harmonic contents in the frequency domain and log compress the Y axis to
represent the plots in dBV form to be compared to the compliance limits.
Waveforms showing the simulated conducted EMI noise spectrum without the EMI filter, with
the passive EMI filter, and with the proposed digital filter are depicted in Fig. 3.12, Fig. 3.13, Fig.
3.14 respectively. As can be seen from these figures, the EMI noise is attenuated by more than
20dBuV, when the digital EMI filter is introduced in the circuit. Note that the digital EMI filter
outperforms the passive EMI filter at the fundamental frequency (500 KHz) and the first few
harmonic peaks. These peaks are labeled on the plot along with their corresponding frequencies.
Table 3.2 presents selective peaks from both PEF and DAEF attenuation performance at different
frequencies.

73

120dBuV

(500KHz,90.3dBu
V)

Conducted Noise

100dBuV

(1MHz,88.3dBuV)
(1.5MHz,84.9dBu
V)

(2MHz,81.28dBu
V)
(2.5MHz,81.4dBuV)

80dBuV
Conducted Emissions CISPR, Class A

60dBuV

40dBuV

20dBuV

0dBuV
150KHz

1.0MH
z

10MHz

30MHz

Frequency

Fig. 3.12 Conducted Noise measurement without Input EMI Filter

120dBuV

100dBuV

Conducted Noise

(500KHz,82.6dBu
V)
80dBuV
Conducted Emissions CISPR, Class A

60dBuV

(1.0MHz,67.08dBu
V)
(1.5MHz,56.68dBu
V)
(2.0MHz,84.06dBu
V) (2.5MHz,43.76dBu
V)

40dBuV

20dBuV

0dBuV

20dBuV150KHz

1.0MHz

10MHz

Frequency

Fig. 3.13 Conducted Noise measurement with Passive Input EMI Filter

74

30MHz

120dBuV

Conducted Noise

100dBuV
(500K,71.99dBuV)
(1.0M,71.93dBuV)
(1.5M,69.0dBuV)

80dBuV

(2.0M,65.57dBuV)
(2.5M,65.5dBuV)

Conducted Emissions CISPR, Class A

60dBuV

40dBuV

20dBuV

0dBuV

-20dBuV

1.0MHz

150KHz

10MHz

Frequency

Fig. 3.14 Conducted Noise measurement with Proposed Digital Input EMI Filter

Table 3.2 Comparison of attenuation performance between PEF and DAEF using
simulation results
Peak attenuation

Peak attenuation

Peak attenuation

with PEF

with DAEF

without EMI Filter

(dBV)

(dBV)

(dBV)

0.5

82.6

71.99

90.3

67.8

71.93

88.93

1.5

56.68

69.0

84.9

50.06

65.57

81.28

2.5

43.76

65.50

81.4

Harmonic Freq.
Peaks (MHz)

75

30MHz

The binary plots of the most significant bit (MSB) and least significant bit (LSB) are shown in
Fig. 3.15 as well as the noise signal at the output of the DAC and the sensed noise signal. As
mentioned before, the injected noise signal theoretically should be the exact replica of the sensed
noise signal with 180o phase shift. However, at higher frequencies, above 30MHz, the injected
signal start to exhibit a slight delay in the phase shift as shown below.
U13:DB0
U13:DB1
U13:DB2
U13:DB3
U13:DB15
U13:DB14
U13:DB13
U33:DB12
2.0V

Sensed Noise
Freq= 33MHz to 500MHz

Injected Noise

0V

-2.0V
573.9900us

574.0000us

V(R87:1)

574.0100us

574.0200us

574.0300us

574.0400us

V(Vsense)

574.0500us

574.0600us

574.0700us

574.0800us

Time

Fig. 3.15 Output of the ADC and the DAC in time domain

3.7 Experimental Results of the Proposed Techniques in a Stand-alone

Configuration
In order to validate the proposed technique, a 75W AC/DC power converter including power
factor correction (PFC) control was used as the Equipment under test (EUT) for this experiment.
The conducted emission measurements were performed on the EUT as per CISPR22 [87]
conducted emissions measurements setup. Three scenarios of testing were considered, the first
being the EUT without any EMI filters installed. The second measurement was done with the

76

passive EMI filter installed in the EUT. In the third case, the measurements were done with only
the proposed DSP-based digital active EMI filter. The test setup is shown in Fig. 3.16 below.
The experiment plots pertaining to the proof-of-concept are illustrated in the following figures.
Fig. 3.17 shows the sensed ripple voltage and the injected ripple voltage at the input and the
output of the DAEF. Note that the waveforms are 1800 out-of-phase for EMI noise cancellation
with the frequency identical to the switching frequency of the power converter or the EUT.
DAE Filter

AD/DC Power
Converter
(EUT)

Fig. 3.16 Conducted emissions testing experimental setup

77

Sensed ripple Signal

Injected ripple signal

Fig. 3.17 Input and output voltage signal of the proposed DAE Filter
The plot in Fig. 3.18 shows the spectrum of the conducted emissions of the EUT without any
filtering in place. High amplitude peaks up to 80dB in magnitude can be seen in the lower
frequency spectrum. The plot in Fig. 3.19 shows significant amplitude attenuation with the
introduction of the passive filter at the input of the EUT. Similarly, Fig. 3.20 shows the
attenuation performance when the PEF is replaced by the DAEF. Attenuation up to 30dB can be
achieved using this filtering method.
Table 3-3 presents selective peaks from both PEF and DAEF attenuation performance at different
frequencies. A comparative graph is depicted in Fig. 3.21 to support the validity of the method
and to confirm the claim of replacing the PEF by the DAEF while improving the attenuation
performance.

78

dBuV
100
90
80
70
EN 55022; Class B Conducted, Quasi-Peak

60

EN 55022; Class B Conducted, Average

50
40
30
20
10
0

10

4/17/2011 4:04:24 PM

(Start = 0.15, Stop = 30.00) MHz

Fig. 3.18 Conducted emission spectrum of EUT without filters

dBuV
100
90
80
70
60

EN 55022; Class B Conducted, Quasi-Peak

50

EN 55022; Class B Conducted, Average

40
30
20
10
0
1

10
(Start = 0.15, Stop = 30.00) MHz

Fig. 3.19 Conducted emission spectrum of EUT with PEF

79

dBuV
100
90
80
70

EN 55022; Class B Conducted, Quasi-Peak

60

EN 55022; Class B Conducted, Average

50
40
30
20
10
0
1

10

4/17/2011 4:46:12 PM

(Start = 0.15, Stop = 30.00) MHz

Fig. 3.20 Conducted emission spectrum of EUT with DAEF

Table 3-3 Comparison between experimental and simulation results
Peak attenuation

Peak attenuation

Peak attenuation

with PEF

with DAEF

without EMI Filter

(dBV)

(dBV)

(dBV)

0.5

47.46

36.49

53.12

31.43

34.13

43.78

1.5

25.20

29.69

50.00

40.0

26.34

51.74

2.5

40.0

22.69

51.86

Harmonic Freq.
Peaks (MHz)

80

Fig. 3.21 Comparative attenuation between PEF and DAEF

3.8 Summary
In this chapter, a novel DSP-based technique to suppress conducted EMI emissions in power
converters has been proposed. This technique exploits the theory of sampling using data
acquisition devices such as ADC and DAC for discrete time conversion of the EMI noise source.
The impulse function to represent the sampling process has been used for the sensed signal
recovery. The system building blocks have been explained. The ZOH of the signal acquisition has
been pointed out of being the interface between the continuous and the discrete signal. The
analysis of the mixed system that is partially discrete and partially continuous has been
performed. The system transfer function has been derived using s-domain equivalent parameters.
The frequency response of the attenuation transfer function has led to the determination of the
magnitude and the phase. The figure-of-merit of the attenuation transfer function, in terms of
magnitude, has revealed that the gain of the injector has a direct impact on the increase of the
magnitude within the desired bandwidth. Finally, the simulation and the experimental results
prove the validity of replacing the PEF by the proposed DAEF in the power converter.
81

Chapter 4
Proposed FPGA-Based EMI Suppression Technique (FPGABEST)

4.1 Introduction
The issues with the existing methods previously mentioned in terms of their performance and
their limitations have paved the way for the proposed technique that surpasses these drawbacks.
The DSP based solution for EMI mitigation proposed earlier, has a slight disadvantage which
resides in the delay embedded in the execution of the algorithm instructions that is processed
sequentially. This execution delay can results in phase lag between the sensed signal and the
injected signal which has a direct impact on the attenuation performance. Therefore, in this
chapter, an FPGA based EMI suppression technique is proposed to alleviate the problem of the
phase delay while using the same interface circuit. This method uses a field programmable gate
array (FPGA) device, in order to exploit its concurrent operation [88]-[91]. All the internal logic
elements of the FPGA, and therefore the control algorithm, are executed continuously and
simultaneously. The control algorithm has been developed in Very high speed integrated circuit

Hardware Description Language (VHDL) [92]-[96]. This method is as flexible as any software
solution. The same algorithm can be synthesized into any FPGA device and even has a possible
direct path to a custom chip. In this way, the FPGA could be substituted by an Application
Specific Integrated Circuit (ASIC), opening interesting possibilities in EMI filtering techniques in
terms of performance, cost and flexibility. VHDL has been used for modeling the phase inversion
by using a logic inverter implemented in VHDL.
This chapter is organized as follows. In section 2, the principle of operation of the proposed
FPGABEST is described. In section 3, the circuit analysis and the expression for the z-domain
82

transfer function of the proposed technique is derived. The key design waveforms are presented.
Finally, section 4 summarizes the key elements of the proposed technique and provides a brief
comparison between the DSPBEST and FPGABEST in terms of their performance and
limitations. Note that both techniques can be referred to, for simplicity, as Digital EMI filter.

4.2 Principle of operation

The process of operation for this technique is almost similar to the one proposed in chapter 3,
except for the algorithm used in this method. This difference will be outlined in this section. The
sensing and the injection circuits remain unchanged.
The continuous time interference source generated in the power converter is sensed through an
RC-high pass filter. The continuous time signal is converted into its equivalent discrete time
using ZOH and DAC functions; with specific sampling period T. The sampling frequency is the
clock frequency of the DAC, which is selected based on the sampled signal. It is usually 10 times
the sampled signal frequency. The discrete time sampled signal in bits format is then processed
using logic inverter to produce a complement for each bit received. The output of the DAC is the
continuous time signal of the original sensed signal with 180o phase shift. This later is used to
counteract the interference noise. The sampled signal is processed using VHDL algorithm, with a
set of instructions that can be executed simultaneously. This method reduces the delay time
significantly which in turn minimizes the phase error between the injected/processed noise signal
and the reference EMI signal.
Note that the feedback loop elements such as the RC- low pass, high-pass filters, the ADC and
the DAC can be modeled using VHDL code, which can be implemented in an FPGA device.
Fig. 4.1 illustrates the configuration of the proposed technique connected to a power converter.

83

Lf

Z>>>

Iout
SW1
Rload
SW2

ESR
Vout

Vin
Cf

Sensor

Injector
Controller/
Compensator

Analog Interface

ADC

DAC

14

N-bits inverter

n
14

Number of bits used for variable

Synthesizable VHDL Model

Fig. 4.1 Proposed FPGABEST block diagram connected to a buck converter

4.3 Analysis and Design Approach

The proposed FPGA-Based EMI Suppression Technique flow diagram is shown in Fig. 4.2
+

Y(s)

X(s)

Conducted noise signal

X(s)
Converter Side

Quiet
Port

Discrete System
(ZOH + DAC)

K1

G(s)
Injector

D(z)

K2
T

H(s)
Sensor

Synthesizable VHDL code

Fig. 4.2 Feedback loop diagram of the proposed FPGA-Based EST

84

Similar to the approach used for the DSP-Based EST, the noise attenuation transfer function can
be derived using the equivalent two port network model as shown in Fig. 4.3

X(s)

Y(s)

Feedback Path
F(s)

Quiet Port

Noisy Port

Fig. 4.3 two-port network model

Therefore, the continuous-time feedback loop transfer function of the noise attenuation can be
written as.
(4-1)

Where, F(s) is the feedback components blocks of the proposed technique. Y(s) is the noise
current at the Quiet port and X(s) is the noise current at the Noisy port.
The insertion-loss approach could also be used to derive the attenuation transfer function.
However, this method is more complex.
As opposed to the DSP-Based EST, in which the transfer function was derived in continuoustime, the transfer function of the FPGA-Based EST is obtained using discrete-time model.
Furthermore, it is imperative to investigate the characteristics of the discrete-time model, simply
because, the sensor and the injector blocks exist in continuous-time, whereas the sampler and the
85

ZOH are discrete-time. This mixed continuous and discrete time models make the analysis of the
feedback loop more complicated. To overcome this problem, one would convert all the feedback
components to their discrete-time equivalent at specific sampling instances. In this case, the
complete feedback loop can be analyzed using straight-forward application of standard discretetime model. Thus, this leads to the discussion of the approximation methods which are used to
convert the continuous-time model (s-domain) to its equivalent discrete-time (z-domain).
There are three main methods of approximation, the numerical integration which is sub-divided
onto three methods, the forward rule, the backward rule and the trapezoidal rule also known as
the Tustins method. The second approximation is called the pole-zero mapping which maps the
zeros and the poles of the continuous-time into the poles and zeros of the discrete-time
equivalents, using the relation

The third approximation is the zero-order hold (ZOH) equivalent. This method is preferred
because of its simplicity and accuracy as compared to other approximations.
To obtain an expression for the noise attenuation transfer function, each block of the feedback
path of must be converted to its z-domain equivalent. The sensor, the injector and the DAC-ZOH
will be approximated in the next paragraphs and the final expression for the noise attenuation will
be derived thereof.

4.3.1 The sensor discretization

The continuous-time transfer function of the RC high pass filter (HPF) is given as.
(4-2)
Where

is the corner frequency of the HPF. With

written as.

86

, the transfer function can be re-

(4-3)
Hence, the ZOH equivalent approximation can be applied to obtain the discrete-time equivalent.
(4-4)
We have
(4-5)
Substituting equation (5) into (4), the discrete-time transfer function can be obtained as.
(4-6)
4.3.2 The Injector discretization
The s-domain expression of the RC Low-pass filter (LPF) is given by.
(4-7)
Where

is the corner frequency of the (LPF). With,

the transfer function can be re-

written as.
(4-8)
Similarly, the ZOH equivalent approximation can be applied to obtain the discrete-time
equivalent.
(4-9)
After the partial expansion of

, the final discrete-time transfer function of the LPF can be

written as.
(4-10)

87

Where, T is the sampling period of the DAC.

4.3.3 The DAC discretization

The continuous-time transfer function as derived in Chapter 2 is given by.
(4-11)
Applying the ZOH approximation to the s-domain transfer function, the z-domain transfer
function is obtained as.

(4-12)
The term

reduces to

in the z-domain. Therefore;

(4-13)
After substituting (4.13) into (4.12), and re-arranging, the discrete-time transfer function
of the DAC can be expressed as.
(4-14)
4.3.4 Discrete-time Closed Loop Transfer Function
The closed-loop transfer function of the system can be obtained as:
(4-15)
Where F(s) is the feedback path in the continuous time:
(4-16)
Where K1 and K2 are constant gain as defined in Chapter 3.
(4-17)

88

(4-18)
(4-19)
Let 1 = a and 1/2 = b, then
(4-20)

Discrete-time system transforms can be written as.

(4-21)

Since
(4-22)
Then

(4-23)

Simplifying and rearranging this equation, F(z) can be finally written as:
89

(4-24)

Hence the closed-loop transfer function becomes

(4-25)

Finally,
(4-26)

Where,
and

is the injector gain, assumed to be 30, and

is the inverter gain which is equal to -1

are the corner frequency of the LPF and the HPF respectively equal to 10 KHz and 30

MHz; The choice of the K1 is based on the transmission line loss, in an ideal situation the loss is
negligible and the injection gain is unity. Hence, base on measurements, the value of K 1 is
optimized to be equal to 30.
Substituting the numerical values in (4.26), the final transfer function becomes,
(4-27)
The plot of the frequency response magnitude of the above discrete-time equation provides an
evaluation in terms of EMI attenuation of the FPGA-Based EST. This plot is in-line with the one
obtained in Chapter 3 using the continuous-time model. The plot in Fig. 4.4 exhibits an
attenuation performance of more than 70dB at 100 KHz with the loop gain K 1 maintained at 30;
however, the effectiveness of this method depends primarily on the open loop gain of the digital
active filter, i.e. increasing the value of K1 will increase the performance of the noise attenuation,
as shown in Fig. 4.4.
90

Fig. 4.4 Noise attenuation performance of the discrete-time transfer function

4.4 Summary
In this chapter, an FPGA-based technique to suppress conducted EMI emissions in power
converters has been introduced. The principle of operation of the proposed technique has been
explained. The sampled noise is processed using VHDL algorithm, with a set of instructions that
can be executed simultaneously, hence reducing the delay time. The analysis and design approach
were carried out in z-domain. Using the theory of ZOH approximation the closed loop transfer
function is derived in discrete-time. With the sample rate of 10 times the noise bandwidth, it was
found that the approximation was adequate in meeting the design requirements. Furthermore, the
91

frequency response magnitude of the noise attenuation was plotted and shown that increasing the
gain of the injector k1, will directly impact the performance of the noise attenuation. Finally,
comparing the two techniques presented in chapter 3 and chapter 4, one can say that the
difference resides in their performance and the cost of the implementation. In other words, the
FPGA-Based EST performs slightly better than the DSP-Based technique, since this later rely on
the sequential execution of the algorithm, whereas, the FPGA-Based technique, the algorithm is
executed simultaneously which can be translated into a better attenuation. The other factor is the
cost; in this case the cost for implementing the DSP-Based technique is much cheaper than the
FPGA-Based technique.

92

Chapter 5
Integration of the Proposed DAEF in a Digital Controller of a grid-tied
Photovoltaic Micro-inverter

5.1 Introduction
This chapter presents an industrial application case study, in which the proposed DAEF is
integrated into an FPGA-based digital controller of a grid-tied micro-inverter used in solar power
conversion. As opposed to the stand-alone version of the DAEF, the control algorithm is added to
the inverter main program to form a digital control system. Hence, further reduction of the size,
cost and space of the overall power inverter printed circuit board (PCB).
In section 5.2, the general description of the grid-tied PV inverters and their use in Photovoltaic
(PV) power generation are presented. Section 5.3, as a case study, the modeling of the microinverter controller including the DAEF has been investigated. The expression for the control-tooutput transfer function is required to verify the stability of the micro-inverter, using the gain and
phase margin criteria. Experimental results showing the performance of the integrated DAEF in
the micro-inverter are illustrated in section 5.4. Finally, a summary is given in section 5.5.

5.2 Description and Principle of Operation of the Grid-tied Inverters

The main purpose for a grid-tied photovoltaic (PV) inverter is to convert the raw solar energy
from PV panels and feed it to the grid with high efficiency and high power quality. The recent
developments in the PV applications are centered on the utility grid interface rather than standalone systems. In Canada, a government subsidy in forms of tax credit has been introduced to
encourage the use of photovoltaic energy. This incentive makes it possible to the householders to
receive government subsidies representing half of the total cost of the equipment used to harvest
93

the solar energy. There are different configurations for connecting this equipment to the grid.
However, all these approaches are based on an inverter which converts the solar energy into
electrical energy that can be exploited by the consumer. The power inverter is the critical
component in the PV power conversion. A significant progress in the development of the
inverters dedicated to PV systems has been achieved in the last decade. These inverters are not
limited to DC/AC power conversion, but also they do track the maximum power delivered by the
PV panel to maximize the energy throughput. Moreover, they are equipped with monitoring
circuits to ensure a safe operation and to provide protection in the event of power failure, hence,
increasing the reliability of the system. These safety features are enforced by international and
local safety standards such as the UL1741 [97] and IEEE1547 [98]. Currently, there are three
main interface architectures of PV inverters: the centralized inverters, the strings technology and
inverters integrated into the panels or micro-inverters. These architectures are further reviewed in
the following subsections.

5.2.1 Centralized Inverters architecture

In the case of centralized inverter architecture, large numbers of various solar panels (>10kW) are
assembled in lines to form Strings [99], [101]. These strings interface the power inverter through
an isolation diode. The harvest power is then injected into the grid using the power inverter as
shown in Fig. 5.1. The advantage of this configuration is that the central inverter presents high
energy efficiency at reduced costs. The main function of the inverter is to convert the DC power
form the strings into an instantaneous current and voltage suitable for the grid injection. Another
advantage of this architecture is that the power inverter is a two-port network that can be easily
connected to the PV strings. This makes the inverter achieve an efficiency of 95% to 97% with
transformless connection. However, there are numerous drawbacks pertaining to this architecture
namely the issue of shading. For example, in order to feed the grid with 240Vac, a DC voltage of
94

350V is required at the input of the inverter. This is not always the case, since a bad panel or
partial shading will prevent the PV system to generate an adequate DC voltage level at the input
of the inverter. There are other examples, such as high-voltage DC cables interconnecting the PV
modules and the power inverter, power losses due to a centralized maximum power point
tracking (MPPT), and losses in the string isolation diodes. The grid-connected interface stage
(the bridge inverter) is usually line commutated by means of thyristors, generating many current
harmonics and hence poor power quality. Moreover, the reliability of the system is compromised,
since it depends only on one centralized inverter. Thus, when a failure on the central inverter
occurs, it causes a complete system shutdown, consequently, causing production downtime. All
these issues make this architecture less desirable. Thus, a different architecture that overcomes
these problems, in particular the issue of power quality, is required.

AC
DC

AC
Grid

Fig. 5.1 Centralized PV system Architecture

5.2.2 String Inverters architecture
Just as for the centralized architecture, the PV system consists of strings; however, they are
individually connected to an inverter as shown in Fig. 5.2. Thus each string has its own MPPT
controller. This technology reduces considerably the losses due to the effects of shading, while
95

eliminating those caused by the isolation diodes. The technical properties of this architecture
increase the reliability of the PV system. However, the number of medium power inverters is
considerably increased which dramatically increases the cost of the PV system as compared to the
previous architecture.
The advantages and the benefits to use the string inverter architecture over the centralized
architecture are detailed in [102]. However, both architectures have the issue of shading which
has an impact on the PV system throughput. A better solution consists of integrating the low
power inverter known as micro-inverter in each solar panel. This will be briefly described in the
following section.
AC
DC

AC
DC

AC
DC

AC
Grid

Fig. 5.2 String Inverters Architecture

5.2.3 Multi-strings inverter architecture
The multi-string inverter shown in Fig. 5.3 provides improvements to the string inverter
architecture, where several strings are interfaced with their own DC/DC converter to a common
DC/AC inverter [103], [104]. Each DC/DC converter has its own MPPT controller. Hence, any
string failure can be easily detected and isolated. Flexibility is another feature of this architecture.

96

Further system expansion can easily be achieved since a new string with DC/DC converter can be
plugged into the existing platform.
The multi-string architecture can be manipulated to produce a modular PV system to mitigate the
problem with MPPT error detection. This modification consists of integrating the DC/DC
converter with its own MPPT controller to the solar panel. The DC/DC converters are connected
in series to provide the power inverter with an adequate voltage and the strings are then connected
in parallel in order to achieve the desired power. This is illustrated in Fig. 5.4.

DC

String1

AC

DC

DC
DC

String2
DC

DC

String3
DC

Fig. 5.3 Multi-strings Inverter Architecture

97

AC
Grid

DC
DC
DC
DC
DC
DC

AC

DC
DC

DC

AC
Grid

String1
String2

DC
DC
DC
DC

Fig. 5.4 Multi-strings Architecture with distributed MPPT

This architecture is in the development phase and has not yet been approved for deployment.
However, theoretical studies have already proved the feasibility and the stability of such a system.
The improvement is centered in the MPPT controller efficiency compared to other architectures.

5.2.4 Micro-inverters architecture

In this architecture, each solar panel has its own inverter as shown in Fig. 5.5, which theoretically
eliminates the power losses between the solar modules regardless of their location, hence,
resolving the issue of shading [105]-[116].

98

AC
DC

AC
Grid

AC
DC

AC
DC

AC
DC

Fig. 5.5 Micro-inverter Architecture

This architecture is flexible and compatible for future growth using the plug-and-play feature of
the micro-inverter unit. The main disadvantage of this architecture is the efficiency of the microinverter which is low compared to the previous architectures due to the wide voltage difference
between the input and the output which requires high voltage amplification/boost. Moreover,
micro-inverters induce additional wiring costs at the AC side, since each panel must be connected
to the grid. This architecture is suitable for PV systems ranging from low to medium power.
Depending on a specific application and power requirements, the above architectures can be
combined to form a hybrid system to provide an optimum design solution. Table 5-1 illustrates
the differences between the architectures discussed above.

99

Table 5-1 Characteristics Evaluation of different PV systems architectures

Centralized
Inverter

String Inverter
Architecture

Micro-Inverter
Architecture

Architecture
PV Input Voltage
DC Losses
(Cables)

340-800

150-800

20-80

~1%

Negligible

~2%

Inverter Efficiency

95-97%

92-96%

87-93%

Fault Detection

Simple

Complex

Complex

In any case, the selection of architecture depends on the required power delivery and the cost per
watt of the installed PV system. This is depicted in Fig. 5.6.

3$/W

String architecture

2.5$/W

Multi strings
architecture

2$/W

Central Architecture

1.5$/W

Price of the Inverter per Watt installed

Micro-inverters
architecture

1$/W
0$/W
1kW

10kW

100kW

Inverter Rated Power

Fig. 5.6 Cost of PV inverter as a function of the rated power

5.3 Micro-Inverter Circuit Description and Controller Design Techniques

A typical micro-inverter schematic diagram with its digital controller is depicted in Fig. 5.7. The
power circuit of the micro-inverter consists of two stages: DC/DC converter and DC/AC inverter.
100

As an interface between the PV panels and the DC/AC inverter, the DC/DC converter performs a
dual function of a) boosting the PV DC voltage of 40V to a DC voltage of 340V which is
required at the input of the inverter in order to feed the grid with 240Vac; and b) tracking the
maximum power delivered by the PV panel to maximize the energy throughput. Then the second
stage DC/AC inverter converts the DC power into an instantaneous current and voltage suitable
for the grid injection.
The digital control system consists of three main control functions: the MPPT control, the output
inductor current ILf, and the EMI control. Therefore, in the case of the two stage micro-inverter, a
control algorithm is designed to keep the first stage of the inverter (DC/DC converter) operating
at maximum power. While, the second stage control algorithm is dedicated to regulate the
instantaneous current or voltage to be injected into the grid.
PV Panel

Dboost

Lboost

Dflyback

T1

S1

S3

Lf

Z>>> Grid

Cboost

SWboost

Cbus

SWflyback

Cf
S2

S4

To S2 & S3

Vbus

To S1 & S4

Iin
ILf

Vin

Control Algorithm
(MPPT+ Inverter
Control + EMI Control)

ADC
DAC

FPGA-Based Controller

Vgrid

Sensor
(HPF)
Injector
(LPF)

Fig. 5.7 Schematic diagram of a micro-inverter including the digital controller

The first stage control regarding the MPPT is not within the scope of this research work and will
not be discussed in this chapter. As an industrial application case study, this research work will

101

focus on the integration of the proposed DAEF into the second stage control of the microinverter.
To verify the seamless integration of the DAEF into the digital controller of the micro-inverter, it
is required to investigate the stability of the inverter. This can be achieved by deriving the openloop transfer function of the micro-inverter and use one of the stability criteria such as root-locus
or gain-phase margin techniques. Furthermore, a compensator or a controller design is often
required to satisfy the stability conditions under different load and line variations.
As opposed to the DC/DC converters, it is difficult to design a micro-inverter/inverters controller
with high control gain at the fundamental frequency. This is particularly due to their time varying
voltages and/or currents. However, there exist three types of controller design techniques which
are currently used in single-phase power inverters.
The first technique [117], [118] is similar to that of DC/DC converters, with the assumptions that
the voltages and currents are DC variables instead of time variant parameters. This linear timeinvariant controller design approach proves to be inadequate for this type of systems since it
causes a significant steady state error in both amplitude and phase. In order to damp the resonance
of the LC filter in a single-phase inverter and to improve the control bandwidth, various multiple
loop controllers were proposed in literature, including capacitor current feedback, inductor current
feedback and their variations [119]-[124].
The second design approach [125]-[127] is to use a carrier sinusoidal control signal which is
multiplied by the output of the compensator rectified signal to produce a sinusoidal wave shape.
This signal is fed to the pulse width modulator to provide the gating signal of the inverter bridge
MOSFETs. This approach has two negative aspects: first, the gain of the control loop is
continuously varied along the sinusoidal waveform. The minimum gain at the zero crossing point
may cause significant distortion of the output signal due to the variation in the loop gain; second,
102

the regulator performance is very poor under variable load which results in excessive harmonic
contents due to the modulation effect of the compensator output with the carrier reference signal.
The third approach [128] which is adopted in this chapter, presents an alternative way for
controlling the instantaneous inductor current of single-phase DC/AC inverters using Direct
Quadrature (D-Q) reference frame control technique. In a D-Q reference frame, the physical
(Real) Circuit, in conjunction with an "Imaginary Orthogonal Circuit'', is transformed from the
stationary frame to the DQ rotating frame so that the steady state voltage or current in DQ frame
becomes DC variables allowing the design of controller using design techniques developed for
DC/DC converters. This design approach can achieve infinite control gain which results in zero
steady-state error at the fundamental frequency and better dynamic performance of the system.

5.3.1 Output current control in D-Q frame

The controller architecture using the D-Q reference frame control technique of the two-stage
micro-inverter is depicted in Fig. 5.8. This controller diagram consists of three control blocks:
MPPT controller, EMI controller, and the output inductor current controller.
SWboost

Vgrid

ILf

Driver

Vin

Pin

cycle
delay

ID

R-I
IIm
To
D-Q
Imaginary Orthogonal
Transform
Circuit Variable

IQ

Duty_D

Current
Compensator
in
D-Q
Frame

Duty_Q

D-Q
To
R-I
Transform

Duty_R

To Switch Drivers

Iin

LPF

Switching Pattern

MPPT
Controller

HPF

EMI
Controller

Real Circuit Variable

To injection point

S1 & S4

S2 & S3

PLL

ID_ref

IQ_ref

Vgrid

Fig. 5.8 Block diagram micro-inverter controller architecture in rotating D-Q frame
103

It can be seen from Fig. 5.8 that the real variables, which are the output inductor current ILf and
the grid voltage Vgrid, are used to construct the imaginary circuit variables. These later are
transformed into the D-Q rotating frame using the Real-Imaginary (R-I) stationary frame. The
Proportional and Integral (PI) compensator is designed in the rotating frame with constant current
reference ID_ref and IQ_ref. This generates the duty cycle control signals Duty_Q and Duty_D. The
next step is the inverse transform of the duty cycle signals from D-Q frame to R-I stationary
frame. Finally, the duty cycle signals of the imaginary circuit is decoupled from the R-I stationary
frame and only the duty ratio of the real circuit is applied to the DC/AC inverter stage.
Equations (5.1) and (5.2) [128] provide the definition of the rotating transformation matrix from
the stationary frame to D-Q rotating frame. Equation (5.3) and (5.4) [128] are the inverse
transformation from the D-Q rotating frame, back to R-I stationary frame.

(5.1)

(5.2)
Where
and

and

represent the inductor current and the capacitor voltage in the rotating frame,

are the real and the imaginary circuit variables respectively,

the sinusoidal waveform,

is the initial phase and

is the peak value of

is the fundamental frequency.

(5.3)

(5.4)
The circuit model in R-I stationary frame is depicted in Fig. 5.9.The average model of the real
and imaginary circuits can be obtained using the inductor current and the capacitor voltage of the
LC output filter and can be expressed in (5.5) and (5.6).

104

I_R

L_f
R_ESR

DRVbus

C_f

V_R

Zgrid

Ip
Vbus

I_I

R
+

V_I

DIVbus
-

Zgrid

Fig. 5.9 Average circuit model in R-I stationary frame

(5.5)
(5.6)
By applying the D-Q transformation stated in (5.1) and (5.2) to (5.5) and (5.6), yield a circuit
model in the rotating frame which is expressed as.

(5.7)

(5.8)
The circuit model reflecting this transformation is depicted in Fig. 5.10.

105

wL_fI_q

L_f

I_D

R_ESR
DdVbus

wC_eqV_q

C_f

V_D

Zgrid

Ip(D_Q)
wL_fI_d

L_f

I_Q

Vbus

R_ESR
DqVbus

wC_eqV_d

C_f

V_Q

Zgrid

Fig. 5.10 Equivalent circuit model in D-Q rotating frame

It is important to mention that the vector quantities expressed in (5.5) and (5.6) are time-variant,
whereas the quantities in (5.7) and (5.8) are constant DC values. Hence, the design of the closed
loop compensator to ensure the stability of the inverter system can be derived using the
conventional method similar to DC/DC converters. This is realized in the next section.

5.4 Controller design for micro-inverter and stability verification

Design parameters for the micro-inverter, which are based on SPARQ systems [129] microinverter product, are given as:

Topology: first stage buck-boost DC/DC converter, second stage full bridge DC/AC
inverter

Input voltage Vin=30-50Vdc

Output Voltage Vout=240Vac max, Output current Iout=1.25A

Switching frequency Fs=50KHz

106

Output filter components, L=500H, C= 2.2F

Desired current loop bandwidth Fbw=10KHz

Desired phase margin PM=30-90 degrees

The block diagram of the inductor current control loop in the s-domain and its corresponding
digitized system are shown in Fig. 5.11and Fig. 5.12 respectively. Four transfer functions (TF)
are required to verify the system stability. Namely, the plant or the inverter Gp(s), the decoupling
TF resulting from the D-Q transformation Gd(s), the DAEF transfer function FDAEF(s) derived in
chapter 2, and the compensator Gc(s) which need to be designed to fulfill the stability
requirement.
Compensator(Controller)

ILf_ref(s)

Gd(s)

Gc(s)

Plant (Converter + Modulator) DAEF

Gp(s)

GDAEF(s)

ILf(s)

K(sensor)

Fig. 5.11 Current Control Loop in Continuous time

Compensator(Controller)
E(n)

ILf_ref(n)
+

Plant (Converter + Modulator) DAEF

U(n)

Gc(z)

Hc

ZOH

Gd(s)

Gp(s)

GDAEF(s)

K(sensor)
FPGA/DSP

Fig. 5.12 Corresponding discrete model of the current control loop

107

ILf(t)

The open-loop transfer function (TF) for the system without the compensator, can be written as.
(5.9)
Where;
is the modulator gain;

and Vs is the peak value of the oscillator ramp signal.

is the plant DC gain,

is the plant TF which is derived using (5.5) and (5.6) as follows.
(5.10)
(5.11)
Hence,
(5.12)
(5.13)
Substituting (5.12) into (5.13) and including the modulator gain Km and plant gain Kb, the control
to output inductor current TF can be obtained as
(5.14)
The decoupling TF is expressed as,
(5.15)
Finally, the transfer function of the DAEF is given by,
(5.16)

108

Therefore, the uncompensated control-to-inductor current open loop transfer function of the
micro-inverter system, can be evaluated in Matlab and written as,

(5.17)

The bode plot of the open loop uncompensated system transfer function is shown in Fig. 5.13.
The plot exhibits an unstable system, with infinite phase margin and the -20dB slope is far from
crossing the unity gain line (0dB line). Hence, to satisfy the stability criteria, the system must be
compensated.

Fig. 5.13 Bode plot of the open loop un-compensated control system
5.4.1 Compensator design
As previously mentioned, the imaginary circuit model provides a way to transform the real
circuit into the D-Q rotating frame. This converts the sinusoidal steady state into a DC steady
109

state operating point. This conversion allows the micro-inverter compensator to be designed
according to DC/DC converters design method. In this case, the type III compensator is found to
be adequate for this 7th order control system (5.17).
The type III compensator is referred to as double-pole double-zero compensation network
because it introduces double zeros into the error amplifier compensation to reduce the steep gain
slope above the double pole caused by the L-C filter and its associated -1800 phase shift. Type III
compensation network can achieve fast transient response and may provide more than 70 phase
boost. The circuit diagram of the type III compensator is shown in Fig. 5.14.

C2
C3

R3
R2

Vin

C1
Vout

R1
+

Rbias

Vref

Fig. 5.14 Schematic Diagram of Type III Compensator

The transfer function of the compensator of is given as.

GC ( s )

1 sR2C1 1 sC3 R1 R3

CC
sR1 C1 C2 1 sR3C3 1 sR2 1 2
C1 C2

(5.18)

R1 is arbitrarily chosen to be 10 k, so that the parameters values of the circuit can be evaluated
using the K-factor method [130] as follows:

M P 90

K tan
45
4

(5.19)

110

Where M is the desired phase margin in degree, and P is the phase-shift of the converter at
crossover frequency.

C2

1
15.2
2Fc GEA R1

pF

(5.20)

C1 C2 K 1 20 pF

(5.21)

R2

K
1.2 M
2Fc C1

(5.22)

R3

R1
7.5 K
K 1

(5.23)

C3

1
2Fc K R3

1.4 nF

(5.24)

Replacing the parameters values in (5.18), the transfer function of the compensator can be rewritten as,

(5.25)
The type III compensator has a double zero located at a frequency fz below Fc, and a double pole
located at a frequency fp above Fc given as,

fz

Fc
6.5 kHz
K

(5.26)

(5.27)
For complete calculation details of the type III compensator used in this design, please refer to
Appendix D of this thesis.
The gain and phase of the compensator transfer function are shown in Fig. 5.15 and Fig. 5.16
respectively. The plots reveal the amount of the gain and phase boost required to achieve the
system stability.
111

110

Magnitude (dB)

80

50

20

10
1

10

100

1 10

1 10

1 10

1 10

1 10

Frequency (Hz)

Fig. 5.15 Compensator gain plot: Gain boost of 104dB

10

Phase (deg)

50

90

130
1

10

100

1 10

1 10

1 10

1 10

Frequency (Hz)

Fig. 5.16 Compensator Phase plot: Phase boost of 46 deg.

112

1 10

The control-to-inductor current open loop transfer function of the micro-inverter system,
including the compensator, is evaluated in Matlab and written as,

(5.28)

The Bode plot of the micro-inverter compensated control system is shown in Fig. 5.17. It can be
seen that the control system exhibits a gain margin of 28dB and phase margin of 79 degrees.
These parameters are large enough in providing the desired stability of the closed loop control
system.

Fig. 5.17 Bode plot of the compensated micro-inverter control system

113

The Nyquist plot, including the time-delay produced by the ZOH function, is shown in Fig. 5.18.
According to the Nyquist theorem, the net number of the encirclement N is equal to the number
of zeros in the right half-plane (RHP) minus the number of open loop poles P in the right halfplane, in other words;
(5.29)
In the case of the micro-inverter, the number of poles of the open loop TF is P=0, and the number
of zeros in the RHP of the closed loop TF is Z=0, therefore, N=0, which implies that the system is
stable. This is shown in Fig. 5.18, where there is no encirclement of the -1 point. This also proves
that the ZOH delay function is insignificantly low to have an impact on the system stability.

Fig. 5.18 Nyquist Plot of the micro-inverter closed loop control system
114

5.5 Experimental results

The experimental prototype discussed in chapter 3 was applied to the micro-inverter as a proofof-concept. The parameters of the micro-inverter unit were given in section 5.4. Due to the wide
discrepancies between the sampling rates of the power controller compared to the one required by
the DAEF, the latter cannot be implemented inside the FPGA device of the already built-in
micro-inverter controller. This will involve significant modification of the micro-inverter PCB.
Hence, the measurements were done with the stand-alone version of the DAEF. An integrated
version of the DAEF will be dealt with in the next chapter.
The test setup is shown in Fig. 5.19, where the DAEF is connected to the micro-inverter unit. The
unit is fed from a PV-simulator to generate the specific power curve at maximum curve or
maximum power point (MPP). The output of the micro-inverter is connected to the AC-grid
through an isolation transformer. The conducted emission testing run according to CISPR16 test
setup and using CISPR22 standard limits.
Unit Under Test
(UUT)

Test Receiver

PV Simulator
LISN

Fig. 5.19 Conducted emissions test setup

115

The first test was performed with the passive EMI filter only. The results are presented in Fig.
5.20.
The second round of testing was done without any filters in the micro-inverter unit. i.e.: the
passive EMI filter components were removed from the converter unit. The results are shown in
Fig. 5.21.

dBuV
80
70

EN 55022; Class B Conducted, Quasi-Peak

60

EN 55022; Class B Conducted, Average

50
40
30
20
10
0
-10
-20
1

10
(Start = 0.15, Stop = 30.00) MHz

Fig. 5.20 Conducted emissions spectrum of the micro-inverter with passive EMI filter

The last measurement was conducted with the DAEF prototype connected to the AC-side of the
micro-inverter unit. The resulting EMC spectrum is depicted in Fig. 5.22.
As it can be observed, from Fig. 5.20 and Fig. 5.22, the EMI attenuation performance of the
DAEF prototype can match or outperform the one with the passive EMI filter. Furthermore, this
confirms the viability of the proposed DAEF to replace the conventional passive EMI filter.
116

Hence, significant reduction of the PCB space, regardless of the power rating of the microinverter unit, can be achieved.

dBuV
80
70

EN 55022; Class B Conducted, Quasi-Peak

60

EN 55022; Class B Conducted, Average

50
40
30
20
10
0
-10
-20
1

10
(Start = 0.15, Stop = 30.00) MHz

Fig. 5.21 Conducted emissions spectrum of the micro-inverter without EMI filters

dBuV
80
70

EN 55022; Class B Conducted, Quasi-Peak

60

EN 55022; Class B Conducted, Average

50
40
30
20
10
0
-10
-20
1

10
(Start = 0.15, Stop = 30.00) MHz

Fig. 5.22 Conducted emissions spectrum of the micro-inverter with DAEF installed
117

5.6 Summary
The main objective of this chapter is to prove the feasibility of replacing the conventional passive
EMI filter by the DAEF in a solar grid-tied micro-inverter. This is to say that the DAEF can be
integrated into the digital controller of the micro-inverter.
First, this chapter started by providing a brief introduction of the grid-tied photovoltaic inverter. It
described one of the critical components that made up the solar PV system, the micro-inverter. Its
principle of operation was briefly discussed. Then different PV architectures were presented. It is
found that the grid-tied micro-inverter configuration is the best suited to resolve the issue of
shading and minimize cable losses between PV panels. However, there is a trade-off between
efficiency and architecture. The centralized configuration tends to have better efficiency than the
micro-inverter string configuration.
Second, the design and modeling of the micro-inverter was thoroughly analyzed using the D-Q
modeling technique to transform the real circuit into an imaginary circuit, in order to find the DC
operating point. In this state the compensator can be designed using the DC/DC design method.
The closed loop and open loop transfer functions were derived. The stability of the micro-inverter
was verified.
Finally, the experiment results were presented to prove the validity of the DAEF to be integrated
in the micro-inverter circuit as an EMI suppression technique. Hence, significant reduction of the
PCB space regardless of the power rating can be achieved.

118

Chapter 6
Proposed DAEF Integration in a DSP-Based DC-DC Digital Controller
Used in Electric Vehicle (EV) Battery Charger

6.1 Introduction
This chapter presents an industrial application case study, in which the proposed DAEF is
integrated into a DSP-based digital controller of a DC-DC converter used in electrical vehicles
power conversion system. As opposed to the stand-alone version of the DAEF, the control
algorithm is added to the inverter main program to form a digital control system, leading to
further reduction of the size, cost and space of the overall power inverter printed circuit board
(PCB).
In section 6.2, general description of the EV power conversion system and the different
topologies that are used as a battery chargers, are presented. In section 6.3, the closed loop control
system of the full bridge DC-DC converter is studied. The design of the compensator, taking into
account the DAEF transfer function, is presented. The frequency response of the dual voltage and
current control loops is required to verify the stability of the DC-DC converter, using the gain and
phase margin criteria. Experimental results showing the performance of the integrated DAEF in
the digital controller are illustrated in section 6.4. Finally, a summary is given in section 6.5.

6.2 EV Power Conversion System Description

The automotive industry faces two large-scale challenges: collective awareness of the man-made
impact on the environment and the world oil reserves depletion. These two issues are undeniable
and still form the top agendas of a large number of people and institutions; persistent changes are
therefore required. These changes follow two non-conflicting paths; a sociological approach to
119

transportation and a reduction of the environmental impact caused by the vehicles. The
sociological approach requires a radical change in personal attitudes, and a significant overhaul of
the economical activities related to transportation. The attitude is somewhat impossible given our
dependence on cars. However, a technical solution to reduce the environmental impact is rather
collectively acceptable. This is embodied by the electric vehicle (EV). Moreover, the advent of
the all-electric vehicle faces two pitfalls: a lack of technical maturity and a difficulty of the public
acceptance. This is mainly due to its autonomy which is limited by the energy stored in the
battery and the re-charge time; whereas, the conventional internal combustion engine vehicle
(ICEV) has more mobility in terms of mileage and an insignificant time to re-fill the tank. Today,
most of the technical efforts focus on these two aspects namely autonomy and re-charge time.
Unfortunately, the results have not reached the market expectations. This leads to a compromise
solution which is the hybrid (gas/electrical) vehicle (HV). While, the all-electric vehicle is not
ready for large scale deployment, the hybrid vehicle (HV) and fuel cell vehicle (FCV) are a
reality with more than a million cars on the road.
Many research efforts have been focused on developing efficient, reliable, and low-cost power
conversion techniques for the future new energy vehicles [131]-[136]. Two distinct
configurations are available: the plug-in hybrid electric vehicle (PHEV); and the fuel cell hybrid
electric vehicle (FCHEV). This later has an advantage of using hydrogen based energy required
for its autonomy. However, the FCHEV is seen as a long term solution due to its actual cost and
its complex manufacturing. The FCHEV configuration is shown in Fig. 6.1.

120

Gas Tank
Fuel Cell

Combustion Engine/
Motor

Boost Conv.

Buck/Boost
Conv.

DC/AC
Inverter
Battery

Electric
Motor

Wheel

Clutch System
Wheel

Differentiator

Fig. 6.1 Hybrid Parallel Traction System

As for the PHEV, it is a full hybrid vehicle with particular characteristics of having high voltage
batteries which can be charged using a conventional 110Vac outlet. The drive train consists of
two drive options, one is the full drive in which the vehicle is driven using full electrical energy
stored in the batteries, whereas, the other option is the mixed drive where the combustion engine
is used when necessary. These options make the PHEV one of the best vehicles in terms
performance, lower CO2 emissions and higher fuel economy. The first PHEV prototype was

121

designed in 2004 by California cars initiative. Other prototypes emerged then after. The block
diagram of the PHEV configuration is depicted in Fig. 6.2.

Gas Tank

HV
Batteries

AC/DC
Converter

Full Bridge
DC-DC
Converter

Combustion
Engine/Motor

DC/AC
Inverter

LV
Battery

Auxiliary
Circuits

Electric
Motor

Wheel

Clutch System
Wheel
Differentiator

Fig. 6.2 Plug-in Hybrid Vehicle Configuration

In both configurations, the alternative energy source is used to assist the propulsion of the vehicle
during transient and to absorb the kinetic energy during regenerative braking. In the FCHEV
topology, the fuel cell pack is connected to the DC Bus via a boost converter and the energy
storage battery is connected to the DC Bus via a bidirectional DC-DC converter. In the PHEV,
122

the source of energy is directly drawn from the grid and it is used to charge the high voltage (HV)
battery pack through the AC-DC converter which includes power factor correction (PFC)
strategy. The HV battery provides the required energy to drive the electric AC motor through the
DC-AC inverter. The full bridge DC-DC converter is tapped from the HV battery source to
charge the low voltage (LV) battery to provide power to auxiliary circuits. The focus of this
chapter is to integrate the DAEF into the digital controller of the full-bridge DC-DC low voltage
battery charger. The stability assessment of the DC-DC converter including the DAEF will be
investigated, to ensure a safe operation of the converter while providing a significant EMI
suppression.

6.3 Circuit Analysis

6.3.1 Circuit Description
Switched-mode power converters are widely used in energy storage applications, due to their high
efficiency, relatively small size and low cost. In addition, to maintain low profile power
converters, their switching frequency needs to be increased. This results in higher losses and EMI
pollution which is critical for PHEV because of the susceptible vehicle computer. To resolve the
above issues, a resonant converter should be used with zero-voltage switching (ZVS) or zerocurrent switching features. This inherent soft-switching makes the resonant converter to be an
adequate candidate for many power applications [137]-[143]. The full-bridge resonant DC/DC
converters are the most popular topology used in the power range of one to few kilowatts (15KW). Since the switch ratings are optimized for the full- bridge topology, this topology is
extensively used in industrial applications, in particular to be used as auxiliary chargers in the
automotive industry [144]-[147]. High efficiency, high power density and high reliability are the
bench-mark features of this topology. The power circuit of the full-bridge converter with an
123

asymmetric auxiliary circuit is shown in Fig. 6.3. The steady-state analysis of this circuit is
explained in [148].

S1

S3

C1

C3

Laux1

Laux2
VAO

HV Battery
300Vdc

VBO

C4

S2

S4

C2

Ll

Lf1

Lf2

T1
LV Battery
12Vdc
Cf
SR1

SR2

Fig. 6.3 Full-bridge ZVS resonant converter

This circuit can be divided into the following functional blocks: two auxiliary circuits (C1, C2,
Laux1) and (C3, C4, Laux2), full-bridge MOSFET (S1. S2, S3, S4) , a series resonant tank , a high
frequency power transformer T1 , Synchronous rectifier (SR1, SR2) and the output filter (Lf1, Lf2,
Cf).
The auxiliary circuit has the following functions:
Inductors Laux1 and Laux2 provide compensating current to achieve ZVS at higher input voltage.
Capacitors C1, C2 and C3, C4 split the dc input voltage.
The LV battery requires high current and a constant low voltage in this application, and the
current doublers (synchronous rectifier) are used to effectively lower the output inductor copper
124

losses. Hence, the overall efficiency of the power converter can be significantly improved. The
operating principles of the current doublers synchronous rectifier are fully addressed in [149].

6.3.2 Controller Design Strategies and Stability Assessment

Low cost and high performance Digital Signal Processing (DSP) device, with integrated analog
to digital (ADC) converters and pulse width modulator (PWM) makes the digital control of
power converters an attractive control solution. DSP based digital control allows the
implementation of more functions such as power management and circuit protection without the
need for additional discrete components. A few advantages of digital control are: 1) flexibility of
design modifications, 2) susceptibility to environmental variations, 3) aging and 4) better noise
immunity. There are two different approaches in designing a digital controller for switch mode
power converters. Namely, design by emulation, also known as digital redesign, and direct digital
design. The former is being the most popular since it requires minimum exposure in the zdomain. The digital redesign method is based on an analog compensator which is derived in the sdomain using traditional design methods. The analog controller is then converted to a discretetime compensator by some approximate techniques such as: backward Euler, bilinear and
pole/zero matching. Although the backward Euler method and the pole/zero matching method
produce simpler transfer functions in the z-domain, the bilinear method provides good
approximation as it preserves the gain and phase of the analog transfer function up to
approximately one-tenth of the sampling frequency. In the direct digital controller method, the
continuous time power plant model is first converted into its discrete equivalent model with ZOH
and the sampler. Once this is available, the discrete-time compensator is designed directly in the
z-domain using methods similar to the continuous-time frequency response methods. This has the
advantage that the poles and zeros of the digital controller, are directly placed, resulting in a

125

better load transient response. The phase margin and bandwidth of the closed loop system are also
improved as a result.

6.3.3 Digital Controller Design

The direct digital controller approach is adopted in this application. In this method, the average
modeling of the power stage is obtained in the continuous time. Digital poles and zeros with the
integrator are added to design the compensator which is converted to the s-domain using the
relationship,
(6.1)
The layout of the closed loop block diagram including the proposed DAEF is depicted in Fig. 6.4.
The control system consists of two independent digital control loops embedded into one DSP
device and acts upon the power converter. The first loop consists of a dual external voltage loop
and an inner current loop. The external voltage loop takes the reference value of the output
voltage from the charging curve of the battery. This curve varies according to the battery
characteristics and the interface impedance between the battery and the converter. The measured
voltage is discretized using the ADC converter that is integrated into the DSP device. The
resulting digital error is compensated by the digital voltage controller HV(z). The digital
controller determines the reference value of the charging current of the inner loop. This value is
compared to the measured current. The current error is compensated by the current controller
HC(z) in order to produce the proper phase angle for the modulator. The second loop is the DAEF
controller which senses the EMI noise at the input lead of the battery charger. The discretization
of the conducted interference noise is done using a high frequency analog-to-digital converter
(ADC) with a sampling frequency of 250MBPS. A binary inverter is used to invert the EMI noise
signal and a digital-to-analog converter (DAC) to re-construct the noise signal prior to injecting it
back to the input of the power converter. The RF inductor is necessary to de-couple the injection
126

point from the sensed point to prevent the noise signal from flowing towards the auxiliary circuits
interfacing the power converter.

Power Plant and Sensing

Vin
RF Inductor
S1

S3

C1

C3

Laux1

Laux2
VAO

HV Battery
300Vdc

VBO

C4

S4

S2

Hsense1(s)

C2

Vout
Ll

Lf1

Lf2

T1
LV Battery
12Vdc
Cf
SR1

SR2
Hsense(s)

Hinj(s)

Sensor
Vs1

Vs2 Vs3 Vs4

Kpwm

KADC

KDAC

Kinv(z)

KADC

Phase-shift Modulator
KADC

Iref
Z-Td/Ts

Delay

ZOH

Hinteg(z)

Integrator

Hinteg(z)

Hc(z)

Current loop
Compensator

Integrator

HV(z)

Voltage loop
Compensator

Vref

DSP Chip (eZdsp)

Fig. 6.4 closed loop block diagram of the EV auxiliary battery charger
In order to investigate the stability of the converter system including the DAEF, the frequency
response of all the blocks need to be characterized.
127

In order to have an infinite dc loop gain to ensure a zero steady-state error, the output of
compensator passes through an Euler integrator. The integrator is described by the following
transfer function.
(6.2)
A soft complex conjugate zero pair is chosen due to its 180 degrees phase boost and its gain
increase of 40dB/decade. This is illustrated in Fig. 6.5. The transfer function of the complex zero
pair is given by.
(6.3)

8
20log H comp f 2
9
20log H comp f 2
10
20log H comp f 2
12
20log H comp f 2

171.102

10

11

De
cr
ea

sin

arg H comp f 2
arg H comp f 2

Magnitude

20log H comp f 2

arg H comp f 2

50

arg H comp f 2
arg H comp f 2

100 100
100
100

1 10

1 10

Frequency
f

1 10
5
10

180

200

150

180

Phase

100

180

50

CD

180

ecr
eas
ing

180

5.324 50
100
100

1 10

1 10

f
Frequency

1 10
5
110

Fig. 6.5 Bode Plot of soft complex digital zero-pair used for the system compensation
Using the conventional average modeling techniques, the closed loop control-to-output voltage
transfer function and control-to-inductor current transfer function of the uncompensated system,
can be expressed respectively as.

(6.4)

(6.5)

128

Where;

ZOH is the zero-order-hold transfer function given as.

(6.6)
is the delay function given as.
(6.7)
is the analog to digital converter gain, with n the number of bits

(6.8)
is the output voltage sensor which consists of the sensing gain
RC filter whose time-constant is

and a first-order

. This is given as.

(6.9)

is the gain of the PWM, given as.

(6.10)
Where

and m is the register bits format.

The transfer function of the control to output current of the converter is derived as

(6.11)
Where

and

are the output filter capacitor, the output inductor and the load resistor

respectively.
Similarly, the control to output voltage of the converter is derived as.

(6.12)

129

is the transfer function of the digital active EMI filter and it is given by.

(6.13)
Using equations (6.2), (6.3), (6.4) and (6.5), the loop gains of the inner current loop and the outer
voltage loop of the compensated system can be respectively written as.

(6.14)
(6.15)
Fig. 6.6, Fig. 6.7, Fig. 6.8, and Fig. 6.9 show the frequency response of the converter system for
the inner current and the outer voltage loop gains with compensation, taking into account the
parameters presented in Table 6-1. These plots indicate that the system without the compensation
would result in an unstable system. Adding a soft-complex zero pair of b=256 produces a phase
boost of 180o at about 20 KHz in the inner current loop. The digital zero generates a significant
increase in the phase margin of the voltage loop. The compensated current loop has a cross-over
frequency of 200 KHz with a phase margin of 40o. Similarly, the outer voltage compensated loop
gain exhibits a 64o phase margin at 6 KHz cross-over frequency. Low control bandwidth is used
for the voltage loop, due to the slow response of the energy accumulator or the battery. Further
details can be found in Appendix D.

130

150

Magnitude (dB)

100
50
0

0
50
100
150
10

100

1 10

4
5
1 10
1 10
Frequency (Hz)

1 10

1 10

uncompensated system
compensated system
Fig. 6.6 Frequency response of the current loop gain (Magnitude)
270

Magnitude (dB)

180
90
0
90

180

180
270
10

100

1 10

1 10
1 10
Frequency (Hz)
4

1 10

uncompensated
compensated

Fig. 6.7 Frequency response of the current loop gain (Phase)

131

1 10

100
65
Magnitude (dB)

30

5
40
75
110
145
180
10

100

3
4
1 10
1 10
Frequency (Hz)

1 10

1 10

Uncompensated
Compensated

Fig. 6.8 Frequency response of the outer voltage loop gain (Magnitude)
270

Magnitude (dB)

180
90
0
90
90

180

180
270
10

100

1 10
1 10
Frequency (Hz)
3

1 10

Uncompensated
Compensated

Fig. 6.9 Frequency response of the outer voltage loop gain (Phase)

132

1 10

Table 6-1 Converter parameters

Input voltage

300 Vdc

Output voltage

12 Vdc

Output current

90 Amps

Output inductor Lf

1.6 H

Output capacitor Cf

200 F

Load resistance Ro

0.133

Switching frequency fs

200 KHz

Sampling frequency fclock

250 MHz

6.4 Experimental Results and Validations

To verify the co-existence of the DAEF along with the digital controller of the power converter, a
2KW DC-DC battery charger has been built. The system parameters are reported in Table 6-1.
The control algorithm is implemented using TMX320F28335 eZdSp board. This offers a very
flexible environment for advanced calculations. A conditioning circuit was designed as an
interface between the DSP and the power converter. A 14 bits DAC is placed on the prototype
PCB to interface the 14 bits digital data coming from the DSP device. The re-constructed noise
signal is then injected back into the input lead of the DC-DC converter. The complete system test
setup is depicted in Fig. 6.10. Two main tests have been conducted: The first test is the step
response measurements on the load and line to reveal the stability of the system; and, the second
measurement is the evaluation of the performance of the DAEF in terms of noise attenuation of
the conducted EMI.

133

DSP Board

DC-DC
Converter
(EUT)

Fig. 6.10 DC-DC converter conducted emissions test setup

Fig. 6.11 shows the system transient response to a step up disturbance from 25% to 75% on load
current. A negligible overshoot is observed with the system settling down after few cycles.
Similarly, Fig. 6.12 shows the system response when the load current is stepped down from 75%
to 25%.

134

Fig. 6.11 Transient response to a step up change in the load current

Fig. 6.12 Transient response to a step down change in the load current
135

The conducted emission measurements were carried out according to CISPR16-1 test method.
The first test was done with the passive EMI filter designed into the DC-DC converter and the
result is shown in Fig. 6.13. An average noise peak of 60dBuV across the spectrum (150 KHz
30 MHz) can be observed, with the highest peak at 74dBuV.

Fig. 6.13 Conducted emission spectrum with the passive EMI filter
The second test was conducted with no EMI filter installed in the DC-DC converter. The result is
reflected in Fig. 6.14. From this figure, an average noise peak of 80dBuV can be seen, with the
highest peak at 94dBuV.

136

Fig. 6.14 Conducted emissions spectrum with no EMI filter installed

Finally, a third test was performed with the DAEF only. The result is shown in Fig. 6.15. An
average peak of 60dBuV is obtained, with the highest peak at 68dbuV.

Fig. 6.15 Conducted emissions spectrum with DSP-Based DAEF installed

137

From the above conducted EMI spectrum plots, it can be deduced that replacing the passive EMI
filter with the DAEF produces similar or better performance, across the frequency range of 150
KHz to 30MHz.

6.5 Summary
In this chapter, the seamless integration of the DAEF has been demonstrated as being a valid EMI
solution for an industrial application such as the Electric vehicle DC-DC battery charger. This
chapter briefly introduce the power conversion system of a battery powered Electric Vehicle. It
describe the different variations of the EV, namely the hybrid (HEV) and the PHEV. This later
proves to be the best drive system configuration compared to other topologies. The circuit
analysis for the full-bridge resonant DC-DC converter used as a battery charger in the PHEV was
presented. The digital controller design, including the DAEF was derived and the stability
assessment was theoretically verified. Finally, experimental results were illustrated to validate the
co-existence of the DAEF with the digital controller and to achieve a significant EMI attenuation
without the need for the passive EMI filter.

138

Chapter 7
Conclusions & Future Work

7.1 Conclusions
Industrial trends tend to converge towards power converters that can operate at switching
frequencies in the 1-10 MHz range, to achieve greater power density and improved transient
response. However, these technological advances come with a price tag. A tremendous EMI noise
is generated in the power unit, which consequently pollute the utility systems. An immediate
solution would be a passive EMI filter to suppress the conducted emissions and to fulfill the EMC
requirements set forth by government authorities and international standards. The actual
challenge is that the passive EMI filtering solutions are inadequate in following the power density
trend. In other words, the greater the power density of the converter, the bigger the passive filter.
In most cases, the passive EMI filter takes one quarter to a half of the PCB space of the power
converter. To meet the next generation requirements of these applications, in terms of EMI
suppression, four ideas have been proposed in this thesis. These ideas can be summarized as
follows:
1. A DSP-based technique to suppress conducted EMI emissions in power converters has
been proposed. This technique exploits the theory of sampling using data acquisition
devices such as ADC and DAC for discrete time conversion of the EMI noise source. The
impulse function to represent the sampling process has been used for the sensed signal
recovery. The figure-of-merit of the attenuation transfer function, in terms of magnitude,
has revealed that the gain of the injector has a direct impact on the increase of the
magnitude within the desired bandwidth. Finally, the simulation and the experimental

139

results prove the validity of the proposed EMI suppression technique, which can the
passive EMI filters in the power converter.
The content of this chapter has been submitted to the IEEE transactions on power
electronics.
2. An FPGA-based technique to suppress conducted EMI emissions in power converters has
been introduced. The principle of operation of the proposed technique has been
explained. The sampled noise is processed using VHDL algorithm, with a set of
instructions that can be executed simultaneously, hence reducing the delay time. The
analysis and design approach were carried out in z-domain. Using the theory of ZOH
approximation the closed loop transfer function is derived in discrete-time. With the
sample rate of 10 times the noise bandwidth, it was found that the approximation was
adequate in meeting the design requirements. Finally, comparing the two techniques
presented in chapter 3 and chapter 4, it can be concluded that the difference resides in
their performance and the cost of the implementation. In other words, the FPGA-Based
DAEF performs slightly better than the DSP-Based DAEF, since this later rely on the
sequential execution of the algorithm, whereas for the FPGA-Based technique, the
algorithm is executed simultaneously which results in improved attenuation. The other
factor is the cost; in this case the cost for implementing the DSP-Based technique is much
cheaper than the FPGA-Based technique.
The content of this chapter is subject to patent application in the US and Canada. It has
also been submitted for publication in the IEEE Transactions on Industrial Electronics.
3. Integration of the Proposed DAEF in a Digital Controller of a grid-tied Photovoltaic
Micro-inverter has been realized. The design and modeling of the micro-inverter was
140

thoroughly analyzed using the D-Q modeling technique to transform the real circuit into
an imaginary circuit, in order to find the DC operating point. In this state the compensator
can be designed using the DC/DC design method. The closed loop and open loop transfer
functions were derived. The stability of the micro-inverter was verified. Finally, the
experiment results were presented to prove the validity of the DAEF to be integrated in
the micro-inverter circuit as an EMI suppression technique. Hence, significant reduction
of the PCB space regardless of the converter power rating can be achieved.
4. The seamless integration of the DAEF has been demonstrated as being a valid EMI
solution for an industrial application such as the Electric vehicle DC-DC battery charger.
The power conversion system of a battery powered Electric Vehicle has been briefly
introduced. Different variations of the EV have been described, namely the Hybrid
Electric Vehicle (HEV) and the Plug-in Hybrid Electric Vehicle (PHEV). The circuit
analysis for the full-bridge resonant DC-DC converter used as a battery charger in the
PHEV has been presented. The digital controller design, including the DAEF has been
derived. The stability assessment has been theoretically verified. Finally, experimental
results were illustrated to validate the co-existence of the DAEF with the digital
controller and to achieve a significant EMI attenuation without the need for the passive
EMI filter.

7.2 Future Work

The following paragraphs outline the possible future work of the topic proposed in this thesis.
The stand-alone configuration of the DAEF proposed in chapter 3 and chapter 4 has been
implemented using off-the-shelf DSP and FPGA devices respectively. This can drive the cost of
the proposed solution much higher than the passive solution counterpart. In this regard, it might
141

be possible to explore an application specific integrated circuit (ASIC) to provide a smaller, more
reliable and cost effective solution.
The integrated solution proposed in chapter 5 and chapter 6 is based on control algorithm to
reverse the phase of the sensed interference signal. The DAC and the ADC converters used in this
application are discrete components, hence proper PCB grounding need to be addressed. Future
research might be possible to convert the DAC and the ADC functions into a VHDL code as well
as the sense and the injection circuits. The final product would be one single package digital EMI
filter that can be a plug-and-play or an add-on feature into the power converter controller.

142

References
[1]

IEC Draft 22G-WG4-11 Electromagnetic compatibility of power drive systems, Oct. 1994

[2]

H. Ott, "Electromagnetic compatibility Engineering," John Wiley & Son, 2009

[3]

M.C. Caponet, & F. Profumo, "Devices for the separation of the common and differential
mode noise: design and realization," Applied Power Electronics Conference and Exposition,
2002. APEC 2002. Seventeenth Annual IEEE , vol.1, no., pp.100-105 vol.1, 2002

[4]

A. A. Toppeto, Test method to differentiate common mode and differential mode noise, in
Proc. IEEE EMC Symp., Rotterdam, Netherlands, 1979, pp. 497-502

[5]

J. Roudet, R. Scheich, and V. Handel, EMI conducted emission in differential mode

emanating from a SCR: Phenomena and noise level prediction, in Proc. IEEE 1993 APEC,
San Diego, CA, 1993

[6]

J. Roudet, R. Scheich, and A. Orlandi, Origin and propagation of common mode currents
occurring in a bridge rectifier in Proc., 15th Int. Telecommun. Energy Conf., Paris, France,
Sept. 27-30, 1993

[7]

C. R. Paul and K. B. Hardin, Diagnosis and reduction of conducted noise emission, IEEE
Trans. Electromagnetic Compatibility., vol. 30, no. 4, pp. 553-560. 1988. New York: Van
Nostrand Reinhold, 1991

[8]

G. Antonini, S. Christina and A. Orlandi,EMC characterization of SMPS device: Circuit and

Radiated emission model IEEE Transactions on Electromagnetic Compatibility, Vol. 38, No.
3, pp. 300-309, Aug. 1996

[9]

J. Roudet, R. Scheich, and J. Mahdavi, Conducted RFI emission from A DC-DC converter
with sinusoidal line current, in Proc. IEEE 1993 IAS Conf, Toronto, Canada, 1993

143

[10]

D. W. P. Thomas, C. Cristopulos, and E.T. Pereira, Calculation of radiated electromagnetic

fields from cables using time-domain simulation, IEEE Trans. Electromagnetic.
Compatibility, vol. 36, No. 3, pp. 201-205, Aug. 1994

[11]

EN55011 Limits and methods of measurement of radio disturbance characteristics of

industrial, scientific and medical (ISM) radio frequency equipment, pp.12-87, 1999-08

[12]

EN55022 (CISPR22) Information Technology Equipment (ITE) Radio disturbance

characteristics Limits and methods of measurement, pp.10-62, February 1995

[13]

B. Choi, and B. H. Cho, Intermediate Line Filter Design to Meet Both Impedance
Compatibility and EMI Specifications IEEE Transactions on Power Electronics, Vol.10,
No.5, pp. 583-588, Sept. 1995

[14]

J. Miyashita, M. Mitsuzawa, T. Karube, K. Yamasawa, and T. Sato, Measurement of the

Source Impedance of Conducted Emission Using Mode Separable LISN: Conducted
Emission of a Switching Power Supply Electrical Engineering in Japan, Vol. 139, No. 2,
2002

[15]

H. Matsuda et al, "Analysis of common mode noise in switch mode power supplies", NEC
Technical Report. 1998, Vol. 51, pp. 60-65

[16]

S. Ye, W. Eberle, and Y. F. Liu, A Novel EMI Filter Design Method for Switching Power
Supplies IEEE Transactions on Power Electronics, Vol. 19, No. 6, November 2004

[17]

P. Li and B. Lehman, Accurate Loop Gain Prediction for DC-DC Converter Due to the
Impact of Source/Input Filter IEEE Transactions on Power Electronics, Vol.20, No.4, pp.
754- 761, July 2005

[18]

D. Zhang, D. Y. Chen, M. J. Nave, and D. Sable, Measurement of noise impedance of offline converters, IEEE Transactions on Power Electronics, vol. 15, pp. 820825, Sept. 2000

144

[19]

R. D. Middlebrook, Design techniques for preventing input filter oscillations in switched

mode regulators, in Proc. Powercon78, 1978, pp. A3.1-A3.16.

[20]

M. Jin, and M. Weiming, Power Converter EMI Analysis Including IGBT Nonlinear
Switching Transient Model IEEE Transactions on Industrial Electronics, Vol. 53, No. 5,
October 2006

[21]

C. Hua, C. Shen, and G. Peng, Design of an Input Filter to Suppress Conducted EMI of a
Single Phase UPS Inverter In Proc. IEEE 22nd International Conference IECON, vol.3,
pp.1699 1704, 5-10 Aug.1996

[22]

F.L. Martin, F.W. Arthur, Input filter Design for multiple-module DC power systems IEEE
Transactions on Power Electronics, Vol.11, No.3, pp. 472 - 488, May 1996

[23]

F. C. Lee, and Y. Yu, Input filter design for switching regulators, IEEE Transactions on
Aerospace and Electronic System, vol. AES-15, no. 5, pp. 627-634, 1979

[24]

T. Guo, D. T. Chen, and F. C. Lee,Separation of the Common-Mode and Differential-Mode

Conducted EMI Noise IEEE Transactions on Power Electronics, Vol. 11, No. 3, May 1996

[25]

M. J. Nave, Power Line Filter Design for Switched-Mode Power Supplies. New York: Van
Nostrand Reinhold, 1991

[26]

R.D. Middlebrook, Input Filter Considerations in Design and Application of Switching

Regulators in Proc. IEEE Industry Applications Soc. Annual. Meeting, 1976, pp. 336-382

[27]

P. K. Jain, A. St-Martin, and G. Edwards, Asymmetrical pulse-width modulated resonant

dc/dc converter topologies IEEE Transactions on Power Electronics, vol.11, pp.413422,
May1996

[28]

G. Hua, et al, Novel Zero Voltage Transition PWM Converters, Proceedings of the Power
Electronics Specialist Conference, Spain, June 29 - July 3, 1992.

145

[29]

M. M. Jovanovic, W. A. Tahisz, and F. C. Lee, High frequency off- line power conversion
using zero voltage switching quasiresonant and multi-resonant techniques, IEEE Trans.
Power Electronics, pp. 459-469. Oct. 1989

[30]

W. A. Tahisz and F. C. Lee, Zero voltage switching multi-resonant techniques-a novel

approach to improve performance of high frequency quasi-resonant converters Power
Electronics Specialists Conference, vol. 1, pp. 9-17, 1988

[31]

V. Vorperian, Quasi-square-wave converters: Topologies and analysis IEEE Trans. Power

Electronics, Vol. 3, No. 2, pp. 183-191, Apr. 1988

[32]

R. Zeng, D. Y. Chen, and F. C. Lee, Variations of quasi-resonant dc-dc topologies, in

IEEE Power Electronics Spec. Conf., 1986, pp. 381-392

[33]

M. K. Kazimierczuk and X. T. Bui, Class E dc/dc converters with an inductive impedance

inverter, IEEE Trans. Power Electronics, pp. 124-135, Jan. 1989

[34]

M. M. Jovanovic, D. C. Hopkins, and F. C. Lee, Evaluation and design of megahertzfrequency off-line zero current switched quasiresonant converters IEEE Trans. Power
Electron., pp. 136-146, Jan. 1989

[35]

D. C. Hopkins, M. M. Jovanovic, F. C. Lee, and F. W. Stephenson, Hybridized off-line 2MHz zero current switched quasiresonant converters IEEE Trans. Power Electronics, pp.
147-154, Jan. 1989

[36]

P. Jain. H. Soin, and M. Cardella, Constant frequency resonant dc/dc converter topologies
with zero switching losses IEEE Trans. Aerospace Electronic Syst., vol. 30, no. 2 pp. 534544, Apr. 1994

[37]

P. K. Jain, Asymmetrical pulse width modulated resonant dc/dc converter U.S. Patent
5159541, Oct. 27, 1992

146

[38]

D. Zhang and D. Chen, An Experimental Comparison of Conducted EMI emissions between

Zero-Voltage Transition Circuit and a Hard Switching Circuit, IEEE Proc. Power
Electronics Spec. Conf., 1996, pp. 1992-1997

[39]

S.Mangat, M. Qiu, and P.Jain, A Modified Asymmetrical Pulse-Width Modulated Resonant

DC/DC Converter Topology IEEE Trans. Power Electronics, Vol.19, No. 1, pp. 104-111,
January 2004

[40]

Hardin et al., United States Patent 5448627, Jan. 1996.

[41]

R. C. Dixon, Spread Spectrum Systems. New York, NY: Wiley, 1984.

[42]

K. B. Hardin, J. T. Fessler, and D. R. Bush, Spread spectrum clock generation for the
reduction of radiated emissions in Proc. IEEE Int. Symp. Electromagnetic Compatibility,
1994, pp. 227231

[43]

H. Li, Y. Cheng, and D. Puar, Dual-loop spread-spectrum clock generator, in Dig. Tech.
Papers, IEEE Int. Solid State Circuits Conf., 1999, pp. 184185

[44]

F. Linand D. Chen, Reduction of power supply EMI emission by switching frequency

modulation, IEEE Trans. Power Electron., vol. 9, pp.132137, Jan. 1994

[45]

Y. F. Yang, L. Yang, and C. Q. Yang, EMI reduction of power supplies by bi-frequency

modulation, in Proc. IEEE Applied Power Electronics Conf. Expo (APEC), Feb. 1317,
1994, pp. 601607

[46]

T. Tanaka, H. Hamasaki, and H.Yoshida, Random-switching controlling DC-to-DC

converters: An implementation using m sequence, in Proc. IEEE Int. Telecommunications
Energy Conf. (INTELEC), Oct. 1923, 1997, pp.431437

[47]

A. C. Wang and S. R. Sanders, Programmed pulse width modulated waveforms for

electromagnetic interference mitigation in DC-DC converters, IEEE Trans. Power Electron.,
vol. 8, no.4,pp.596605, Oct. 1993
147

[48]

K. K. Tse, H. S. H. Chung, S. Y. Hui, and H. C. So, Analysis and spectral characteristics of

a spread-spectrum technique for conducted EMI suppression, IEEE Trans. Power Electron.,
vol. 15, no. 2, pp.399410, Mar. 2000

[49]

T. Ninomiya, M. Shoyama, C. F. Jin, and G. Li, EMI issues in switching power converters,
in Proc. IEEE Int. Symp. Power Semiconductor Devices I. C, (ISPSD), Jun. 47, pp. 8186,
2001

[50]

K. K. Tse, H. S. H. Chung, S. Y. Hui, and H. C. So, A comparative study of using random

switching schemes for DC/DC converters in Proc. IEEE Applied Power Electronics Conf.
Expo (APEC), Mar.14 8, pp. 160166, 1999

[51]

M. M. Bech, J. K. Pedersen, F. Blaabjerg, and A. M. Trzynadlowski, A methodology for

true comparison of analytical and measured frequency domain spectra in random PWM
converters, IEEE Trans. Power Electron., vol. 14, no.3, pp.578586, May 1999

[52]

A. K. Jaroslaw, and L. Piotr J. C. Conducted EMI mitigation in Switch mode converters by

spread spectrum techniques Electrical power quality and Utilization Journal, Vol XI, No 2,
2005

[53]

J. Balcells, A. Santolaria, A. Orlandi, D. Gonzales, and J. Gago, EMI Reduction in Switched

Power Converters Using Frequency Modulation techniques, IEEE Transactions on
Electromagnetic Compatibility, Vol.47, No.3, pp. 569-576, Aug. 2005

[54]

S. Johnson and R. Zane, Custom Spectral Shaping for EMI Reduction in High Frequency
Inverters and Ballast IEEE Transactions on Power Electronics, Vol. 20, No. 6, November
2005

[55]

L. Laskaii, P. N. Enjeti, and I. J. Pitel, White noise modulation of high frequency high
intensity discharge lamp ballasts, IEEE Trans. Ind. Appl., vol. 34, no. 3,pp. 597605,
May/Jun. 1998
148

[56]

N. K. Poon, Techniques for input ripple current cancellation: Classification and

implementation, IEEE Trans. Power Electron., vol. 15, no. 6, pp. 11441152, Nov. 2000.

[57]

Y. C. Son and S. K. Sul, A new active common mode EMI filter for PWM inverter, IEEE
Trans. Power Electron., vol. 18, no. 6, pp. 13091314, Nov. 2003

[58]

P. C. Murphy, An active ripple filtering technique for improving common mode inductor
performance, IEEE Power Electron. Letter., vol. 2, no. 2,pp. 4550, Jun. 2004

[59]

T. Farkas and M. F. Schlecht, Viability of active EMI filters for utility applications, IEEE
Trans. Power Electron., vol. 9, pp. 328337, May 1994

[60]

D. Y. Lee and B. H. Cho, Design of an input filter for power factor correction (PFC) AC to
DC converters employing an active ripple cancellation, in Proc. 3rd Intersoc. Energy
Conversion Eng. Conf., 1996, pp. 582586

[61]

D. C. Hamill, An efficient active ripple filter for use in DCDC conversion, IEEE Trans.
Aero. Electronic Syst., vol. 32, pp. 10771084, July 1996.

[62]

J. W. Kolar, H. Sree, N. Mohan, and F. C. Zach, Novel aspects of an application of zero

ripple techniques to basic converter topologies, IEEE PESC Rec., pp. 796803, 1997

[63]

I. Takahashi, A. Ogata, H. Kanazawa, and A. Hiruma, Active EMI filter for switching noise
of high frequency inverters, in Proc. Power Conversion Conf., Nagaoka, Japan, 1997, pp.
331334

[64]

A. L. Julian, R. Cuzner, G. Oriti, and T. A. Lipo, Active filtering for common mode
conducted EMI reduction in voltage source inverters, in Proc. IEEE APEC, 1998, pp.934
939

[65]

S. Ogasawara, H. Ayano, and H. Akagi, An active circuit for cancellation of common mode
voltage generated by a PWM inverter, IEEE Trans. Power Electron., vol. 13, pp. 835841,
Sept. 1998
149

[66]

[11] D. C. Hamill and P. T. Krein, A zero ripple technique applicable to any DC converter,
in Proc. IEEE PESC Rec., pp.11651171, 1999,

[67]

L. Bruton, Active RC Circuits: Theory and Design. Englewood Cliffs, NJ: Prentice Hall,
1980.

[68]

J. Marrero and C. Pang, Ripple current reduction circuit, U. S. Patent 5038263, Aug. 1991

[69]

L. LaWhite and M. F. Schlecht, Design of active ripple filters for power circuits operating in
the 110MHz range, IEEE Trans. Power Electron., vol. 3,no. 3,pp. 310317, Jul. 1988.

[70]

A. C. Chow and D. J. Perreault, Design and evaluation of an active ripple filter using voltage
injection, in Proc. IEEE Power Electronics Specialist Conf.01, Jun. 1721, pp. 390397,
2001

[71]

Y. C. Son and S. K. Sul, Generalization of active filters for EMI reduction and harmonics
compensation, in Proc. 38th Industry Applications Conf., Oct. 1216, pp. 12091214, 2003

[72]

M. El-Habrouk, Active power filters: A review, Proc. Inst. Elect. Eng. Electric Power
Appl., vol. 147, pp.403413, Sep. 2000

[73]

W. Chen, X. Yang, and Z. Wang, An Active EMI Filtering Technique for Improving Passive
Filter Low Frequency Performance," IEEE Transactions on Electromagnetic Compatibility,
Vol. 48, No.1, Feb. 2006

[74]

Hamza, and P. K. Jain, Conducted EMI noise mitigation in DC-DC converters using active
filtering method, IEEE Power Electronics Specialists Conference, pp. 188 194, 2008

[75]

K.W. Yuk, and, L.Y. Shu, and K.C. David, Synthesis of a wide bandwidth current sensor
using a current transformer for active power filter applications, IEEE- PESC, Vol.1, pp. 270
273, 2000

[76]

Y. Duan, and H. Jin, Digital controller design for switch mode power converters, in Proc.
IEEE Appl. Power Electron. Conf. (APEC), vol. 2, pp. 967973, 1999
150

[77]

J. Xiao, A.V. Peterchev, and S. R. Sanders,Architecture and IC implementation of a digital

VRM controller, in Proc. IEEE Power Electron. Spec. Conf. (PESC), vol. 1, pp. 3847, 2001

[78]

A. Prodic, D. Maksimovic, and R. W. Erickson, Design and implementation of a digital

PWM controller for a high frequency switching dcdc power converter, in Proc. IEEE Ind.
Electron. Soc. Conf. (IECON), vol. 2, pp.893898, 2001

[79]

B. J. Patella, A. Prodic, A. Zirger, and D . Maksimovic, High frequency digital controller IC

for DC/DC converters, in Proc. IEEE Appl. Power Electron. Conf. (APEC), vol. 1, pp. 374
380, 2002

[80]

A. M.Wu, J. Xiao, D. Markovic, and S. R. Sanders, Digital PWM control: Application in

voltage regulation modules, in Proc. IEEE Power Electron. Spec. Conf. (PESC), vol. 1, pp.
7783, 1999

[81]

M. Fuand Q. Chen,A DSP based controller for Power Factor Correction (PFC) in a rectifier
circuit, in Proc. IEEE Appl. Power Electron. Conf. (APEC),vol.1, pp.144149, 2001

[82]

Y.T. Feng, G. L.Tsai, and Y. Y. Tzou, Digital control of a single stage single switch flyback
PFC AC/DC converter with fast dynamic response, in Proc. IEEE Power Electron. Spec.
Conf. (PESC), vol. 2, pp.12511256, 2001

[83]

A. Prodic, J. Chen, R.W. Erickson, and D. Maksimovic, Digitally controlled low harmonic
rectifier having fast dynamic response, in Proc. IEEE Appl. Power Electron. Conf. (APEC),
vol. 1, pp. 476782, 2002

[84]

L. Keh-La, K. Armin, and H. J. Bedrich " Modular Low-Power, High-Speed CMOS Analogto-Digital Converter for Embedded Systems", press, 2004

[85]

PSPICE Cadence simulation Software, http://www.cadence.com/us/pages/default.aspx

[86]

CISPR16-1 standards, International Electro-technical Commission (IEC),Specification for

radio disturbance and immunity measuring apparatus and methods- part 1
151

[87]

EN55022 (CISPR22) Information Technology Equipment (ITE) Radio disturbance

characteristics Limits and methods of measurement, pp.10-62, February 1995

[88]

A. de Castro, P. Zumel, O. Garca, T. Riesgo, and J. Uceda, Concurrent and Simple Digital
Controller of an AC/DC Converter with Power Factor Correction Based on an FPGA, IEEE
Transactions on Power Electronics, Vol. 18, No. 1, January 2003

[89]

S. Hauk,The roles of FPGAs in reprogrammable systems, Proc. IEEE, vol. 86, pp. 615
638, Apr. 1998

[90]

W. Tang, Y. Jiang, G. C. Hua, F. C. Lee, and I. Conen, Power factor correction with flyback
converter employing charge control, in Proc. IEEE Appl. Power Electron. Conf. (APEC),
pp. 293298, 1993

[91]

A. V. Peterchevand S. R. Sanders, Quantization resolution and limit cycling in digitally

controlled PWM converters, IEEE Transactions on Power Electronics, vol. 18, No 1, pp.
301308, 2003

[92]

IEEE Standard VHDL Language Reference Manual, IEEE STD 1076-1993.

[93]

A. Rushton, Ed., VHDL for Logic Synthesis. New York: Wiley, 1998.

[94]

G. Spiazzi, P. Mattavelli, and L. Rossetti, Power factor pre-regulators with improved

dynamic response, in Proc. IEEE Power Electron. Spec. Conf. (PESC), vol. 1, pp. 150156,
1995

[95]

T. Riesgo, Y. Torroja, and E. dela Torre,Design methodologies based on hardware

description languages, IEEE Trans. Ind. Electron., vol. 46, pp. 312, Feb. 1999

[96]

IEEE Standard VHDL Analog and Mixed-Signal Extensions, IEEE Std 1076.1,1999

[97]

UL1741 UL Standard for Safety Inverters, Converters, Controllers and Interconnection

System

Equipment

for

Use

With

Laboratories Inc, May 7, 1999

152

Distributed Energy Resources, Underwriters

[98]

IEEE1547 IEEE Standard for Interconnecting Distributed Resources With Electric Power
Systems, IEEE Std. 1547, 2003.

[99]

M. Calais, J. Myrzik, T. Spooner, and V. G. Agelidis, Inverters for single-phase grid

connected photovoltaic systemsAn overview, in Proc. IEEE PESC02, vol. 2, pp. 1995
2000, 2002

[100]

H. Haeberlin, Evolution of inverters for grid connected PV-systems from 1989 to 2000, in
Proc. 17th Eur. Photovoltaic Solar Energy Conf., Munich, Germany, Oct. 2226, pp. 426
430, 2001

[101]

F. Chan, & H. Calleja , "Reliability Estimation of Three Single-Phase Topologies in GridConnected PV Systems," Industrial Electronics, IEEE Transactions on , vol.58, no.7,
pp.2683-2689, July 2011

[102]

N. P. Papanikolaou, E. C. Tatakis, A. Critsis, and D. Klimis, Simplified high frequency

converter in decentralized grid-connected PV systems: a novel low-cost solution, in Proc.
EPE03, 2003, CD-ROM.

[103]

N. A. Rahim, J. Selvaraj, "Multistring Five-Level Inverter With Novel PWM Control Scheme
for PV Application," Industrial Electronics, IEEE Transactions on , vol.57, no.6, pp.21112123, June 2010

[104]

A.M. Pavan, S. Castellan, S. Quaia, S. Roitti, and G. Sulligoi, " Power Electronic
Conditioning Systems for Industrial Photovoltaic Fields: Centralized or String Inverters? "
Clean Electrical Power, 2007. ICCEP '07. International Conference on, pp., 208 214, 21-23
May 2007

[105]

M. Meinhardt, T. ODonnell, H. Schneider, J. Flannery, C. O. Mathuna, P. Zacharias, and T.

Krieger, Miniaturized low profile module integrated converter for photovoltaic
applications with integrated magnetic components, in Proc. APEC99, vol. 1, pp. 305311,
153

1999
[106]

T. Shimizu, K. Wada, and N. Nakamura, A flyback type single phase utility interactive
inverter with low-frequency ripple current reduction on the DC input for an AC photovoltaic
module system, in Proc. IEEE PESC02, vol. 3, pp. 14831488, 2002

[107]

S. B. Kjaer and F. Blaabjerg, Design optimization of a single phase inverter for photovoltaic
applications, in Proc. IEEE PESC03, vol. 3, pp. 11831190, 2003

[108]

M. Nagao and K. Harada, Power flow of photovoltaic system using buck-boost PWM power
inverter, in Proc. PEDS97, vol. 1, pp.144149, 1997

[109]

S. Mekhilef, N. A. Rahim, and A. M. Omar, A new solar energy conversion scheme

implemented using grid-tied single phase inverter, in Proc. IEEE TENCON00, vol. 3, pp.
524527, 2000

[110]

E. Achille, T. Martir, C. Glaize, and C. Joubert, Optimized DC-AC boost converters for
modular photovoltaic grid-connected generators, in Proc. IEEE ISIE04, pp. 10051010,
2004

[111]

D. C. Martins and R. Demonti, Grid connected PV system using two energy processing
stages, in Conf. Rec. 29th IEEE Photovoltaic Specialists Conf., pp. 16491652, 2002

[112]

A. Lohner, T. Meyer, and A. Nagel, A new panel integratable inverter concept for gridconnected photovoltaic systems, in Proc. IEEE ISIE96, vol. 2, pp. 827831, 1996

[113]

S. B. Kjaer, J.K. Pedersen,and F. Blaabjerg, A Review of Single-Phase Grid-Connected

Inverters for Photovoltaic Modules IEEE Transactions on Industry Applications, vol. 41, no.
5, Sept / Oct 2005

[114]

Q. Li, and P. Wolfs, A Review of the Single Phase Photovoltaic Module Integrated
Converter Topologies with Three Different DC Link Configurations IEEE Transactions on
Power Electronics, vol. 23, no. 3, May 2008
154

[115]

S.V. Araujo, P. Zacharias, & R. Mallwitz, "Highly Efficient Single-Phase Transformerless

Inverters for Grid-Connected Photovoltaic Systems," Industrial Electronics, IEEE
Transactions on , vol.57, no.9, pp.3118-3128, Sept. 2010

[116]

N.A. Rahim, K. Chaniago, , J. Selvaraj, "Single-Phase Seven-Level Grid-Connected Inverter

for Photovoltaic System," Industrial Electronics, IEEE Transactions on , vol.58, no.6,
pp.2435-2443, June 2011

[117]

D.N. Zmood and D.G. Holmes, "Stationary frame current regulation of PWM inverters with
zero steady state error," Proceedings of IEEE Power Electronics Specialists Conference, pp.
1185-1190, 1999,

[118]

Xiaoming Yuan, Willi Merk., Herbert Stemmler, Jost Allmeling, "Stationary

frame

generalized integrators for current control of active power filters with zero steady state error
for current harmonics of concern under unbalanced and distorted operation conditions,"
IEEE Transactions on Industry Applications, Vol. 38, No. 2, pp. 523 -532, Mar/Apr 2002,
[119]

E. Villanueva, P. Correa, J. Rodriguez, & M. Pacas , "Control of a Single-Phase Cascaded HBridge Multilevel Inverter for Grid-Connected Photovoltaic Systems," Industrial Electronics,
IEEE Transactions on , vol.56, no.11, pp.4399-4406, Nov. 2009

[120]

R. A. Mastromauro, M. Liserre, & A. Dell'Aquila , "Study of the Effects of Inductor

Nonlinear Behavior on the Performance of Current Controllers for Single-Phase PV Grid
Converters," Industrial Electronics, IEEE Transactions on , vol.55, no.5, pp.2043-2052, May
2008

[121]

C. Meza, J. J. Negroni, D. Biel, F. Guinjoan, "Energy-Balance Modeling and Discrete

Control for Single-Phase Grid-Connected PV Central Inverters," Industrial Electronics, IEEE
Transactions on , vol.55, no.7, pp.2734-2743, July 2008

[122]

M. Castilla, J. Miret, J. Matas, L. Garcia de Vicuna, & J.M. Guerrero , "Control Design
155

Guidelines for Single-Phase Grid-Connected Photovoltaic Inverters With Damped Resonant

Harmonic Compensators," Industrial Electronics, IEEE Transactions on , vol.56, no.11,
pp.4492-4501, Nov. 2009
[123]

R. Gonzalez, E. Gubia, J. Lopez, & L. Marroyo , "Transformerless Single-Phase MultilevelBased Photovoltaic Inverter," Industrial Electronics, IEEE Transactions on , vol.55, no.7,
pp.2694-2702, July 2008

[124]

R.A. Mastromauro, M. Liserre, T. Kerekes, & A. Dell'Aquila, "A Single-Phase VoltageControlled Grid-Connected Photovoltaic System With Power Quality Conditioner
Functionality," Industrial Electronics, IEEE Transactions on , vol.56, no.11, pp.4436-4444,
Nov. 2009

[125]

J. Selvaraj, N. A. Rahim , "Multilevel Inverter For Grid-Connected PV System Employing

Digital PI Controller," Industrial Electronics, IEEE Transactions on , vol.56, no.1, pp.149158, Jan. 2009

[126]

Q. Zhang, X. Sun, Y. Zhong, M. Matsui, & B. Ren, "Analysis and Design of a Digital PhaseLocked-Loop for Single-Phase Grid-Connected Power Conversion Systems," Industrial
Electronics, IEEE Transactions on , vol.58, no.8, pp.3581-3592, Aug. 2011

[127]

M. Castilla, J. Miret, J. Matas, L.G. de Vicua, & , J.M. Guerrero, "Linear Current Control
Scheme With Series Resonant Harmonic Compensator for Single-Phase Grid-Connected
Photovoltaic Inverters," Industrial Electronics, IEEE Transactions on , vol.55, no.7, pp.27242733, July 2008

[128]

L. Zhigang, L. Alesi, Z. Xiaohu, J. Li, and A. Huang, Digital Controller Design for PV
Inverter with Model Based Technique IEEE proceedings, Energy Congress and Exposition
(ECCE), pp.2950-2955, 2010

[129]

SPARQ systems inc. is a spin-off company under Queens university and its technology
156

transfer PARTEQ innovations. http://www.sparqsys.com/

[130]

Modelling, Analysis and Compensation of the Current Mode Converter, Unitrode

Application Note U-97.

[131]

N.D. Weise, K.K. Mohapatra, & N. Mohan, "Universal utility interface for Plug-in Hybrid
electric vehicles with vehicle-to-grid functionality," Power and Energy Society General
Meeting, 2010 IEEE , vol., no., pp.1-8, 25-29 July 2010

[132]

F. Cheli, F.L. Mapelli, R. Manigrasso, D. Tarsitano , "Full energetic model of a plug-in

hybrid electrical vehicle," Power Electronics, Electrical Drives, Automation and Motion,
2008. SPEEDAM 2008. International Symposium on , vol., no., pp.733-738, 11-13 June 2008

[133]

S.A. Rahman, N. Zhang, & Z. Jianguo, "Modeling and simulation of an energy management
system for Plug-in Hybrid Electric Vehicles," Power Engineering Conference, 2008. AUPEC
'08. Australasian Universities , vol., no., pp.1-6, 14-17 Dec. 2008

[134]

X. Xu, C. Wang, G. Liao, C.P. Yeh, W. Stark, "Development of a Plug-In Hybrid Electric
Vehicle educational demonstration unit," North American Power Symposium (NAPS), 2009 ,
vol., no., pp.1-7, 4-6 Oct. 2009

[135]

S.G. Wirasingha, & A. Emadi, "Classification and Review of Control Strategies for Plug-In
Hybrid Electric Vehicles," Vehicular Technology, IEEE Transactions on , vol.60, no.1,
pp.111-122, Jan. 2011

[136]

M. Ferdowsi, "Plug-in Hybrid Vehicles - A Vision for the Future," Vehicle Power and
Propulsion Conference, 2007. VPPC 2007. IEEE , vol., no., pp.457-462, 9-12 Sept. 2007

[137]

I. Cervantes, S. Perez-Teniers, Zero-voltage-transition control for a class of resonant

converters, IEEE Transactions on Industrial Electronics, Vol 53, No 5, pp. 17471749, 2006

[138]

B.R. Lin, & C.H. Tseng, Analysis of parallel-connected asymmetrical soft-switching

converter, IEEE Trans. Ind. Electron., Vol 54, No 3, pp. 16421653, 2007
157

[139]

Y.C. Chuang, & Y.L. Ke, A novel high-efficiency battery charger with a buck zero-voltageswitching resonant converter, IEEE Trans. Energy Conversion., Vol 22, No 4, pp. 848854,
2007

[140]

Egan, M.G., OSullivan, D.L., Hayes, J.G., Willers, M.J., Henze, C.P.: Power-factorcorrected single-stage inductive charger for electric vehicle batteries, IEEE Trans. Ind.
Electron., Vol 54, No 2, pp. 12171226, 2007

[141]

C. Ying-Chun; K. Yu-Lung, "A Novel High-Efficiency Battery Charger

With

Buck

Zero-Voltage-Switching Resonant Converter," Energy Conversion, IEEE Transactions on ,

vol.22, no.4, pp.848-854, Dec. 2007.
[142]

H.L. Chan, K.W.E. Cheng, & D. Sutanto, A ZCSZVS bi-directional phase-shifted DCDC
converter with extended load range, IEE Proc. Electronic Power Applications, Vol 150, No
3, pp. 269277, 2003

[143]

B.P. McGrath, D.G. Holmes, P.J. Mc Goldrick, & A.D. McIver, Design of a soft-switched 6kW battery charger for traction applications, IEEE Trans. Power Electronics, Vol 22, No 4,
pp. 11361144, 2007

[144]

R. Ayyanar, & N. Mohan, A novel full-bridge DCDC converter for battery charging using
secondary-side control combines soft switching over the full load range and low magnetics
requirement, IEEE Trans. Industrial Applications, Vol 37, No 2, pp. 559565, 2001

[145]

Z.

Xiaohu, W. Gangyao, S. Lukic, & S. Bhattacharya, A. Huang, "Multi-function bi-

directional battery charger for plug-in hybrid electric vehicle application," Energy
Conversion Congress and Exposition, 2009. ECCE 2009. IEEE , vol., no., pp.3930-3936, 2024 Sept. 2009

158

[146]

P.K. Jain, W. Kang; H. Soin, & X. Youhao, "Analysis and design considerations of a load
and line independent zero voltage switching full bridge DC/DC converter topology," Power
Electronics, IEEE Transactions on , vol.17, no.5, pp. 649- 657, Sep 2002

[147]

Pahlevaninezhad, M.; Drobnik, J.; Jain, P.; Bakhshai, A.; , "A Load Adaptive Control
Approach for a Zero Voltage Switching DC/DC Converter Used for Electric Vehicles,"
Industrial Electronics, IEEE Transactions on , Vol. 59, No.2, pp. 920-933, 2012

[148]

H. Al-Atrash, & I. Batarseh, "Digital Controller Design for a Practicing Power Electronics
Engineer," Applied Power Electronics Conference, APEC 2007 - Twenty Second Annual
IEEE , pp.34-41, Feb. 25 2007- March 1 2007

[149]

Y. Panov, and M.M. Jovanovic, "Design and performance evaluation of low-voltage/highcurrent DC/DC on-board modules," IEEE Transactions on Power Electronics, Vol 16, No 1,
pp. 26-33, 2001

159

Appendix A
Simulation Schematics

A.1 DC-DC Converter Operating in Continuous Mode, including the Line

Impedance Stabilization Circuit

S1

M1
IRF640

L2
1uH

V1

R5

output

0.01

C2
100u

g1
g2

IRF640
M2

E1

R81
1

12Vdc

+
-

+
-

R6
0.002

S2

R82
0.00001

+
-

+
-

E
E411

+
-

F1
F

+
-

GAIN = 1

R83

100m

E412
E
C80

20p

R86
0.002

C70

R12

23.7k

L5
1.5mH

C81
536p

816
R80

E410

C82

+
-

pwm_out

+
-

Error Amplifier

stp(V(%IN))

0.2uF

L3

50uH

L4
50uH

C83
100nR85

R84

50

2
C84
100n

R87

C85

10

10n

10k
OUT
+
U7

SAW

V308

GAIN = 10
1

R11

244p

1.5Vdc

V2 = 2.5
PER = 2u
TR = 1.98u

Vinject

V407

50

Vsense

Fig. A.1 OrCAD Simulation Schematic of the DC-DC power converter

160

A.2 Digital Active EMI Filter Module

16 Binary Inverters
U32
1

2
INV
U33

2
INV
U34

2
INV
U35

2
INV
U36

2
INV
U37

2
INV
U38

V408

IN1
IN2

Vsense

OUT

2
INV
U39

1Vdc

U14

Vinject

INV
U40
U13

OFFTIME = .0025uS
DSTM1
ONTIME = .0025uS
CLK
DELAY =
STARTVAL = 0
OPPVAL = 1

IN
CNVRT
STAT

LO

reference

OVR
REF

LGND

V3
2V

DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0

2
INV
U41

2
INV
U42

2
INV
U43

2
INV
U44

16 Bits ADC

2
V

1
V

CNVWHI = 0.01n
CNVWLO = 0.02n

DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8 OUT
DB7
DB6
DB5
DB4
DB3 REF
DB2
DB1 LGND
DB0

reference

16 Bits DAC

INV
U45
2
INV
U46
2

INV
U47

1
V

2
INV

Title

Fig. A. 2 OrCAD Simulation Schematic of the DAEF Module

<Title>

Size
Document Number
Custom<Doc>
Date:

161

Tuesday , January 19, 2010

R
Sheet

of

Appendix B
Circuit Layout & Selected Components List

B.1 Circuit Layout

Fig. B.1 and Fig. B.2 show the DAEF PCB prototype layout in OrCAD. The final PCB size
should be 1/3 of the one shown in Fig. B.4, considering SMT components on both sides of the
PCB.

Fig. B.1 PCB Top Layer of the DAEF

`
Fig. B.2 PCB Bottom Layer of the DAEF
162

Fig. B.3 Unpopulated PCB prototype of the DAEF

Fig. B.4 Populated PCB Prototype of the DAEF

163

B.2 Selected Components

Table B. 1 Main Components List
Description

Component

Manufacturer/Distributer

High speed Analog to

KAD5514P-25

IntersiL

ISL5957-SOIC

IntersiL

TMS320F28335

Texas Instrument

Cyclone II, EP2C35F672C6N

Altera Corporation

Crystal Oscillator

Si590

Silicon Labs

RF Transformer

ADT1-1WT

Mini Circuits

RC-Sensor

0.1F/1K

Digikey

RC-injector

1nF/30

Digikey

AD-DC Converter (PFC)

75W Off Line converter

Digikey

DC-DC Converter

2KW DC-DC Battery Charger

Freescale

DC-AC Micro-inverter

200W PV Inverter

SPARQ systems

Digital Converter (ADC)

High speed Digital to
Analog Converter (DAC)
Digital Signal Processor
(DSP)
Field Programmable Gate
Array (FPGA)

164

Appendix C
Matlab Analysis file

C.1 Transfer Functions Evaluation

k1=100;

% the DAEF feed-forward injection gain

k2=-1;

% DAEF phase reversal gain

T=0.5e-8;

% the sampling period

numa=[1 0];dena=[1 10e+3];

% Sensor TF

numb=[0 1];denb=[10e+6 1];

% Injector TF

numc=[2

0];denc=[T

+8e+8*T

0];%

ZOH

transfer

function,

using

approximation
[num1,den1]=series(k1*k2*numa,dena,numb,denb);
[num2,den2]=series(num1,den1,numc,denc);% open loop TF of DAEF
[num,den]=cloop(num2,den2,-1);

%Closed Loop TF of DAEF

printsys(num,den)

% evaluation of the DAEF

Km=0.4;

% modulator gain

Ka=-25;

% Controller gain

Kb=80;

% Plant DC gain

Kd=0.5;numk=[0 0.5];denk=[0 1];

Vbus=250;

% voltage bus, after the first stage DC/DC converter

Lf=500e-6;

% Output inductor value

Cf=2.2e-6;

% Output capacitor value

Z=0.3;

% Output impedance

nump=[0 Kb*Km*Vbus];denp=[Lf*Cf Lf/Z 1]; % Plant TF ====> Gp(s)

165

Pade

numd=[0 1];dend=[Lf 1];

%decoupling TF ===> Gd(s)

[num3,den3]=series(nump,denp,numd,dend);

%TF of Gd(s)*Gp(s)

[num4,den4]=series(num3,den3,num,den)%open loop TF of Gd(s)*Gp(s)*F(s)

[num5,den5]=feedback(num4,den4,numk,denk,-1);%closed

loop

TF

of

Gp(s)*F(s)and Kd
printsys(num4,den4)

% open loop TF

w=logspace(2,4,600);
[mag,phase,w]=bode(num4,den4,w);
margin(mag,phase,w);figure
% This is the type 3 compensator used for the inverter control system
num_comp=[0.58e-9 4.8e-5 1];

%Numerator of the type 3 compensator

den_comp=[3.8e-15 0.73e-11 0.35e-6 0];% Denomenator of the compensator

printsys(num_comp,den_comp)
[num6,den6]=series(num4,den4,Ka*num_comp,den_comp);%open

loop

with

compensator printsys(num6,den6)
[num7,den7]=feedback(num6,den6,numk,denk,-1);%closed

loop

compensator
printsys(num7,den7)
w=logspace(2,4,600);
[mag,phase,w]=bode(num6,den6,w);% Open loop Phase & Gain Margin
margin(mag,phase,w);figure
[mag1,phase1,w]=bode(num7,den7,w);% Closed loop PM & GM
margin(mag1,phase1,w);figure
[Gm,Pm,Wcg,Wcp]=margin(mag1,phase1,w);
H=tf(num7,den7);
nyquist(H); % This is the Nyquist plot of the Closed loop TF
title(['Gm=',num2str(Gm),'Pm=',num2str(Pm)]);figure

166

with

step(num7,den7);
End of program
Matlab output file;

1) The DAEF Transfer Function

(C. 1)
2)

This is the transfer function before compensation;

(C. 2)

3)

This is the compensator Transfer Function;

(C. 3)
4) This is the overall open loop transfer function of the inverter
system;

(C. 4)

5) This is the overall closed loop transfer function of the inverter

system;

(C. 5)

167

Appendix D
MathCAD Analysis File

D.1 Attenuation Plot of the DAEF

f1 10010
1 f1
6

f2 30 10

2 f2
6

f 100 200 50 10

( f) 2 f
j

k1 10 20 100
k2 1

1
6

25010

T F k1

j 1 j 2

j 2 1 2 j 1 2

k1 k2 2
T j
1 e

168

15

20log TF100 ( f)

30

45

60
100

1 10

1 10

1 10
f

1 10

1 10

1 10

Frequency response of the DAEF - Magnitude

Fig. D.1 Frequency response of the DAEF - Magnitude

200

100

arg TF 100 ( f)

180

100

200
10

100

1 10

1 10

1 10

1 10

1 10

Frequency response of the DAEF - Phase

Fig. D.2 Frequency response of the DAEF - Phase

169

1 10

1 10 1.2 10 400010
j

1
6

20010

Zero Order Hold Transfer Function:

ZOH

j T

1e

j
100

150

20log ZOH

200

250

300
6
1 10

1 10

1 10

1 10

Magnitude plot of the ZOH

Fig. D.3 Magnitude plot of the ZOH

170

1 10

10

50

arg ZOH

180

100

150

200
6
1 10

1 10

1 10

1 10

Phase plot of the ZOH

Fig. D.4 Phase plot of the ZOH

D.2 Compensator Design

Compensator design using DC/DC converters method

Input and output voltage:

Vin 250, Vo 200,

Duty cycle:
D

Vo
Vin

D 0.8

Output current: Io 2 3 20
Switching frequency:
Output filter:
Lo 50010

Zo(Io) 0.3

171

1 10

10

Co 2.2 10

Resonant frequency:
fLC

1
2 LoCo
3

fLC 4.799 10

Frequency response:
6

f 10 50 2 10

( f) 2 f
j

PWM Oscillator Ramp: Vs 2.5

Reference voltage: Vref 2.5

1.0 Control-to-output transfer function

Feedback gain:

KFB

Power circuit gain:

PWM gain:

Vref
Vin

KPWR Vin

KMOD

1
Vs

K LC Io

Filter gain:

1
Lo
2
1 j
j LoCo
Zo( Io)

172

Control-to-output transfer function plot

T Io KFBKPWRKMODKLC Io

40
4

20log T ( f) 2

32
68
104
140
10

1 10

1 10

100

1 10

1 10

1 10

( f)

Fig. D.5 Gain plot of the plant transfer function

0

45

arg T ( f) 2

180

90

135

180
100

1 10

1 10

1 10

1 10

( f)

2
Fig. D.6 Phase plot of the plant transfer function

173

1 10

Type III Compensation Network

Crossover frequency:
Fc

1
fs
5

Fc 1 10

Required amplifier gain:

G 20 log T ( Fc ) 2

Minimum phase margin:

DPM 45 degree

Required phase boost:

Boost(Io) DPM arg T (Fc) Io

180

90

Boost(2) 46.828

Choose Compensator type III when the boost is less than 180 deg.

a) Zeros and poles Location

The K factor:

Boost ( 2)

K tan
45

180

K 2.319

Double-zero location:
Fz

Fc
K

Fz 6.567 10

174

Double-pole location:
4

Fp 1.523 10

Fp Fc K

Maximum bandwidth @ 2A:

3

BW 5.228 10

BW Fp Fc

Type III Compensator circuit parameters:

GEA 10

G
20

R1 10 10

C2

GEA 104.773

1
2 FcGEAR1

11

C2 1.519 10

11

C1 2.003 10

C1 C2(K 1)

R2

R3

C3

K
6

2 Fc C1

R2 1.21 10

R1
K1

R3 7.583 10

1
2 Fc K R3

C3 1.378 10

Type-III Compensator transfer function plot

TEA

1 j R2C1 1 j C3(R1 R3)

j R1( C1 C2) 1 j R3C3 1 j R2

175

C1C2

C1 C2

110

Magnitude (dB)

80

50

20

10
1

10

100

1 10

1 10

1 10

1 10

1 10

Frequency (Hz)

Fig. D.7 Type 3 compensator magnitude plot

10

Phase (deg)

50

90

130
1

10

100

1 10

1 10

1 10

1 10

Frequency (Hz)

Fig. D.8 DC-DC Converter Digital Controller Design

176

1 10

DC-DC Converter Design Specifications

Output voltage:
Vo 12

Output current :
Io 90
Ro

Vo
Io

Ro 0.133

Filter Inductor :

Lo 1.6 10

Filter Capacitor:
Co 20010

Input Voltage :
Vin 300

Clock/Sampling frequency:
Fs 20010

The ADC maximum voltage range:

Vadc 3
j

1
5

f 10 150 10010

Control to Output Transfer function of the outer voltage loop:

Tv

vo ( s)
d ( s)

177

Control to Output Transfer function of the inner current loop:

Gi

i( s)
d ( s)

Laplace function:
s ( f) j2 f

Time constant of the sensing filter:

0.6 10

Vin
Lo
2
1 s ( f)
s ( f) LoCo
Ro

Gv( f)

Outer loop voltage transfer function:

Vin( 1 RoCos ( f) )

Gi( f)

Ro s ( f) Lo s ( f) LoCoRo

Inner loop current transfer function:

Ksense

1
20

Gain of the sense circuit:

K1 50

Feed-forward gain of the DAEF:

K2 1

Feedback gain of the DAEF:

f2 30 10

Corner frequency of the LPF:

f1 10010

Corner frequency of the HPF:

178

1 2 f1
2 2 f2

Hsen (f)

Ksense
1 s(f)

The sense circuit Transfer function:

n 12

ADC Gain:
n

Kadc

12
Vadc

PWM Gain:
Kpwm( f) 1.2

Digital Controller, soft complex zero-pair:

b 2
c 2

n 10
j 2

Hcomp( f c) 1 2 e
b

f
Fs

j 2 f
1
Fs

1 e

179

10

11
20log Hcomp f 2
13
20log Hcomp f 2
10
20log Hcomp f 2
12
20log Hcomp f 2
20log Hcomp f 2

50

100
10

1 10

1 10

100

1 10

1 10

1 10

1 10

Fig. D.9 Digital compensator gain for different values of b and c

200

11

13

12

10

11

arg Hcomp f 2
arg Hcomp f 2
arg Hcomp f 2
arg Hcomp f 2
arg Hcomp f 2

180

150

180

100
180

180 50

180

50
100

1 10

1 10

1 10

1 10

Fig. D.10 Phase of the digital compensator for different values of b and c
180

1 10

Integrator Transfer Function:

1

Hinteg( f)

j 2

1e

f
Fs

Delay time Transfer Function:

j 2

Hdelay( f) e

f
Fs

Zero Order Hold Transfer Function:

j 2

ZOH( f)

1e
j 2

f
Fs

f
Fs

1
Fs

The transfer Function of the Digital active EMI filter

Gdaef ( f)

s ( f) 1 s ( f) 2
f

j 2

K1 K2 2
Fs
s ( f) 1 2 s ( f) 1 2
1 e

Open loop gain of the inner current loop can be expressed as:
Ti_comp( f c) Hdelay(f) ZOH ( f) Hsen ( f) Kadc Gi( f) Hcomp ( f c) Hinteg( f)

Ti_uncomp( f) Hdelay( f) ZOH ( f) Hsen ( f) Kadc Gi( f)

Voltage loop gain of the compensated system:

181

T v_compf
( c)

Gv( f) Gdaef ( f) Hsen ( f) Kadc Hinteg( f) Hcomp( f c) Hcomp( f c) Hinteg( f) Hdelay( f) ZOH( f) Kpwm( f)
1 Hdelay( f) ZOH( f) Hsen ( f) Kadc Gi( f) Hcomp( f c) Hinteg( f)

Voltage loop gain of the Un-compensated system:

T v_unf
( )

Gv( f) Gdaef ( f) Hsen ( f) Kadc Hdelay( f) ZOH( f) Kpwm( f)

1 Hdelay( f) ZOH( f) Gi( f) Hsen ( f) Kadc

150

20010

Magnitude (dB)

100
20log Ti_uncomp( f)

20log Ti_comp( f c)

50
0

0
50
100
150
10

100

1 10

1 10
f

1 10

1 10

Frequency (Hz)
uncompensated system
compensated system

Fig. D.11 Bode plot of the Gain Transfer function of the inner current loop

182

1 10

Magnitude (dB)

270
225
180
135
180 90
arg ( Ti_uncomp( f) )
45

0
180 45
arg ( Ti_comp( f c) )

90
135
180
225
270
10

20010

180

180

100

1 10

1 10
f

1 10

1 10

1 10

Frequency (Hz)
uncompensated
compensated

Fig. D.12 Phase response of the open loop transfer function for the current inner loop

100

610

Magnitude (dB)

65
30
20log Tv_un( f)

20log Tv_comp( f c)

40
75
110
145
180
10

1 10

1 10

100

1 10

1 10

f
Frequency (Hz)
Uncompensated
Compensated

Fig. D.13 Bode plot of the open loop gain transfer function for the outer voltage loop

183

Magnitude (dB)

270
231.43
192.86
154.29
115.71
360
77.14
arg( Tv_un( f) )

38.57
0
360 38.57
arg( Tv_comp( f c) )
77.14

115.71
154.29
192.86
231.43
270
10

610

90
180

100

1 10

1 10

1 10

f
Frequency (Hz)
Uncompensated
Compensated

Fig. D.14 Phase response of the open loop transfer function for the outer voltage loop

184

1 10

Appendix E
DSP Program
/****************************************************************
*****************
// This code is modified to reverse the phase of the acquired
noise signal // coming from the ADC outputs
//
// The task of this program is to run ADC0 in continuous mode.
// The results are used to adjust the duty cycle of PWM1
// The 12 bit digit is out on pins GPIO4-GPIO15
// The Strobe signal is given on GPIO27.
//
//
*****************************************************************
*****************/
#include
<math.h>
#include
"PS_bios.h"
#include "DSP2833x_Device.h"
// DSP2833x Headerfile Include
File
#include "DSP2833x_EPwm_defines.h"
typedef float DefaultType;
#define

GetCurTime() PS_GetSysTimer()

void Task();
DefaultType
fGblV2 = 0.0;
unsigned int a=0;

//-----------------------------------------------void InitEPwm1Gpio(void)
{
EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0;
// Enable pull-up on
GPIO0 (EPWM1A)
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0;
// Enable pull-up on
GPIO1 (EPWM1B)
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1;
// Configure GPIO0 as
EPWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1;
// Configure GPIO1 as
185

EPWM1B
EDIS;
}
//-----------------------------------------------void InitEPwm1()
{
// EPWM Module 1 config
EPwm1Regs.TBPRD = 0xFFFF;
EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
// Master
module
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_CMPB;
// Sync
down-stream module
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on
CTR=Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on
CTR=Zero
EPwm1Regs.AQCTLA.bit.ZRO
EPwm1A
EPwm1Regs.AQCTLA.bit.CAU
EPwm1Regs.AQCTLB.bit.ZRO
EPwm1A
EPwm1Regs.AQCTLB.bit.CAU

= AQ_SET; // set actions for

= AQ_CLEAR;
= AQ_CLEAR; // set actions for
= AQ_SET;

EPwm1Regs.CMPA.half.CMPA = 0xFFFF/2; // adjust duty for

output EPwm1A
}
//-----------------------------------------------void Task()
{
//

//This is ADC ISR

GpioDataRegs.GPASET.bit.GPIO27 = 1;
a = AdcRegs.ADCRESULT0;
GpioDataRegs.GPADAT.all =a;
EPwm1Regs.CMPA.half.CMPA = a;
GpioDataRegs.GPASET.bit.GPIO27 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO27 = 1;
186

}
//-----------------------------------------------void Initialize(void)
{
PS_SysInit(30, 10);
PS_InitTimer(0, 0xffffffff);
PS_ResetAdcConvSeq();
PS_SetAdcConvSeq(eAdcCascade, 0, 1.0);
PS_AdcInit(0, !0);
// ----------------------------------EALLOW;
GpioCtrlRegs.GPAPUD.all = 0;

// Enable pullup on GPIO27-

31
GpioCtrlRegs.GPADIR.all = 0xFFFF;

// GPIO0-31 = output

// Enable an GPIO output on GPIO27, set it high

GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0;
// Enable pullup on
GPIO27
GpioDataRegs.GPASET.bit.GPIO27 = 1;
// Load output latch
GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 0; // GPIO27 = GPIO27
GpioCtrlRegs.GPADIR.bit.GPIO27 = 1;
// GPIO27 = output
EDIS;
// -----------------------------------InitEPwm1Gpio();
InitEPwm1();
// ---------------------------------------------------------}
void main()
{
Initialize();
PS_EnableIntr();
PS_EnableDbgm();
for (;;) {
Task();
}
}

// Enable Global interrupt INTM

187