up time

8/6/12
& hold time constraints? What do they signify? Which one is critical for estimating

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Question :
What are set up time & hold time
constraints? What do they signify? Which
one is critical for estimating maximum
clock frequency of a circuit?

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Answers:

General

Setup time is the minimum time prior to trigerring edge of the clock
pulse upto which the data should be kept stable at the flip-flop
input so that data could be properly sensed at the input.Hold time
is the minimum time after the clock edge upto which the data
should be kept stable in order to trigger the flip flop at right
voltage level. Setup time is required in order to find the maximum
clock frequency of a circuit.

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Submitted by MOHAMMAD USAID ABBASI (usaidabbasi@yahoo.com)

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Setup time :It is the minimum time before the clock edge the input
should be stable.This is due to the input capacitance present at
the input.It takes some time to charge to the particular logic level
at the input.

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Hold time:It is the minimum time the input should be present

stable after the clock edge.This is the time taken for the various
switching elements to transit from saturation to cut off and vice
versa.

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So basically set up and hold time is the window during which the
input should be stable.Any changes in the input during the window
period may lead to voltage levels which is not recognised by the
subsequent stages and the circuit may go to metastable stage.

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Submitted by Thomas Varghese (tomcrux@fastmail.fm)

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suppose ur flip-flop is positive edge triggered. time for which data

should be stable prior to positive edge clock is called setup time
constraint .

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Time for which data should be stable after the positive edge of
clock is called as hold time constraint.

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if any of these constraints are violated then flip-flop will enter in

meta stable state, in which we cannot determine the output of
flip-flop.

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there are two equation:

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up time
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& hold time constraints? What do they signify? Which one is critical for estimating
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1. Tcq + Tcomb> Tskew + Thold

2. Tcq + Tcomb<Tskew +T - Tsetup
Tcq is time delay when data enters the flip-flop and data comes
at output of flip flop.
Tcomb is the logic delay between two flip flop.
Tskew is the delay of clock to flip flop: suppose there are two flip
flop ,if clock reaches first to source flip flop and then after some
delay to destination flip flop ,it is positive skew and if vice versa
then negative skew.
so if u take 2 eq you will see that setup time is the determining
factor of clock's time period.
Submitted by Sanjum Bhatia (sanjumbhatia4@yahoo.co.in)

Setup Time: Minimum time period during which data must be stable
before the clock makes a valid transition. For example, for a
posedge triggered flip-flop, with a setup time of 2 ns, Input Data
(i.e. R and S in the case of RS flip-flop) should be stable for at
least 2 ns before clock makes transition from 0 to 1.
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Hold Time: Minimum time period during which data must be stable
after the clock has made a valid transition. For example, for a
posedge triggered flip-flop, with a hold time of 1 ns. Input Data
(i.e. R and S in the case of RS flip-flop) should be stable for at
least 1 ns after clock has made transition from 0 to 1.

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Just for further understanding:

A FF actually consists of two latches with clock as enable for first
LATCH and inverted clock used as enable for second LATCH.
This will form a negative edge triggered FF. Inverting the clocks
will form a positively edge triggered FF.
Setup time is the time required to charge the input (parasitic)
capacitance of the first latch. Hold time is the time required to
charge the input capacitance of the second latch.
The capacitance depends on the width of the metal lines and
hence on the library used.

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