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ADAPTIVE DC-DC CONVERTER

By
Chad Thomson
John VanHyfte
ECE 345
TA: In Seop Lee
May 3, 1999
Project 36

ii
ABSTRACT
This report focuses on the design, construction, and testing of an adaptive dc-dc converter with digital
feedback control. These types of converters are used to power todays advanced microprocessors. The
converter takes the high voltage from a computer power supply and reduces it to a lower level required
by the microprocessor. This lower level is requested by the microprocessor through a five bit digital
word. The converter reads this word and outputs the correct voltage to the processor. Four main
components make up the complete system. These components are the buck circuit, the pulse width
modulation controller, the digital to analog converter, and the microprocessor. In addition to the
standard performance tests of a dc-dc converter, a special test was conducted to verify that the actual
output voltage corresponded to the reference voltage provided by the digital to analog converter.

iii
TABLE OF CONTENTS
i.
ii.
iii.

Title
Abstract
Table of Contents

Chapter

Page

1.

Introduction (JJV).......1

2.

Pulse Width Modulator (JJV)


2.1
Design Procedure ...4
2.2
Design Details..5

3.

Digital to Analog Converter (JJV)


3.1
Design Procedure 7
3.2
Design Details..7

4.

Buck Converter (CET)


4.1
Design Procedure 8
4.2
Design Details10

5.

Counter Circuit (CET)


5.1
Design Procedure and Details ...12

6.

Design Verification (CET)


6.1
Output Resistor .13
6.2
Inductor .13
6.3
Digital to Analog Converter ..13
6.4
Complete Converter ..14
6.5
Efficiency ..14
6.6
Percent Error .14
6.7
Switching Frequency 15
6.8
Timing Capacitor ..15
6.9
Error Analysis ...15

7.

Cost Analysis (CET)..16

8.

Conclusions (JJV).....17
Appendix 1.
Appendix 2.

Figures (CET/JJV) 18
Data Tables (CET) 23

References (CET/JJV) ..25

1
1. INTRODUCTION
This report presents an in-depth explanation on how to design and build an adaptive DC-DC converter.
Through the utilization of digital feedback control, the converter provided a variable output voltage
based upon a digitally requested voltage.

This type of adaptable power supply applies to high-end microprocessors such as the Intel Pentium II.
Due to power consumption in digital computer chips being proportional to the voltage squared, these
advanced microprocessors minimize power consumption, and therefore heat, by continuously requesting
lower input voltages until an on-board test circuit begins to report errors. The processor requests these
specific input voltages by outputting a five-bit digital word to the converter. The converter then
interprets the digital word and adjusts its output voltage to the specified value.

The power supply will convert a 5V input to a 1.6-3.3V output by utilizing a dc-dc buck converter. A
pulse width modulation controller chip will drive the converters power MOSFET and the digital
feedback control of the PWM will be executed through an outboard digital to analog converter. To test
and verify proper converter operation, a binary counter circuit will be utilized to simulate the five-bit
output of the Pentium II.

The project is comprised of a buck converter, a pulse width modulation controller, a digital to analog
converter, and a microprocessor simulator. The following is a description of these four major
subsections. These subsections are shown graphically by the block diagram in Figure 1. (All figures
and tabls appear at the end of the report.)

The buck converter is a switching converter that uses energy storage components to transfer power from
the input to the output. This buck converter was used since the output voltage was always lower than
the input voltage. The PWM circuit controls the duty ratio of the power MOSFET, switch 1. A diode

2
was used in the buck converter for the second switch. The diode duty ratio is automatic, as the diode
will turn on when the MOSFET turns off. The duty ratio of the switches controls the output voltage.
The inductance value was selected by solving for a maximum critical inductance and based on the
availability of inductors. The capacitance value was selected based on the inductance and output ripple
specifications. Figure 3 shows a diagram of the buck circuit.

The pulse width modulation chip, also known as a PWM, provides an adjustable switching controller for
the power MOSFET. In addition to controlling the MOSFET, the PWM chip contains part of the
feedback circuit for the converter. This part of the feedback loop consists of an error correction circuit
that directly controls the PWM section of the chip. The error correction circuit compares the converter
output voltage to the reference voltage supplied by the DAC. Through this comparison, the circuit is
able to make the necessary duty ratio adjustments for the MOSFET controller. This duty ratio
adjustment allows the output voltage to precisely match the voltage requested.

The digital to analog converter, also known as a DAC, contains the remaining parts of the feedback
circuit. It provides the link between the digital output of the Pentium II and the analog input of the
PWM chip. Specifically, the DAC input accepts a 5-bit digital word from the Pentium II output. Based
on Intels voltage identification code table, the DAC converts the digital input word to the correct analog
output voltage. Therefore, it effectively provides a precision reference voltage for the PWM error
correction circuit.

The Pentium II processor sends a digital word to the power supply to request a specified output voltage
level. The processor attempts to keep the voltage level low to reduce power consumption. Devices
report errors when the voltage becomes too low on the processor. The processor then requests higher
voltages until no errors are reported and so on. The processor is constantly changing the voltage level to

3
adapt to the changing power needs. A counter circuit was used to simulate the processors voltage
requests, by sending a five-bit digital word to the DAC.

Performance Specifications
The output voltage performance specifications were chosen to be in line with Intel [4]. Additionally, the
output power was limited at low voltages to ensure safe current levels.

Input Voltage

+5V

Output Voltage

+1.6V 3.3V, 5%

Output Voltage Ripple

< 10%

Output Power

10W (Highest Voltage Only)

In order to validate these performance specifications and proper operation, a series of tests were
performed. These tests are:

1.
2.
3.
4.
5.
6.

Verify that current is always in continuous mode.


Verify that the output voltage spans the specified range.
Verify that ripple meets output specification.
Verify the high voltage power output.
Verify the output voltage agrees with the requested voltage.
Verify that the output power resistor is 1 10%.

4
2. PULSE WIDTH MODULATOR
2.1 Design Procedure
A switching buck converter requires a regulated square wave to drive the gate of the power MOSFET.
This is achieved using a pulse width modulation integrated circuit. There are many PWM ICs available
with a host of features and applications to choose from. The PWM chosen for this project was the
Linfinity LX1661 Advanced PWM Controller. This PWM was selected for two main reasons. It was
specifically designed and optimized for digitally controlled microprocessor power supplies, and
therefore, it contained an internal error comparator circuit for duty ratio adjustment. The internal error
comparator increases final converter reliability and simplicity. Secondly, it used a separate digital to
analog converter. There are other alternative PWMs available for this application, but most have the
DAC integrated into the PWM to simplify the circuit even further. It was critical for this project to use a
separate PWM and DAC because this allowed accurate verification of proper converter operation. By
using a separate DAC, it was possible to measure its output reference voltage independently of the
converter output voltage. Therefore, allowing the direct comparison of the two values and accuracy
calculations.

It was necessary to program the PWM to operate at the correct switching frequency. This was
accomplished by connecting an external timing capacitor to the PWM. The correct value for the timing
capacitor depended on the desired frequency of operation. This capacitor value was calculated using
Equation (2.1) from Linfinity [1].

1 V in

V out

f (152
. .29V
s

dis

out

(2.1)

The PWM also contained a current limiting circuit to protect the microprocessor from high current
levels. By measuring the voltage drop across a known resistor, the PWM was able to monitor the
current supplied to the microprocessor. The threshold voltage for the current limiting comparator was

5
VTRIP. Designating the maximum current as ITRIP, the sense resistance, RSENSE, was calculated using
Ohms Law and is given by Equation (2.2).

sense

V
I

trip

(2.2)

trip

The final capacitor value that must be calculated for the PWM was the error comparator input bypass
capacitor. This capacitor was placed between the error comparator input pins to reduce jitter and noise
due to extremely fast response to transient disturbances. Calculation of this capacitance value, CERROR,
was achieved through Equation (2.3) from Linfinity [1].

error

(2.3)

The remaining resistor and capacitor values required for the PWM do not vary with changing converter
specifications. The manufacturer supplied these values since they remained constant in all applications.
Therefore, all remaining resistor and capacitor values were obtained from the Linfinity [1], [2].

2.2 Design Details

As stated in the Design Procedure there were three component values that needed to be calculated for
the PWM. These values are CT, RSENSE, and CERROR . The switching frequency, Fs, of the converter was
selected to be 100kHz, and IDIS was internally fixed at 200A. Using Equation (2.1) the timing
capacitance CT was found to be 1242pF.

The PWMs current sense comparator threshold voltage, VTRIP, was 100mV. Maximum operating
current for the converter was determined to be 3.3A. A value of 6.6A, twice the maximum operating
current, was chosen to be the shut down current ITRIP. This would ensure that the converter would not
shut down due to mild current peaks during transients. Applying VTRIP and ITRIP to equation (2.2)
resulted in RSENSE being equal to 15m.

6
The final value to be calculated was CERROR, the error comparator bypass capacitor. Using Equation
(2.3) and the timing capacitance CT, the value of CERROR was found to be 621pF. A complete diagram of
the PWM circuit containing all necessary and calculated components is given in Figure 2.

7
3. DIGITAL TO ANALOG CONVERTER
3.1 Design Procedure

A digital to analog converter was required to convert the digital voltage requests from the
microprocessor to the precision reference voltage used by the pulse width modulation controller. There
are many digital to analog converters in production, but these are general application eight-bit
converters. They do not apply to this converter application because their output scaling does not match
the voltage identification table from Intel [4]. The microprocessors, for which this converter is
designed, use a five-bit digital word to request different voltage levels. This coding scheme uses a nonstandard scaling table, and therefore, a special digital to analog converter was necessary for this
application. The Linfinity LX1670 5-bit digital to analog converter was chosen for the project. This
digital to analog converter was chosen for three reasons. It was specifically designed to comply with the
Intel VID table. Additionally, the DAC did not require an outboard zener diode to provide a reference
voltage. This makes for increased simplicity in the completed converter. Finally, the LX1670 was
designed to complement and work together with the LX1661 PWM, thereby, making integration of the
two straightforward.

3.2 Design Details

The DAC required no external components for operation. Its VID inputs did require a special interface
circuit since they were not TTL compatible. This circuit is addressed in Chapter 5. In addition, the
DAC was initially tested at all output levels to ensure proper operation. This test is shown in the Design
Verification section. The complete diagram of the DAC and PWM is shown in Figure 2.

8
4. BUCK CONVERTER
4.1 Design Procedure

The microprocessor operates on voltage levels that are always lower than the 5V input source. The
buck, buck-boost and boost-buck converters are capable of this conversion. The buck-boost and boostbuck have an additional feature of polarity reversal on the output voltage. The microprocessor can not
operate with negative voltages. Since the computer power supply has one common ground, an isolated
ground is not available. The buck converter uses the same ground as the computer power supply. The
buck converter has very few parts and is cost efficient. The buck topology was chosen for the converter.
Buck converters require devices that approximate an ideal switch. Power MOSFETs, BJTs, diodes, and
SCRs are close approximations to ideal switches. Power MOSFETs have better efficiency than BJTs.
The PWM provides a voltage based square wave so a MOSFET was selected as switch 1 as shown in
Figure 3. A diode was used for switch 2 since no control is necessary to turn a diode on and off. The
IRL3103 MOSFET was selected based on Linfinity [1]. The MBR1035 schottky diode was selected
based on Linfinity [1]. The other components of a buck converter are a series inductor, parallel
capacitor, and output resistor. When switch 1 is on, the series inductor stores energy. When switch 2 is
on, the inductor discharges energy to the load resistor. The capacitor maintains a constant voltage across
the load resistor.

The choice of switching frequency is the first step in designing a converter. A switching frequency of
100kHz was selected. This value of frequency is a standard switching frequency used in most
converters and complied with the PWM specifications. The choice of inductor is based on the selection
of the switching frequency. The most important design aspect of the inductor is the critical inductance
value Lcrit. The critical inductance is the minimum inductance value necessary to maintain continuous
mode operation. If the current in the inductor becomes negative, the inductor is operating in
discontinuous mode. Discontinuous mode operation can lead to inconsistent switching and

9
unpredictable results. The maximum critical inductance value was calculated using Equation (4.1)
from Krein [3], for the entire range of output voltages.

Lcrit =

(1 D1)

(4.1)

2 f

R is the output resistance, f is the switching frequency and D1 is the duty ratio of switch 1. The duty
ratio is the percent of one cycle in which a switch is on. The duty ratio of switch 1 was calculated using
Equation (4.2) from Krein [3].

V
D=V

out

(4.2)

in

The duty ratio is the only value in Equation (4.2) that varies. The duty ratio varies as the output voltage
varies over the specified range.

Once the inductor value is selected, the output capacitance can be determined based on the output ripple
voltage specifications. The maximum allowable voltage ripple was calculated using Equation (4.3) from
Krein [3].

max

= 2( %ripple)V out ,max imum

(4.3)

The minimum capacitance value needed to meet the specification requirements was calculated using
Equation (4.4) from Krein [3].

min

.5 i
f 2v

c , peak

(4.4)

max

The peak inductance value was calculated using Equation (4.5) from Krein [3].

ic, peak =

i = v t
2
L
l

(V V )( D )
in

out

f L

(4.5)

10
The maximum value of icpeak corresponds to the largest minimum capacitance value. Vout and D2 are
the only values that can change in this equation. The largest value of (Vin-Vout)*D2 corresponds to the
largest value of icpeak. The largest value of (Vin-Vout)*D2 occurs when the output voltage is at a
minimum. D2 is the duty ratio of switch 2 as shown in Figure 3. The duty ratio D2 was calculated using
Equation (4.6) from Krein [3].

V
D =1 D =1 V
2

out

(4.6)

in

The output resistor was chosen based on the power output specifications. The value of the output
resistor was calculated using Equation (4.7).

output

V
=
P

2
out

(4.7)

out

4.2 Design Details


Equation (4.1) was used to calculate the critical inductance value over the entire range of output
voltages. The maximum critical inductance value is 3.4uH. In order to ensure that the converter did not
operate in discontinuous mode a 75H 10A inductor was selected. This value is more than a factor of
10 times larger than the critical inductance. The maximum icpeak value was calculated using Equation
(4.5) with Vin = 5V, Vout = 1.6V, f = 100kHz, D2 = .68 and L = 75H. The maximum value of icpeak =
0.3083A. The minimum capacitance needed to meet ripple specifications was calculated using Equation
(4.4) with f = 100kHz, icpeak = 0.3083A, and vmax = 0.033V. The minimum capacitance value Cmin =
23.4F. Two 1000F 16V aluminum electrolytic capacitors were selected based on the calculation of
Cmin and from Linfinity [1].

The output power specification of 10W at the highest output voltage was selected in order to keep the
current levels small to ensure the safety of the circuit components and protoboard. The resistance value
was calculated using Equation (4.7) with Pout = 10W and Vout = 3.3V. The calculated resistor value was

11
1.089. A 50W 1 resistor was chosen to represent the load of the microprocessor. A complete
schematic diagram with all the component values is shown in Figure 3.

12

5. COUNTER CIRCUIT
5.1 Design Procedure and Details
A binary counter was used to simulate the changing voltage requests of the microprocessor. There were
many binary counters to choose from. The selection of the binary counter was based solely on the
availability of the chip. The 74LS191N synchronous 4-bit binary counter was selected. The fifth bit of
the DAC VID code is a scaling bit that changes the magnitude of the increments. This bit was changed
using a switch so the scaling could be controlled by hand. The clock signal of the counter chip was a
0.3Hz 5Vo-p square wave. This frequency was selected so that the outputs of the DAC and the converter
could be observed for a few seconds before changing. A switch controlled the count enable pin on the
counter so a specific voltage level could be observed for an extended period. The DAC VID pins are not
compatible with standard TTL 5V logic. The VID pins are internally pulled high. A three-state output
buffer was needed to interface the counter with the DAC. The CD74HCT125E high speed CMOS quad
buffer was selected. The buffer needed to be a high speed CMOS logic as per Linfinity [2]. This
particular chip was selected over many similar chips based on the inverting inputs of the output enable
pins. The counter outputs were connected to the output enable pins of the buffer. When the counter
value was a logic level 1, the output of the buffer was a high impedance state. This allowed the DAC to
be internally pulled high. When the counter was a logic level 0, the output of the buffer was enabled.
The input of the buffer was connected to ground and therefore a logic level 0 was output to the DAC.
Figure 4 shows the internal schematic of one buffer circuit. OE' is the output enable, A is the input
signal and Y is the output signal as shown in Figure 4. The diagram of the counter circuit is shown in
Figure 5.

13

6. DESIGN VERIFICATION
6.1 Output Resistor
The output resistor was specified to be 1 10%. The resistor was measured using a dc resistance test.
A dc resistance test consists of applying a voltage from a dc power supply and measuring the voltage
and current through the resistor. Table 1 shows the voltage, current and corresponding resistance values
for the two 1 resistors. The resistance was calculated using Equation (6.1).

V
I

(6.1)

The values in Table 1 are slightly out of the specified tolerance. The resistance values were always
larger in magnitude than the specification. This increase in output resistance will decrease the output
current and output power. Since the output current was limited for safety, the slight error in resistance
did not severely affect the converter operation.

6.2 Inductor
The inductor was measured using an RLC bridge to verify the manufacturer specifications. The
measured value of the inductor was 66.8H. This discrepancy, combined with other factors, had an
effect on the converter performance.

6.3 Digital to Analog Converter


The DAC reference voltage was tested independent of the rest of the converter circuit. Table 2 shows
the VID binary code, the expected voltage from Linfinity [2], and the measured reference voltage. The
measured values were within the manufacturer specification of 5% from Linfinity [2].

14

6.4 Complete Converter


The complete converter was tested for voltage, current and power with a 1 output resistor. Table 3
shows the VID code, DAC reference voltage, input voltage from power supply, input power from power
supply, converter output voltage, converter output power and output voltage ripple. The measurements
were all within the specified tolerances.

6.5 Efficiency
The efficiency of the converter was calculated using Equation (6.2) and the test results from Table 3.

=P

out

(100%)

(6.2)

in

Figure 6 shows the plot of efficiency versus output voltage. The efficiencies were lower than expected.
Efficiencies in the range of 80% to 90% were expected. The long leads, protoboard and thermal
dissipation are factors that affect the efficiency. This converter is intended to be surface mounted and
therefore would reduce the losses in the circuit. The power MOSFET did not have a snubber circuit. A
snubber circuit would have reduced the thermal dissipation in the MOSFET and improved the overall
efficiency.

6.6 Percent Error

The percent error was calculated using Equation (6.3) and the values from Table 3. Figure 7 shows the
graph of percent error versus output voltage.

%error

out

V ref

ref

(100%)

(6.3)

15
6.7 Switching Frequency

The expected switching frequency was 100kHz. The actual switching frequency was 40kHz. The
timing capacitor of the PWM sets the switching frequency. The switching frequency was 40kHz
regardless of the capacitance value. Figure 8 shows a HPVee plot of the gate drive signal versus time.

6.8 Timing Capacitor

The value of the timing capacitor had an adverse affect on the ripple voltage. Several capacitors were
used to obtain the best ripple waveforms. The ripple is the magnitude of the peak to peak value of the
sawtooth waveform of the ac component of the output ripple. The effective series resistance of the
output capacitors causes a voltage jump each time a switch turns on or off. The waveform in the voltage
range 2V to 2.7V was not a sawtooth waveform. The ac component of the output voltage was a
sinusoidal wave. The ripple measurement was obtained from the peak to peak magnitude of the
oscillations. The specifications required the ripple voltage to be less than 330mV. All the ripple
voltages measured were within the specified tolerance.

6.9 Error Analysis

The performance of the converter deteriorated with each use. Therefore, the output resistance was
increased to 2. The converter worked as expected with the increased output resistance. The errors in
the converter with the 1 output resistor were due to the low switching frequency and the low value of
the inductor. The current through the inductor became negative at the extreme high and low output
voltages. The converter operated in discontinuous mode for those voltage levels. The gate drive signal
was not a square wave and caused unpredictable output voltages.

16
7. COST ANALYSIS

The total project cost is the cost of labor plus the cost of the parts. The total time per member was 80 h.
The total labor cost was calculated using Equation (7.1).

Labor

total

(25$ / h )(25. )(labor

actual

(7.1)

The total labor cost was $10,000. Table 4 shows the values of the individual parts and the total cost of
the parts. The grand total of the project was $10,055. The estimated cost was $9438.

17
8. CONCLUSIONS

The adaptive dc-dc converter met all performance specifications. In all cases, the output ripple voltage
was within the plus or minus five percent tolerance, and the output power nearly met the specified value
of 10W. Additionally, the converter was able to output the full range of voltages specified by the
voltage identification table from Intel [4]. Converter efficiency proved to be lower than expected but
was still acceptable. Utilizing synchronous rectification, the efficiency could be improved by replacing
the diode with a MOSFET. Additionally, the use of a snubber circuit on the MOSFET would further
increase the overall efficiency of the converter. An alternative PWM should be selected to allow the
user to adjust the switching frequency over a wider range. Overall, the converter performed as expected.

18
APPENDIX 1. FIGURES

Figure 1. Block diagram of complete circuit.

Figure 2. Schematic diagram of PWM and DAC.

19
APPENDIX 1. FIGURES

Figure 3. Schematic diagram of buck converter.

Figure 4. Schematic diagram of internal buffer circuit.

20

APPENDIX 1. FIGURES

Figure 5. Schematic diagram of counter circuit.

Efficiency (%)

Efficiency vs. Vout


75
70
65
60
1

3
Vout (V)

Figure 6. Plot of efficiency vs. Vout.

21
APPENDIX 1. FIGURES

Percent Error
(%)

Percent Error vs. Vout


1.5
1
0.5
0
1.4

2.4
Vout (V)

Figure 7. Plot of percent error vs. Vout.

Figure 8. HPVee plot of 40 kHz gate drive signal.

3.4

Figure 9. Complete circuit schematic diagram.

APPENDIX 1. FIGURES

22

23
APPENDIX 2. DATA TABLES

TABLE 1. RESULTS OF DC RESISTANCE TEST.


Resistor
1
1
1
1
1
2
2
2
2
2

Voltage (V)
1.88
2.345
2.891
3.414
3.75
1.596
1.67
2.12
2.54
2.83

Current (A)
1.6
2.0
2.5
3.0
3.3
1.43
1.997
2.496
3.001
3.298

Resistance ()
1.175
1.173
1.156
1.138
1.136
1.116
1.195
1.177
1.18
1.16

TABLE 2. DAC REFERENCE VOLTAGE TEST RESULTS.


VID Code (binary)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

Vreference theoretical (V)


2.05
2.000
1.950
1.900
1.850
1.800
1.750
1.700
1.650
1.600
1.550
1.500
1.450
1.400
1.350
1.300
3.50
3.40
3.30
3.20
3.10
3.00
2.90
2.80
2.70
2.60
2.50
2.40
2.30
2.20
2.10
2.00

Vreference measured (V)


2.05
2.00
1.95
1.90
1.836
1.786
1.737
1.687
1.638
1.584
1.540
1.49
1.441
1.392
1.343
1.293
3.52
3.41
3.31
3.21
3.11
3.01
2.91
2.81
2.71
2.62
2.52
2.42
2.32
2.22
2.12
2.02

24
APPENDIX 2. DATA TABLES

TABLE 3. COMPLETE CIRCUIT TEST RESULTS.


DAC code (binary)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

Vref (Vdc)
2.06
2.01
1.96
1.91
1.842
1.791
1.742
1.692
1.644
1.593
1.544
1.494
3.54
3.44
3.33
3.23
3.03
3.13
2.93
2.83
2.73
2.63
2.53
2.43
2.33
2.23
2.13
2.03

Vin (Vrms)
5.04
5.04
5.05
5.05
5.05
5.05
5.03
5.05
5.04
5.04
5.04
5.05
4.80
4.83
4.87
4.89
4.92
4.89
4.92
4.94
4.96
4.97
4.99
5.00
5.02
5.03
5.03
5.04

Pin (W)
4.74
4.52
4.32
4.13
3.93
3.73
3.56
3.39
3.22
3.04
2.85
2.7
12.2
11.69
10.91
10.32
9.28
10.03
8.9
8.52
8.00
7.43
6.82
6.33
5.86
5.40
4.98
4.56

Vout (Vdc)
2.052
2.003
1.954
1.905
1.856
1.807
1.758
1.709
1.662
1.612
1.564
1.515
3.491
3.392
3.294
3.195
2.998
3.096
2.900
2.802
2.7058
2.607
2.510
2.411
2.314
2.216
2.118
2.021

Pout (W)
3.06
2.91
2.77
2.64
2.50
2.37
2.25
2.12
2.01
1.89
1.77
1.66
8.73
8.25
7.78
7.31
6.43
6.84
6.04
5.65
5.24
4.90
4.55
4.19
3.84
3.53
3.21
2.94

TABLE 4. BREAKDOWN OF COMPONENT COSTS.


Part
MOSFET
Diode
PWM chip
DAC chip
PC expansion board
Switches
LED bank
Resistors
Capacitors
Power resistors
Inductor
Current sense resistor
Binary counter
3-state buffer

Quantity
1
1
1
1
2
1
1
several
6
2
1
1
1
1
Total cost of parts = $55

Cost
$2.00
$2.00
$2.00
$2.00
$6.50/each
$0.75
$0.75
$3.00
$0.41/each
$6.50/each
$8.50
$1.50
$2.00
$2.00

Vripple (mV)
22.5
24.0
24.5
23.5
24.5
24.0
22.5
22.5
22.5
21.0
23.0
20.5
100
90
24.5
24
27
100
28
100
100
95
100
90
90
100
100
100

25
REFERENCES

[1] Linfinity, Appl. Note 1660, pp. 1-15.


[2] Linfinity, Appl. Note 1670, pp. 1-7.
[3] P.T. Krein, Elements of Power Electronics. New York: Oxford Press, 1998, pp. 333-338.
[4] Intel, Appl. Note VRM 8.2, pp. 1-8.