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TABLE OF CONTENTS
LIST OF TABLE

LIST OF FIGURES

ABSTRACT

CHAPTER 1
INTRODUCTION TO LOW POWER VLSI
1.1 Introduction
1.2 Basic idea
1.3 Need of the project
1.4 Sub threshold operation

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1.5 General block diagram

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1.6 Organization of thesis

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1.7 Summary

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CHAPTER 2
LITERATURE SURVEY
2.1 Gate Diffusion Input Technique

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2.2 D-flip flop

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2.2.1 Edge-triggered D-flip flop

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2.2.2 Classical positive-edge-triggered D-flip-flop

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2.2.3 Masterslave edge-triggered D-flip-flop

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2.2.4 Edge-triggered dynamic D-storage element

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2.3 Basic flip-flop design

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2.4 Improved flip flop design with delay element

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2.5 PMOS as delay element based flip flop design

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2.6 Proposed D-flip flop design using NMOS as delay element

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2.7 4 bit serial in serial out shift register

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CHAPTER 3
IMPLEMENTATION OF PROPOSED DESIGN
3.1 Serial in serial out shift register

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3.2 Applications

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3.3 Merits

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3.4 Demerits

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CHAPTER 4
ELECTRIC TOOLS DESCRIPTIONS AND COMMANDS
4.1 Electric & LT-spice

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4.2 Schematic Entry

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4.3 Layout entry

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4.4 DRC Check Rule

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4.5 LVS (layout vs. Schematic)

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CHAPTER 5
LT SPICE AND SIMULATION DESCRIPTION
5.1 Aim

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5.2 SPICE Tool flow

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5.3 INSIDE A TYPICAL SPICE FILE

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5.4 Layout Design rules

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5.5 130nm technology

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CHAPTER 6
RESULTS
6.1 Simulation waveforms

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CHAPTER 7
CONCLUSION AND FUTURE SCOPE
REFERENCES

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LIST OF TABLES
Table: 2.2.1: Truth table for position of triggering in D-flip flop
Table 2.2.2: Truth table of D-flip flop
Table-6.1.1 Power comparisons between existed and Proposed GDI Based D-Flip
Flop
Table-6.1.2Comparison of area (transistor Count) with existed and proposed
D-flip flop
Table-6.1.3Power comparison of SISO with existed and proposed D-flip
flop

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LIST OF FIGURES
Fig 1.5.1 Basic GDI cell
Fig 1.5.2 Basic Flip Flop Diagram with GDI Multiplexer
Fig 2.1.1Basic GDI cell
Fig 2.2.1 D-flip flop diagram
Fig 2.2.2 Positive-edge triggered diagram
Fig 2.2.3 positive edge triggered D-flip flop diagram
Fig 2.2.4 master slave edge triggered D-flip flop

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Fig 2.2.5 An implementation circuit of master slave D-flip flop

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Fig 2.3.1 Basic Flip Flop Diagram with GDI Multiplexer

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Fig 2.4.1 Improved Flip Flop with delay element

Fig 2.5.1 Modified D Flip-Flop circuit using PMOS as delay element
Fig 2.5.2 PMOS as delay element schematic diagram
Fig 2. 5.3 PMOS as delay element layout diagram
Fig 2.6.1 Proposed D Flip-Flop circuit using NMOS as delay element
Fig 2.6.2 Proposed D-Flip-Flop schematic diagram using NMOS as delay element

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Fig 2.6.3 Proposed D-Flip-Flop layout diagram using NMOS as delay element

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Fig 2.7.1 4-bit serial in serial out shift register block diagram

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Fig 3.1.1 SISO implementation by using four D-flip flops schematic diagram

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Fig 3.1.2 SISO implementation by using four D-flip flops layout diagram

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Fig 4.1.1 Electric software

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Fig 4.1.2 Preferences

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Fig 4.1.3 Project settings

Fig 4.2.1 New Cell
Fig 4.2.2 Schematic Symbols
Fig 4.2.3 Inserting Symbols
Fig 4.2.4 Electric Messages

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Fig 4.2.5 Connection of Symbols

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Fig 4.2.6 Transistor Properties

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Fig 4.2.7 Create New Export

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Fig 4.2.8 Finished Circuit

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Fig 4.2.9 Simulation of Spice deck

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Fig 4.3.1 Selecting Layout

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Fig 4.3.2 P-Transistor Layout

Fig 4.3.3 N-Transistor Layout
Fig 4.3.4 Joining P MOS and N MOS Layouts
Fig 4.3.5 Approximate distance of Transistors
Fig 4.3.6 P Active-Metal 1 contact
Fig 4.3.7 N Active-Metal contacts on both sides
Fig 4.3.8 Successful connections
Fig 4.4.1 Drain contacts of PMOS and NMOS

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Fig 4.4.2 Metal-1 to P Well contact at the NMOS

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Fig 4.4.3 Connecting the source to Well contact

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Fig 4.4.4 Metal-1 to Polysilicon-1 contact

Fig 4.4.5 Exporting Nodes

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Fig 4.4.6 Creating New Export

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Fig 4.4.7 Vdd and gnd export characteristics

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Fig 4.4.8 Simulation with spice deck

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Fig 4.5.1 Editing a Cell

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Fig 4.5.2 Inv-Schematic

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Fig 4.5.3 Network consistency check

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Fig 4.5.4 Size checking

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Fig 4.5.5 NCC Message

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Fig 5.1.1 Example of voltage source

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Fig 5.3.1 Variable of AC Analysis.

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Fig 5.3.2 LT Spice

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Fig 5.3.3 Output wave form

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Fig 5.3.4 Simulation Wave form

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Fig 5.3.5 Layout and Cross-section of an inverter

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Fig 5.3.6 Transistor nodes

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Fig 5.3.7 Wires

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Fig 5.3.8 Contacts

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Fig 5.3.9 Layout Design

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Fig 5.3.10 Geometric Rules

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Fig 5.3.11 Well Spacing

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Fig 5.3.12 Estimating Area by counting wiring tracks

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Fig 5.3.12 Stick Diagram

Fig 6.1.1 Existed GDI based D-flip flop Simulation waveform.

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Fig 6.1.2 GDI based D-flip flop using PMOS as delay element waveform.

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Fig 6.1.3 proposed GDI based D-flip flop using NMOS as delay element

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Simulation waveform.
Fig 6.1.4 waveforms of SISO with basic D-flip flops multiplexer Simulation.
Fig 6.1.5 Waveforms of SISO with proposed NMOS as a delay element.

ABSTRACT
Power consumption minimization is constantly required to meet increasing
demand for Energy performance requirements. For this, designers of next-generation
systems are trying hard to explore new approaches for least possible power
consumption. Major factor to reduce the power consumption is Scaling of power supply
voltage. To achieve higher drive current and hence better speed, threshold voltage may
be reduced but at the cost of increase in the stand-by power. Operating the circuit with a
supply voltage lower than the threshold voltage i.e. sub threshold region is the technique
to achieve ultra-low power. Sub threshold operation is being examined to stretch lowpower circuit designs beyond the normal modes of operation, with the potential for large
energy savings. Ultra low-power consumption can be achieved by operating digital
circuits with scaled supply voltages. In this report proposed sub threshold circuit is
based on GDI (Gate Diffusion Input)-a new technique of low power digital
combinational circuit design.
This technique allows reducing power consumption, delay and area of digital
circuits, while maintaining low complexity of logic design as compared to other CMOS
circuits. Electric Tool is used to design the schematic and layout level diagrams of our
project. The LT-SPICE tool will be used for simulation of the Spice code which tests
the functionality of our generated layout and schematic blocks.