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SPECIFICATION: Specifications
Mounting Type: Surface Mount
Number of Gates:15000 ~ 200000
Number of I/O:60 ~ 260
Number of LABs/CLBs:96 ~ 1176
Number of Logic Elements/Cells:432 ~ 5292
Package / Case:100-TQFP ~ 456-BBGA
Total RAM Bits:16384 ~ 57344
Voltage - Supply:2.375 V ~ 2.625 V
In XC9572-PC84, the macro cells which corresponds to the input/output pins are
69 macro cells in the 72 macro cells. In case of XC95108-PC84, they are 69
macro cells in the 108 macro cells. The macro cells which don't correspond to the
input/output pins can be used only in the logic circuits inside.
Features
Temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macro cells
Within Function Block
- Global and product term clocks, output enables,
Set and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
Macro cell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design
protection
High-drive 24 mA outputs
UNIVERSAL BOARD:This is a unique board that accepts any PLD device of any make or package.This
striking feature has been introduced by MILMAN to cater to the needs of design
engineers.
SPECIFICATION:
32 digital input/outputs (Bi-directional) with LED indication
4-key switches in 2X2 matrix format
4 seven segment multiplexed LED display
RS232 driver interface with 9 pin D-type connector for serial code
verification
Power-ON reset circuit with reset key
On board 3.57/6 MHz clock
Polarity free power connector
On board JTAG interface, which eliminates the costly JTAG cable, required
for downloading the design.
ADDITIONAL COMPONENT:
1. Digital input/output: Total 32 digital I/O with LED indication are
provided, which can be used as bidirectional port.
2. Keyboard: Total 4 keys are provided in 2X2-matrix format. There are
two-scan line (SL0 & SL1) and two-return lines (RL0 & RL1).
3. Display: Four seven segment multiplexed LED displays are provided.
The segment a to dp are common to all the displays and the
common point is driven through DIS0 to DIS3. A state 1 will turn
ON particular segment and 0 will switch off. Also DIS0 to DIS1 are
active low.
4. Power on reset circuit: The power ON reset circuit with reset key is
provided with active high output.
5. Clock: On board clock of 3.57 /6 MHz is available.
PIN ASSIGNMENT:
SPARTAN 3E
1. Design the circuit that you would like to map to the Xilinx part on the FPGA.
You can use schematics, or Verilog, or a mixture of both.
2. Simulate your circuit using the ISE Simulator and a Verilog testbench to
provide inputs to the circuit. Use if statements in your testbench to make it selfchecking.
3. Generate a UCF file to hold constraints such as pin assignments (later well use
the UCF file for other constraints like timing and speed). Use the PlanAhead tool
to generate this file.
4. Assign the I/O pins in your design to the pins on the FPGA that you want them
connected to.
5. Synthesize the design for the FPGA using the XST synthesis tool.
6. Implement the design to map it to the specific FPGA on the Spartan-3E board
7. Generate the programming .bit file that has the bitstream that configures the
FPGA.
8. Connect your Spartan3 board to the computer and use the iMPACT tool to
program the FPGA using the bit stream.
ON BOARD FEATURES
Intel Corporation for the 128 Mbit Strata Flash memories.
Linear Technology for the SPI-compatible A/D and D/A converters, the
programmable pre-amplifier, and the power regulators for the non-FPGA
components
Micron Technology, Inc. for the 32M x 16 DDR SDRAM
SMSC for the 10/100 Ethernet PHY
STMicroelectronics for the 16M x 1 SPI serial Flash PROM
Texas Instruments Incorporated for the three-rail TPS75003 regulator supplying
most of the FPGA supply voltages
Xilinx, Inc. Configuration Solutions Division for the XCF04S Platform Flash
PROM and their support for the embedded USB programmer
Xilinx, Inc. CPLD Division for the XC2C64A CoolRunner -II CPLD
Xilinx Spartan-3E has in-built clock of 50 MHz frequency.
Experiment 1
Aim- Design of a 4 bit counter using Verilog in Xilinx 8.1 platform and
implement it in SPARTAN II kit.
Theory-
Procedure:
1. Click on this icon. For Starting a new project
9. Click Next.
12. Write the Verilog code for the counter in the window
shown below.
Note: You may be asked to save the VHDL file, and your
design will be checked for syntax errors (these will need to
be fixed before you can proceed).
14. We want to create a UCF file, so click yes.
16. Enter the pin names for each signal in the Design Object
List at the left as shown here. Click File > Save.
17. This dialog may appear when saving the file select XST
Default :<>
Code:
`timescale 1ns / 1ps
module Counter(input clk, input rst, output reg [3:0]
count);
integer temp;
always @ (posedge clk)
begin
if (rst)
begin
count <= 4'b0000;
temp <= 0;
end
else if (temp == 5000000)
begin
count <= count +1;
temp <= 0;
end
else
temp <= temp+1;
end
endmodule
Experiment-2
Aim- To design a 1 bit full adder in Xilinx 8.1 and implement it on
SPARTAN 2 kit.
Theory-
Code:
`timescale 1ns / 1ps
module FA1(a, b, cin, cout, sum);
input a;
input b;
input cin;
output cout;
output sum;
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (cin & a);
endmodule
Experiment-3
Aim- To display last 4 digit of your roll number in 7 segment display of
Code:
module AminSevenSeg(input clk, output reg [7:0]out, output reg [3:0] enable);
reg [15:0]temp=16'b0000000000000000;
always @ (posedge clk )
begin
temp=temp+1;
end
always@ *
case(temp[15:14])
2'b00: begin
enable = 4'b1110;// active low enable biases PNP to make it ON (i.e., DIS-0)
out= 8'b11101101; // data for 5
end
2'b01: begin
enable = 4'b1101; // active low enable biases PNP to make it ON (i.e., DIS-1)
out= 8'b11111101; // data for 6
end
2'b10: begin
enable = 4'b1011;// active low enable biases PNP to make it ON (i.e., DIS-2)
out= 8'b11101111;// data for 9
end
default:
begin
enable = 4'b0111;// active low enable biases PNP to make it ON (i.e., DIS-3)
out= 8'b11111111;// data for 8
end
endcase
endmodule
Experiment-4
Aim- To display and blink last 4 digit of your roll number in 7 segment
Code:
`timescale 1ns / 1ps
module blink(input clk, output reg [7:0]out, output reg [3:0] enable);
reg [15:0]temp=16'b0000000000000000;
reg [20:0]delay=21'b000000000000000000000;
always @ (posedge clk )
begin
temp=temp+1;
delay=delay+1;
end
always@ *
begin
case(temp[15:14])
2'b00: begin
enable = 4'b1110;// active low enable biases PNP to make it ON (i.e., DIS-0)
out= 8'b11101101; // data for 5
end
2'b01: begin
enable = 4'b1101; // active low enable biases PNP to make it ON (i.e., DIS-1)
out= 8'b11111101; // data for 6
end
2'b10: begin
enable = 4'b1011;// active low enable biases PNP to make it ON (i.e., DIS-2)
out= 8'b11101111;// data for 9
end
default:
begin
enable = 4'b0111;// active low enable biases PNP to make it ON (i.e., DIS-3)
out= 8'b11111111;// data for 8
end
endcase
end
endmodule
Experiment-5
Aim- To display and rotate HELP in 7 segment display of SPARTAN 2 kit
Code:
`timescale 1ns / 1ps
module rotation(input clk, output reg [7:0]out, output reg [3:0] enable );
reg [15:0]temp=16'b0000000000000000;
reg [20:0]delay=21'b000000000000000000000;
reg [3:0]param[3:0];
reg [3:0]next;
initial
begin
param[0]=4'b1110;
param[1]=4'b1101;
param[2]=4'b1011;
param[3]=4'b0111;
end
always @ (posedge clk )
begin
temp=temp+1;
delay=delay+1;
if(delay==21'b111111111111111111111 )
begin
next=param[0];
param[0]=param[1];
param[1]=param[2];
param[2]=param[3];
param[3]=next;
end
else
case(temp[15:14])
2'b00: begin
enable = param[0];// active low enable biases PNP to make it ON (i.e., DIS-0)
out= 8'b01110011; // data for 5
end
2'b01: begin
enable = param[1]; // active low enable biases PNP to make it ON (i.e., DIS1)
out= 8'b00111000; // data for 6
end
2'b10: begin
enable = param[2];// active low enable biases PNP to make it ON (i.e., DIS-2)
out= 8'b01111001;// data for 9
end
default:
begin
enable = param[3];// active low enable biases PNP to make it ON (i.e., DIS-3)
out= 8'b01110110;// data for 8
end
endcase
end
endmodule
Experiment-6
Aim- Design a 4 bit Johnson counter and implement it on SPARTAN 3E
kit.
A Johnson counter is a modified ring counter, where the inverted output
from the last flip flop is connected to the input to the first. The register cycles
through a sequence of bit-patterns. The MOD of the Johnson counter is 2n if n
flip-flops are used. The main advantage of the Johnson counter counter is that it
only needs half the number of flip-flops compared to the standard ring counter
for the same MOD.
Theory-
Clk
1
2
3
4
5
6
7
8
9
Q0
0
1
1
1
1
0
0
0
0
Q1
0
0
1
1
1
1
0
0
0
Q2
0
0
0
1
1
1
1
0
0
Q3
0
0
0
0
1
1
1
1
0
Code:
`timescale 1ns / 1ps
module AminJohnson (input direction, rst, clk_in, output reg [3:0] count);
if(!rst)
begin
if(direction)
begin
count[3:1] <= count[2:0];
count[0]<=!count[3];
end
else
begin
end
end
else
count[3:0] <= 4'b0000;
end
endmodule
Experiment - 7
Aim- Design of a 4 bit LFSR (Linear feedback shift resistor) using Verilog
and implement it in SPARTAN 3E kit.
Theory:
LFSR:
In computing, a linear-feedback shift register (LFSR) is
register whose input bit is a linear function of its previous state.
a shift
The most commonly used linear function of single bits is exclusiveor (XOR). Thus, an LFSR is most often a shift register whose input bit is
driven by the XOR of some bits of the overall shift register value.
The initial value of the LFSR is called the seed, and because the
operation of the register is deterministic, the stream of values
produced by the register is completely determined by its current (or
previous) state. Likewise, because the register has a finite number of
possible states, it must eventually enter a repeating cycle. However, an
LFSR with a well-chosen feedback function can produce a sequence of
bits which appears random and which has a very long cycle.
Applications
of
LFSRs
include
generating pseudo-random
numbers, pseudo-noise sequences, fast digital counters, and whitening
sequences. Both hardware and software implementations of LFSRs are
common.
Circuit Diagram :
Code:
`timescale 1ns / 1ps
module lfsr(input clk, rst, en, input[3:0]load, output reg [3:0] out);
FreqDiv instance_name(.clk_out(clk_out),.clk_in(clk));
wire feedback;
assign feedback=(out[2]^out[3]);
always @(posedge clk_out)
begin
if(rst)
out=4'b1111;
else if(en)
out[3:0]=load[3:0];
else
out={out[2:0],feedback}; // OUT[3] <= feedback
end
endmodule
begin
clk_out=1'b0;
count=0;
end
always @(posedge clk_in)
if (count==44999999)
begin
count<=0;
clk_out<=~clk_out;
end
else
count<=count+1;
endmodule
Experiment - 8
Aim - Display your name in 16*2 LCD using Verilog in SPARTAN 3E kit.
Theory:
LCD
The Spartan-3A/3AN Starter Kit board prominently features a 2-line by 16character liquid crystal display (LCD). The FPGA controls the LCD via the eightbit data interface. The Spartan-3A/3AN Starter Kit board also supports the four-bit
data interface to remain compatible with other Xilinx development boards.
CHARACTER LCD INTERFACE
Signal name
FPGA Pin
Function
LCD_DB<7>
LCD_DB<6>
LCD_DB<5>
LCD_DB<4>
LCD_DB<3>
LCD_DB<2>
LCD_DB<1>
LCD_DB<0>
LCD_E
Y15
AB16
Y16
AA12
AB12
AB17
AB18
Y13
AB4
LCD_RS
Y14
LCD_RW
W13
"LCD_E"
"LCD_RS"
"LCD_RW"
"LCD_DB<7>"
"LCD_DB<6>"
"LCD_DB<5>"
"LCD_DB<4>"
"LCD_DB<3>"
"LCD_DB<2>"
"LCD_DB<1>"
"LCD_DB<0>"
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
Power-On Initialization
The initialization sequence first establishes that the FPGA application wishes to
use the Four-bit data interface to the LCD as follows:
1. Wait 15 ms or longer, although the display is generally ready when the FPGA
finishes. Configuration. The 15 ms interval is 750,000 clock cycles at 50 MHz
2. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
3. Wait 4.1 ms or longer, which is 205,000 clock cycles at 50 MHz
4. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
5. Wait 100 s or longer, which is 5,000 clock cycles at 50 MHz
6. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
7. Wait 40 s or longer, which is 2,000 clock cycles at 50 MHz
8. Write LCD_DB<7:4> = 0x2, and pulse LCD_E High for 12 clock cycles.
9. Wait 40 s or longer, which is 2,000 clock cycles at 50 MHz
Display Configuration
After the power-on initialization is completed, the four-bit interface is established.
The next part of the sequence configures the display:
1. Issue a Function Set command, 0x28, to configure the display for operation on
the Spartan kit.
2. Issue an Entry Mode Set command, 0x06, to set the display to automatically
increment the address pointer.
3. Issue a Display On/Off command, 0x0C to turn the display on and disable the
cursor and blinking.
4. Finally, issue a Clear Display command. Allow at least 1.64 ms (82,000 clock
cycles) after
Issuing this command.
Code:
`timescale 1ns / 1ps
// data to be dispalyed
default: inst<=6'h10;
endcase
SF_CE0<=1;
LCD_E<=count[20];
LCD_RS<=inst[5]; //1-> data 0-> command
LCD_RW<=inst[4]; // 1->read 0->write
SFD_8<=inst[0];
SFD_9<=inst[1];
SFD_10<=inst[2];
SFD_11<=inst[3];
end
endmodule
Experiment - 9
Aim- Display and blink your name in 16*2 LCD using Verilog in SPARTAN
3E kit.
Code:
`timescale 1ns / 1ps
//power on initialization
0: inst<= 6'h03;
1: inst<= 6'h03;
2: inst<= 6'h03;
3: inst<= 6'h02;
//default: inst<=6'h10;
endcase
end
// data to be dispalyed
end
always@ (posedge clk)
begin
SF_CE0<=1;
SFD_E<=count[20];
SFD_RS<=inst[5]; //1-> data 0-> command
SFD_RW<=inst[4]; // 1->read 0->write
SFD_8<=inst[0];
SFD_9<=inst[1];
SFD_10<=inst[2];
SFD_11<=inst[3];
end
endmodule
Experiment 10
Aim- Design of a full adder using IP core (core generator &
architecture wizard)
Code:
module adder(input clk, c_in, input a[1:0], b[1:0], output s[2:0] );
ipcoreyour_instance_name (
.a(a),
// input [1 : 0] a
.b(b),
// input [1 : 0] b
.clk(clk),
// input clk
// output [2 : 0] s
Experiment 11
Aim- Use of system generator without chipscope for adder.
Theory
SYSTEM GENERATOR
System Generator for DSP is the industrys leading high-level tool for
designing high-performance DSP systems using Xilinx All Programmable
devices. With System Generator for DSP, create production-quality DSP
algorithms in a fraction of time compared to traditional RTL.
Develop highly parallel systems with the industrys most advanced
FPGAs
Provide system modeling and automatic code generation from
Simulink and MATLAB (The Mathworks, Inc.)
Integrates RTL, embedded, IP, MATLAB and hardware components
of a DSP system
A key component of the Xilinx DSP Targeted Design Platform
System Generator for DSP is part of the Vivado System Edition Design
Suite. With System Generator for DSP, developers with little FPGA
design experience can quickly create production quality FPGA
implementations of DSP algorithms in a fraction of traditional RTL
development times.
Procedure1. All programs-> Xilinx design tools -> ISE design suite 14.1 ->
System generator-> system generator -> Simulink ->sink ->scope
(for output)-> write click on scope and add to the model. Save the
model at describe location with a file name.
2. Xilinx block set -> basic elements ->add gateway out, 2 gateway
In, system generator.
3. Xilinx block set -> maths-> addsub.
4. Double click Gateway In-> change arithmetic type to Unsigned.
Set the number of bits and binary point.
5. Go to implementation tab and checks specify IOB location
constraint -> assign input pin location in FPGA. Repeat the same
for both inputs to adder.
6. Double click on gateway out -> checks specify IOB location
constraint -> assign input pin location in FPGA.
7. Double click on Addsub-> basic tab->click on addition option ->
output tab-> precision user defined -> arithmetic sign ->
unsigned -> select the number of bits and binary point.
8. Double click on system generator -> clock in -> A/O compilation ->
bitstream .Part->SPARTAN 3E-> XC3S500E-> -4 -> FG320.Hardware
description language -> Verilog. Clocking -> clock pin -> C9.
9. Now generate file.
10.
For dumping into kit:
11.
All programs-> Xilinx design tools -> ISE design suite 14.1 >ISE design tool -> 32- bit tools -> Impact.
12.
Select the bit file and program as before(bit file name is
generated inside netlist directory) bitfile name is file_name .bit.
Circuit Diagram :
Experiment 12
Aim- Use of system generator with chipscope for adder.
Theory-
CHIPSCOPE
ChipScope Pro tool inserts logic analyzer, system analyzer, and virtual
I/O low-profile software cores directly into your design, allowing you to
view any internal signal or node, including embedded hard or soft
processors. Signals are captured in the system at the speed of
operation and brought out through the programming interface, freeing
up pins for your design. Captured signals are then displayed and
analyzed using the ChipScope Pro Analyzer tool.
The ChipScope Pro tool also interfaces with your Agilent Technologies
bench test equipment through the ATC2 software core. This core
synchronizes the ChipScope Pro tool to Agilents FPGA Dynamic Probe
add-on option. This unique partnership between Xilinx and Agilent gives
you deeper trace memory, faster clock speeds, more trigger options,
and system-level measurement capability all while using fewer pins on
the FPGA device.
The ChipScope Pro Serial I/O Toolkit provides a fast, easy, and
interactive setup and debug of serial I/O channels in high-speed FPGA
designs. The ChipScope Pro Serial I/O Toolkit allows you to take biterror ratio (BER) measurements on multiple channels and adjust highspeed serial transceiver parameters in real-time while your serial I/O
channels interact with the rest of the system.
ChipScope Pro Key Features:
Analyzer trigger and capture enhancements makes taking repetitive
measurements easy to do
Enhancements to the Virtex-5 and Virtex-6 System Monitor console make it
easier to access on-chip temperature, voltage, and external sensor data
PROCEDURE:
1.
2.
3.
5.
6.
7.
8.
9.
10.
Circuit Diagram :