library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.hrmt_package.all;

entity DES_Encryption is
port(
clk,rst

: in

std_logic;

key_in :

in

unsigned(63 downto 0);

Message

in

unsigned(63 downto 0);

cipher_text : out unsigned(63 downto 0));

end DES_Encryption;

architecture Behavioral of DES_Encryption is

type LR_Matrix

signal L,R

is array (16 downto 0) of unsigned(31 downto 0);

: LR_Matrix := (others => (others => '0'));

signal RegL,RegR

: LR_Matrix := (others => (others => '0'));

signal REGkey,key

: hrmt_array := (others => (others => '0'));

signal Shift_REGkey : type_Shift_REGkey :=(others => (others => '0'));

signal Reg5L : type_array16_subtype_unsigned_31_0 := (others => (others =>

'0'));

signal cipher_text_int : unsigned(63 downto 0) := (others => '0');

begin

Inst_Round_Key_Generator : entity work.Round_Key_Generator

port map (
clk => clk,
rst => rst,
key_in =>

key_in,

key_out => key

);

Inst_REG_Round_Key_Generator: entity
work.REG_Round_Key_Generator
PORT MAP(
clk => clk,
rst => rst,
key_in => key,
key_out => REGkey
);

Inst_Initil_Permutation_Module : entity work.Initial_Permutation_Module

port map (
Message => Message,
L0

=> L(0),

R0

=> R(0));

Inst0_REG_LnRn: entity work.REG_LnRn

PORT MAP(
clk => clk,

rst => rst,

Ln => L(0),
Rn => R(0),
RegLn => RegL(0),
RegRn => RegR(0)
);

Inst1_Shift_Reg_4Stage_32bit: entity work.Shift_Reg_4Stage_32bit

PORT MAP(
clk => clk,
rst => rst,
input => RegL(0),
output => Reg5L(0)
);

Inst1_Round_Function : entity work.Round_Function

port map (
clk => clk,
rst => rst,
Ln_Minus_1 =>Reg5L(0) ,
Rn_Minus_1 =>RegR(0) ,
Kn

=>REGkey(1) ,

Ln

=>L(1) ,

Rn

=>R(1));

Inst1_REG_LnRn: entity work.REG_LnRn

PORT MAP(
clk => clk,

rst => rst,

Ln => L(1),
Rn => R(1),
RegLn => RegL(1),
RegRn => RegR(1)
);

Inst_Shift_Reg_Round_Function2: entity work.Shift_Reg

generic map(
--n_bit => 48,
n_shift => 5)
PORT MAP(
clk => clk,
rst => rst,
input => REGkey(2),
output => Shift_REGkey(2)
);

Inst2_Shift_Reg_4Stage_32bit: entity work.Shift_Reg_4Stage_32bit

PORT MAP(
clk => clk,
rst => rst,
input => RegL(1),
output => Reg5L(1)
);

Inst2_Round_Function : entity work.Round_Function

port map (
clk => clk,
rst => rst,
Ln_Minus_1 =>Reg5L(1) ,
Rn_Minus_1 =>RegR(1) ,
Kn

=>Shift_REGkey(2) ,

Ln

=>L(2) ,

Rn

=>R(2));

Inst2_REG_LnRn: entity work.REG_LnRn

PORT MAP(
clk => clk,
rst => rst,
Ln => L(2),
Rn => R(2),
RegLn => RegL(2),
RegRn => RegR(2)
);

Inst_Shift_Reg_Round_Function3: entity work.Shift_Reg

generic map(
--n_bit => 48,
n_shift => 10)
PORT MAP(
clk => clk,
rst => rst,
input => REGkey(3),
output => Shift_REGkey(3)

);

Inst3_Shift_Reg_4Stage_32bit: entity work.Shift_Reg_4Stage_32bit

PORT MAP(
clk => clk,
rst => rst,
input => RegL(2),
output => Reg5L(2)
);

Inst3_Round_Function : entity work.Round_Function

port map (
clk => clk,
rst => rst,
Ln_Minus_1 =>Reg5L(2) ,
Rn_Minus_1 =>RegR(2) ,
Kn

=>Shift_REGkey(3) ,

Ln

=>L(3) ,

Rn

=>R(3));

Inst3_REG_LnRn: entity work.REG_LnRn

PORT MAP(
clk => clk,
rst => rst,
Ln => L(3),
Rn => R(3),
RegLn => RegL(3),
RegRn => RegR(3)

);

Inst_Shift_Reg_Round_Function4: entity work.Shift_Reg

generic map(
--n_bit => 48,
n_shift => 15)
PORT MAP(
clk => clk,
rst => rst,
input => REGkey(4),
output => Shift_REGkey(4)
);

Inst4_Shift_Reg_4Stage_32bit: entity work.Shift_Reg_4Stage_32bit

PORT MAP(
clk => clk,
rst => rst,
input => RegL(3),
output => Reg5L(3)
);

Inst4_Round_Function : entity work.Round_Function

port map (
clk => clk,
rst => rst,
Ln_Minus_1 =>Reg5L(3) ,
Rn_Minus_1 =>RegR(3) ,
Kn

=>Shift_REGkey(4) ,

Ln

=>L(4) ,

Rn

=>R(4));

Inst4_REG_LnRn: entity work.REG_LnRn

PORT MAP(
clk => clk,
rst => rst,
Ln => L(4),
Rn => R(4),
RegLn => RegL(4),
RegRn => RegR(4)
);

Inst_Shift_Reg_Round_Function5: entity work.Shift_Reg

generic map(
--n_bit => 48,
n_shift => 20)
PORT MAP(
clk => clk,
rst => rst,
input => REGkey(5),
output => Shift_REGkey(5)
);

Inst5_Shift_Reg_4Stage_32bit: entity work.Shift_Reg_4Stage_32bit

PORT MAP(
clk => clk,
rst => rst,

input => RegL(4),

output => Reg5L(4)
);

Inst5_Round_Function : entity work.Round_Function

port map (
clk => clk,
rst => rst,
Ln_Minus_1 =>Reg5L(4) ,
Rn_Minus_1 =>RegR(4) ,
Kn

=>Shift_REGkey(5) ,

Ln

=>L(5) ,

Rn

=>R(5));

Inst5_REG_LnRn: entity work.REG_LnRn

PORT MAP(
clk => clk,
rst => rst,
Ln => L(5),
Rn => R(5),
RegLn => RegL(5),
RegRn => RegR(5)
);

Inst_Shift_Reg_Round_Function6: entity work.Shift_Reg

generic map(
--n_bit => 48,
n_shift => 25)

PORT MAP(
clk => clk,
rst => rst,
input => REGkey(6),
output => Shift_REGkey(6)
);

Inst6_Shift_Reg_4Stage_32bit: entity work.Shift_Reg_4Stage_32bit

PORT MAP(
clk => clk,
rst => rst,
input => RegL(5),
output => Reg5L(5)
);

Inst6_Round_Function : entity work.Round_Function

port map (
clk => clk,
rst => rst,
Ln_Minus_1 =>Reg5L(5) ,
Rn_Minus_1 =>RegR(5) ,
Kn

=>Shift_REGkey(6) ,

Ln

=>L(6) ,

Rn

=>R(6));

Inst6_REG_LnRn: entity work.REG_LnRn

PORT MAP(
clk => clk,

rst => rst,

Ln => L(6),
Rn => R(6),
RegLn => RegL(6),
RegRn => RegR(6)
);

Inst_Shift_Reg_Round_Function7: entity work.Shift_Reg

generic map(
--n_bit => 48,
n_shift => 30)
PORT MAP(
clk => clk,
rst => rst,
input => REGkey(7),
output => Shift_REGkey(7)
);

Inst7_Shift_Reg_4Stage_32bit: entity work.Shift_Reg_4Stage_32bit

PORT MAP(
clk => clk,
rst => rst,
input => RegL(6),
output => Reg5L(6)
);

Inst7_Round_Function : entity work.Round_Function

port map (

clk => clk,

rst => rst,
Ln_Minus_1 =>Reg5L(6) ,
Rn_Minus_1 =>RegR(6) ,
Kn

=>Shift_REGkey(7) ,

Ln

=>L(7) ,

Rn

=>R(7));

Inst7_REG_LnRn: entity work.REG_LnRn

PORT MAP(
clk => clk,
rst => rst,
Ln => L(7),
Rn => R(7),
RegLn => RegL(7),
RegRn => RegR(7)
);

Inst_Shift_Reg_Round_Function8: entity work.Shift_Reg

generic map(
--n_bit => 48,
n_shift => 35)
PORT MAP(
clk => clk,
rst => rst,
input => REGkey(8),
output => Shift_REGkey(8)
);

Inst8_Shift_Reg_4Stage_32bit: entity work.Shift_Reg_4Stage_32bit

PORT MAP(
clk => clk,
rst => rst,
input => RegL(7),
output => Reg5L(7)
);
Inst8_Round_Function : entity work.Round_Function
port map (
clk => clk,
rst => rst,
Ln_Minus_1 =>Reg5L(7) ,
Rn_Minus_1 =>RegR(7) ,
Kn

=>Shift_REGkey(8) ,

Ln

=>L(8) ,

Rn

=>R(8));

Inst8_REG_LnRn: entity work.REG_LnRn

PORT MAP(
clk => clk,
rst => rst,
Ln => L(8),
Rn => R(8),
RegLn => RegL(8),
RegRn => RegR(8)
);

Inst_Shift_Reg_Round_Function9: entity work.Shift_Reg

generic map(
--n_bit => 48,
n_shift => 40)
PORT MAP(
clk => clk,
rst => rst,
input => REGkey(9),
output => Shift_REGkey(9)
);

Inst9_Shift_Reg_4Stage_32bit: entity work.Shift_Reg_4Stage_32bit

PORT MAP(
clk => clk,
rst => rst,
input => RegL(8),
output => Reg5L(8)
);

Inst9_Round_Function : entity work.Round_Function

port map (
clk => clk,
rst => rst,
Ln_Minus_1 =>Reg5L(8) ,
Rn_Minus_1 =>RegR(8) ,
Kn

=>Shift_REGkey(9) ,

Ln

=>L(9) ,

Rn

=>R(9));

Inst9_REG_LnRn: entity work.REG_LnRn

PORT MAP(
clk => clk,
rst => rst,
Ln => L(9),
Rn => R(9),
RegLn => RegL(9),
RegRn => RegR(9)
);

Inst_Shift_Reg_Round_Function10: entity work.Shift_Reg

generic map(
--n_bit => 48,
n_shift => 45)
PORT MAP(
clk => clk,
rst => rst,
input => REGkey(10),
output => Shift_REGkey(10)
);

Inst10_Shift_Reg_4Stage_32bit: entity work.Shift_Reg_4Stage_32bit

PORT MAP(
clk => clk,
rst => rst,
input => RegL(9),
output => Reg5L(9)
);

Inst10_Round_Function : entity work.Round_Function

port map (
clk => clk,
rst => rst,
Ln_Minus_1 =>Reg5L(9) ,
Rn_Minus_1 =>RegR(9) ,
Kn

=>Shift_REGkey(10) ,

Ln

=>L(10) ,

Rn

=>R(10));

Inst10_REG_LnRn: entity work.REG_LnRn

PORT MAP(
clk => clk,
rst => rst,
Ln => L(10),
Rn => R(10),
RegLn => RegL(10),
RegRn => RegR(10)
);

Inst_Shift_Reg_Round_Function11: entity work.Shift_Reg

generic map(
--n_bit => 48,
n_shift => 50)
PORT MAP(
clk => clk,
rst => rst,

input => REGkey(11),

output => Shift_REGkey(11)
);

Inst11_Shift_Reg_4Stage_32bit: entity work.Shift_Reg_4Stage_32bit

PORT MAP(
clk => clk,
rst => rst,
input => RegL(10),
output => Reg5L(10)
);

Inst11_Round_Function : entity work.Round_Function

port map (
clk => clk,
rst => rst,
Ln_Minus_1 =>Reg5L(10) ,
Rn_Minus_1 =>RegR(10) ,
Kn

=>Shift_REGkey(11) ,

Ln

=>L(11) ,

Rn

=>R(11));

Inst11_REG_LnRn: entity work.REG_LnRn

PORT MAP(
clk => clk,
rst => rst,
Ln => L(11),
Rn => R(11),

RegLn => RegL(11),

RegRn => RegR(11)
);

Inst_Shift_Reg_Round_Function12: entity work.Shift_Reg

generic map(
--n_bit => 48,
n_shift => 55)
PORT MAP(
clk => clk,
rst => rst,
input => REGkey(12),
output => Shift_REGkey(12)
);

Inst12_Shift_Reg_4Stage_32bit: entity work.Shift_Reg_4Stage_32bit

PORT MAP(
clk => clk,
rst => rst,
input => RegL(11),
output => Reg5L(11)
);

Inst12_Round_Function : entity work.Round_Function

port map (
clk => clk,
rst => rst,
Ln_Minus_1 =>Reg5L(11) ,

Rn_Minus_1 =>RegR(11) ,
Kn

=>Shift_REGkey(12) ,

Ln

=>L(12) ,

Rn

=>R(12));

Inst12_REG_LnRn: entity work.REG_LnRn

PORT MAP(
clk => clk,
rst => rst,
Ln => L(12),
Rn => R(12),
RegLn => RegL(12),
RegRn => RegR(12)
);

Inst_Shift_Reg_Round_Function13: entity work.Shift_Reg

generic map(
--n_bit => 48,
n_shift => 60)
PORT MAP(
clk => clk,
rst => rst,
input => REGkey(13),
output => Shift_REGkey(13)
);

Inst13_Shift_Reg_4Stage_32bit: entity work.Shift_Reg_4Stage_32bit

PORT MAP(

clk => clk,

rst => rst,
input => RegL(12),
output => Reg5L(12)
);

Inst13_Round_Function : entity work.Round_Function

port map (
clk => clk,
rst => rst,
Ln_Minus_1 =>Reg5L(12) ,
Rn_Minus_1 =>RegR(12) ,
Kn

=>Shift_REGkey(13) ,

Ln

=>L(13) ,

Rn

=>R(13));

Inst13_REG_LnRn: entity work.REG_LnRn

PORT MAP(
clk => clk,
rst => rst,
Ln => L(13),
Rn => R(13),
RegLn => RegL(13),
RegRn => RegR(13)
);

Inst_Shift_Reg_Round_Function14: entity work.Shift_Reg

generic map(

--n_bit => 48,

n_shift => 65)
PORT MAP(
clk => clk,
rst => rst,
input => REGkey(14),
output => Shift_REGkey(14)
);

Inst14_Shift_Reg_4Stage_32bit: entity work.Shift_Reg_4Stage_32bit

PORT MAP(
clk => clk,
rst => rst,
input => RegL(13),
output => Reg5L(13)
);

Inst14_Round_Function : entity work.Round_Function

port map (
clk => clk,
rst => rst,
Ln_Minus_1 =>Reg5L(13) ,
Rn_Minus_1 =>RegR(13) ,
Kn

=>Shift_REGkey(14) ,

Ln

=>L(14) ,

Rn

=>R(14));

Inst14_REG_LnRn: entity work.REG_LnRn

PORT MAP(
clk => clk,
rst => rst,
Ln => L(14),
Rn => R(14),
RegLn => RegL(14),
RegRn => RegR(14)
);

Inst_Shift_Reg_Round_Function15: entity work.Shift_Reg

generic map(
--n_bit => 48,
n_shift => 70)
PORT MAP(
clk => clk,
rst => rst,
input => REGkey(15),
output => Shift_REGkey(15)
);

Inst15_Shift_Reg_4Stage_32bit: entity work.Shift_Reg_4Stage_32bit

PORT MAP(
clk => clk,
rst => rst,
input => RegL(14),
output => Reg5L(14)
);

Inst15_Round_Function : entity work.Round_Function

port map (
clk => clk,
rst => rst,
Ln_Minus_1 =>Reg5L(14) ,
Rn_Minus_1 =>RegR(14) ,
Kn

=>Shift_REGkey(15) ,

Ln

=>L(15) ,

Rn

=>R(15));

Inst15_REG_LnRn: entity work.REG_LnRn

PORT MAP(
clk => clk,
rst => rst,
Ln => L(15),
Rn => R(15),
RegLn => RegL(15),
RegRn => RegR(15)
);

Inst_Shift_Reg_Round_Function16: entity work.Shift_Reg

generic map(
--n_bit => 48,
n_shift => 75)
PORT MAP(
clk => clk,
rst => rst,

input => REGkey(16),

output => Shift_REGkey(16)
);

Inst16_Shift_Reg_4Stage_32bit: entity work.Shift_Reg_4Stage_32bit

PORT MAP(
clk => clk,
rst => rst,
input => RegL(15),
output => Reg5L(15)
);

Inst16_Round_Function : entity work.Round_Function

port map (
clk => clk,
rst => rst,
Ln_Minus_1 =>Reg5L(15) ,
Rn_Minus_1 =>RegR(15) ,
Kn

=>Shift_REGkey(16) ,

Ln

=>L(16) ,

Rn

=>R(16));

Inst16_REG_LnRn: entity work.REG_LnRn

PORT MAP(
clk => clk,
rst => rst,
Ln => L(16),
Rn => R(16),

RegLn => RegL(16),

RegRn => RegR(16)
);

Inst_Initil_Permutation_Inverse : entity work.Initial_Permutation_Inverse

port map (
R => RegR(16),
L => RegL(16),
Cipher_Text => cipher_text_int);

Inst_REG64: entity work.REG64

PORT MAP(
clk => clk,
rst => rst,
input => cipher_text_int,
q => cipher_text
);

end Behavioral;