Analog Integr Circ Sig Process (2011) 67:103107

DOI 10.1007/s10470-011-9609-6

MIXED SIGNAL LETTER

Configurable array of low-complex SAR ADCs

Sergio Saponara

Received: 26 November 2010 / Revised: 27 December 2010 / Accepted: 24 January 2011 / Published online: 6 February 2011
 Springer Science+Business Media, LLC 2011

Abstract An array of low-complex SAR ADCs, configurable in time-interleaved (TI) or parallel modes to reach 1
GS/s or to serve multiple inputs at hundreds of MS/s, is
proposed in this letter. Each SAR ADC channel exploits a
threshold-configuring scheme, to avoid internal DAC thus
saving circuit complexity, plus a dynamic comparator
which allows for power consumption scalable versus processing speed. Implementation results in 90 nm 1 V CMOS
technology are presented and compared to the state of
the art.
Keywords AnalogDigital Converter (ADC) 
Successive Approximation Register (SAR)  TimeInterleaving (TI)

1 Introduction
Emerging applications such as wireless video sensor networks, or unplugged multimedia acquisition and short range
connectivity in home/office scenarios, require the integration of high-speed ADCs with limited cost and power
consumption in digital-based embedded systems. Samplerates of GS/s and moderate resolution, around 6 bits, are
required for the ADC to be used in UWB (ultra wide band)
and 60 GHz radio wireless systems [110]. Besides the A/D
interface versus the wireless communication channel other
ADC channels are required, with sample rates from few to
hundreds of MS/s, to acquire the multimedia sensors

S. Saponara (&)
Dipartimento di Ingegneria dellInformazione, Universita` di
Pisa, Via G. Caruso 16, 56122 Pisa, Italy
e-mail: sergio.saponara@iet.unipi.it

data (video camera, voice acquisition systems, multi-axes

accelerometers/gyro for body positioning,).
In the literature specific ADC designs have been proposed for a given speed/resolution requirement, mainly
Flash and pipeline ADCs for high-speed at GS/s and SAR
ADCs for acquisitions within 100 MS/s [1, 1113]. Timeinterleaving of basic ADC channels is also used in literature to design fast converters [27, 1417].
With respect to state of the art this work presents the
design of an ADC build as an array of new thresholdconfiguring SAR channels with Track/Hold (T/H) units.
Implementation results in 90 nm CMOS technology are
also provided. The array, sketched in Fig. 1, is configurable
in two modes: TI mode to convert a single S(t) signal
at 1 GS/s or parallel mode to serve up to 8 inputs,
X1(t),,X8(t), each at 125 MS/s. The array is configurable
through a controller providing the enabling signals to the
T/H ? ADC blocks and to the input and output switch
logic units.
Hereafter Sect. 2 presents the design of the new SAR
ADC channel while Sect. 3 analyses the performance of the
ADC array. CMOS implementation results of the ADC
array in Fig. 1 are discussed in Sect. 4. Conclusions are
drawn in Sect. 5.

2 New SAR ADC channel design

The configurable ADC array, proposed in Fig. 1, adopts as
basic channel a new threshold-configuring SAR, discussed
in this section, whose block diagram is reported in Fig. 2.
The ADC channel architecture in Fig. 2 is based on a
dynamic comparator with configurable thresholds, whose
schematic is reported in Fig. 3, to implement the SAR
algorithm. Small PMOS capacitor arrays are used to

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Analog Integr Circ Sig Process (2011) 67:103107

Sq @ Fs=1/T=1 GHz, X1q..X8q @ F2=1/T2=125 MHz

7 bits/sample SAR ADC channels (8 clock cycles/sample)
S(t) or
X1(t)

S(t) or
X1(t)

T/H +
SAR ADC-1

En1

Fs-clk

S(t) or
X2(t)

X2(t)
Switch
Logic

X2q(mT2)
or null

Sq(n8T+T)
or X2q(mT2)
T/H +
SAR ADC-2

En2

Fs-clk

S(t) or
X8(t)

X8(t)

Sq(nT) or
X1q(mT2)

Sq(n8T) or
X1q(mT2)

T/H +
SAR ADC-8

Fs-clk

Switch
logic

Sq(n8T+7T)
or X8q(mT2)

X8q(mT2)
or null

En8

Time-interleaved (TI) or Parallel

controller

Fig. 1 Simplified block diagram of the configurable ADC array

En=1

Input Sampling, En=0

IN+

Hold &SAR conversion

Dynamic comparator with
configurable thresholds
and offset calibration

INsa
Passive
Sample/Hold
Differential I/O

OUTb
/GO

Sample
Clock

INsb

OUTa

Cconf

Synchronous SAR and calibration controller

Out
(a6..a0)

En

Off-cal

Thr-cal

Fig. 2 Schematic of the new SAR ADC with threshold configurable

dynamic comparator

dynamically configure the comparator thresholds. Therefore differently from known TI SAR ADC arrays [27, 14
17] there is no need for a feedback DAC to generate the
error signal between the sampled input and the comparator
output. This task is performed by the comparator itself. The
ADC architecture in Fig. 2 includes also a passive T/H
with differential input and output. Differently from [1]1
which uses asynchronous logic for the SAR controller
(forcing the adoption in [1] of two different voltages, 1 V
for the analog part and 0.7 V for the digital part), in Fig. 2
we designed a synchronous SAR controller using TrueSingle-Phase-Clock (TSPC) logic to reach high-speed and
adopt the same 1 V single supply voltage for both digital
and analog parts. This way the integration of the ADC as
1
Also [7] adopts a self-timed SAR logic with a requirement of dual
supply voltage, 1.8 and 1.2 V for the digital and analog parts.

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an IP (Intellectual Property) macrocell in digital-based

embedded systems is easier and no extra DC/DC regulators
are required.
We implement the SAR algorithm as follows: (a) the T/H
unit in Fig. 2 samples the new analog input which is held
constant at the comparator input until the conversion is
completed (n ? 1 clock cycles for n-bit conversion, 8 clock
cycles for 7-bit conversion in the ADC channel implemented
in Sect. 4); (ii) the comparator in Figs. 2 and 3, initialized
with a 0 threshold, first takes the decision about the Most
Significant Bit (MSB) which acts as a sign bit; (iii) depending
on the MSB decision, the new threshold is set to VREF/2
and a new comparison is triggered. The above operations
are repeated adding scaled voltage levels of VREF/4,
VREF/8 until all n output bits are chosen. Based on each
comparison results, the synchronous controller determines
the configuration word (Cconf in Fig. 2) needed to configure
the comparator threshold for the next comparison.
The threshold-configurable comparator in Fig. 3 is a
modified version of the dynamic circuit we already used in
[2], where differently from the SAR design proposed in this
letter, a DAC is needed in the feedback loop to create
thresholds for comparison. When the/GO signal in Fig. 3 is
low, the PMOS input pair converts its input voltage into a
current that turns on the back-to-back pair of CMOS
inverters to a metastable region, after which any imbalance
caused by the input signal is amplified to a full-scale signal.
When the/GO input is high, the comparator is reset. A
capacitance imbalance on the nodes Za, Zb and Oa, Ob
determines a threshold shift DVth , which for the target midrange ADC resolutions is first-order proportional to the
input device overdrive voltage and to the relative capaciVgs Vt DC
tance unbalance DC/C: DVth 
C.
2
Digitally controlled variable capacitors, implemented
through binary-weighted arrays of small PMOS transistors,
are added to create such imbalance and implement the
threshold configuring mechanism. Particularly in Fig. 3
Ccoarse binary-weighted arrays of n - 1 PMOS connected
to nodes Oa, Ob allow for a coarse-grained threshold setting
while Cfine arrays of equal-sized PMOS transistors at nodes
Za, Zb determine a finer threshold tuning.
After each conversion step, depending on the SAR controller decision, the Ccoarse and Cfine capacitors in Fig. 3 are
sequentially activated, through the multibit signal named
Cconf in Fig. 2, to generate the closest threshold to a given
input. PMOS capacitors are active high, i.e. the digital
control signals should be set to 1 (Vdd) to enable them.
To overcome PVT (process voltage temperature) variability problems each of the n - 1 binary-scaled main
PMOS varactors (Ccoarse in Fig. 3), employed for generating
the thresholds, can be calibrated independently from the
others through an auxiliary array of basic PMOS capacitors

Analog Integr Circ Sig Process (2011) 67:103107

105

Fig. 3 Schematic of the

threshold configurable dynamic
comparator

disposed in parallel. Figure 4 shows the use of auxiliary

PMOS capacitors for calibration of the first element of the
Ccoarse array of Fig. 3. Configuration bits Thr-cal, accessible
off-chip, control these auxiliary tuning PMOS arrays. During the layout design, to reduce sensitivity to mismatches, all
threshold configuration elements are split into smaller units
disposed using a common centroid technique.
The same imbalance concept is used also for comparator
offset compensation. To this aim Coff arrays of binaryscaled n - 1 PMOS transistors are connected to nodes Oa,
Ob in Fig. 3: the offset compensation PMOS-based
capacitors can be configured using the Off-cal signal in
Fig. 2, accessible off-chip from the ADC user.
Summarizing, the Cconf signal internally generated by
the SAR controller determines at each clock cycle the
configuration of Ccoarse and Cfine PMOS capacitor arrays
while the signals Off-cal and Thr-cal provided off-chip

from the ADC user can be used to calibrate the offset and
the thresholds of the new comparator.
To be noted that differently from this work, in [2]
PMOS capacitors are used only for comparator offset
compensation but not for threshold configuration or calibration. Thus in [2] the use of a DAC in the feedback loop
is mandatory to create thresholds for comparison. With
respect to the scheme in Fig. 2, to reduce the pin count in
the real implemented SAR channel in Sect. 4, the Off-cal
and Thr-cal data are loaded through a serial line in a Serialinput-parallel-output shift register.

3 ADC array performance

Following a design exploration approach similar to [2] (i.e.
adopting top-down architectural simulations annotated

Fig. 4 Threshold calibration

system

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Analog Integr Circ Sig Process (2011) 67:103107

bottom-up with real silicon implementation data of the

building circuits in the 90 nm CMOS technology), the performance of the ADC array has been investigated versus the
number of channels. In this phase we have taken into account
different mismatch sources (offset, gain, bandwidth, timing
skew) and performance metrics (speed, ENOB, power consumption). Since one T/H ? SAR ADC channel takes n ? 1
cycles for n bits then we considered an array size S = n ? 1.
As result of the design space exploration activity Fig. 5
reports the ENOB (Effective Number Of Bits) and the resolution versus the array size S. From the simulation results in
Fig. 5 it is clear that using more than 8 parallel elements turn
into a waste of power and area since ENOB is limited by array
mismatch effects. Figure 5 considers the following mismatch
cost budgets that have been fully met during the layout design
and silicon implementation phases (hence simulations in
Fig. 5 are compliant with measurements in Sect. 4 and
Table 1): offset mismatch ro \ 0.1 LSB, gain mismatch
rg/G \ 1%, clock time skew \ 0.5%, bandwidth mismatch
rbw \ 7%. In the target 90 nm CMOS technology the
threshold configuring dynamic comparator and the synchronous TSPC SAR controller can resolve 1 bit in less than 1 ns.
Hence the implemented array has been sized for 8 channels
thus allowing 7-bit nominal resolution with sampling rate
Fs = 1 GS/s in TI mode. To sustain such rate also the mux/
8
ENOB

Resolution

bits

6
5
4
3
5

Array size S

Fig. 5 ENOB and resolution versus array size

demux circuitry in Fig. 1 has been sized to reach 1 GHz. The

sample-rate of a single ADC channel is 125 MS/s, making it
suitable also for high-speed xDSL communications [18].

4 CMOS implementation results and state-of-art

comparison
The new SAR ADC channel and the whole 8-channel ADC
array have been implemented in 90 nm 1P9M 1 V CMOS
technology. The performance parameters of the whole ADC
array are reported in Table 1 and compared to state-of-art
arrays of SAR ADC. The proposed array of threshold-configuring SAR ADCs is configurable in TI mode to reach 1 GS/s or
in parallel mode to serve multiple inputs, up to 8, at 125 MS/s.
In TI mode the whole array has a throughput up to 1 GS/s
with an ENOB of 5.71 bits at Nyquist-rate, i.e. with an
input signal frequency Fin up to 500 MHz. The power
consumption is 6.8 mW, about 2/3 due to comparators and
T/H units and 1/3 due to digital control, muxing and calibration circuitry. Due to the dynamic nature of the adopted
circuits, the power consumption linearly scales with clock
frequency. The chip area of the whole ADC array,
excluding pads, is 0.4 mm2. The figure of merit (FOM),
evaluated as Power/(Fs * 2ENOB), amounts to 0.13 pJ/
conversion-step being Fs = 1 GHz and the ENOB evaluated at Nyquist-rate, i.e. Fin = is/2.
Table 1 reports a comparison of the proposed ADC array,
configured in TI mode, with known TI SAR converters realized in different CMOS technologies to reach sampling rates
of hundreds of MS/s. With respect to state-of-the-art TI
ADC arrays in 90 nm CMOS technology [24] our design,
see Table 1, achieves better FOM with similar speed
performance.
Compared to the single SAR ADC in [1] our array
achieves in TI mode a throughput higher by a factor 20 and

Table 1 Performance of the ADC array (TI mode) in 90 nm 1 V CMOS and comparison with state-of-art TI SAR ADC
Process

Array size

ENOB

Speed (GS/s)

Power (mW)

FOM (pJ/conv)

Our

90 nm 1 V

5.71

6.8

0.13

[1]

90 nm 1 V/0.7 V

0.05

0.24

0.15

[2]
[3]

90 nm 1 V
90 nm 1.2 V

8
7

5.8
5.6

1
1.2

8.2
16
10

0.15
0.27

[4]

90 nm 1 V

5.1

0.6

[5]

65 nm 1.2 V

4.04

0.5

5.93

0.72

0.49

[6]

65 nm 0.8 V/1.2 V

42 (6 redundant)

4.42

0.25

1.2

0.22

[7]

180 nm 1.2 V/1.8 V

3.66

0.5

7.8

1.1

[14]

65 nm 1.2 V

5.71

0.8

13.59

0.32

[15]

180 nm 1.8 V

3.65

0.5

17.6

2.8

[16]

130 nm 1.2 V

5.3

0.6

5.3

0.22

[17]

0.5 lm 3 V

10

5 (nominal)

0.6

28.5

N/A

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Analog Integr Circ Sig Process (2011) 67:103107

better FOM and ENOB performances. Obviously, being

optimized for speed, our ADC array has a larger area and
power consumption than [1]: 0.4 mm2 and 6.8 mW for our
work versus 0.006 mm2 and 0.24 mW for [1]. Moreover
[1], but also [6, 7], need extra DC/DC converter being
based on dual voltage supplies.
With respect to 65 nm CMOS TI SAR designs in Table 1
[5, 6] our ADC array in 90 nm CMOS has a higher power
consumption but achieves better performances in terms of
speed, ENOB and FOM. Considering the above metric, our
ADC array outperforms also CMOS TI SAR designs realized in older technologies, see [7, 1517] in Table 1.
5 Conclusion
This letter proposed an array of low-complex SAR ADCs
which is configurable in time-interleaved (TI) mode to reach 1
GS/s sample-rate or in parallel mode to serve multiple inputs,
up to 8, each at 125 MS/s. A novel ADC SAR channel design
is presented based on three main circuital solutions: (1) a
threshold-configuring scheme, to avoid internal DAC thus
saving circuit complexity versus state-of-the-art designs; (2) a
TSPC circuitry to reach fast SAR logic decisions; (3) a
dynamic comparator with digitally controlled variable
capacitors. Proper sizing of the ADC array has been done
considering array mismatches. Implementation results in
90 nm 1 V CMOS technology are presented and compared to
the state of the art proving how the proposed ADC design
achieves better FOM with similar speed performances.
Acknowledgment Discussions with Dr. P. Nuzzo from University
of California at Berkeley, Dr. C. Nani from Philips are gratefully
acknowledged.

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Sergio Saponara got the Master of Science, cum laude, and

the Ph.D. degrees in Electronic
Engineering from the University
of Pisa in 1999 and 2003
respectively. In 2002 he was
with IMEC, Leuven (B), as
Marie Curie Research Fellow.
Since 2001 he collaborates with
Consorzio Pisa Ricerche in Pisa.
He is senior researcher at University of Pisa in the field of
electronic circuits and systems.
He holds the chair of electronic
systems for automotive and
automation at the Faculty of Engineering. He co-authored more than
130 scientific publications and holds 5 patents. Sergio Saponara is
also research associate of CNIT and INFN and served as guest editor
of special issues on international journals and as program committee
member of international conferences.

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