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e-ISSN: 2455-5703
I 2Mythili. R
1,2
Research Scholar
1
Department of Information and Communication Engineering 2Department of Electronics and
Communication Engineering
1,2
KIT-Kalaignarkarunanidhi Institute of Technology, Coimbatore-641 402
Abstract
The Content addressable Memory (CAM) is high speed memories that are used in high speed networks, lookup tables and so on.
The data to be searched will be compared with the data stored in the CAM cell and the address of the cell will be returned for the
matched data. The parallel search operation in the memory is the important feature which improves the speed of search
operation in CAM cells. However this parallel search operation will have its impact on the power dissipation, delay and various
other parameters. This paper discusses the various low power CAM cells and analysis of its important parameters.
Keyword- XOR cell, XNOR cell
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I. INTRODUCTION
Most of the memory devices store and retrieve data with respect to memory location address in specific. In Content Addressable
Memory the data to be accessed is identified by its content instead of memory location. Therefore the time required to identify
the data is greatly reduced. The CAM may be either binary or ternary CAM based on the values stored. The binary CAM stores
either 0 or 1 whereas ternary CAM stores a dont care value x in addition and it causes a match regardless of the input bit. In
a conventional CAM cell [1][3] the data will be written into the cells during the write operation (i.e. WL=1) using the bit line BL
and its complement ~BL. During search operation (i.e. WL=0) the search bits are compared with the stored bits of data in each
CAM cell. If the bits in the search line are same as the content of the CAM cell then the match line will be high (i.e. ML=1) or
else it will be low (i.e. ML=0
The basic CAM cell operation is discussed in section II. In section III NAND, NOR and XOR cells are explained in
detail. In section IV the parameters are compared and the conclusion is provided in section V.
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The bit lines and search lines are used together in many CAM cells so that the complexity of interconnection will be
less. The Fig. 1 shows how the cells are interconnected to the match line, search line and bit line. During write operation it acts
asbitlines whereas in search operation it acts as search lines. The sense amplifiers are feed through the match lines from each
cell.
The match lines are recharged high so that they are temporarily in match state. If there is any match in the bits they
remain high and incase of at least one cell mismatch match lines become low by discharging them.
The stored bit and its complementary stored bit are compared with the searchline bits SL and its complement. As shown
in Fig. 2. M1, M2, M3 and M4 are used for the comparison operation which leads to pull down path as dynamic XNOR. Both
M1, M3 pair and M2, M4 pair will be disconnected from ground during the match condition so that there wont be any pulldown
path. During mismatch atleast one of the path will be pulled down as a result the matchline will be low.
B. NAND Type Cell
The three transistors M1, MD and ~MD are used for the comparing the stored bit with the search bit. M1 will be ON incase of
match or else it will be OFF. The M1 transistor is used as the pass transistor. The nMOS connected in series will provide the
NAND [3] operation. If every cell has high ML then the match is obtained.
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Here only two transistors M1 and M2 are used to obtain the comparison between the stored bits and bit to be searched.
When match is obtained the output of the comparator circuit is low and for mismatch the output will be high. During mismatch
M1 and M2 will conduct to provide high output. The outputs of the XOR [3][4] comparator CAM as shown in Fig. 4 are
connected to nMOS in parallel along with the prechargedmatchlines. The XOR CAM cell has important application in networks
for packet forwarding.
D. XOR Using Transmission Gates
The operation is same as the XOR type CAM where the transmission gates used for the comparison operation instead of pass
transistors. The entire voltage range can be made to pass using transmission gates. The switching voltage determines the
transition resistance and the voltage will not loss. If the stored bit value is 0 then TG1 will be ON and for the bit value of 1 then
TG2 will be ON. If the match is found then the out from anyone of the transmission gate will be high.
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The XNOR gate operation similar to the operation of the XOR gate but reverse in its function. During the search
operation the data in the bitline will be compared with the stored bit q. If both q and the value in the bitline are 0 then the nMOS
connected to the ~bl will be ON and for 1 the nMOS connected to bl will be ON and the output will be high for match. Incase of
mismatch both the transistor M2 and M8 will be off and the matchline will be low.
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V. CONCLUSION
CAM is defined as a functional memory with a large amount of bits stored that simultaneously compares the input search bits
with the stored bits. The speed at which the data to be searched is also more. From the experimental results it is clear that XNOR
cell have less power dissipation when compared with other CAM cells. The delay is less in XOR cell so that they are often used
in router memories. The power estimation is made using EDA tool with 180nm technology and the operating voltage is 1.8V.
REFERENCES
[1] Byung-Do Yang and Lee-Sup Kim, A Low-Power CAM Using Pulsed neither NANDNOR Match-Line and ChargeRecycling Search-Line Driver, IEEE journal of solid-state circuits, vol. 40, no. 8, pp. 1736 1744, August 2005.
[2] Jian-weizhang, Yi-zheng ye, and bin-da liu, a current-recycling technique for shadow-match-line sensing in contentaddressable memories, IEEE transactions on very large scale integration (vlsi) systems, vol. 16, no. 6, pp. 677 - 682, June
2008.
[3] Kostas pagiamtzis, Content Addressable Memory circuits and architectures: A tutorial and survey, IEEE journal of solid
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