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ISSN 2321-8665
Vol.04,Issue.14,
October-2016,
Pages:2603-2606

Low Power Square and Cube Architectures using Vedic Sutras

GAJJI LAVANYA1, CH. VENKATESWARA RAO2, RAJAIAH GABBETA3
1

PG Scholar, Abdulkalam Institute of Technological Sciences, Kothagudem, Telangana, India.

Assistant Professor, Abdulkalam Institute of Technological Sciences, Kothagudem, Telangana, India.
3
Professor, Abdulkalam Institute of Technological Sciences, Kothagudem, Telangana, India.

Abstract: In this paper low power square and cube

architectures are proposed using Vedic sutras. Low power and
less area square and cube architectures uses Dwandwa yoga
Duplex combination properties of Urdhva Tiryagbhyam sutra
and Anurupyena sutra of Vedic mathematics. Simulation
results for 8-bit square and 8-bit cube shows that proposed
architectures lowers the total power consumption by 45% and
area by 63% when compared to the conventional architecture.
Also the reduction in power consumption increases with the
increase in bit width Comparison is made between
conventional and Vedic method implementations of square
and cube architecture. Implementation results show a
significant improvement in terms of area, power and delay.
Proposed square and cube architectures can be used for high
speed and low power applications. Synthesis is done on Xilinx
FPGA Device using, Xilinx Family: Spartan 3E, Speed Grade:
- 4. Propagation delay of the proposed 8-bit square is 4ns and
area consumed in terms of slices is 22 and for 8-bit cube
propagation delay is 7.72ns and area consumed in terms of
slices is 58. Dynamic power estimation for square and cube
are 13mW and 16mW respectively.
Keywords:FPGA, Spartan3E, VedicMathematics Simulation.
I. INTRODUCTION
Vedic Mathematics hails from the ancient Indian scriptures
called Vedas or the source of knowledge. This system of
computation covers all forms of mathematics, be it geometry,
trigonometry or algebra. The striking feature of Vedic
Mathematics is the coherence in its algorithms which are
designed the way our mind naturally works. This makes it the
easiest and fastest way to perform any mathematical
calculation mentally. Vedic Mathematics is believed to be
created around 1500 BC and was rediscovered between 1911
to 1918 by Sri Bharti Krishna Tirthaji (1884-1960) who was a
Sanskrit scholar, mathematician and a philosopher. He
organized and classified the whole of Vedic Mathematics into
16 formulae or also called as sutras. These formulae form the
backbone of Vedic mathematics. Great amount of research
has been done all these years to implement algorithms of
Vedic mathematics on digital processors. It has been observed
that due to coherence and symmetry in these algorithms it can
have a regular silicon layout and consume less area along
with lower power consumption. Normally signal processing
algorithms are developed using high level languages like C or

Matlab using floating point number representations. The

algorithm to architecture mapping using floating point number
representation consumes more hardware which tends to be
expensive. Fixed point number representation is a good option
to implement at silicon level.
Hence our focus in this work is to develop optimized
hardware modules for multiplication operation which is one
of the most frequently used operation in signal processing
applications like Fourier transforms, FIR and IIR filters,
image processing systems, seismic signal processing, optical
signal processing etc. Any attempt to come out with an
optimized architecture for this basic block is advantageous
during the product development stages. Considering fixed
point representation, 16 bit Q15 format and 32 bit Q31 format
provide required precision for most of the digital signal
processing applications and its best suited for implementation
on processors. The advantage it provides over floating point
multipliers is in the fact that Q format fraction multiplications
can be carried out using integer multipliers which are faster
and consume less die area. DSP Processors like TMS320
series from Texas Instruments work on 16 bit Q15 format. In
this paper we propose the implementation of fixed point Qformat high speed multiplier using Urdhava Tiryakbhyam
method of Vedic mathematics. Further we have also
implemented multipliers using normal booth algorithm and
Xilinx parallel multiplier Intellectual Property and presented a
comparative study on maximum frequency or speed of these
multipliers.
II.ALGORITHM IMPLEMENTATION
A. Urdhava Tiryakbhyam Method
Urdhava Tiryakbhyam is a Sanskrit word which means
vertically and crosswire in English. The method is a general
multiplicationformula applicable to all cases of multiplication.
It is based on a novel concept through which all partial
products are generated concurrently. Fig. 2 demonstrates a 4
x 4 binary multiplication using this method. The method can
be generalized for any N x N bit multiplication. This type of
multiplier is independent of the clock frequency of the
processor because the partial products and their sums are
calculated in parallel. The net advantage is that it reduces the
need of microprocessors to operate at increasingly higher
clock frequencies. As the operating frequency of a processor
increases the number of switching instances also increases.
This results in more power consumption and also dissipation

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GAJJI LAVANYA, CH. VENKATESWARA RAO, RAJAIAH GABBETA

in the form of heat which results in higher device operating
order to calculate the square of a number Duplex D property
temperatures. Another advantage of Urdhva Tiryakbhyam
of Urdhva Tiryagbhyam is used. In the Duplex, take twice the
multiplier is its scalability. The processing power can easily
product of the outermost pair, and then add twice the product
be increased by increasing the input and output data bus
of the next outermost pair, and so on till no pairs are left.
widths since it has a regular structure .Due to its regular
When there are odd number of bits in the original sequence
structure, it can be easily layout in a silicon chip and also
there is one bit left by itself in the middle, and this enters as
consumes optimum area .As the number of input bits
its square. Thus for 987654321, D= 2 * ( 9 * 1)+2 * (8 * 2)+2
increase, gate delay and area increase very slowly as
* ( 7 * 3)+ 2 * ( 6 * 4)+ 5 * 5=165. Further, the Duplex can be
compared to other multipliers.
explained as follows
For a 1 bit number D is its square.
For a 2 bit number D is twice their product
For a 3 bit number D is twice the product of the outer pair +
the square of the middle bit.
For a 4 bit number D is twice the product of the outer pair +
twice the product of the inner pair.
Thus D (1) = 1 * 1;
D (11) =2 * 1 * 1;
D (101) =2 * 1 * 1+0 * 0;
D (1011) =2 * 1 * 1+2 * 1 * 0;
The Vedic square has all the advantages of the Vedic
multiplier. Further, it is quite faster and smaller than the array,
Booth and proposed Vedic multiplier.
Fig1.
Therefore Urdhava Tiryak-bhyam multiplier is time, space
and power efficient. The line diagram in fig1 illustrates the
algorithm for multiplying two 4-bit binary numbers a3a2a1a0
and b3b2b1b0 The procedure is divided into 7 steps and each
step generates partial products. Initially as shown in step 1 of
fig. 1, the least significant bit (LSB) of the multiplier is
multiplied with least significant bit of the multiplicand
(vertical multiplication). This result forms the LSB of the
product. In step 2 next higher bit of the multiplier is
multiplied with the LSB of the multiplicand and the LSB of
the multiplier is multiplied with the next higher bit of the
multiplicand (crosswire multiplication). These two partial
products are added and the LSB of the sum is the next higher
bit of the final product and the remaining bits are carried to
the next step. For example, if in some intermediate step, we
get the result as 1101, then 1 will act as the result bit(referred
as rn) and 110 as the carry (referred as cn). Therefore cn may
be a multi-bit number. Similarly other steps are carried out as
indicated by the line diagram. The important feature is that all
the partial products and their sums for every step can be
calculated in parallel.
III. SQUARE ARCHITECTURE
Square Architecture using dwandwa yoga property of
urdhvatiryagbhyam sutra [11, 13]. Yavadunam Sutra is used
for Squaring , is limited to the number which are near the base
10,100 etc., The Ekadhikena Purvena Sutra is used for
Squaring, is limited to number which ends with digit 5 only.
The other method Dwandwa Yoga or Duplex is used in two
different senses. The first one is by squaring and the second
one is by cross multiplication. It is used in both the senses. In

Fig2. 8-bit Vedic Square Algorithm.

IV. CUBE ARCHITECTURE
Yavadunam Sutra can be applied for cubing too. The only
difference is tha, take here not the deficit or the surplus but
exactly twice the deficit or the surplus as the case. Again this
sutra is limited to the number which is near base i.e., 10,100
etc., Cubing of 2-digit numbers can also be performed using
another sutra called Anurupyena Sutra [10-11]. To use this,
follow the procedure below:
1. Put down the cube of the left digit of the number to be
cubed as the left most number in a row of 4 numbers.

International Journal of Innovative Technologies

Volume.04, Issue No.14, October-2016, Pages: 2603-2606

Low Power Square and Cube Architectures using Vedic Sutras

2. Put down the square of the left digit multiplied by the
V. RESULT
right digit as the second number in the same row of
numbers
3. Put down the square of the right digit multiplied by the
left digit as the third number in the same row of numbers
4. Put down the cube of the right digit as the right most
number in this row of numbers
5. Under the second number in the row above, put down
twice the second number
6. Similarly, under the third number in the first row, put
down twice the third number
7. Add them up, making sure to carry over excess digits
from right to left. That is the final answer.

Fig4. Simulation waveform of 8-bit square design.

Fig5. Simulation waveform of 8bit cube design.

Fig3. 8-bit Vedic Cube Algorithm.
Note that the first row can also be expressed as writing the
numbers from the cube of the first digit to the cube of the
second digit such that the numbers in between form the same
ratio with respect to each other. In other words, the numbers
in the first row are in geometric progression from the cube of
the first digit to the cube of the second digit. In fact the
constant ratio of the geometric progression is the same as the
ratio between the first and second digits of the number to be
cubed. Also note that the procedure above is a direct result of
the algebraic identity that (a + b)3 = a3 + 3a2b + 3ab2 + b3.
The first line contains the terms a3, a2b, ab2 and b3. The
second row contains the remaining 2a2b and 2ab2 (double of
the middle two terms of the first row). To illustrate, let us
work through some simple Note the carryovers carefully in
the example above. From the right most columns, 12 are
carried over to the left. This gets added to 150, giving 162, of
which 2 remains and 16 is carried over further to the left. This
gets added to 60, giving 76. 6 remains and 7 are carried over
to the left-most column, giving the final sum of 15. Each
column should consist of one digit, with all the excess digits
carried over to the left until the left-most column, which
obviously will not have any carryover out of it.

VI. CONCLUSION
Due to its regular and parallel structure it can be concluded
that Vedic Square and cube are faster than conventional
square and cube. Due to factors of timing efficiency, speed,
low power and less area the proposed Vedic square and cube
can be implemented in Arithmetic and Logical Units replacing
the traditional square and cube circuits. It is demonstrated that
this design is quite efficient in terms of area, speed & low
power. Squaring of binary numbers of bit size other than
powers of 2 can also be realized easily. For example, squaring
of a 24-bit binary number can be found by using 32- bit
squaring circuit with 8 MSBs (of inputs) as zero. The idea
proposed here may set path for future research in this
direction. Future scope of research is to reduce area
requirements.
VII. REFERENCES
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International Journal of Innovative Technologies

Volume.04, Issue No.14, October-2016, Pages: 2603-2606

GAJJI LAVANYA, CH. VENKATESWARA RAO, RAJAIAH GABBETA

Mathematics," in Proceedings IEEE International SoC Design
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in Abdulkalam Institute of Technology. Her
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International Journal of Innovative Technologies

Volume.04, Issue No.14, October-2016, Pages: 2603-2606