CSE404

Digital Systems Design Sessional

Design of 4-bit Arithmetic &

Logic Unit (ALU)

Section
Group No.
Writers Roll
Writers Name
Group Members

B1
03
1205016
Rashid Abid Rafi
1205016
1205026
1205028
1205034

Date of Submission:

1205052
04 October 2016

Introduction:
An arithmetic and logic unit (ALU) is a multi-operation, combinational-logic digital
function. It can perform a set of basic arithmetic instructions and a set of logic
operations. The ALU has a number of selection lines to select a particular
operation in the unit.
The design of a typical ALU is carried out in three stages:
i)
ii)
iii)

Firstly, the design of arithmetic section is undertaken.

Secondly, the design of the logic selection will be considered.
Finally, the arithmetic section is modified in a way that it can perform
both arithmetic and logic operations.

Problem Specification:
Required Flags:
Carry
Sign
Overflow
Zero

Design and Implementation Issues:

All outputs and flag status must be directed to LED.
Flags will be affected as per the rules of Assembly Language.
Any SSI (AND, OR, NOT, XOR etc.) and MSI (MUX, Decoder, Adder etc.) chip can
be used.
Emphasis should be given on efficiency of design and minimization of ICs used.
Late submission will result in reduced marking.
For simulation you can use any software (like Proteus).
While demonstration you must bring your group specification.

Block Diagram:

cs2
Cout

cs1
cs0

Assigned Operations:
cin
cs2

cs1

cs0

Functions for
Group 3

Transfer A

Increment A

Subtract with borrow

Subtract

OR

AND

Boolean Function Formulation:

From problem specification we can see that,
when cs1=0, Operations: Transfer, Increment, Subtract with Borrow, Subtract
(Arithmetic Operations)
when cs1=1, Operations: OR, AND (Logical Operations)
so, clearly cs1 is the mode selection bit between arithmetic & logical operations.
Lets design this ALU for 1 bit.
Xi

Yi

cs2
1 bit Full Adder

Fi

cs1
cs0

i)

So, for arithmetic operations:

cs1

cs2

cs0

Xi

Yi

cin

Operations

Transfer

INC

SWB

Sub

So, for arithmetic operations,

Xi = CS1. Ai
Yi = CS1.CS2. B

ii)

And, for Logical Operations:

cs1

cs2

cs0

Yi
0
Bi

Xi
Ai +Bi
Ai +Bi

Xi = CS1 (Ai+ CS2Bi + CS2Bi) = CS1.Ai + CS1.(CS2 Bi)

Yi = CS1.CS2.B + CS1.CS2. 0 = CS1.CS2.B

iii)

So, combining Arithmetic & Logic Operations, we get:

Xi = CS1. Ai + CS1.Ai + CS1.(CS2 Bi) = Ai + CS1.(CS2 Bi)

Yi = CS1.CS2. B+ CS1.CS2.B = CS2.B

So, the ultimate boolean function for 1 bit ALU is:

Xi = Ai + CS1.(CS2 Bi)
Yi = CS2.B

Flag Register:
S= F4
Z= (F1+F2+F3+F4)
C= Cout
V= ?

Operations
OR
AND

In order to determine V flag, we need to calculate C4 (outmost carry) and Cin4

(input carry at the MSB). But if we use a 4 bit Full Adder, we cannot have the input carry.
For this reason, the whole design is implemented carefully in a different approach.

A4 i A3 i A2 i A1 i
B4 0 B3 0 B2 0 B1 0
(+)
F4 d4 F3 d3 F2 d2 F1 d1
i = input dummy. i = 1 in case of arithmetic operations and i=0 in logical
operations.
d = output dummy.
So,
V= F4 d4, as d4 indicates there has been an input carry propagation to MSB.

4 bit Full Adder

4 bit Full Adder

Complete Circuit Diagram:

The whole ALU was simulated in Proteus (isis) software. The full circuit design is
attached herewith.

IC Count:
1)
2)
3)
4)
5)

AND Gate (7408) : 2

OR Gate (7432) : 2
XOR Gate (7486) : 2
NOT Gate (7404) : 1
4bit Full Adder (7483) : 2

Discussion:
1) The whole design is implemented with two 4 bit full adders. This could have
been done with one 4 bit full adder if we stated overflow flag (V) in a
different manner.
If V was computed with only sign bits (as only same signs can produce
overflow), this could have been done with only 4 bit full adder.
2) In many cases, the ICs are defective and could produce erroneous result if
not tested properly.
3) The wires can be defective too.
4) The LEDs used to show the output might be defective and could operate on
floating voltage and lighten up erroneously.
5) IC counts were minimized to make the circuit design optimal in the sense of
circuitry and power consumption.
6) The whole circuit should be implemented very very carefully.

U8:A
1

3
2
74LS86

U1:A
1
3

2
74LS32

U1:B
4

U3

6
5

A4

10
8
3
1

74LS32

U1:C

A3

11
7
4
16

10

A2

74LS32

13

U1:D
12

A1

A1
A2
A3
A4

S1
S2
S3
S4

9
6
2
15

F4

B1
B2
B3
B4
C0

F3

?
C4

14

F2

74LS83

11
13

74LS32

F1

U2:A
1

U8:B

1
3

3
2

74LS86

B3

U2:B
4

B2

6
5

11
7
4
16

74LS86

7408

U2:C

U5:C

9
8

U6:B

U4
10
8
3
1

U5:B
6

13

10

A1
A2
A3
A4

S1
S2
S3
S4

9
6
2
15

U9:A

8
3

74LS32
14

CS1

U5:D
11
6
7408

U7:A

CS0

U6:C

1
3
6

2
7408

74LS04

U7:B
4

U6:D
13

6
5
12
7408

74LS04

U7:C
9

U6:E
11

8
10
10
7408

74LS04

U6:F
9

U7:D
8

12
11

74LS04

13
7408

74LS04

?
74LS32

13

74LS32
C4

U9:B

74LS86

12

10

7408

13

CS2

U6:A

12
11

U9:C

74LS04

74LS83

10

74LS86

B1
B2
B3
B4
C0

74LS86

U2:D

6
7408

B4

B1

U5:A