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EC 2257-ELECTRONICS CIRCUITS II AND SIMULATION LAB MANUAL
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II YEAR
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EC 2257-ELECTRONICS CIRCUITS II AND SIMULATION LAB MANUAL
II YEAR
Preface
This laboratory manual is prepared by the Department of Electronics and communication
engineering for Electronics Circuits II and Simulation Lab (EC 2257). This lab manual can be used
as instructional book for students, staff and instructors to assist in performing and understanding the
experiments. In the first part of the manual, experiments as per syllabus are described and in the
second part of the manual, experiments that are beyond the syllabus but expected for university
laboratory examination are displayed. This manual will be available in electronic form from
Acknowledgement
We would like to express our profound gratitude and deep regards to the support offered
by the Chairman Shri. A.Srinivasan. We also take this opportunity to express a deep sense of
gratitude to our Principal Dr.B.Karthikeyan,M.E, Ph.D, for his valuable information and
guidance, which helped us in completing this task through various stages. We extend our hearty
thanks to our head of the department Prof.B. Revathi @ Ponmozhi, M.E, (Ph.D), for her
constant encouragement and constructive comments.
Finally the valuable comments from fellow faculty and assistance provided by
the
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II YEAR
CONTENTS
S.No
TOPIC
PAGE
NO
4
5
1. System Requirements
2. Syllabus
3. List of Experiments
Design and Analysis of Current Series Feedback Amplifier
1
2
Design and Analysis of Voltage Shunt Feedback Amplifier
Design and Analysis of RC phase shift Oscillator
3
4
Design and Analysis of Wein Bridge Oscillator
5
Design and Analysis of Hartley Oscillator
6
Design and Analysis of Colpitts Oscillator
Design and Analysis of Class-C Tuned Amplifier
7
Design and Analysis of Collector coupled Astable Multivibrator
8
Design and Analysis of Monostable Multivibrator
9
10 Design and Analysis of Bistable Multivibrator
11 Design and Analysis of Wave Shaping Circuits.
12 Simulation of Differential Amplifier.
6
12
18
23
27
32
36
41
45
49
53
66
13
14
15
69
74
77
16
80
17
85
18
88
19
91
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II YEAR
1. SYSTEM REQUIREMENTS
HARDWARE REQUIREMENTS
Processors
RAM
256 MB or Higher
Hard Disk
20 GB or Higher
Operating System
Windows 2000/XP/NT
SOFTWARE REQUIREMENTS
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II YEAR
SYLLABUS
Quantity Required
8
4
6
6
2
6
1
6
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Remarks
(0-30V)
+ / - 12V
30MHZ
Digital
Analog
1 MHz
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EX NO: 01
DATE :
II YEAR
Aim:
To design and test the current-series feedback amplifier and to calculate the following
parameters with and without feedback.
1. Mid band gain.
2. Bandwidth and cut-off frequencies.
3. Input and output impedance.
Components & Equipment required:
S.NO
APPARATUS
RANGE
(0-30)V
1.
Power supply
2.
Function generator
3.
CRO
4.
Transistor
5.
Resistors
6.
Capacitors
7.
Connecting wires
(0-20M)Hz
QUANTITY
1
1
1
BC107
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II YEAR
Circuit diagram:
(i)
Without feedback:
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II YEAR
Theory: The current series feedback amplifier is characterized by having shunt sampling and
series mixing. In amplifiers, there is a sampling network, which samples the output and gives to
the feedback network. The feedback signal is mixed with input signal by either shunt or series
mixing technique. Due to shunt sampling the output resistance increases by a factor of D and
the input resistance is also increased by the same factor due to series mixing. This is basically
transconductance amplifier. Its input is voltage which is amplified as current.
Design:
(i)
Without feedback:
VCC = 12V;
IC = 1mA;
fL = 50Hz;
S = 2;
RL = 4.7K;
hfe = re = 26mV / IC = 26;
hie = hfe re = VCE= Vcc/2 (transistor Active) = VE = IERE = Vcc/10
Applying KVL to output loop, we get
VCC = ICRC + VCE + IERE
RC = ?
Since IB is very small when compare with IC,
IC IE
RE = VE / IE = ?
S = 1+ RB / RE = 2
RB = ?
VB = VCC R2 / (R1 + R2)
RB = R1 || R2
R1 = ?
R2 =?
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II YEAR
Co = 1 / (2f XCo) = ?
XCE = RE/10 = ?
CE = 1 / (2f XCE) ?
(ii)
Tabular column:
(i) Without feedback:
Vi=
S.No
Frequency (Hz)
Output Voltage
(V0) (volts)
Gain = V0/Vi
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Gain = 20
log(V0/Vi) (dB)
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(iii)
II YEAR
With feedback:
Vi=
S.No
Output Voltage
(V0) (volts)
Frequency (Hz)
Gain = V0/Vi
Gain = 20
log(V0/Vi) (dB)
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II YEAR
Result: Thus the current series feedback amplifier is designed and constructed and the following
parameters are calculated.
Theoretical
With feedback
Without
feedback
Practical
With feedback
Without
feedback
Input
impedance
Output
impedance
Gain
(midband)
Bandwidth
1. Define feedback?
A portion of the output signal is taken from the output of the amplifier and is
combined with the normal input signal. This is known as feedback.
2. Define positive feedback?
If the feedback signal is in phase with input signal, then the net effect of the
feedback will increase the input signal given to the amplifier. This type of feedback is
said to be positive or regenerative feedback.
3. Define negative feedback?
If the feedback signal is out of phase with the input signal then the input
voltage applied to the basic amplifier is decreased and correspondingly the output is
decreased. This type of feedback is known as negative or degenerative feedback.
4. Define sensitivity?
Sensitivity is defined as the ratio of percentage change in voltage gain with
feedback to the percentage change in voltage gain without feedback.
5. What are the types of feedback? i. Voltage-series feedback ii. Voltage-shunt series
iii.Current- series feedback
iv.Current-shunt feedback
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EX NO: 02
II YEAR
DATE :
AMPLIFIER
Aim:
To design and test the voltage-shunt feedback amplifier and to calculate the following
parameters with and without feedback.
S.NO
1.
2.
3.
4.
5.
6.
7.
APPARATUS
Power supply
RANGE
(0-30)V
Function generator
(0-20M)Hz
CRO
Transistor
QUANTITY
1
1
1
BC107
Resistors
Capacitors
Connecting wires
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II YEAR
Circuit Diagram:
(i) Without Feedback:
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II YEAR
Theory:
In voltage shunt feedback amplifier, the feedback signal voltage is given to the base of
the transistor in shunt through the base resistor RB. This shunt connection tends to decrease the
input resistance and the voltage feedback tends to decrease the output resistance. In the circuit
RB appears directly across the input base terminal and output collector terminal. A part of output
is feedback to input through RB and increase in IC decreases IB. Thus negative feedback exists
in the circuit. So this circuit is also called voltage feedback bias circuit. This feedback amplifier
is known a transresistance amplifier. It amplifies the input current to required voltage levels. The
feedback path consists of a resistor and a capacitor.
Design
(i) Without Feedback:
VCC = 12V;
IC = 1mA;
AV = 30;
Rf = 2.5K;
S = 2;
hfe = ;
=1/ Rf = 0.0004
re = 26mV / IC = 26;
hie = hfe re =
VCE= Vcc/2 (transistor Active) =
VE = IERE = Vcc/10 =
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II YEAR
R2 =
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II YEAR
Tabular Column:
(i) Without Feedback:
Vi=10mV
Frequency (Hz)
Vo (Volts)
Gain = V0/Vi
Gain = 20
log(V0/Vi) (dB)
Frequency (Hz)
Vo (Volts)
Gain = V0/Vi
Gain = 20
log(V0/Vi) (dB)
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II YEAR
Result: Thus the voltage shunt feedback amplifier is designed and constructed and the following
parameters are calculated.
Theoretical
With feedback
Without
feedback
Practical
With feedback
Without
feedback
Input
impedance
Output
impedance
Gain
(midband)
Bandwidth
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II YEAR
EX NO: 03
DATE :
Aim: To design and construct a RC phase shift oscillator for the given frequency (f0).
Components & Equipment required:
S.NO
1.
2.
3.
4.
5.
6.
7.
APPARATUS
Power supply
RANGE
(0-30)V
Function generator
(0-20M)Hz
CRO
Transistor
QUANTITY
1
1
1
BC107
Resistors
Capacitors
Connecting wires
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II YEAR
Circuit Diagram:
Theory: In the RC phase shift oscillator, the required phase shift of 180 in the feedback loop
from the output to input is obtained by using R and C components, instead of tank circuit. Here a
common emitter amplifier is used in forward path followed by three sections of RC phase
network in the reverse path with the output of the last section being returned to the input of the
amplifier. The phase shift is given by each RC section =tan1 (1/rc). In practice R-value is
adjusted such that becomes 60. If the value of R and C are chosen such that the given
frequency for the phase shift of each RC section is 60. Therefore at a specific frequency the total
phase shift from base to transistors around circuit and back to base is exactly 360 or 0. Thus
the Barkhausen criterion for oscillation is satisfied
Design:
VCC = 12V; IC = 1mA; C = 0.01F; fo = ; S = 2; hfe =
re = 26mV / IC = 26;
hie = hfe re =
VCE= Vcc/2 (transistor Active) =
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II YEAR
VE = IERE = Vcc/10
Applying KVL to output loop, we get
VCC = ICRC + VCE + IERE
RC =
Since IB is very small when compare with IC,
IC IE
RE = VE / IE =
S = 1+ RB / RE = 2
RB = VB = VBE + VE =
VB = VCC R2 / (R1 + R2)
RB = R1 || R2
R1 =
R2 =
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II YEAR
CE = 1 / (2f XCE) =
Feedback Network:
f0 = ;
C = 0.01f;
R=
Procedure:
1. Connections are made as per the circuit diagram.
2. Switch on the power supply and observe the output on the CRO (sine wave).
3. Note down the practical frequency and compare with its theoretical frequency.
Model Graph:
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II YEAR
Tabular Column:
AMPLITUDE(V)
TIME(ms)
FREQUENCY(HZ)
Result: Thus RC phase shift oscillator is designed and constructed and the output sine wave
frequency is calculated as
Theoretical
Practical
Frequency
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II YEAR
EX NO: 04
DESIGN AND ANALYSIS OF WIEN BRIDGE OSCILLATOR
DATE :
Aim: To design a wien bridge oscillator and to draw its output waveform.
Components & Equipment required:
s.no
1
2
3
4
5
6
7
Range
IC741
2.88uF,0.01uF,0.08uF
15k,8.8k,12k,1.18k
-
Quantity
1
1
5
7
1
1
As
required
Theory:
The wein bridge oscillator is a standard circuit for generating low frequencies in the range of 10
Hz to about 1MHz.The method used for getting +ve feedback in wein bridge oscillator is to use
two stages of an RC-coupled amplifier. Since one stage of the RC-coupled amplifier introduces a
phase shift of 180 deg, two stages will introduces a phase shift of 360 deg. At the frequency of
oscillations f the +ve feedback network shown in fig makes the input & output in the phase. The
frequency of oscillations is given as f =1/2R1C1R2C2 In addition to the positive feedback
Design:
Select
appropriate
transistor
and
note
down
its
specification
such
as
in
the
active
region.Assume
Vcc,VceQ,IcQ,Vcc.
where
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II YEAR
R2=SXRE
Vcc[(R2/R1)+R2]=VRE +VBE(sat)
VR1+VR2=Vcc
Using the condition for sustained oscillation hfe>4k+23+29/k,where k=Rc/R. compute C
for designed desired frequency f1 using formula for frequency of oscillation.
F=1/2 1212
Compute Cin,Xcin<=Zin/10, where Xcin is the impedance offered by the coupling
capacitor for the frequency of interest and Zin is the input resistance at the transistor.Compute
CE,the impadance XCE<=RE/10.
Procedure:
1. Connections are made as per the circuit diagram
2. Feed the output of the oscillator to a C.R.O by making adjustments in the Potentiometer
connected in the +ve feedback loop, try to obtain a stable sine Wave.
3. Measure the time period of the waveform obtained on CRO. & calculate the Frequency of
oscillations.
4. Repeat the procedure for different values of capacitance
Circuit Diagram:
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II YEAR
design:
F=1/2RC
R=1/2FC
Given F=1KHZ
Assume, C=0.1F,
R=1.5k.
R3/R4=2.
Assume
R3=1k,R4= 500
R=R1=R2=1.5k
C=C1=C2=0.1F
Tabulation:
AMPLITUDE(V)
TIME(ms)
FREQUENCY(HZ)
Model Graph:
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II YEAR
Result:
Thus a Wien bridge oscillator is designed and the output waveform is drawn.
Theoretical
Practical
Frequency
1. Define Oscillator
A circuit with an active device is used to produce an alternating current is called
an oscillator circuit.
2. What is a tuned amplifier?
The amplifier with a circuit that is capable of amplifying a signal over a narrow band of
frequencies are called tuned amplifiers.
3. What happens to the circuit above and below resonance?
Above resonance the circuit acts as capacitive and below resonance the circuit acts as
inductive.
5. What is Q factor?
It is the ratio of reactance to resistance.
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II YEAR
EX NO: 05
DATE :
Aim: To design and construct the given oscillator for the given frequency (fO).
APPARATUS
Power supply
RANGE
(0-30)V
Function generator
(0-20M)Hz
CRO
QUANTITY
1
1
1
Transistor
BC107
Resistors
Capacitors
DIB
DCB
Connecting wires
Theory:
Hartley oscillator is a type of sine wave generator. The oscillator derives its initial output
from the noise signals present in the circuit. After considerable time, it gains strength and
thereby producing sustained oscillations. Hartley Oscillator have two major parts namely
amplifier part and feedback part. The amplifier part has a typically CE amplifier with voltage
divider bias. In the feedback path, there is a LCL network. The feedback network generally
provides a fraction of output as feedback.
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II YEAR
Circuit Diagram:
Design:
Given Specifications,
Vcc=12V, S=6, VRE=3V, hfe=300, fc=12kHz, VBE(sat)=0.7, IcQ=1.6mA.
Let L1=100uH, L1/L2=hfe, L2=?
i)VcEQ=Vcc/2=6V
ii)VRE=ICQ.RE=1.6x10 -3.RE=3
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RE=1.857k.
Vcc=VCEQ+ICQ (RC+RE)
12= 6+1.6x10 -3 (RC+1.875x10 3)
RC=1.875k
iii)R2=SxRE=11.25k
iv)Vcc(R2/(R1+R2)=VRE+VBE(sat)
R1=25.29k
L1/L2=hfe=300
Assume, L1=100H,
L2=0.33 H.
f=1/2 (1 + 2)
C=0.1753F.
CE=1/(2fcXcE)=0.0707 F.
Zin=R1||R2||hie=2.997k
Xcin=Zin/10
Cin=1/(2fcXcin)=0.0442 F.
Procedure:
1. Connections are made as per the circuit diagram.
2. Switch on the power supply and observe the output on the CRO (sine wave).
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II YEAR
3. Note down the practical frequency and compare with its theoretical frequency.
Model Graph:
Tabulation:
AMPLITUDE(V)
TIME(ms)
FREQUENCY(HZ)
Result: Thus Hartley oscillator is designed and constructed and the output sine wave frequency
is calculated as
Theoretical
Practical
Frequency
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II YEAR
EX NO: 06
DATE :
Aim: To design and construct the given oscillator at the given operating frequency.
APPARATUS
Power supply
RANGE
(0-30)V
Function generator
(0-20M)Hz
CRO
Transistor
QUANTITY
1
1
1
BC107
Resistors
Capacitors
DIB
DCB
Connecting wires
Theory:
A Colpitts oscillator is the electrical dual of a Hartley oscillator. In the Colpitts circuit,
two capacitors and one inductor determine the frequency of oscillation. The oscillator derives its
initial output from the noise signals present in the circuit. After considerable time, it gains
strength and thereby producing sustained oscillations. It has two major parts namely amplifier
part and feedback part. The amplifier part has a typically CE amplifier with voltage divider bias.
In the feedback path, there is a CLC network. The feedback network generally provides a
fraction of output as feedback.
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Circuit Diagram:
Design:
Vcc=8V, S=6, VRE=3V, hfe=300, fc=12kHz, VBE(sat)=0.7, IcQ=1.8mA.
Let L1=100uH,L1/L2=hfe,L2=?
i)VcEQ=Vcc/2
ii)Vcc=VcEQ+IcQ.RE,VRE=ICQ.RE=IE.RE
RE=VRE/VCQ
iii)R2=S.RE
iv)Vcc(R2/(R1+R2)=VRE+VBE(sat)
re=(26x10-3)/ICQ
R1=Vcc.R2/(R1+R2) -R2
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v)Cin=1/(2fcXcin);Xcin=Zin/10
Zin=R1||R2||hie
vi)CE=1/(2fcXcE)
XcE=RE/10
vii)fc=1/2 (,Ceq=C1||C2
viii)Vcc=VcEQ+ICQ(Rc+RE)
Procedure:
1. Rig up the circuit as per the circuit diagrams (both oscillators).
2. Switches on the power supply and observe the output on the CRO (sine wave).
3. Note down the practical frequency and compare with its theoretical frequency.
Model Graph:
Tabulation:
AMPLITUDE(V)
TIME(ms)
FREQUENCY(HZ)
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II YEAR
Result: Thus Colpitts oscillator is designed and constructed and the output sine wave frequency
is calculated as
Theoretical
Practical
Frequency
1. What is neutralization?
The effect of collector to base capacitance of the transistor is neutralized by
introducing a signal that cancels the signal coupled through collector base capacitance.
This process is called neutralization.
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EX NO: 07
II YEAR
DATE :
Aim: To design and construct a single tuned amplifier and to plot the frequency response.
APPARATUS
Power supply
RANGE
(0-30)V
Function generator
(0-20M)Hz
CRO
Transistor
QUANTITY
1
1
1
BC107
Resistors
Capacitors
DIB
DCB
Connecting wires
Theory:
The amplifier is said to be class c amplifier if the Q Point and the input signal are selected
such that the output signal is obtained for less than a half cycle, for a full input cycle Due to such
a selection of the Q point, transistor remains active for less than a half cycle .Hence only that
much Part is reproduced at the output for remaining cycle of the input cycle the transistor
remains cut off and no signal is produced at the output. The total Angle during which current
flows is less than 180.This angle is called the conduction angle, Qc.
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Circuit Diagram:
Design:
VCC = 12V; IC = 1mA; fo = ; S = 2; hfe =
Q = 5; L = 1Mh
re = 26mV / IC = 26;
hie = hfe re =
VCE= Vcc/2 (transistor Active) =
VE = IERE = Vcc/10
Applying KVL to output loop, we get VCC = ICRC + VCE + IERE
RC =
Since IB is very small when compare with IC, IC IE
RE = VE / IE =
S = 1+ RB / RE = 2
RB =
VB = VBE + VE =
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C=
Procedure:
1. Connect the circuit as per the circuit diagram.
2. Set Vi = 50 mV (say), using the signal generator.
3. Keeping the input voltage constant, vary the frequency from 0Hz to3MHz in regular steps and
note down the corresponding output voltage.
4. Plot the graph: Gain (dB) Vs Frequency
Tabular Column:
Vi = 50 mV
Frequency (Hz)
Vo (Volts)
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Gain = 20
log(V0/Vi) (dB)
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Result: Thus single tuned amplifier is designed and constructed for the given operating
frequency and the frequency response is plotted.
2. What is unloaded Q?
It is the ratio of stored energy to the dissipated energy in a reactor or resonator.
4. What is up converter?
When the mixer circuit is used to translate signal to high frequency, then it is called up
converter.
5. What is an amplifier?
An amplifier is a device which produces a large electrical output of similar
characteristics to that of the input parameters.
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II YEAR
EX NO: 08
DATE :
Aim: To design and construct an astable multivibrator using transistor and to plot the output
waveform.
Components / Equipments Required:
S.NO
1.
2.
3.
4.
5.
6.
APPARATUS
Power supply
CRO
Transistor
Resistors
Capacitors
RANGE
(0-30)V
(0-20M)Hz
BC107
4.9K, 1.6M
0.45nF
QUANTITY
1
1
2
2 each
2
Connecting wires
Circuit Diagram:
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Theory:
Astable multivibrator is also known as free running multivibrator. It is rectangular wave
shaping circuit having non-stable states. This circuit does not need an external trigger to change
state. It consists of two similar NPN transistors. They are capacitor coupled. It has 2 quasi-stable
states. It switches between the two states without any applications of input trigger pulses. Thus it
produces a square wave output without any input trigger. The time period of the output square
wave is given by, T = 1.38RC.
Design Procedure:
VCC = 10V; IC = 2mA;VCE (sat) = 0.2V; f = 1KHz; hfe =
RC =( VCC - VCE (sat) )/ IC =(12 0.2 )/ 0.002 = 5.9k.
R hfe RC = 315 * 5.9 * 103 = 1.85M
R = 1.5M.
T = 1.38RC
C = T / (1.38R) = (1 * 10-3) / (1.38 * 1.5 * 106)= 0.48nF
Procedure:
1. Connections are made as per the circuit diagram.
2. Switch on the power supply.
3. Note down the output TON, TOFF and output voltage from CRO.
4. Plot the output waveform in the graph.
Tabular Column:
Amplitude (V)
TON (ms)
TOFF (ms)
Frequency(HZ)
VO1
VO2
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Model Graph:
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RESULT: Thus the astable multivibrator is designed and constructed using transistor and its
output waveform is plotted.
1, What is a Multivibrator?
The electronic circuit which are used to generate non sinusoidal waveforms are
called Multivibrators.
4, When will the circuit change from stable state in bistable Multivibrator ?
when an external trigger pulse is applied, the circuit changes from one stable state
to another.
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EX NO: 09
DATE :
Aim: To design and construct monostable multivibrator using transistor and to plot the output
waveform.
Components / Equipments Required:
S.NO
1.
2.
3.
4.
5.
6.
APPARATUS
Power supply
CRO
RANGE
(0-30)V
(0-20M)Hz
Transistor
BC107
Resistors
4.9K, 1.6M
Capacitors
0.45nF
QUANTITY
1
1
2
2 each
2
Connecting wires
Circuit Diagram:
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Theory:
Monostable multivibrator has two states which are (i) quasi-stable state and (ii) stable
state. When a trigger input is given to the monostable multivibrator, it switches between two
states. It has resistor coupling with one transistor. The other transistor has capacitive coupling.
The capacitor is used to increase the speed of switching. The resistor R2 is used to provide
negative voltage to the base so that Q1 is OFF and Q2 is ON. Thus an output square wave is
obtained from monostable multivibrator.
Design Procedure:
VCC = 12V; VBB = -2V; IC = 2mA; VCE (sat) = 0.2V; f = 1KHz; hfe =
RC =( VCC - VCE (sat) )/ IC =(12 0.2 )/ 0.002 = 5.9k.
IB2(min) = IC2 / hfe =
Select IB2 > IB2(min)
IB2 =
R=( VCC - VCE (sat) )/ IB2
T = 0.69RC
C = T / 0.69R =
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Procedure:
1. Connections are made as per the circuit diagram.
2. Switch on the power supply
3. Observe the output at collector terminals.
4. Trigger Monostable with pulse and note down the output TON, TOFF and voltage from CRO.
5. Plot the waveform in the graph.
Tabular Column:
Input
Output
Width (ms)
TON(ms)
TOFF(ms)
Voltage(V)
TON(ms)
TOFF(ms)
Voltage(V)
Model Graph:
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Result: Thus the monostable multivibrator is designed and constructed using transistor and its
output waveform is plotted.
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EX NO: 10
DATE :
APPARATUS
Power supply
CRO
RANGE
(0-30)V
(0-20M)Hz
Transistor
BC107
Resistors
4.9K, 1.6M
Capacitors
0.45nF
QUANTITY
1
1
2
2 each
2
Connecting wires
Circuit Diagram:
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Theory:
The bistable multivibrator has two stable states. The multivibrator can exist indefinitely
in either of the twostable states. It requires an external trigger pulse to change from one stable
state to another. The circuit remains in one stable state until an external trigger pulse is applied.
The bistable multivibrator is used for the performance of many digital operations such as
counting and storing of binary information. The multivibrator also finds an applications in
generation and pulse type waveform.
Design:
VCC =12V; VBB = -12V; IC = 2mA; VCE (sat) = 0.2V; VBE (sat) = 0.7V
R2 = 1.8M
Let R1 = 10K, C1 = C2 = 50pF
Procedure:
1. Connections are made as per the circuit diagram.
2. Set the input trigger using trigger pulse generator.
3. Note the output waveform from CRO and plot the graph.
Tabular Column:
Input
Voltage
(V)
Input
Output
Width (ms)
TON(ms)
TOFF(ms)
Voltage(V)
ISSUE: 01 REVISION: 00
TON(ms)
TOFF(ms)
Voltage(V)
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Model Graph:
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Result: Thus bistable multivibrator has been constructed and its output waveforms are studied
5. What finally decides the shape of the waveform for bistable multivibrator?
The spacing of the triggering pulses
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EX NO: 11
II YEAR
DATE :
Aim: To design and implement different wave shaping circuits (Differentiator, Integrator,
Clipper and Clamper).
Components / Equipments Required:
S.NO
1.
2.
4.
5.
6.
APPARATUS
Function / Pulse generator
RANGE
(0 3M)Hz
CRO
(0-20M)Hz
Resistors
1K / 100K
Capacitors
0.1F
QUANTITY
1
1
1
1
Connecting wires
Theory:
(i) Differentiator: The high pass RC network acts as a differentiator whose output voltage
depends upon the differential of input voltage. Its output voltage of the differentiator can be
expressed as,
Vout = d/dt .Vin
(ii) Integrator: The low pass RC network acts as an integrator whose output voltage depends
upon the integration of input voltage. Its output voltage of the integrator can be expressed as,
Vout = Vin dt
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(iii) Clipper: This circuit is basically a rectifier circuit, which clips the input waveform
according to the required specification. The diode acts as a clipper. There are several clippers
like positive clipper, negative clipper, etc. Depending upon the connection of diode it can be
classified as series and shunt.
(iv) Clamper: The clamper circuit is a type of wave shaping circuit in which the DC level of the
input signal is altered. The DC voltage is varied accordingly and it is classified as positive
clamper or negative clamper accordingly.
Circuit Diagram:
(i) Differentiator:
(ii) Integrator:
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(iii) Clipper:
(a) Series Positive Clipper:
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(iv) Clamper:
(a) Positive Clamper:
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Design:
(i) Differentiator:
f = 1KHz
= RC = 1ms
If C = 0.1F
Then R = 10K
For T << , Choose R = 1K and
For T >> , Choose R = 100K
(ii) Integrator:
f = 1KHz
= RC = 1ms
If C = 0.1F
Then R = 10K
For T << , Choose R = 1K and
For T >> , Choose R = 100K
Procedure:
1. Connect the circuit as per the circuit diagram.
2. Set Vin = 5V and f = 1KHz.
3. Observe the Output waveform and plot the graph.
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Model Graph:
(i) Differentiator
(ii) Integrator
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(iii) Clipper:
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II YEAR
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(iv) Clamper:
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Result: Thus different wave shaping circuits are studied and their output waveforms are plotted.
1.Define Integrator.
The output waveform similar to the time integral of the input waveform i.e Vo = 1/RC
Vidt.
2.Define differentiator.
The output waveform is the first derivative of the input waveform i.e Vo = RC(dVi/dt).
3.Define Clipper.
The circuit with which the wave form is shaped by removing a portion of input signal
without distorting the remaining part of the alternating waveform is called a clipper.
4.Define Clampers.
Clamping network shift a signal to different dc level i.e it introduce a to an ac signal.
Hence the clamping network is also known as dc restorer.
5.Define Comparator.
The nonlinear circuit which was used to perform the operation of clipping may also be
used perform the operation of comparison and this circuit is called comparator.
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EX NO: 12
SIMULATION OF DIFFERENTIAL AMPLIFIER
DATE :
Circuit Diagram:
Procedure:
EDWin 2000 -> Schematic Editor: The circuit diagram is drawn by loading components from the
library. Wiring and proper net assignment has been made. The values are assigned for relevant
components.
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EDWin 2000 -> Mixed Mode Simulator: The circuit is preprocessed. The waveform marker is
placed at the output of the circuit. GND net is set as reference net. The Transient Analysis
parameters have been set. The Transient Analysis is executed and output waveform is observed
in Waveform Viewer.
EDWin 2000 -> EDSpice Simulator: The circuit is preprocessed. The waveform marker is placed
at the output of the circuit. The Transient Analysis parameters are also set. The Transient
Analysis is executed and output waveform is observed in Waveform Viewer.
Model Graph:
Result: Thus the output waveform was observed in the waveform viewer.
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EX NO: 13
SIMULATION OF ASTABLE MULTIVIBRATOR
DATE :
Circuit Diagram:
Astable Multivibrator-Symmetrical
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Astable Multivibrator-Asymmetrical
Procedure:
EDWin 2000 -> Schematic Editor: The circuit diagram is drawn by loading components from the
library. Wiring and proper net assignment has been made. The values are assigned for relevant
components.
EDWin 2000 -> Mixed Mode Simulator: The circuit is preprocessed. The waveform marker is
placed at the output of the circuit. GND net is set as reference net. The Transient Analysis
parameters have been set. The Transient Analysis is executed and output waveform is observed
in Waveform Viewer.
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EDWin 2000 -> EDSpice Simulator: The circuit is preprocessed. The waveform marker is placed
at the output of the circuit. The Transient Analysis parameters are also set. The Transient
Analysis is executed and output waveform is observed in Waveform Viewer.
Model Graph:
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Result: Thus the output waveform was observed in the waveform viewer.
Astable Multivibrator-Symmetrical
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Astable Multivibrator-Asymmetrical
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EX NO: 14
SIMULATION OF MONOSTABLE MULTIVIBRATOR
DATE :
Circuit Diagram:
Procedure:
EDWin 2000 -> Schematic Editor: The circuit diagram is drawn by loading components from the
library. Wiring and proper net assignment has been made. The values are assigned for relevant
components.
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EDWin 2000 -> Mixed Mode Simulator: The circuit is preprocessed. The waveform marker is
placed at the output of the circuit. GND net is set as reference net. The Transient Analysis
parameters have been set. The Transient Analysis is executed and output waveform is observed
in Waveform Viewer.
EDWin 2000 -> EDSpice Simulator: The circuit is preprocessed. The waveform marker is placed
at the output of the circuit. The Transient Analysis parameters are also set. The Transient
Analysis is executed and output waveform is observed in Waveform Viewer.
Model Graph:
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Result:
Thus the output waveform was observed in the waveform viewer.
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EX NO: 15
SIMULATION OF BISTABLE MULTIVIBRATOR
DATE :
Circuit Diagram:
Procedure:
EDWin 2000 -> Schematic Editor: The circuit diagram is drawn by loading components from the
library. Wiring and proper net assignment has been made. The values are assigned for relevant
components.
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EDWin 2000 -> Mixed Mode Simulator: The circuit is preprocessed. The waveform marker is
placed at the output of the circuit. GND net is set as reference net. The Transient Analysis
parameters have been set. The Transient Analysis is executed and output waveform is observed
in Waveform Viewer.
EDWin 2000 -> EDSpice Simulator: The circuit is preprocessed. The waveform marker is placed
at the output of the circuit. The Transient Analysis parameters are also set. The Transient
Analysis is executed and output waveform is observed in Waveform Viewer.
Model Graph:
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Result: Thus the output waveform was observed in the waveform viewer.
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EX NO: 16
SIMULATION OF ACTIVE FILTERS
DATE :
Aim: To simulate the Active filters: Butterworth 2nd order Low Pass and High Pass Filter by
using PSICE.
System Required:
Circuit Diagram:
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Procedure:
EDWin 2000 -> Schematic Editor: The circuit diagram is drawn by loading components from the
library. Wiring and proper net assignment has been made. The values are assigned for relevant
components.
EDWin 2000 -> Mixed Mode Simulator: The circuit is preprocessed. The waveform marker is
placed at the output of the circuit. GND net is set as reference net. The Transient Analysis
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parameters have been set. The Transient Analysis is executed and output waveform is observed
in Waveform Viewer.
EDWin 2000 -> EDSpice Simulator: The circuit is preprocessed. The waveform marker is placed
at the output of the circuit. The Transient Analysis parameters are also set. The Transient
Analysis is executed and output waveform is observed in Waveform Viewer.
Model Graph:
Low Pass Filter:
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Result: Thus the output waveform was observed in the waveform viewer.
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EX NO: 17
SIMULATION OF ANALOG TO DIGITAL CONVERTER
DATE :
Circuit Diagram:
Procedure:
EDWin 2000 -> Schematic Editor: The circuit diagram is drawn by loading components from the
library. Wiring and proper net assignment has been made. The values are assigned for relevant
components.
EDWin 2000 -> Mixed Mode Simulator: The circuit is preprocessed. The waveform marker is
placed at the output of the circuit. GND net is set as reference net. The Transient Analysis
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parameters have been set. The Transient Analysis is executed and output waveform is observed
in Waveform Viewer.
EDWin 2000 -> EDSpice Simulator: The circuit is preprocessed. The waveform marker is placed
at the output of the circuit. The Transient Analysis parameters are also set. The Transient
Analysis is executed and output waveform is observed in Waveform Viewer.
Model Graph:
M O D EL GR AP H :
Input (A)
Time in ms
Input (B)
Amplitude in volts
Time in ms
Input (C)
Time in ms
Input (D)
Time in ms
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Result: Thus the output waveform was observed in the waveform viewer.
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EX NO: 18
SIMULATION OF ANALOG MULTIPLIER
DATE :
Circuit Diagram:
SPICE Program:
V1 1 0 1V
V2 4 0 1V
R1 1 2 1K
R2 4 5 1K
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R3 3 7 1K
R4 6 7 1K
R5 7 8 1K
R6 10 0 1K
D1 2 3 DA
D2 5 6 DA
D3 8 9 DA
.MODEL DA D
X1 2 0 3 IOP
X2 5 0 6 IOP
X3 7 0 8 IOP
X4 9 0 10 IOP
.SUBCKT IOP M P V0
RI M P 1G
E V0 0 P M 2E5
.ENDS
.DC V1 -1 1 0.1
.PROBE
.END
Result: Thus the output waveform was observed in the waveform viewer.
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EX NO: 19
SIMULATION OF CMOS INVERTER, NAND AND NOR
DATE :
Aim: To plot the transient characteristics of output voltage for the given CMOS inverter, NAND
and NOR from 0 to 80s in steps of 1s.
System Required:
Circuit Diagram:
(i) CMOS Inverter:
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Theory:
(i) Inverter CMOS is widely used in digital ICs because of their high speed, low power
dissipation and it can be operated at high voltages resulting in improved noise immunity. The
inverter consists of two MOSFETs. The source of p-channel device is connected to +VDD and
that of n-channel device is connected to ground. The gates of two devices are connected as
common input.
(ii) NAND It consists of two p-channel MOSFETs connected in parallel and two n-channel
MOSFETs connected in series. P-channel MOSFET is ON when gate is negative and N-channel
MOSFET is ON when gate is positive. Thus when both input is low and when either of input is
low, the output is high.
(iii) NOR It consists of two p-channel MOSFETs connected in series and two n-channel
MOSFETs connected in parallel. P-channel MOSFET is ON when gate is negative and Nchannel MOSFET is ON when gate is positive. Thus when both inputs are high and when either
of input is high, the output is low. When both the inputs are low, the output is high.
Truth Table:
(i) Inverter
Input
0
1
Output
1
0
(ii) NAND
V1
0
0
1
1
V2
0
1
0
1
ISSUE: 01 REVISION: 00
Output
1
1
1
0
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EC 2257-ELECTRONICS CIRCUITS II AND SIMULATION LAB MANUAL
II YEAR
(iii) NOR
V1
0
0
1
1
V2
0
1
0
1
Output
1
0
0
0
Model Graph:
(i) Inverter
(ii) NAND
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EC 2257-ELECTRONICS CIRCUITS II AND SIMULATION LAB MANUAL
II YEAR
(iii) NOR
Result: Thus the output waveform was observed in the waveform viewer.
(i) Inverter
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EC 2257-ELECTRONICS CIRCUITS II AND SIMULATION LAB MANUAL
II YEAR
(ii) NAND
(iii) NOR
ISSUE: 01 REVISION: 00
94
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EC 2257-ELECTRONICS CIRCUITS II AND SIMULATION LAB MANUAL
II YEAR
VIVA:
ISSUE: 01 REVISION: 00
95
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EC 2257-ELECTRONICS CIRCUITS II AND SIMULATION LAB MANUAL
II YEAR
APPENDIX
FEATURES
Low current (max. 100 mA)
Low voltage (max. 45 V).
APPLICATIONS
General purpose switching and amplification.
DESCRIPTION
NPN transistor in a TO-18; SOT18 metal package.
PNP complement: BC177.
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EC 2257-ELECTRONICS CIRCUITS II AND SIMULATION LAB MANUAL
II YEAR
SYMBOL
CBO
V
CEO
I
CM
P
PARAMETER
collector-base voltage
BC107
CONDITIONS
UNIT
50
30
45
20
200
mA
300
mW
110
450
BC108
110
800
BC109
200
800
100
BC108; BC109
collector-emitter voltage
BC107
open base
BC108; BC109
peak collector current
total power dissipation
Tamb 25 C
FE
DC current gain
BC107
IC = 2 mA; VCE = 5 V
fT
MAX.
open emitter
tot
MIN.
transition frequency
ISSUE: 01 REVISION: 00
MHz
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EC 2257-ELECTRONICS CIRCUITS II AND SIMULATION LAB MANUAL
II YEAR
Diffused Junction
High Current Capability and Low Forward Voltage Drop
Surge Overload Rating to 30A Peak
Low Reverse Leakage Current
Lead Free Finish, RoHS Compliant (Note 3)
Mechanical Data
Case: DO-41
Case Material: Molded Plastic. UL Flammability Classification Rating 94V-0
Moisture Sensitivity: Level 1 per J-STD-020D
Terminals: Finish - Bright Tin. Plated Leads Solderable per MIL-STD-202, Method 208
Polarity: Cathode Band
Mounting Position: Any
Ordering Information: See Page 2
Marking: Type Number
Weight: 0.30 grams (approximate)
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EC 2257-ELECTRONICS CIRCUITS II AND SIMULATION LAB MANUAL
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Characteristic
Symbol
V RRM
VRWM
DC Blocking Voltage
Unit
50
100
200
400
600
800
1000
35
70
140
280
420
560
700
VR
V R(RMS)
IO
1.0
IFSM
30
V FM
1.0
= 25C
5.0
IRM
C
j
R JA
TA
T J, T STG
15
pF
100
K/W
C
+150
-65 to
+150
Notes: 1. Leads maintained at ambient temperature at a distance of 9.5mm from the case.
2. Measured at 1.0 MHz and applied reverse voltage of 4.0V DC.
3. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied, see
2002/95/EC Annex Notes.
ISSUE: 01 REVISION: 00
50
EU Directive
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