Title: Designing a Half Adder using CMOS.

ABSTRACT:
CMOS logic is a newer technology, based on the use of complementary MOS transistors to
perform logic functions with almost no current required. This makes these gates a\very useful in
battery-powered applications. They will work with supply voltages as low as 3 volts and as high
as 15 volts. The main objective of this experiment was to be familiar to half adder and to
construct a Half Adder with CMOS.
Characteristics:

The switching characteristics is very fast.

It does not vary with temperature.

Power dissipation is directly proportional to the operating frequency.

High noise immunity.

Advantages:

High fan-out capability

Good noise immunity

High operating speed

Operates at wide variable supply voltage.

Low power dissipation

Disadvantages:

Large chip size

More expensive

High output impedance

Introduction:
ADDER:
In electronics, an adder or summer is a digital circuit that performs addition of numbers. In many
computers and other kinds of processors, adders are used not only in the arithmetic logic unit(s),
but also in other parts of the processor, where they are used to calculate addresses, table indices,
and similar operations.
Although adders can be constructed for many numerical representations, such as binary-coded
decimal or excess-3, the most common adders operate on binary numbers. In cases where two's

complement or ones' complement is being used to represent negative numbers, it is trivial to

modify an adder into an adder subtractor. Other signed number representations require a more
complex adder.

Fig.1:Half adder logic diagram

The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C).
The carry signal represents an overflow into the next digit of a multi-digit addition. The value of
the sum is 2C + S. The simplest half-adder design, pictured above, incorporates an XOR gate for
S and an AND gate for C. With the addition of an OR gate to combine their carry outputs, two
half adders can be combined to make a full adder.
The half-adder adds two input bits and generate carry and sum which are the two outputs of halfadder. The input variables of a Half adder are called the Augend and addend bits. The output
variables are the Sum and Carry. The Truth table and equations for the Half adder are:

Theory and Methodology:

The Half Adder Circuit

1-bit Adder with Carry-Out
Symbol

Truth Table
A
B
SUM
0
0
0
0
1
1
1
0
1
1
1
0
Boolean Expression: Sum = A B Carry = A . B

CARRY
0
0
0
1

From the truth table we can see that the SUM (S) output is the result of the Ex-OR gate and the
Carry-out (Cout) is the result of the AND gate. One major disadvantage of the Half Adder circuit
when used as a binary adder, is that there is no provision for a "Carry-in" from the previous
circuit when adding together multiple data bits.
For example, suppose we want to add together two 8-bit bytes of data, any resulting carry bit
would need to be able to "ripple" or move across the bit patterns starting from the least
significant bit (LSB). The most complicated operation the half adder can do is "1 + 1" but as the
half adder has no carry input the resultant added value would be incorrect. One simple way to
overcome this problem is to use a Full Adder type binary adder circuit.
In this experiment, we implemented and constructed two circuits:
1. A Half Adder Sum with CMOS.
2. A Half Adder Carry with CMOS.

Fig. : Circuit diagram for half adder Sum.

Fig. : Circuit diagram for half adder Carry Out.

To design any logic circuit first the truth table is needed to be established using different
combinations of logic 0 and 1 to get the desired output. After that the gate level design is
found from which transistor level design is done using desired transistors. Here CMOS is used
for the transistor level design of the Half Adder. The whole process is given step wise below:

Pre-Lab Homework:
1/ Ans:
Truth table of half adder:

A
0
0
1
1

B
0
1
0
1

Truth Table
SUM
0
1
1
0

CARRY
0
0
0
1

2/ FULL ADDER: A logic Circuit Which is used for adding Three Single bit Binary
numbers is known as Full Adder.The circuit diagram and Truth Table of Full Adder is
Shown Below:

Apparatus:
1) PMOS: 4[pcs]
2) NMOS: 4[pcs]
3) IC 7404(Inverter): 2[pcs]
4) Connecting Wires
5) Trainer Board

Precautions:
1/After setting up each circuit, the connections were re-checked before input voltage was given.
2/Enough voltage was applied to just to turn on the transistors but not so much that the transistor
is damaged.
3/ For any short circuits in the circuit all connections were checked before input voltage was
applied.
4/We had tried avoiding all errors during the whole experiment.

Experimental Procedure:
1/ The circuit was simulated for half adder sum and half adder carry out using Multisim.
2/The output was verified of the simulation.
3/Then the output was verified again after implementing the circuit on the trainer board.

Fig.4: Circuit diagram for half adder Sum.

Fig.5: Circuit diagram for half adder CarryOut

Simulation and Results:

Figure : Half Adder sum (Input -0 0, output-0)

Figure : Half Adder sum (Input -1 0, output-1)

Figure : Half Adder sum (Input -1 1, output-0)

Figure : Half Adder carry (Input -1 1, output-1)

Figure : Half Adder carry (Input -0 1, output-0)

Figure : Half Adder carry (Input -0 0, output-0)

Table 2 Comparison of Simulation and Experiment results
INPUT INPUT SIMULATION EXPERIMENT SIMULATION EXPERIMENT
A

CARRY-OUT

CARRY-OUT

SUM

SUM

0V

0V

0.06 V

0.11 V

0.05 V

0.06 V

0V

5V

0.66 V

0.57 V

5V

4.91 V

5V

0V

0.66 V

0.57 V

5V

4.94 V

5V

5V

5V

4.97 V

0.10 V

0.15 V

Answers to Questions:
1/Ans:
Table 3: Comparison of the hardware, from simulation and the expected values for the
Carry-Out .
INPUT

INPUT

EXPECTED

SIMULATION

EXPERIMENT

CARRY-OUT

CARRY-OUT

CARRY-OUT

0V

0V

0V

0.06V

0.11V

0V

5V

0V

0.66V

0.57V

5V

0V

0V

0.66V

0.57V

5V

5V

5V

5V

4.97 V

Table 4: Comparison of the hardware, from simulation and the expected values for the Sum
.
INPUT

INPUT

EXPECTED

SIMULATION

EXPERIMENT

CARRY-OUT

CARRY-OUT

CARRY-OUT

0V

0V

0V

0.05V

0.060 V

0V

5V

5V

5V

4.91 V

5V

0V

5V

5V

4.94 V

5V

5V

0V

0.10 V

0.15 V

2/Ans:
Fig : Full Adder using CMOS.

Discussion & Conclusion:

During the experiment the half adder the result was notas expected. Then the circuit was checked
properly and it was the circuit was not accurately implemented. Then the problem was fixed and
the expected result was obtained.
By this experiment we are able to understand the working procedure of CMOS as a half adder. It
is better to examine the experiment theoretically before starting the practical experiment.
Sometimes it is seen that the simulated result does not matches with the practical result.
REFERENCE:
1/http://www.electronics-tutorials.ws/combination/comb_7.html
2/ Lab manual