Digital Electronics

Module 3
Combinational and Sequential Logic Circuits

PREPARED BY

Giridhari muduli
January 2013

Combinational and Sequential Logic Circuits

Module Objectives
Upon successful completion of this module, students should be able to:

Describe the operation of the XOR, XNOR gates.

Describe the operation of the clocked and un-clocked SR-Latch.

Describe the operation of the D and JK Flip Flops.

Distinguish between combinational logic and sequential logic.

Use of sequential logic in simple applications.

Module Contents:
#

Topic

Page No.

1.

Introduction to Combinational logic

03

2.

The Exclusive-OR (XOR)

04

3.

The Exclusive-NOR (XNOR)

05

Module 3: Combinational and Sequential Logic Circuits

4.

Lab Activity#3

07

5.

Lab Activity#4

10

6.

Sequential Logic

12

7.

Latches and Flip-Flops

12

8.

The NOR Gate S-R Latch

13

9.

Level Triggered Latch

16

10.

Level Triggered D-Type latch

18

11.

Edge-Triggered Flip Flop

20

12.

Lab Activity#1 (XOR)

22

13.

Lab Activity#2 (XNOR)

23

14.

Lab Activity#5 (Clocked SR-Latch)

25

15.

Lab Activity#6 (JK-Flip Flop)

29

Module 3: Combinational and Sequential Logic Circuits

1. INTRODUCTION
Combinational logic: When logic gates (such as AND, OR and NOT) are
connected together to produce a specified output for certain specified
combinations of input variables, with no

storage involved, the resulting

network is called combinational logic.

Definition
The combinational logic can be defined as is that logic in which all
outputs are directly related to the current combination of values on
its inputs.
Combinational logic is probably the easiest circuitry to design. The outputs
from a combinational logic circuit depend only on the current inputs. Much of
logic design involves connecting simple combinational logic circuits to
construct a larger circuit that performs a much more complicated function.
Simple and often-used combinational logic circuits are XOR and XNOR.

1.1 The Exclusive-OR and Exclusive-NOR gates

These two gates are actually formed by a combination of other gates already
discussed. Because of their fundamental importance in many applications,
these gates are treated as basic gates with their own unique symbols.

Module 3: Combinational and Sequential Logic Circuits

2 The Exclusive-OR (XOR)

2.1 The XOR Logic Circuit and Symbol
Referring to logic circuit in Figure 1, you can see how an XOR gate is made up
of the combination of AND, OR, and NOT gates. The standard symbol for the
XOR gate is shown in Figure 2. Note that XOR gate has only two inputs, it
never has more than two inputs.

Figure 2 XOR logic

symbol
Figure 1 XOR logic Circuit

2.2 XOR Logical Operation and Truth Table

The logical operation of XOR is such that the output is

INPUTS

high only when the two inputs are at opposite levels.

The operation of XOR with two inputs A and B and

output X is stated as follows:

If A is LOW and B is HIGH, OR if A is HIGH and B is

LOW, then X is HIGH

If A and B are both HIGH or both LOW, then X is
LOW

OUTPUT

Table 1 Truth table

for XOR gate

The truth table illustrates this operation is Table 1.

2.3 XOR Logical Function
The two variables expression X = A B is called the Logical XOR Function.
Referring to logic circuit in Figure 1, XOR function can be illustrated as
follows:

The inputs to the AND-1 are

A and B ;

then

Y1 A B .

The inputs to the AND-2 are

A and B ;

then

Y2 A B .

Module 3: Combinational and Sequential Logic Circuits

Continue (XOR Logical Function)

then X Y1 Y2 .

The inputs to the OR are

Hence X = A B = ( A B ) + ( A B ) and it mean the following:

Y1 and Y2 ;

If (A and B) are at opposite levels; then X is high. Otherwise X is Low.

3. The Exclusive-NOR (XNOR)

3.1 The XNOR Logic Circuit
Referring to logic circuit in Figure 3; you can see how an XNOR gate is made
up of the combination of AND, OR, and NOT gates.
A

AND

Y1

NOT

OR
NOT

AND

NOT

Y2

Figure 3 XOR logic Circuit

3.2 The XNOR Symbol

Standard

symbol

for

the

Exclusive-NOR

(XNOR) gate is shown in Figure 4. The XNOR

gate has only two inputs. The bubble on the
output indicates that its output is opposite
that of XOR gate.

Figure 4 XNOR logic symbol

Module 3: Combinational and Sequential Logic Circuits

3.3 XNOR Logical Operation and Truth Table

The logical operation of XNOR is such that when the

INPUTS

two inputs are opposite the output is LOW. The

operation of XNOR with two inputs A and B and output

X can be stated as follows:

If A is LOW and B is HIGH, OR if A is HIGH and B is

LOW, then X is LOW

If A and B are both HIGH or both LOW, then X is

OUTPUT

Table 2 Truth table

for XNOR gate

HIGH
The truth table illustrates this operation is Table 2.
3.4 XNOR Logical Function
The expression

X A B

is called the Logical XNOR Function. Referring to

logic circuit in Figure 3, XNOR function can be illustrated as follows:

The output of the XOR part is Z = A B.

But the output of XNOR part is

Then the output of XNOR can be written as

X Z.
X A B

and it means:

If A and B both are High or both Low, then X is High. Otherwise X is Low.
Applications: Google to find at least 2-applications for each gate.
XOR

XNOR

a)

a)

b)

b)

c)

c)

Module 3: Combinational and Sequential Logic Circuits

Module 3: Combinational and Sequential Logic Circuits

Sequential Logic
A digital logic function made of basic logic gates (AND, OR, NOT, etc.) in
which the output values depend not only on the values currently being
presented to its inputs, but also on previous input values.
Definition
Briefly the sequential logic can be defined as is that logic in which the
output depends on a sequence of its input values.

Latches and Flip-Flops

In this part of the module we will examine two types of sequential logic
circuits: the Latches and the Flip-Flops. Latches and Flip-Flops are
bistable elements having two stable states. Because of their storing ability,
they are useful as basic building block for registers and memories.
1) Latches

2) Flip-Flops

It is a bistable element that can have its output latched

HIGH (Set) or LOW (Reset), hence the name S-R Latch.
It is a synchronous bistable device that can have its output
changes state only on the clock edge.

Main difference between Latches and Flip-Flops

Latch: It is active when clock either at logic high level or at low level.

Flip-Flop: It is active only on the clock edges.

Example of Latches

Example of Flip-Flops

1) SR Latch

1) JK flip-flops

2) Clocked SR Latch

2) T-type flip-flops

3) D Latch

3) Edge triggered D-FF

Module 3: Combinational and Sequential Logic Circuits

The NOR Gate S-R Latch

The most basic memory element is the S-R LATCH. The S-R latch has two
main inputs: the Set (S) and the REST (R), and two outputs Q and
Two-inputs R and S, and two-outputs Q and

Q.

It has

The S-R Latch Logic Circuit and Symbol

Figure 9 shows how SR latch is formed with two cross-coupled NOR-gates. R,
Q,

and Q are the inputs and the output of gate G1. S, Q, and

are the

inputs and the output of gate G2. These arrangements must preserve,
otherwise the Set and Reset will have the opposite meaning. The symbol of
the NOR-Gate S-R latch is shown in Figure 10.
R

NOR
G1

NOR
G2

Figure 9 S-R Latch logic Circuit

Figure 10 Latch logic symbol

SR latch Logical Operation

Referring to Figure 9, initially assume that both inputs R and S and

output Q are LOW [i.e. R = S = 0 and Q = 0]

Now G2 inputs are G = 0 and S = 0, therefore G2 output is

G1 inputs are Q = 1 and R = 0, therefore G1 output is Q = 0.

Change S to HIGH G2 inputs become Q = 0 and S = 1, therefore G2

output is

= 1.

= 0.

Now G1 inputs will change to

= 0 and R = 0, therefore G1 output will

change to Q = 1 the latch is in the Set state.

Solve Exercise 1 to find out the other inputs combinations and their
corresponding outputs states.

Module 3: Combinational and Sequential Logic Circuits

Important Note
Note that the inputs condition (S = R = 1) is not allowed, because it
generates unpredictable output state and it is called invalid condition.
Exercise #1

Change S back to LOW and follow the same process given above to
determine the states of the outputs Q an

Q.

Change R to HIGH and follow the same process to determine the states
of the outputs Q and

Q.

NOR Gate S-R Latch Truth Table

If the input S is ON and the R is OFF, the output (Q) will be set to ON.

If the input S is OFF and the R is ON, the output (Q) will be set to OFF.

If both the inputs S and R are OFF, the output (Q) will remain the same
as its previous value.

If both the inputs S and R are ON, the output state is unpredictable.

The truth table of S-R latch which illustrates this operation is Table 6.
Inputs

Outputs

Operation

No Change (same as previous)

The output Set to ON

The output Reset to OFF

Invalid condition

unpredictable output state

Table 6 Truth table for S-R Latch

Terminology used
Terms

Meanings

No change

Latch remains in previous state (store the previous output.

Latch Set

The output (Q) Set to ON (i.e. Q = 1).

Latch Reset

The output (Q) Reset to OFF (i.e. Q = 0).

Invalid

Simultaneous Highs on both inputs (i.e. R = S =1) not

Condition

allowed. It generates unpredictable output state.

Solution to Exercise #1
10

Module 3: Combinational and Sequential Logic Circuits

the latch is in the Set state, therefore G1 output is Q = 1

Changing S back to LOW G2 inputs become Q = 1 and S = 0,

therefore G2 output is

Now G1 inputs is

= 0.

= 0 and R = 0 G1 output remain unchanged in the

Set state Q = 1.

Remember G2 output is
Q

= 0, changing R to HIGH G1 inputs become

= 0 and R = 1, therefore G1 output is Q = 0 the latch is in the

Reset state.

Notes:
....
....
....
....
....
....
....
....
....
....
....
....
....

11

Module 3: Combinational and Sequential Logic Circuits

9. Level Triggered Latches

To have control over the Latchs operation, a clock signal is applied to decide
when a latch is enabled or disabled and when the output changes its state.
The clock signal ensures that the device is triggered into operation at the
right time and is denoted with C Clock Signal or EN Enable Signal.
Definition
The Level Triggered latch can be defined as a logic device that changes its
output state in response to a HIGH or LOW level of the clock; and hence the
name Level Triggered latch.
9.1 Level Triggered S-R Latch
The operation of Level Triggered SR latch is the same as SR Latch except that
its output state changes only when the clock level is HIGH.
9.2 Level Triggered SR latch Logic Symbol
Figure 11 shows the logic symbol of
level-triggered SR latch.
The logic circuit for a level-triggered
S-R latch is shown in Figure 12.
This logic circuit illustrates how S-R
latch is modified to add the clock
Figure 11 Level Triggered SR latch logic
symbol

input (CK).

9.3 Level Triggered SR latch Logic Circuit

R

AND

NOR

NOR

CK

AND

Figure 12 Level Triggered SR latch logic Circuit

12

Module 3: Combinational and Sequential Logic Circuits

9.4 Level Triggered SR latch operation and Truth Table

Referring to the logic circuit in Figure 12, you can see that the inputs to the
latch (S and R) are only enabled when the clock signal (CK) is HIGH. This
can be realized as follows:

When the level of the clock signal is HIGH (logic-1), the two-AND gates
passes the (S and R) inputs through to the latch and the device is
enabled.

When the level of the clock signal is LOW (logic-0), the two-AND gates
blocks the (S and R) inputs from reaching the latch and the device is
disabled.

The when CK is HIGH, the circuit operation is identical to that of the SR

latch. The truth table illustrates this operation is shown in Table 7.
Latch

Outputs

Comments

CK

Inputs

NO Change

AND Inputs

No Change (same as previous)

The output Set to ON

The output Reset to OFF

Invalid

unpredictable output state

As long as the clock level CK is LOW

the output remain same as previous
(No Change will occur).

Table 7 Truth table for Level Triggered SR Latch

Notes:
....
....

13

Module 3: Combinational and Sequential Logic Circuits

10. Level Triggered D-type Latch

The D-type latch is basically a S-R latch with small circuit modification. This
modification was introduced to ensure that the S and R inputs are never
HIGH or LOW at the same time. So D-latch is used to eliminate the
undesirable invalid state occurs in the S-R latch.
Definition
The D-type latch is a Data-type circuit that can latch (store) a binary 1 or 0.
10.1 D-type Latch Logic Circuit and Symbol
The basic D-type latch logic circuit is
shown in Figure 14. It has only two
inputs: D Data-input and CK Clockinput. The NOT gate ensure that the
inputs to the AND gates are at opposite
level and consequently the inputs S and R
to the latch are at opposite level. The
logic symbol for the D-type latch is shown

Figure 13 Level Triggered D-type

latch logic symbol

in Figure 13.
10.2 Level Triggered D-Type latch Logic Circuit

Figure 14 Level Triggered D-Type latch logic Circuit

14

Module 3: Combinational and Sequential Logic Circuits

10.3 Level Triggered D-Type latch operation and Truth Table

Referring to the logic circuit in Figure 14, the operation of D-type Latch can
be explained as follows:

As long as the clock level is Low, the AND gates outputs S and R are also
Low. With low level S and R, the output Q remains unchanged.

When the CK is High, the input S follows D and the input R follows

Therefore with CK = High, when D is High the latch will Set and when D

D.

is Low the latch will Reset.

This can be stated another way, the output Q follows the input D when
CK is High (D = 1 the latch Set, D = 0 the latch Reset).

The truth table illustrates this operation is shown in Table 8.

AND Inputs

Latch
Inputs

Outputs

Comments

CK

NO

Change

The output Reset to OFF

The output Set to ON

As long as the CK is LOW, the

output remains same as previous.

Table 8 Truth table for Level Triggered D Latch

Notes:
....
....
....
....

15

Module 3: Combinational and Sequential Logic Circuits

11. Edge-Triggered Flip Flop

Edge-Triggered Flip Flop is a type of flip-flop in which the data are entered
and appear on the output on the same clock edge. They are of two types:
a) Positive Edge-Triggered JK-FF

b) Negative Edge-Triggered JKFF

In this type the FF responses to the

In this type the FF responses to the

Positive Edge of the clock

Negative Edge of the clock

11.1 Edge-Triggered J-K Flip Flop

The J-K flip-flop is the most widely used type of flip-flop. The operation of JKFF is identical to that of the S-R flip-flop in the SET, RESET, and NOChange conditions. The difference is that the JK-FF has no Invalid State.
11.2 Edge-Triggered JK-FF Symbol
Figure 15 shows a basic positive EdgeTriggered JK-FF. It differ from the S-R flip-flop
in that the Q output is connected back to the
input of G1, and the

output is connected

back to the input of G2. J and K are the two

control inputs. The logic symbol for EdgeTriggered JK-FF is shown in Figure 16.

Figure 16 Edge-Triggered JKFF logic symbol

11.3 Edge-Triggered JK-FF Logic Circuit

Figure 15 Level Triggered D-Type latch logic Circuit

16

Module 3: Combinational and Sequential Logic Circuits

11.4 Edge-Triggered JK-FF Truth Table

If CK is LOW, no matter what (J or K) are the output remains the same.

If both J and K are LOW, no matter CK is the output remains the same.

On the positive edge if J is HIGH and K is LOW, the flip-flop will SET.

On the positive edge if J is LOW and K is HIGH, the flip-flop will RESET.

If both J and K are HIGH, the flip-flop will Toggle on each clock pulse.

The truth table illustrates this operation is shown in Table 9.

Inputs

Outputs

Comments

CK

No Change (same as previous)

No Change (same as previous)

The Flip-Flop RESET

The Flip-Flop SET

The Flip-Flop Toggle

Table 9 Truth table of JK Flip Flop

Terminology used
Terms
Toggle

17

Meanings
The action of a flip-flop when it changes state on each clock pulse.
(The output switches back and forth between OFF and ON)

Module 3: Combinational and Sequential Logic Circuits

18

Module 3: Combinational and Sequential Logic Circuits