0.

35um CMOS Devices Model Parameters

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0.35um CMOS Devices Model Parameters

MYSC02-403
Revision 4.0

Revision Author
Department
Document Location
Approval Committee
Confidentiality Status
Archive Requirement

Muhamad Amri Ismail

Wafer Fab Design Library
Department Document Center
Author Immediate Superior
MIMOS Authorized Recipient Only
Not Applicable

0.35um CMOS Devices Model Parameters

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Revision History
Rev No
1.0

Date
12 Jun
2007

Change History

Originator

First version of device model parameters extracted

from qualified 0.35 um CMOS process

Muhamad Amri
Ismail

(a) CMOS transistor (Dated:7 Sep 06)

(b) Parasitic bipolar (Dated:20 Mar 07)
(c) Diode (Dated:7 Sep 06)
(d) Resistor (Dated:1 Nov 06)

2.0

(e) PIP Capacitor (Dated:1 Nov 06)

16/09/2008 New template

3.0

11/03/2009

4.0

New template MIMOS Wafer fab 2009

New reviews and approval records due to
organizational changes.
24/02/2011 New device models extracted from new silicon data
of lot E203 MY0085 mask

MIMOS INTERNAL USE ONLY

o
o

Fairuz Niza
Abu Bakar
Robiah Hussin

Muhamad Amri
Ismail

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0.35um CMOS Devices Model Parameters

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Review and Approval Records

Document Originator
Department

Name

Title

Muhamad Amri Ismail

Senior Engineer

Date

Signatory

Wafer Fab Design

Library

Document Review
Name

Title

Department

Muhamad Amri Ismail

Senior Engineer Design Library

Date

Signatory

Date

Signatory

Document Approval
Name

Title

Iskhandar Md Nasir

Senior Staff
Engineer

MIMOS INTERNAL USE ONLY

Department
Wafer Fab Design
Library

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0.35um CMOS Devices Model Parameters

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Confidential Proclamation

This document contains MIMOS confidential information and is intended for MIMOS
authorized recipient only. No part of this document may be reproduced or transmitted in
any form or by any means without the prior written permission from MIMOS.

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0.35um CMOS Devices Model Parameters

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TABLE OF CONTENTS
1.

2.

3
4

6
7

PAGE

TRANSISTOR MODEL ...................................................................................... 5

1.1
Flexibility of device model Parameter...................................................... 5
1.2
BSIM3v3 Parameter List ......................................................................... 7
1.3
BSIM3v3 SPICE Model......................................................................... 10
1.4
Comparison between Model versus Wafer............................................ 12
1.5
Simulated Critical Parameters............................................................... 14
1.6
Measured versus Simulated Results of Ring Oscillator ......................... 15
1.7
BSIM3v3 Corner-case Models .............................................................. 16
BIPOLAR GUMMEL-POON MODEL .............................................................. 17
2.1
Flexibility of Model ................................................................................ 17
2.2
Parameter List ...................................................................................... 18
2.3
SPICE Model ........................................................................................ 19
DIODE MODEL ................................................................................................ 20
3.1
Parameter List ...................................................................................... 20
3.2
SPICE Model ........................................................................................ 21
RESISTOR MODEL ......................................................................................... 22
4.1
Parameter List ...................................................................................... 22
4.2
POLY1 SPICE Model............................................................................ 22
4.3
NWELL SPICE Model ........................................................................... 22
4.4
NDIFF SPICE Model............................................................................. 23
4.5
PDIFF SPICE Model ............................................................................. 23
4.6
HRES SPICE model ............................................................................. 23
4.7
Example on how to run the model......................................................... 24
PIP CAPACITOR MODEL ............................................................................... 25
5.1
Parameter List ...................................................................................... 25
5.2
SPICE model ........................................................................................ 25
5.3
Example on how to run the model......................................................... 27
Interconnection Line Line Capacitance ..................................................... 28
6.1
Typical Interconnect Capacitance Table ............................................... 29
SUPPORT.......................................................................................... 30

APPENDIX 1:
APPENDIX 2:
APPENDIX 3:
APPENDIX 4:

Fitting Results For MOSTransistor Model31

Fitting Results for BJT Model..84
Fitting Results for Resistor Model..89
Fitting Results for Capacitor Model..105

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1. TRANSISTOR MODEL

1.1

Flexibility of device model Parameter

Parameters used by BSIM3v3.2.4 can be broadly classified into three categories namely the
device structure parameters, DC parameters and capacitance parameters. In order to derive
device structure parameters, it is necessary to measure the device process parameters such as
gate oxide thickness (TOX) and junction depth (XJ).
DC measurements are performed using HP 4142 parametric analyzer to obtain all the typical
current vs. voltage plots. CV measurements are performed using HP 4284 high frequency LCR
meter to obtain all the capacitance vs. voltage plots. Measurement and extraction modules from
Agilent ICCAP are used to control the test equipment and extract related BSIM3v3.2.4 model
parameters.
There is only a single transistor model for 3.3V CMOS. In deriving this model, 14 devices with
different L, W sizes were used for model fitting to cover the various device corners. The four main
device corners are large (L=20, W=20), narrow (L=20, W=0.4), short (L=0.35, W=20) and small
(L=0.35, W=0.4).

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(0.4/20)

(0.5/20)
(20/20)

20

Channel Width, W (um)

(0.35/20) (0.45/20)

(0.6/20)

(0.35/1)
(0.35/0.8)

(20/1.0)
(20/0.8)

(0.35/0.6)

(20/0.6)

(0.35/0.4)

(20/0.4)

Channel Length, L (um)

20

MOS Transistor Model Binning

(Transistor with different W/L provided by 0.35 um CMOS with AMS option)

Notes:
BSIM3v3.2.4 MOS model was used for modeling MIMOSs 3.3V CMOS devices. It is a physicsbased sub-micron MOS technology SPICE model. Single scalable BSIM3v3.2.4 model with
supporting bin parameters was used as modeling methodology. The binning parameters can be
introduced in the model set when the core parameters (approx. 50 DC parameters) are not
sufficient to fit certain W and L geometries.

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1.2

0.35um CMOS Devices Model Parameters

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BSIM3v3 Parameter List

LEVEL

Model selector (Level 49 for BSIM3v3 in HSPICE)

TOX

Gate oxide thickness

XJ

Junction depth

NCH

Channel doping concentration

VTH0

Threshold voltage at Vbs=0 for large device

K1

First order body effect coefficient

K2

Second order body effect coefficient

K3

Narrow width coefficient

K3B

Body effect coefficient of K3

W0

Narrow width coefficient

NLX

Lateral non-uniform doping parameter

DVT0

First coefficient of short channel effect on Vth

DVT1

Second coefficient on short channel effect on Vth

DVT2

Body bias coefficient of short channel effect on Vth

DVT0W

First coefficient of narrow width effect on Vth for small channel length

DVT1W

Second coefficient of narrow width effect on Vth for small channel length

DVT2W

Body-bias coefficient of narrow width effect for small channel length

U0

Mobility at Temp = Tnom

UA

First order mobility degradation coefficient

UB

Second order mobility degradation coefficient

UC

Body effect of mobility degradation coefficient

VSAT

Saturation velocity at Temp = Tnom

A0

Bulk charge effect coefficient for channel length

AGS

Gate bias coefficient of Abulk

B0

Bulk charge effect coefficient for channel width

B1

Bulk charge effect width offset

KETA

Body-bias coefficient of bulk charge effect

A1

First non-saturation effect parameter

A2

Second non-saturation factor

RDSW

Parasitic resistance per unit width

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0.35um CMOS Devices Model Parameters

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PRWB

Body-effect coefficient of Rdsw

PRWG

Gate bias coefficient of Rdsw

WR

Width offset from Weff for Rds calculation

WINT

Width offset fitting parameter from I-V without bias

LINT

Length offset fitting parameter from I-V without bias

XL

The masking and etching effects of channel length.

XW

The masking and etching effects of channel width.

DWG

Coefficient of Weffs gate dependence

DWB

Coefficient of Weffs substrate body bias dependence

VOFF

Offset voltage in the subthreshold region at large W and L

NFACTOR

Subthreshold swing factor

ETA0

DIBL coefficient in subthreshold region

ETAB

Body-bias coefficient in subthreshold DIBL effect

DSUB

DIBL coefficient exponent in subthreshold region

CIT

Interface trap capacitance

CDSC

Drain/source to channel coupling capacitance

CDSCB

Body-bias sensitivity of Cdsc

CDSCD

Drain-bias sensitivity of Cdsc

PCLM

Channel length modulation parameter

PDIBLC1

First-output resistance DIBL effect correction parameters

PDIBLC2

Second-output resistance DIBL effect correction parameters

PDIBLCB

Body-effect coefficient of DIBL correction parameters

DROUT

L dependence coefficient of the DIBL correction parameter in Rout

PSCBE1

First substrate current body-effect parameter

PSCBE2

Second substrate current body-effect parameter

PVAG

Gate dependence of Early voltage

DELTA

Effective Vds parameter

ALPHA0

The first parameter of impact ionization current

ALPHA1

Isub parameter for length scaling

BETA0

The second parameter of impact ionization current

CGSO

Non LDD region source-gate overlap capacitance per channel length

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CGDO

Non LDD region drain-gate overlaps capacitance per channel length

CGBO

Gate bulk overlap capacitance per unit channel length

CJ

Bottom junction capacitance per unit area at zero bias

MJ

Bottom junction capacitance grating coefficient

MJSW

Source/Drain sidewall junction capacitance grading coefficient

CJSW

Source/Drain sidewall junction capacitance per unit area

CJSWG

Source/drain gate sidewall junction capacitance grading coefficient

PBSW

Source/drain sidewall junction built-in potential

PB

Bottom built-in potential

PBSWG

Source/Drain gate sidewall junction built-in potential

DLC

Length offset fitting parameter from C-V

DWC

Width offset fitting parameter from C-V

WL

Coefficient of length dependence for width offset

WLN

Power of length dependence of width offset

WW

Coefficient of width dependence for width offset

WWN

Power of width dependence of width offset

WWL

Coefficient of length and width cross term for width offset

LL

Coefficient of length dependence for length offset

LLN

Power of length dependence for length offset

LW

Coefficient of width dependence for length offset

LWN

Power of width dependence for length offset

LWL

Coefficient of length and width cross term for length offset

TNOM

Temperature at which parameters are extracted

UTE

Mobility temperature exponent

KT1

Temperature coefficient for threshold voltage

KT1L

Channel length dependence of the temperature coefficient for Vth

KT2

Body-bias coefficient of Vth temperature effect

UA1

Temperature coefficient for Ua

UB1

Temperature coefficient for Ub

UC1

Temperature coefficient for Uc

AT

Temperature coefficient for saturation velocity

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1.3

0.35um CMOS Devices Model Parameters

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BSIM3v3 SPICE Model

*
* ----------------------------------------------------------------------* Model card for BSIM3v3.2.4
* Date : 06.12.2010
Lot E203 Wafer # 5
Version 5
* 0.35 um CMOS (with AMS option)
Typical Case Model
* Lmin=0.35um
Lmax=20um
Wmin=0.4um
Wmax=20um
* Model Names:
NCH
NMOS model
*
PCH
PMOS model
* ----------------------------------------------------------------------*
.MODEL NCH NMOS
LEVEL = 49
+ VERSION = 3.24
BINUNIT = 2
MOBMOD = 1
+ CAPMOD = 3
NOIMOD = 1
PARAMCHK = 1
+ DELTA = 0.01
TNOM = 27
TOX = 7E-009
+ TOXM = 7E-009
NCH = 2.261E+017
XJ = 1.5E-007
+ NGATE = 0
XL = 0
VTH0 = 0.4182
+ K1 = 0.5398
K2 = 0.008717
K3 = 6.72
+ K3B = -0.8524
W0 = 4.441E-021
NLX = 2.414E-007
+ DVT0 = 0.8534
DVT1 = 0.5559
DVT2 = 0.02602
+ DVT0W = 2.077
DVT1W = 1.033E+006
DVT2W = 0.02181
+ ETA0 = 2.22E-015
ETAB = -0.01686
DSUB = 0.5202
+ U0 = 313.5
UA = -8.277E-010
UB = 2.179E-018
+ UC = 5.414E-011
VSAT = 7.417E+004
A0 = 1.601
+ AGS = 0.3042
B0 = 1.571E-007
B1 = 0
+ KETA = 0.000577
A1 = 1E-015
A2 = 0.995
+ RDSW = 489.6
PRWB = -0.03951
PRWG = 0.05153
+ WR = 1.031
WINT = 2.433E-007
WL = -3.459E-014
+ WLN = 1.022
WW = -3.57E-014
WWN = 1.038
+ WWL = 3.349E-021
DWG = -8.822E-009
DWB = 1.26E-008
+ LINT = 1.32E-008
LL = -1.654E-016
LLN = 1
+ LW = -1.267E-015
LWN = 1.005
LWL = -7.663E-023
+ VOFF = -0.08112
NFACTOR = 0.9595
CIT = 0
+ CDSC = 0.00119
CDSCB = -7.374E-005
CDSCD = 0.0001122
+ PCLM = 1.556
PDIBLC1 = 0.2966
PDIBLC2 = 0.004945
+ PDIBLCB = 0
DROUT = 0.56
PSCBE1 = 4.809E+008
+ PSCBE2 = 2.361E-005
PVAG = 0.3701
VBM = -3.3
+ ALPHA0 = 1.191E-007
ALPHA1 = 9.29
BETA0 = 20.47
+ JS = 2.762E-006
JSW = 2.926E-012
NJ = 1.154
+ IJTH = 1.00E-003
CJ = 0.00151403
MJ = 0.399389
+ PB = 0.882812
CJSW = 6.8984E-010
MJSW = 0.286203
+ PBSW = 0.773437
CJSWG = 5E-010
MJSWG = 0.33
+ PBSWG = 1
CGDO = 2E-010
CGSO = 2E-010
+ CGBO = 1E-012
CGSL = 0
CGDL = 0
+ CKAPPA = 0.6
CF = 0
NOFF = 0.5
+ VOFFCV = -0.3
ACDE = 1
MOIN = 15
+ DLC = 5.9E-008
DWC = 0
LLC = 0
+ LWC = 0
LWLC = 0
WLC = 0
+ WWC = 0
WWLC = 0
CLC = 1E-007
+ CLE = 0.6
ELM = 2
XPART = 0.5
+ KT1 = -0.3942
KT1L = -1.735E-024
KT2 = -0.04349
+ UTE = -1.327
UA1 = 2.162E-009
UB1 = -2.634E-018
+ UC1 = -8.449E-011
AT = 1.342E+004
PRT = 237.4
+ XTI = 3
TPB = 2.253E-003
TPBSW = 1.531E-003
+ TPBSWG = 0
TCJ = 1.070E-003
TCJSW = 806.6E-006
*
*
*

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0.35um CMOS Devices Model Parameters

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.MODEL PCH PMOS

+ VERSION = 3.24
+ CAPMOD = 3
+ DELTA = 0.01
+ TOXM = 7E-009
+ NGATE = 0
+ K1 = 0.6112
+ K3B = -3.941
+ DVT0 = 1.151
+ DVT0W = 2.003
+ ETA0 = 0.2934
+ U0 = 180.8
+ UC = -7.498E-012
+ AGS = 0.3025
+ KETA = -0.01317
+ RDSW = 3076
+ WR = 1.069
+ WLN = 0.9846
+ WWL = 2.504E-021
+ LINT = 2.224E-008
+ LW = -2.005E-014
+ VOFF = -0.08311
+ CDSC = 0.000149
+ PCLM = 15.37
+ PDIBLCB = 0
+ PSCBE2 = 0.001
+ ALPHA0 = 2.034E-008
+ JS = 2.418E-006
+ IJTH = 1.00E-003
+ PB = 1.073
+ PBSW = 0.8500
+ PBSWG = 1
+ CGBO = 1E-012
+ CKAPPA = 0.6
+ VOFFCV = -0.35
+ DLC = 3E-008
+ LWC = 0
+ WWC = 0
+ CLE = 0.6
+ KT1 = -0.7123
+ UTE = -1.892
+ UC1 = -8.702E-011
+ XTI = 3
+ TPBSWG = 0
*
*

MIMOS INTERNAL USE ONLY

BINUNIT = 2
NOIMOD = 1
TNOM = 27
NCH = 1.778E+017
XL = 0
K2 = -0.04294
W0 = 2.381E-007
DVT1 = 0.2435
DVT1W = 5.3E+006
ETAB = -0.0669
UA = 1.434E-009
VSAT = 1.045E+005
B0 = 1.237E-007
A1 = 1E-015
PRWB = 0.008293
WINT = 2.17E-007
WW = -2.178E-014
DWG = -1E-008
LL = -5.175E-015
LWN = 1.12
NFACTOR = 1.772
CDSCB = 0.0001942
PDIBLC1 = 0.02417
DROUT = 0.56
PVAG = 23.27
ALPHA1 = 0.01681
JSW = 2.788E-012
CJ = 0.00121572
CJSW = 5.236E-010
CJSWG = 5E-010
CGDO = 2.05E-010
CGSL = 0
CF = 0
ACDE = 1
DWC = 0
LWLC = 0
WWLC = 0
ELM = 2
KT1L = 4.137E-008
UA1 = 1.365E-009
AT = 5000
TPB = 2.404E-003
TCJ = 1.192E-003

LEVEL = 49
MOBMOD = 1
PARAMCHK = 1
TOX = 7E-009
XJ = 1.5E-007
VTH0 = -0.6043
K3 = -6.781
NLX = 3.254E-007
DVT2 = -0.07311
DVT2W = -0.032
DSUB = 0.7126
UB = 9.406E-019
A0 = 1.401
B1 = 0
A2 = 0.995
PRWG = -0.1075
WL = -4.739E-014
WWN = 1.031
DWB = -8.131E-009
LLN = 1.005
LWL = 6.527E-021
CIT = 0
CDSCD = 0.0006654
PDIBLC2 = 1.002E-006
PSCBE1 = 9.552E+008
VBM = -3.3
BETA0 = 21.28
NJ = 1.145
MJ = 0.521306
MJSW = 0.3686
MJSWG = 0.33
CGSO = 2.05E-010
CGDL = 0
NOFF = 0.5
MOIN = 15
LLC = 0
WLC = 0
CLC = 1E-007
XPART = 0.5
KT2 = -0.07602
UB1 = -6.01E-018
PRT = 210.8
TPBSW = 2.217E-003
TCJSW = 981.1E-006

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1.4

0.35um CMOS Devices Model Parameters

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Comparison between Model versus Wafer

a) T = 27C

Idsat (NMOS)
L/W(um/um)
20/20
20/0.4
20/0.6
20/0.8
20/1
0.35/20
0.4/20
0.45/20
0.5/20
0.6/20
0.35/0.4
0.35/0.6
0.35/0.8
0.35/1

Idsat (PMOS)

Measured
4.851000E-04

Model
4.947850E-04

Measured
-1.389500E-04

Model
-1.402860E-04

5.350000E-06

4.974300E-06

-1.230400E-06

-1.200500E-06

7.150500E-06

7.350460E-06

-2.405500E-06

-2.261660E-06

1.040950E-05

1.109890E-05

-3.376000E-06

-3.512430E-06

1.447500E-05

1.538680E-05

-4.543000E-06

-4.835380E-06

1.017150E-02

1.020490E-02

-5.171500E-03

-5.083440E-03

9.538500E-03

9.651780E-03

-4.644000E-03

-4.602850E-03

9.037500E-03

9.170210E-03

-4.209500E-03

-4.209520E-03

8.528500E-03

8.744210E-03

-3.937500E-03

-3.882120E-03

7.835000E-03

8.017360E-03

-3.453500E-03

-3.368120E-03

1.983000E-04

2.002130E-04

-8.000000E-05

-8.174260E-05

2.829500E-04

2.653530E-04

-1.287000E-04

-1.210930E-04

3.639500E-04

3.482740E-04

-1.669500E-04

-1.658220E-04

4.283000E-04

4.389760E-04

-1.971000E-04

-2.127100E-04

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0.35um CMOS Devices Model Parameters

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b) T = 70C

Idsat (NMOS)
L/W(um/um)
20/20
20/0.4
20/0.6
20/0.8
20/1
0.35/20
0.4/20
0.45/20
0.5/20
0.6/20
0.35/0.4
0.35/0.6
0.35/0.8
0.35/1

Idsat (PMOS)

Measured
3.925000E-04

Model
4.196288E-04

Measured
-1.224500E-04

Model
-1.305244E-04

4.627830E-06

4.252131E-06

-1.147600E-06

-1.117772E-06

6.104500E-06

6.268968E-06

-2.159500E-06

-2.103332E-06

8.756000E-06

9.449263E-06

-3.023000E-06

-3.265779E-06

1.207000E-05

1.308652E-05

-4.059000E-06

-4.495857E-06

9.434500E-03

9.534527E-03

-4.903000E-03

-4.837226E-06

8.686500E-03

8.964252E-03

-4.369500E-03

-4.366467E-03

8.278500E-03

8.471779E-03

-3.967000E-03

-3.983063E-03

7.745000E-03

8.039644E-03

-3.695500E-03

-3.665327E-03

7.090000E-03

7.310801E-03

-3.221500E-03

-3.169250E-03

1.847500E-04

1.870207E-04

-7.634000E-05

-7.876594E-05

2.632500E-04

2.479158E-04

-1.229000E-04

-1.163457E-04

3.382000E-04

3.254147E-04

-1.591000E-04

-1.590469E-04

3.978500E-04

4.101861E-04

-1.881000E-04

-2.037952E-04

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0.35um CMOS Devices Model Parameters

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c) T = 125C

Idsat (NMOS)
L/W(um/um)
20/20
20/0.4
20/0.6
20/0.8
20/1
0.35/20
0.4/20
0.45/20
0.5/20
0.6/20
0.35/0.4
0.35/0.6
0.35/0.8
0.35/1

Idsat (PMOS)

Measured
3.101000E-04

Model
3.494474E-04

Measured
-1.080350E-04

Model
-1.231426E-04

3.950730E-06

3.575037E-06

-1.084500E-06

-1.054692E-06

5.317500E-06

5.256216E-06

-1.954000E-06

-1.982235E-06

7.463500E-06

7.905923E-06

-2.720500E-06

-3.077264E-06

1.062000E-05

1.093558E-05

-3.640000E-06

-4.236705E-06

8.626500E-03

8.750879E-03

-4.619500E-03

-4.611403E-03

7.930500E-03

8.172528E-03

-4.095000E-03

-4.155214E-03

7.455000E-03

7.677975E-03

-3.703000E-03

-3.784749E-03

6.947000E-03

7.248096E-03

-3.437500E-03

-3.478510E-03

6.275000E-03

6.532418E-03

-2.977500E-03

-3.001903E-03

1.772000E-04

1.717034E-04

-7.279000E-05

-7.595979E-05

2.519500E-04

2.276437E-04

-1.167500E-04

-1.118825E-04

3.313000E-04

2.988113E-04

-1.507500E-04

-1.526956E-04

3.826000E-04

3.766527E-04

-1.786000E-04

-1.954588E-04

1.5 Simulated Critical Parameters

Typical case model
Width/Length

VT_N

IDSAT_N

VT_P

IDSAT_P

(unit: um)

(unit: V)

(unit: uA/um)

(unit: V)

(unit: uA/um)

Short, 20/0.35

0.5651

510

-0.7079

-255

Large, 20/20

0.4233

25

-0.6068

-7

MIMOS INTERNAL USE ONLY

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0.35um CMOS Devices Model Parameters

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1.6 Measured versus Simulated Results of Ring Oscillator

Eleven different ring oscillator sub-circuits are used in the transistor model verification. The
descriptions of the related inverter ring oscillator are as follows:
Name

Gate length

Fan-out

Stage #

RO1

0.35um

31

RO2

0.35um

31

RO3

0.35um

31

RO4

0.35um

31

RO5

0.35um

101

RO6

0.35um

257

RO7

0.5um

101

RO8

1.0um

101

RO9

0.35um

101

RO10

0.5um

101

RO11

1.0um

101

The total simulation delay of the related ring oscillators are as follows:
Ring_osc
RO1

Measured
delay (ns)
4.525

Simulated
delay (ns)
4.755

RO2

8.448

8.650

RO3

10.58

10.66

RO4

16.86

16.81

RO5

14.32

15.31

RO6

36.36

38.82

RO7

21.21

23.07

RO8

53.87

58.37

RO9

33.90

34.52

RO10

54.05

55.88

RO11

156.6

160.8

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1.7 BSIM3v3 Corner-case Models

The skew parameters are listed below for corner-case simulation. Users can change these
parameters in the model file to generate the worst case simulation. The skewed parameters for the
worst-case are as follows:
Device

Parameter

Unit

TT

SS

FF

SF

FS

NMOS

TOX

7.0E-09

7.5E-09

6.5E-09

7.0E-09

7.0E-09

NMOS

XL

0.02E-06

-0.02E-06

NMOS

VTH0

0.4182

0.5182

0.3182

0.5182

0.3182

NMOS

CJ

F/m^2

1.514E-03

1.665E-03

1.399E-03

1.665E-03

1.399E-03

NMOS

CJSW

F/m

6.898E-10

7.588E-10

6.208E-10

7.588E-10

6.208E-10

NMOS

CGDO

F/m

2E-10

2.2E-10

1.8E-10

2E-10

2E-10

NMOS

CGSO

F/m

2E-10

2.2E-10

1.8E-10

2E-10

2E-10

PMOS

TOX

7.0E-09

7.5E-09

6.5E-09

7.0E-09

7.0E-09

PMOS

XL

0.02E-06

-0.02E-06

PMOS

VTH0

-0.6043

-0.6793

-0.5293

-0.5293

-0.6793

PMOS

CJ

F/m^2

1.216E-03

1.338E-03

1.094E-03

1.094E-03

1.338E-03

PMOS

CJSW

F/m

5.236E-10

5.760E-10

4.712E-10

4.712E-10

5.760E-10

PMOS

CGDO

F/m

2.05E-10

2.255E-10

1.845E-10

2.05E-10

2.05E-10

PMOS

CGSO

F/m

2.05E-10

2.255E-10

1.845E-10

2.05E-10

2.05E-10

Notes:
(1)

TT is the typical case model, SS is the worst case model, FF is the best case model, SF is
slow NMOS and fast PMOS model while FS is fast NMOS and slow PMOS model.

(2)

Using corner model, you can add these skew parameters directly into typical model. ( e.g.
TOX, XL, VTH0, CJ, CJSW, CGDO and CGSO)

(3)

The worst case values for CJ and CJSW are based on assumption of 10% variation in the
process variation of P+, N+ and well implantation.

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2.

BIPOLAR GUMMEL-POON MODEL

2.1

Flexibility of Model
(a) Two parasitic bipolar models are available for this 0.35 um CMOS technology, namely
vpnp10 for vertical pnp 10x10 and vpnp5 for vertical pnp 5x5.
(b) Parameters are extracted from vertical P+/NW/PSUB test pattern.
(c) The model is suitable for forward mid-current and constant BF operating ranges.
(d) The nominal temperature is 25 C and the valid temperature range is 25 C ~ 125 C.
(e) The layout and sizes of bipolar transistor used for fitting are:

(i) Emitter area, vpnp10 = 10 * 10 = 100 um2, base area = 13.8 * 13.8 = 190.44 um2
13.8 um
10 um

B
E

P+

N+

P+diff

N+

P+

N-WELL

0.55 um
0.75 um

(ii) Emitter area, vpnp5 = 5 * 5 = 25 um2, base area = 8.8 * 8.8 = 77.44 um2
8.8 um
5 um

B
E

P+

N+

P+diff

N+

P+

N-WELL

0.55 um
0.75 um

MIMOS INTERNAL USE ONLY

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2.2

0.35um CMOS Devices Model Parameters

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Parameter List

LEVEL

Model selector (Level 1 for Gummel-Poon in HSPICE)

IS

Transport saturation current

BF

Ideal maximum forward Beta

NF

Forward current emission coefficient

BR

Ideal maximum reverse Beta

NR

Reverse current emission coefficient

ISE

Base emitter leakage saturation current

NE

Base emitter leakage emission coefficient

ISC

Base collector leakage saturation current

NC

Base collector leakage emission coefficient

VAF

Forward early voltage

VAR

Reverse early voltage

IKF

Knee current for forward Beta high current roll-off

IKR

Knee current for reverse Beta high current roll-off

RB

Zero bias base resistance

RBM

Minimum base resistance

IRB

Base resistance roll-off current

RE

Emitter resistance

RC

Collector resistance

XTB

Forward and reverse Beta temperature exponent

EG

Energy gap for modeling temperature

XTI

Temperature exponent for modeling

TRB1

RB linear temperature coefficient

TRC1

RC linear temperature coefficient

TIKF1

IKF linear temperature coefficient

MIMOS INTERNAL USE ONLY

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2.3

0.35um CMOS Devices Model Parameters

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SPICE Model

**********************************************************************
* 0.35 um CMOS Process (2P3M)
* PARASITIC BIPOLAR GUMMEL-POON MODELS
* Device Name: vpnp10 Model name: vpnp10 Emitter size = 10um x 10um
* Device Name: vpnp5
Model name: vpnp5
Emitter size = 5um x 5um
**********************************************************************
*
*
.LIB parasitic_pnp
*
.MODEL vpnp10 pnp (
LEVEL = 1
+ IS
= 1.094E-016
BF
= 2.554
NF
= 1.046
+ BR
= 0.3315
NR
= 1.053
ISE
= 5.59E-018
+ NE
= 1.122
ISC
= 7.657E-014
NC
= 1.348
+ VAF
= 201
VAR
= 15.65
IKF
= 0.001848
+ IKR
= 0.1
RB
= 83.9
RBM
= 11.64
+ IRB
= 1.004E-015
RE
= 45.61
RC
= 157.8
+ XTB
= 1.84
EG
= 1.16
XTI
= 3.68
+ TRB1 = 0.0198
TRC1 = 0.02
TIKF1 = -3.07E-003 )
*
.MODEL vpnp5 pnp (
LEVEL = 1
+ IS
= 3.76E-017
BF
= 3.087
NF
= 1.051
+ BR
= 0.2069
NR
= 1.046
ISE
= 1.044E-018
+ NE
= 1.102
ISC
= 3.516E-014
NC
= 1.316
+ VAF
= 193.2
VAR
= 12.91
IKF
= 0.0009233
+ IKR
= 0.1
RB
= 109.8
RBM
= 0.675
+ IRB
= 7.827E-005
RE
= 49.64
RC
= 166.6
+ XTB
= 1.92
EG
= 1.16
XTI
= 3.68
+ TRB1 = 0.0153
TRC1 = 0.02
TIKF1 = -3.29E-003 )
*
.ENDL parasitic_pnp

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DIODE MODEL

The parameters are extracted from P+/N-WELL (p-type) and N+/P-WELL (n-type) diode structures.
The nominal temperature is 25C and the valid temperature range is up to 125C.
DC diode measurements are swept from -0.7V to -0.02V while junction diode capacitance
measurements are swept from -3.3V to 0.2V for n-type diode. HSPICE junction diode model level 3
is used.
3.1 Parameter List
LEVEL
IS
JSW
N
RS
IK
IKR
VB
IBV
TRS
CTA
CTP
EG
TCV
GAP1
GAP2
TLEV
FC
TREF
TLEVC
FCS
TPB
TPHP
XTI
CJ
MJ
PB
CJSW
MJSW
PHP

Diode model selector

Saturation current
Sidewall saturation current per unit junction periphery
Emission coefficient
Ohmic series resistance
Forward knee current
Reverse knee current
Reverse breakdown voltage
Current at breakdown voltage
Resistance temperature coefficient
Temperature coefficient for area junction cap
Temperature coefficient for periphery junction cap
Energy gap for pn junction diode
Breakdown voltage temperature coefficient
First bandgap correction factor
Second bandgap correction factor
Temperature equation selection for diode
Coefficient for forward-bias depletion area cap formula
Model reference temperature
Level selector for diode temperature
Coefficient for forward-bias depletion periphery
Temperature coefficient for PB
Temperature coefficient for PHP
Saturation current temperature exponent
Zero-bias junction capacitance per unit junction area
Area junction grading coefficient
Area junction contact potential
Zero-bias junction cap per unit junction periphery
Periphery junction grading coefficient
Periphery junction contact potential

MIMOS INTERNAL USE ONLY

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3.2

0.35um CMOS Devices Model Parameters

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SPICE Model

**********************************************************************
* 0.35 um CMOS Process (2P3M)
* HSPICE DIODE MODELS
* Device Name: ndiode
Model name: ndiode
n-type diode
* Device Name: pdiode
Model name: pdiode
p-type diode
*
**********************************************************************
* how to use:
*
Diode n-type:
ndiode
*
.lib 'mimos_analog.lib' diodes
*
D1 1 4 ndiode AREA=100p PJ=104u
*
*
Diode p-type:
pdiode
*
.lib 'mimos_analog.lib' diodes
*
D1 1 4 ndiode AREA=100p PJ=104u
*
*--------------------------------------------------------------*
*
* AREA and PJ should be specify according to layout
*
.lib diodes
* hspice level-3
.model pdiode D
+LEVEL = 3
IS = 1.572E-006
JSW = 5.788E-012
+N = 1.104
RS = 5.958E-007
IK = 2.11E+007
+IKR = 0.00
VB = 10
IBV = 0.001
+LM = 0.00
LP = 0.00
WM = 0.00
+WP = 0.00
XM = 0.00
XOI = 1.00E+04
+XOM = 1.00E+04
XP = 0.00
XW = 0.00
+TRS = 0
CTA = -0.002186
CTP = 0.00103
+EG = 1.16
TCV = -0.0006
GAP1 = 4.73E-04
+GAP2 = 1.11E+03
TLEV = 1
FC = 0
+TREF = 25.0
TLEVC = 1
FCS
= 0
+TPB = 0.0003136
TPHP = 0.001592
XTI = 1
+CJ = 0.001216
MJ = 0.5213
PB = 1.073
+CJSW = 5.236E-010
MJSW = 0.5213
PHP = 0.8500
+AREA = 3.92E-008
PJ = 0.00084
*
* hspice level-3
.model ndiode D
+LEVEL = 3
IS = 8.298E-006
JSW = 2.961E-011
+N = 1.220
RS = 2.771E-007
IK = 2.11E+007
+IKR = 0.00
VB = 10
IBV = 0.001
+LM = 0.00
LP = 0.00
WM = 0.00
+WP = 0.00
XM = 0.00
XOI = 1.00E+04
+XOM = 1.00E+04
XP = 0.00
XW = 0.00
+TRS = 0
CTA = -0.003085
CTP = 4.441E-018
+EG = 1.16
TCV = -0.0006
GAP1 = 4.73E-04
+GAP2 = 1.11E+03
TLEV = 1
FC = 0
+TREF = 25.0
TLEVC = 1
FCS
= 0
+TPB = 0.0003112
TPHP = 0.005429
XTI = 1
+CJ = 0.001514
MJ = 0.3994
PB = 0.8828
+CJSW = 6.898E-010
MJSW = 0.2862
PHP = 0.7734
+AREA = 3.92E-008
PJ = 0.00084
*
*
.ENDL diodes
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0.35um CMOS Devices Model Parameters

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RESISTOR MODEL
There are 5 resistor models which are extracted from different 2-point probe resistor structures.
The resistor models are RPOLYH, RPOLY1, RNWELL, RNDIFF and RPDIFF. The model
parameters of the resistor models are functions of the width and length of the resistor, where
one model for each type of resistor could cover different sizes.
Resistors are measured at 3 different temperatures and the temperature parameters are valid
from 25 C to 125 C. The resistor models are valid up to 3.3V. First and second order voltage
coefficients are also extracted.

4.1

Parameter List

RSH
TC1
TC2
TEMPER
DEL
VC1
VC2

Sheet resistance value

First order temperature coefficient for resistor
Second order temperature coefficient for resistor
Temperature node
Difference between drawn length/width and actual length/width
First order voltage coefficient for resistor
Second order voltage coefficient for resistor

4.2 RPOLYH SPICE Model

*
* rpolyh = model for RPOLYH
*
.subckt rpolyh 1 2 l=length w=width
.param rsh=1192
tc1=-683.5e-6
tc2=450.3e-9 t='temper'
.param tpar='1.0+tc1*(t-25.0)+tc2*(t-25.0)*(t-25.0)'
.param vc1=1.00e-06
vc2=1.00e-06
.param dw=39.02e-09
dlr=1.849e-06
r1 1 2 'rsh*((L-(2*dlr))/(W-(2*dw)))*(1+vc1*abs(v(2,1))+vc2*v(2,1)*v(2,1))*tpar'
.ends rpolyh
*

4.3 RPOLY1 SPICE Model

*
* rpoly1 = model for RPOLY1
*
.subckt rpoly1 1 2 l=length w=width
.param rsh=101.3
tc1=334.1e-6 tc2=2.480e-6 t='temper'
.param tpar='1.0+tc1*(t-25.0)+tc2*(t-25.0)*(t-25.0)'
.param vc1=2.206e-04
vc2=1.6408e-04
.param dw=81.00e-09
dlr=3.978e-06
r1 1 2 'rsh*((L-(2*dlr))/(W-(2*dw)))*(1+vc1*abs(v(2,1))+vc2*v(2,1)*v(2,1))*tpar'
.ends rpoly1
*

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4.4 RNWELL SPICE Model

*
* nwl = model for RNWELL
*
.subckt nwl 1 2 l=length w=width
.param rsh=1556
tc1=3.038e-3 tc2=23.06e-6 t='temper'
.param tpar='1.0+tc1*(t-25.0)+tc2*(t-25.0)*(t-25.0)'
.param vc1=13e-03
vc2=1e-06
.param dw=244.3e-09
dlr=5.916e-06
r1 1 2 'rsh*((L-(2*dlr))/(W-(2*dw)))*(1+vc1*abs(v(2,1))+vc2*v(2,1)*v(2,1))*tpar'
.ends nwl
*

4.5 RNDIFF SPICE Model

*
* dfn = model for RNDIFF
*
.subckt dfn 1 2 l=length w=width
.param rsh=146.75
tc1=1.122e-3 tc2=4.514e-6 t='temper'
.param tpar='1.0+tc1*(t-25.0)+tc2*(t-25.0)*(t-25.0)'
.param vc1=90.00e-05
vc2=1.00e-06
.param dw=679.0e-09
dlr=16.29e-06
r1 1 2 'rsh*((L-(2*dlr))/(W-(2*dw)))*(1+vc1*abs(v(2,1))+vc2*v(2,1)*v(2,1))*tpar'
.ends dfn
*

4.6 RPDIFF SPICE model

*
* dfp = model for RPDIFF
*
.subckt dfp 1 2 l=length w=width
.param rsh=207.2
tc1=802.8e-6 tc2=3.549e-6 t='temper'
.param tpar='1.0+tc1*(t-25.0)+tc2*(t-25.0)*(t-25.0)'
.param vc1=90.00e-05
vc2=1.00e-06
.param dw=81.81e-09
dlr=1.400e-06
r1 1 2 'rsh*((L-(2*dlr))/(W-(2*dw)))*(1+vc1*abs(v(2,1))+vc2*v(2,1)*v(2,1))*tpar'
.ends dfp
*

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0.35um CMOS Devices Model Parameters

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4.7 Example on how to run the model

Simulation Input File for Resistor Model

.options
+ POST=1
.SUBCKT Rpolyh_L100_W2 1 2
.lib '035resistor.mod' RPOLYH
* For RPOLYH resistor example
XR 1 2 rpolyh
+ W = 2E-006
+ L = 0.0001
.ends
XCKT 1 2 Rpolyh_L100_W2
* START SOURCES
V2GRO 2 0 DC 0
V1GRO 1 0 DC 0
* END SOURCES
.TEMP 27
.DC V1GRO 0 3.3 0.1
.PRINT DC I(V1GRO)
.END

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0.35um CMOS Devices Model Parameters

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Page 25 of 105

CAPACITOR MODEL

The capacitor model was extracted from 2 different PIP capacitors of sizes100u x 100u and 200u x
200u respectively. Beside that, the NCAP and PCAP models are also provided.
5.1 Parameter List
COX
DEL
TC1
TC2
TEMPER
VC1
VC2

Bottomwall capacitance
Difference between drawn width and actual width or length
First order temperature coefficient for capacitor
Second order temperature coefficient for capacitor
Temperature node
First order voltage coefficient
Second order voltage coefficient

5.2 SPICE model

*
.LIB capacitance
*
*
* cpoly = PIP capacitor
*
*
.subckt cpoly pos neg
.param pip_cox=1.0857951e-3 tc1=4.5268020e-5 tc2=-8.3248820e-9 t='temper'
.param tpar='1.0+tc1*(t-25.0)+tc2*(t-25.0)*(t-25.0)'
.param vc1=-3.50e-04
vc2=1e-6
.param del=7.6884939e-07
.param pip_carea='pip_cox*(w-(2*del))*(l-(2*del))'
.param pip_ct='pip_carea*tpar'
c1 pos neg c='pip_ct*(1+vc1*(v(pos,neg))+vc2*v(pos,neg)*v(pos,neg))'
.ends cpoly
*
*
*
* ncap = NMOS capacitor
*
*
.subckt ncap 1 2
.param tcv1=49.048e-6 tcv2=719.2085e-9
mcap 3 4 3 3 mosmod
rgate 1 4 r=10 tc1=1.2e-3 tc2=3.6e-6
rwell 3 2 r=0.02 tc1=1.2e-2 tc2=3.6e-5
.model mosmod nmos level=49
+ version=3.24
paramchk=1
+ tox=7.98e-09
nch=2.261e17
+ vth0=0.4182
k1=0.5398
+ moin=15
noff=0.5
+ dwc=2.433e-7
dlc=1.32e-8
+ cdsc=0
cdscb=0
+ is=1e-18
js=0
+ cj=1e-15
cjsw=0
+ cgdo=1e-15
cgso=1e-15
+ rs=1e10
rd=1e10

MIMOS INTERNAL USE ONLY

tref=25
nsub=6e16
acde=1

cdscd=0
jsw=0
cgbo=0

Page 25 of 105

0.35um CMOS Devices Model Parameters

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Page 26 of 105

+ kt1=-0.3942
kt2=-0.04349
+voffcv='(tcv2*temper*temper+tcv1*temper+5.5)'
.ends
*
*
*
*
* pcap = PMOS capacitor
*
*
.subckt pcap 1 2
.param tcv1=49.048e-6 tcv2=719.2085e-9
mcap 3 4 3 3 mosmod
rgate 1 4 r=10 tc1=1.2e-3 tc2=3.6e-6
rwell 3 2 r=0.02 tc1=1.2e-2 tc2=3.6e-5
.model mosmod pmos level=49
+ version=3.24
paramchk=1
tref=25
+ tox=8.88e-09
nch=1.778e17
nsub=6e16
+ vth0=-0.9543
k1=0.6112
acde=1
+ moin=15
noff=0.5
+ dwc=2.17e-7
dlc=2.224e-8
+ cdsc=0
cdscb=0
cdscd=0
+ is=1e-18
js=0
jsw=0
+ cj=1e-15
cjsw=0
+ cgdo=1e-15
cgso=1e-15
cgbo=0
+ rs=1e10
rd=1e10
+ kt1=-0.7123
kt2=-0.07602
+voffcv='(tcv2*temper*temper+tcv1*temper+5.5)'
.ends
*
*
*
.ENDL capacitance

MIMOS INTERNAL USE ONLY

Page 26 of 105

0.35um CMOS Devices Model Parameters

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Date: 24/02/2011

Page 27 of 105

5.3 Example on how to run the model

Simulation Input File for Capacitor Model

.options
+ TNOM = 25
+ POST=1
*
.lib '035capacitor.mod' cpoly
* For CPOLY capacitor example
.SUBCKT Cap_100u_100u 1 2
XC1 1 2 cpoly
+ W=0.0001 L=0.0001
.ENDS
XCKT 1 2 Cap_100u_100u
* Start sources
Vp10 4 0 AC 1 0
Vpp1 1 4 DC 0
Vp1 2 0 DC 0.0
* End sources
I2 2 0 0.0
.TEMP 25
.AC LIN 1 1MEG SWEEP Vpp1 LIN 67 -3.3 3.3
.OPTION CAPTAB=1
.PLOT AC I(Vp1)
.PRINT AC CAP(2)
.END

MIMOS INTERNAL USE ONLY

Page 27 of 105

6.0

0.35um CMOS Devices Model Parameters

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Date: 24/02/2011

Page 28 of 105

Interconnection Line Line Capacitance

The interconnect capacitance simulation results using Raphael (Synopsys) field solver are listed in
this section. The simulation structure is: Structure A shown below Conductor array above the
infinite plate:

Notes:
1. The condition line is using the minimum width of design rule.
2. For Structure A, the top layer is used as a conduction line layer and the bottom conduction
layer are used as the infinite plate.

MIMOS INTERNAL USE ONLY

Page 28 of 105

6.1

Structure
PO-FOX
PO2-FOX
PO2-PO
M1-FOX
M1-OD
M1-PO
M1-PO2
M2-FOX
M2-OD
M2-PO
M2-PO2
M2-M1
M3-FOX
M3-OD
M3-PO
M3-PO2
M3-M1
M3-M2

0.35um CMOS Devices Model Parameters

MYSC02-403

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Date: 24/02/2011

Page 29 of 105

Typical Interconnect Capacitance Table

Width

Space

Csum

Ccoupli

Cgnd

Cfringe

Carea

(um)

(um)

(fF/um)

(fF/um)

(fF/um)

(fF/um)

(fF/um2)

0.65
0.65
0.35
0.35
0.35
0.35
0.50
0.50
0.50
0.50
0.50
0.50
0.50
0.50
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60

0.50
2.5
0.45
2.50
0.45
2.50
0.45
2.50
0.45
2.50
0.45
2.50
0.45
2.50
0.50
2.50
0.50
2.50
0.50
2.50
0.50
2.50
0.50
2.50
0.50
2.50
0.50
2.50
0.50
2.50
0.50
2.50
0.50
2.50
0.50
2.50

1.26E-01
1.24E-01
1.82E-01
1.47E-01
5.78E-01
5.67E-01
2.74E-01
1.48E-01
2.98E-01
1.75E-01
2.62E-01
1.43E-01
2.73E-01
1.50E-01
2.33E-01
1.32E-01
2.23E-01
1.30E-01
1.99E-01
1.03E-01
2.02E-01
1.04E-01
2.00E-01
1.20E-01
3.18E-01
1.65E-01
3.07E-01
1.60E-01
1.60E-01
9.50E-02
2.68E-01
1.22E-01
2.68E-01
1.32E-01
2.73E-01
1.57E-01

9.87E-03
1.44E-03
4.76E-02
3.87E-03
2.98E-02
2.15E-03
1.08E-01
1.45E-02
1.12E-01
1.74E-02
1.03E-01
1.75E-02
1.08E-01
1.84E-02
9.16E-02
1.72E-02
8.56E-02
1.45E-02
8.30E-02
1.81E-02
8.40E-02
1.83E-02
7.41E-02
1.03E-02
1.35E-01
3.82E-02
1.29E-01
3.54E-02
6.41E-02
1.95E-02
1.19E-01
3.21E-02
1.14E-01
2.74E-02
1.06E-01
2.46E-02

1.06E-01
1.21E-01
8.65E-02
1.39E-01
5.19E-01
5.62E-01
5.77E-02
1.19E-01
7.37E-02
1.41E-01
5.51E-02
1.08E-01
5.69E-02
1.13E-01
5.01E-02
9.78E-02
5.22E-02
1.01E-01
3.34E-02
6.64E-02
3.38E-02
6.73E-02
5.20E-02
9.91E-02
4.86E-02
8.87E-02
4.85E-02
8.93E-02
3.18E-02
5.60E-02
2.97E-02
5.75E-02
4.00E-02
7.73E-02
6.10E-02
1.08E-02

1.79E-02
2.54E-02
2.33E-02
4.96E-02
7.50E-02
9.67E-05
1.40E-02
4.49E-02
1.88E-02
5.22E-02
1.44E-02
4.10E-02
1.49E-02
4.29E-02
1.27E-02
3.65E-02
1.27E-02
3.71E-02
8.79E-03
2.53E-02
8.88E-03
2.56E-02
1.20E-02
3.55E-02
1.47E-02
3.47E-02
1.43E-02
3.48E-02
9.86E-03
2.20E-02
8.76E-03
2.27E-02
1.12E-02
2.98E-02
1.63E-02
3.98E-02

1.08E-01
1.08E-01
1.14E-01
1.14E-01
1.05E00
1.05E00
5.95E-02
5.95E-02
7.23E-02
7.23E-02
5.25E-02
5.25E-02
5.41E-02
5.41E-02
4.13E-02
4.13E-02
4.45E-02
4.45E-02
2.64E-02
2.64E-02
2.67E-02
2.67E-02
4.66E-02
4.66E-02
3.21E-02
3.21E-02
3.30E-02
3.30E-02
2.02E-02
2.02E-02
2.03E-02
2.03E-02
2.95E-02
2.95E-02
4.75E-02
4.75E-02

MIMOS INTERNAL USE ONLY

Page 29 of 105

7.0

0.35um CMOS Devices Model Parameters

MYSC02-403

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Date: 24/02/2011

Page 30 of 105

SUPPORT

For questions or information, please contact

Iskhandar Md Nasir (Senior Staff Engineer)
Tel: +60 3 8995 5000 ext5149, +60 3 8657 9907 (DL)
Email: iskhand@mimos.my
Muhamad Amri Ismail (Senior Engineer, Design Library)
Tel: +60 3 8995 5000 ext5220
Email: amris@mimos.my
MIMOS Wafer Fab Design Library
Mimos Berhad, Technology Park Malaysia, 57000 Kuala Lumpur, Malaysia
Tel: +603 8995 5000

MIMOS INTERNAL USE ONLY

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0.35um CMOS Devices Model Parameters

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Date: 24/02/2011

Page 31 of 105

APPENDIX 1: Fitting Results for MOS Transistor Model

Attached are the IV fitting results of NMOS and PMOS at 3-different temperatures
1. Figure 1a to 14a Fitting Id vs. Vd & Vg, transfer and output characteristic of 3.3V NMOS
with different channel width (W) and length (L) at T=27C.
2. Figure 1b to 14b Fitting Id vs. Vd & Vg, transfer and output characteristic of -3.3V PMOS
with different channel width (W) and length (L) at T=27C.
3. Figure 15a to 16a Fitting Rout vs. Vd, for short and small devices of NMOS
4. Figure 15b to 16b Fitting Rout vs. Vd, for short and small devices of PMOS
5. Figure 17a Fitting of CV curves, at T=27C of NMOS
6. Figure 17a Fitting of CV curves, at T=27C of PMOS
7. Figure 18a to 21a Fitting Id vs. Vd & Vg, transfer and output characteristic of 3.3V NMOS
with different channel width (W) and length (L) at T=70C for length scale devices.
8. Figure 22a to 25a Fitting Id vs. Vd & Vg, transfer and output characteristic of 3.3V NMOS
with different channel width (W) and length (L) at T=125C for length scale devices.
9. Figure 18b to 21b Fitting Id vs. Vd & Vg, transfer and output characteristic of 3.3V PMOS
with different channel width (W) and length (L) at T=70C for length scale devices.
10. Figure 22b to 25b Fitting Id vs. Vd & Vg, transfer and output characteristic of 3.3V PMOS
with different channel width (W) and length (L) at T=125C length scale devices.
The explanation about the different W and L are as follows:
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14

Device
Large_m
Narrow_m
Narrow_m1
Narrow_m2
Narrow_m3
Short_m
Short_m1
Short_m2
Short_m3
Short_m4
Small_m
Small_m1
Small_m2
Small_m3

L (um)
20
20
20
20
20
0.35
0.4
0.45
0.5
0.6
0.35
0.35
0.35
0.35

MIMOS INTERNAL USE ONLY

W (um)
20
0.4
0.6
0.8
1
20
20
20
20
20
0.4
0.6
0.8
1

Size category
Ideal transistor
Wide transistor
Width scale
Width scale
Width scale
Short transistor
Length scale
Length scale
Length scale
Length scale
Small device
Length & width scale
Length & width scale
Length & width scale

Page 31 of 105

0.35um CMOS Devices Model Parameters

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Date: 24/02/2011

Page 32 of 105

idvg @ low Vds

L=20um
W=20um

NMOS
1.00E-03

3.00E-05

1.00E-06

Ids (A)

Ids (A)

NMOS
4.00E-05

2.00E-05

=0
Vbs stop = -3.3
Vbs step =-0.55
Vds
= 0.1
measure
simulate

idvg @ low Vds

L=20u
W=20u

1.00E-09

Vbs start
1.00E-05

Vbs start

0.00E+00
0.00

1.00

2.00

3.00

=0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

Vgs (V)

NMOS

3.00

4.00

Vgs (V)

idvd @ vbs=0V
L=20um
W=20um

NMOS

6.00E-04

Gds @ vbs=0V
L=20um
W=20um

4.00E-04

3.00E-04

Ids (A)

Gds (1/ohm)

4.00E-04

2.00E-04

2.00E-04

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

1.00E-04

0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 1a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=20/20. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

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0.35um CMOS Devices Model Parameters

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Rev 4.0

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Date: 24/02/2011

Page 33 of 105

idvg @ low Vds

L=20um W=0.4um

NMOS

idvg @ low Vds

L=20um W=0.4um

NMOS

4.00E-07
1.00E-05

1.00E-07

3.00E-07

Ids (A)

Ids (A)

1.00E-09

2.00E-07

1.00E-11

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

1.00E-07

0.00E+00
0.00

1.00

2.00

3.00

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

1.00E-13

1.00E-15
0.00

4.00

1.00

Vgs (V)

2.00

3.00

4.00

Vgs (V)

idvd @ vbs=0V
NMOS
L=20 W=0.4

NMOS

Gds @ vbs=0V
L=20um W=0.4um

4.00E-06

6.00E-06

3.00E-06

Ids (A)

Gds (1/ohm)

4.00E-06

2.00E-06

2.00E-06

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

1.00E-06

0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 2a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=0.4/20. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

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0.35um CMOS Devices Model Parameters

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Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 34 of 105

idvg @ low Vds

L=20um
W=0.6um

NMOS
1.00E-03

6.00E-07

1.00E-06

Ids (A)

Ids (A)

NMOS
8.00E-07

4.00E-07

=0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

idvg @ low Vds

L=20um
W=0.6um

1.00E-09

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

Vbs start
2.00E-07

0.00E+00
0.00

1.00

2.00

3.00

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

Vgs (V)

3.00

4.00

Vgs (V)

NMOS

idvd @ vbs=0V
NMOS
L=20um
W=0.6um

Gds @ vbs=0V
L=20um
W=0.6um

8.00E-06

8.00E-06

6.00E-06

Gds (1/ohm)

Ids (A)

6.00E-06

4.00E-06

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-06

0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

4.00E-06

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-06

0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 3a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=0.6/20. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

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0.35um CMOS Devices Model Parameters

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Date: 24/02/2011

Page 35 of 105

NMOS

idvg @ low Vds

L=20um
W=0.8um

NMOS

1.20E-06

idvg @ low Vds

L=20um
W=0.8um

1.00E-03

1.00E-06

Ids (A)

Ids (A)

8.00E-07

1.00E-09

4.00E-07

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

Vgs (V)

NMOS

3.00

4.00

Vgs (V)

idvd @ vbs=0V
L=20um
W=0.8um

NMOS

Gds @ vbs=0V
L=20um
W=0.8um

1.00E-05

1.20E-05

8.00E-06

Ids (A)

Gds (1/ohm)

8.00E-06

6.00E-06

4.00E-06
4.00E-06

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-06

0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 4a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=0.8//20. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

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0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 36 of 105

idvg @ low Vds

L=20um
W=1um

NMOS
1.00E-03

1.20E-06

1.00E-06

Ids (A)

Ids (A)

NMOS
1.60E-06

8.00E-07

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

4.00E-07

0.00E+00
0.00

1.00

2.00

3.00

1.00E-09

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

idvg @ low Vds

L=20um
W=1um

1.00

2.00

idvd @ vbs=0V
L=20um
W=1um

NMOS

1.60E-05

1.60E-05

1.20E-05

1.20E-05

Gds (1/ohm)

Ids (A)

NMOS

8.00E-06

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

4.00E-06

0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs (V)

Vgs (V)

3.00

4.00

Gds @ vbs=0V
L=20um
W=1um

8.00E-06

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

4.00E-06

0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 5a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=1/20. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

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0.35um CMOS Devices Model Parameters

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Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 37 of 105

NMOS

idvg @ low Vds

L=0.35um
W=20um

NMOS

1.60E-03

idvg @ low Vds

L=0.35um
W=20um

1.00E+00

1.00E-03
1.20E-03

Ids (A)

Ids (A)

1.00E-06

8.00E-04

1.00E-09

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

4.00E-04

0.00E+00
0.00

1.00

2.00

3.00

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

Vgs (V)

NMOS

3.00

4.00

Vgs (V)

idvd @ vbs=0V
L=0.35um
W=20um

NMOS

1.20E-02

Gds @ vbs=0V
L=0.35um
W=20um

1.60E-02

1.20E-02

Ids (A)

Gds (1/ohm)

8.00E-03

8.00E-03

4.00E-03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

4.00E-03

0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 6a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=20/0.35. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 37 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 38 of 105

NMOS

idvg @ low Vds

L=0.4um
W=20um

NMOS

1.60E-03

idvg @ low Vds

L=0.4um
W=20um

1.00E+00

1.00E-03
1.20E-03

Ids (A)

Ids (A)

1.00E-06

8.00E-04

1.00E-09

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

4.00E-04

0.00E+00
0.00

1.00

2.00

3.00

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

Vgs (V)

NMOS

3.00

4.00

Vgs (V)

idvd @ vbs=0V
L=0.4um
W=20um

NMOS

Gds @ vbs=0V
L=0.4um
W=20um

1.60E-02

1.20E-02

1.20E-02

Ids (A)

Gds (1/ohm)

8.00E-03

8.00E-03

4.00E-03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

4.00E-03

0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 7a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=20/0.4. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 38 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 39 of 105

NMOS

idvg @ low Vds

L=0.45um
W=20um

NMOS

idvg @ low Vds

L=0.45um
W=20um

1.00E+00

1.20E-03

1.00E-03

8.00E-04

Ids (A)

Ids (A)

1.00E-06

1.00E-09
4.00E-04

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

NMOS

3.00

4.00

Vgs (V)

Vgs (V)

idvd @ vbs=0V
L=0.45um
W=20um

NMOS
1.20E-02

8.00E-03

8.00E-03

Ids (A)

Gds (1/ohm)

1.20E-02

Gds @ vbs=0V
L=0.45um
W=20um

4.00E-03

4.00E-03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 8a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=20/0.45. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 39 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 40 of 105

NMOS

NMOS

idvg @ low Vds

L=0.5um
W=20um

idvg @ low Vds

L=0.5um
W=20um

1.00E+00

1.20E-03

1.00E-03

8.00E-04

Ids (A)

Ids (A)

1.00E-06

1.00E-09
4.00E-04

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

NMOS

3.00

4.00

Vgs (V)

Vgs (V)

idvd @ vbs=0V
L=0.5um
W=20um

NMOS
1.20E-02

8.00E-03

8.00E-03

Ids (A)

Gds (1/ohm)

1.20E-02

Gds @ vbs=0V
L=0.5um
W=20um

4.00E-03

4.00E-03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 9a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=20/0.5. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 40 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 41 of 105

NMOS

idvg @ low Vds

L=0.6um
W=20um

NMOS

8.00E-04

1.00E-03

6.00E-04

1.00E-06

idvg @ low Vds

L=0.6um
W=20um

Ids (A)

1.00E+00

Ids (A)

1.00E-03

4.00E-04

1.00E-09

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

2.00E-04

0.00E+00
0.00

1.00

2.00

3.00

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

Vgs (V)

NMOS

3.00

4.00

Vgs (V)

idvd @ vbs=0V
L=0.6um
W=20um

NMOS
1.00E-02

8.00E-03

8.00E-03

6.00E-03

6.00E-03

Ids (A)

Gds (1/ohm)

1.00E-02

Gds @ vbs=0V
L=0.6um
W=20um

4.00E-03

4.00E-03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-03

0.00E+00
0.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-03

0.00E+00
1.00

2.00
Vds (V)

3.00

4.00

0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 10a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=20/0.6. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 41 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 42 of 105

NMOS

idvg @ low Vds

L=0.35um
W=0.4um

NMOS

3.00E-05

idvg @ low Vds

L=0.35um
W=0.4um

1.00E-03

1.00E-06

Ids (A)

Ids (A)

2.00E-05

1.00E-09

1.00E-05

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

Vgs (V)

NMOS

3.00

4.00

Vgs (V)

idvd @ vbs=0V
L=0.35um
W=0.4um

NMOS

Gds @ vbs=0V
L=0.35um
W=0.4um

3.00E-04

2.50E-04

2.00E-04

2.00E-04

Ids (A)

Gds (1/ohm)

1.50E-04

1.00E-04

1.00E-04

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

5.00E-05

0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 11a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=0.4/0.35. All measurements
and simulations at 27C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 42 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 43 of 105

idvg @ low Vds

L=0.35um
W=0.6um

NMOS
1.00E-03

3.00E-05

1.00E-06

Ids (A)

Ids (A)

NMOS
4.00E-05

2.00E-05

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

1.00E-05

0.00E+00
0.00

1.00

2.00

3.00

1.00E-09

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

Vgs (V)

NMOS

idvg @ low Vds

L=0.35um
W=0.6um

3.00

4.00

Vgs (V)

idvd @ vbs=0V
L=0.35um
W=0.6um

NMOS

3.00E-04

Gds @ vbs=0V
L=0.35um
W=0.6um

4.00E-04

3.00E-04

Ids (A)

Gds (1/ohm)

2.00E-04

2.00E-04

1.00E-04

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

1.00E-04

0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 12a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=0.6/0.35. All measurements
and simulations at 27C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 43 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 44 of 105

NMOS

idvg @ low Vds

L=0.35um
W=0.8um

NMOS

6.00E-05

idvg @ low Vds

L=0.35um
W=0.8um

1.00E-03

1.00E-06

Ids (A)

Ids (A)

4.00E-05

1.00E-09

2.00E-05

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

Vgs (V)

NMOS

3.00

4.00

Vgs (V)

idvd @ vbs=0V
L=0.35um
W=0.8um

NMOS

Gds @ vbs=0V
L=0.35um
W=0.8um

5.00E-04

4.00E-04

4.00E-04
3.00E-04

Gds (1/ohm)

Ids (A)

3.00E-04

2.00E-04

2.00E-04

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

1.00E-04

0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

1.00E-04

0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 13a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=0.8/0.35. All measurements
and simulations at 27C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 44 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 45 of 105

NMOS

idvg @ low Vds

NMOS
L=0.35um
W=1um

idvg @ low Vds

L=0.35um
W=1um

1.00E-03

6.00E-05

1.00E-06

Ids (A)

Ids (A)

4.00E-05

1.00E-09

2.00E-05

Vbs start = 0

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

1.00E-12

1.00E-15
0.00

4.00

Vbs stop = -3.3

Vbs step = -0.55
Vds
= 0.1
measure
simulate

1.00

2.00

NMOS

3.00

4.00

Vgs (V)

Vgs (V)

idvd @ vbs=0V
L=0.35um
W=1um

NMOS

Gds @ vbs=0V
L=0.35um
W=1um

6.00E-04

5.00E-04

4.00E-04

4.00E-04

Ids (A)

Gds (1/ohm)

3.00E-04

2.00E-04

2.00E-04

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

1.00E-04

0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 14a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=1/0.35. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 45 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 46 of 105

Rout @ vbs=0V
L=0.35um
W=20um

NMOS
1.00E+05

1.00E+04

1.00E+04

Rout (ohm)

Rout (ohm)

NMOS
1.00E+05

1.00E+03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

1.00E+02

1.00E+01
0.00

1.00

2.00

3.00

1.00E+03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

1.00E+02

1.00E+01
0.00

4.00

1.00

2.00

Vds (V)

Rout @ vbs=0V
L=0.45um
W=20um

NMOS

1.00E+05

1.00E+05

1.00E+04

1.00E+04

1.00E+03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

1.00E+02

1.00E+01
0.00

1.00

2.00

3.00

Vds (V)

4.00

4.00

Rout @ vbs=0V
L=0.5um
W=20um

1.00E+03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

1.00E+02

1.00E+01
0.00

1.00

2.00
Vds (V)

Figure 15a: Fitting Rout vs. Vds Short devices

MIMOS INTERNAL USE ONLY

3.00

Vds (V)

Rout (ohm)

Rout (ohm)

NMOS

Rout @ vbs=0V
L=0.4um
W=20um

Page 46 of 105

3.00

4.00

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 47 of 105

Rout @ vbs=0V
L=0.35um
W=0.4um

NMOS

1.00E+07

1.00E+07

1.00E+06

1.00E+06

Rout (ohm)

Rout (ohm)

NMOS

1.00E+05

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

1.00E+04

1.00E+03
0.00

1.00

2.00

3.00

1.00E+05

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

1.00E+04

1.00E+03
0.00

4.00

1.00

2.00

Vds (V)

Rout @ vbs=0V
L=0.35um
W=0.8um

NMOS

1.00E+07

1.00E+07

1.00E+06

1.00E+06

1.00E+05

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

1.00E+04

1.00E+03
0.00

1.00

2.00

3.00

Vds (V)

4.00

4.00

Rout @ vbs=0V
L=0.35um
W=1um

1.00E+05

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

1.00E+04

1.00E+03
0.00

1.00

2.00
Vds (V)

Figure 16a: Fitting Rout vs. Vds Small devices

MIMOS INTERNAL USE ONLY

3.00

Vds (V)

Rout (ohm)

Rout (ohm)

NMOS

Rout @ vbs=0V
L=0.35um
W=0.6um

Page 47 of 105

3.00

4.00

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 48 of 105

N-type area capacitance

N-type sidewall capacitance

8.00E-11
3.50E-11

AREA = 39 200 um^2

PERIM = 840 um
CJ
MJ
PB

= 1.51403E-03
= 0.399389
= 0.882812

3.00E-11

AREA
PERIM

= 14 560 um^2
= 7 504 um

CJSW
MJSW
PBSW

= 6.8984E-010
= 0.286203
= 0.773437

6.00E-11

CJSW (F)

CJ (F)

2.50E-11

meas
sim

meas
sim
2.00E-11

4.00E-11

1.50E-11

2.00E-11

1.00E-11

-4

-3

-2

-1

-4

Vb (V)

-3

-2

-1

Vb (V)

N-type gate overlap capacitance

4.00E-14
W = 25 um
L = 0.35 um
CGD0 = 2E-10

CGD0 (F)

3.00E-14

meas
simu

2.00E-14

1.00E-14

0.00E+00
-4.00

-2.00

0.00

2.00

4.00

Vg (V)

Figure 17a: Area, sidewall and gate overlap capacitances of n-type device (measured vs. simulated)

MIMOS INTERNAL USE ONLY

Page 48 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 49 of 105

NMOS

idvg @ low Vds

L=0.35um
W=20um

T=70C

NMOS

idvg @ low Vds

L=0.35um
W=20um

T=70C

1.00E+00

1.20E-03

1.00E-03

8.00E-04

Ids (A)

Ids (A)

1.00E-06

1.00E-09
4.00E-04

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure

1.00E-12

simulate
0.00E+00
0.00

1.00

2.00

3.00

simulate
1.00E-15
0.00

4.00

1.00

2.00

NMOS

idvd @ vbs=0V
L=0.35um
W=20um

3.00

4.00

Vgs (V)

Vgs (V)

T=70C

NMOS

1.00E-02

Gds @ vbs=0V
L=0.35um
W=20um

T=70C

1.20E-02

8.00E-03

8.00E-03

Ids (A)

Gds (1/ohm)

6.00E-03

4.00E-03

4.00E-03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-03

0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 18a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=20/0.35. All measurements and
simulations at 70C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 49 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 50 of 105

NMOS

idvg @ low Vds

L=0.4um
W=20um

T=70C

NMOS

1.20E-03

idvg @ low Vds

L=0.4um
W=20um

T=70C

1.00E+00

1.00E-03

8.00E-04

Ids (A)

Ids (A)

1.00E-06

1.00E-09

4.00E-04

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure

1.00E-12

simulate
0.00E+00
0.00

simulate
1.00E-15

1.00

2.00

3.00

4.00

0.00

1.00

2.00

Vgs (V)

NMOS

idvd @ vbs=0V
L=0.4um
W=20um

3.00

4.00

Vgs (V)

T=70C

NMOS

1.00E-02

Gds @ vbs=0V
L=0.4um
W=20um

T=70C

1.20E-02

8.00E-03

8.00E-03

Ids (A)

Gds (1/ohm)

6.00E-03

4.00E-03

4.00E-03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-03

0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 19a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=20/0.4. All measurements and
simulations at 70C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 50 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 51 of 105

NMOS

idvg @ low Vds

L=0.45um
W=20um

T=70C

NMOS
1.00E+00

8.00E-04

1.00E-03

6.00E-04

1.00E-06

idvg @ low Vds

L=0.45um
W=20um

T=70C

Ids (A)

Ids (A)

1.00E-03

1.00E-09

4.00E-04

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure

2.00E-04

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure

1.00E-12

simulate
0.00E+00
0.00

1.00

2.00

3.00

simulate
1.00E-15
0.00

4.00

1.00

2.00

NMOS

idvd @ vbs=0V
L=0.45um
W=20um

3.00

4.00

Vgs (V)

Vgs (V)

T=70

NMOS
1.00E-02

8.00E-03

8.00E-03

6.00E-03

6.00E-03

T=70

Ids (A)

Gds (1/ohm)

1.00E-02

Gds @ vbs=0V
L=0.45um
W=20um

4.00E-03

4.00E-03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-03

0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-03

0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 20a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=20/0.45. All measurements and
simulations at 70C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 51 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 52 of 105

NMOS

idvg @ low Vds

L=0.5um
W=20um

T=70C

NMOS

8.00E-04

1.00E-03

6.00E-04

1.00E-06

T=70C

Ids (A)

1.00E+00

Ids (A)

1.00E-03

idvg @ low Vds

L=0.5um
W=20um

4.00E-04

1.00E-09

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure

2.00E-04

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure

1.00E-12

simulate
0.00E+00
0.00

1.00

2.00

3.00

simulate
1.00E-15
0.00

4.00

1.00

2.00

Vgs (V)

NMOS

idvd @ vbs=0V
L=0.5um
W=20um

3.00

4.00

Vgs (V)

T=70C

NMOS
1.00E-02

8.00E-03

8.00E-03

6.00E-03

6.00E-03

T=70C

Ids (A)

Gds (1/ohm)

1.00E-02

Gds @ vbs=0V
L=0.5um
W=20um

4.00E-03

4.00E-03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-03

0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-03

0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 21a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=20/0.5. All measurements and
simulations at 70C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.

MIMOS INTERNAL USE ONLY

Page 52 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 53 of 105

NMOS

idvg @ low Vds

L=0.35um
W=20um

T=125C

NMOS

idvg @ low Vds

L=0.35um
W=20um

T=125C

1.00E+00

1.20E-03

1.00E-03

8.00E-04

Ids (A)

Ids (A)

1.00E-06

1.00E-09
4.00E-04

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure

1.00E-12

simulate
0.00E+00
0.00

1.00

2.00

3.00

simulate
1.00E-15
0.00

4.00

1.00

NMOS

idvd @ vbs=0V
L=0.35um
W=20um

2.00

3.00

4.00

Vgs (V)

Vgs (V)

T=125C

NMOS

1.00E-02

Gds @ vbs=0V
L=0.35um
W=20um

T=125C

1.20E-02

8.00E-03

8.00E-03

Ids (A)

Gds (1/ohm)

6.00E-03

4.00E-03

4.00E-03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-03

0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 22a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=20/0.35. All measurements and
simulations at 125C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 53 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 54 of 105

NMOS

idvg @ low Vds

L=0.4um
W=20um

T=125C

NMOS
1.00E+00

8.00E-04

1.00E-03

6.00E-04

1.00E-06

idvg @ low Vds

L=0.4um
W=20um

T=125C

Ids (A)

Ids (A)

1.00E-03

1.00E-09

4.00E-04

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure

2.00E-04

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure

1.00E-12

simulate
0.00E+00
0.00

1.00

2.00

3.00

simulate
1.00E-15
0.00

4.00

1.00

2.00

NMOS

idvd @ vbs=0V
L=0.4um
W=20um

3.00

4.00

Vgs (V)

Vgs (V)

NMOS

T=125C
1.00E-02

8.00E-03

8.00E-03

6.00E-03

6.00E-03

T=125C

Ids (A)

Gds (1/ohm)

1.00E-02

Gds @ vbs=0V
L=0.4um
W=20um

4.00E-03

4.00E-03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-03

0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-03

0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 23a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=20/0.4. All measurements and
simulations at 125C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 54 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 55 of 105

NMOS

idvg @ low Vds

L=0.45um
W=20um

T=125C

NMOS
1.00E+00

8.00E-04

1.00E-03

6.00E-04

1.00E-06

idvg @ low Vds

L=0.45um
W=20um

T=125C

Ids (A)

Ids (A)

1.00E-03

1.00E-09

4.00E-04

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure

2.00E-04

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure

1.00E-12

simulate
0.00E+00
0.00

1.00

2.00

3.00

simulate
1.00E-15
0.00

4.00

1.00

2.00

NMOS

idvd @ vbs=0V
L=0.45um
W=20um

3.00

4.00

Vgs (V)

Vgs (V)

T=125C

NMOS

8.00E-03

Gds @ vbs=0V
L=0.45um
W=20um

T=125C

1.00E-02

8.00E-03
6.00E-03

Gds (1/ohm)

Ids (A)

6.00E-03

4.00E-03

4.00E-03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-03

0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-03

0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 24a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=20/0.45. All measurements and
simulations at 125C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 55 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 56 of 105

NMOS

idvg @ low Vds

L=0.5um
W=20um

T=125C

NMOS

idvg @ low Vds

L=0.5um
W=20um

T=125C

1.00E+00

8.00E-04

1.00E-03
6.00E-04

Ids (A)

Ids (A)

1.00E-06

4.00E-04

1.00E-09

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure

2.00E-04

Vbs start = 0
Vbs stop = -3.3
Vbs step = -0.55
Vds
= 0.1
measure

1.00E-12

simulate

simulate
1.00E-15
0.00

0.00E+00
0.00

1.00

2.00

3.00

4.00

1.00

2.00

idvd @ vbs=0V
L=0.5um
W=20um

T=125C

NMOS

8.00E-03

8.00E-03

6.00E-03

6.00E-03

Gds (1/ohm)

Ids (A)

NMOS

4.00E-03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-03

0.00E+00
0.00

1.00

2.00
Vds (V)

3.00

4.00

Vgs (V)

Vgs (V)

3.00

4.00

Gds @ vbs=0V
L=0.5um
W=20um

T=125C

4.00E-03

Vgs start = 0.8

Vgs stop = 3.3
Vgs step = 0.5
Vbs
=0
measure
simulate

2.00E-03

0.00E+00
0.00

1.00

2.00

3.00

4.00

Vds (V)

Figure 25a: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V NMOS W/L=20/0.5. All measurements and
simulations at 125C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 56 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 57 of 105

PMOS

idvg @ low Vds

L=20um
W=20um

PMOS

1.20E-05

idvg @ low Vds

L=20um
W=20um

1.00E-03

1.00E-06

-Ids (A)

-Ids (A)

8.00E-06

1.00E-09

4.00E-06

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate
0.00E+00
0.00

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00E-15
1.00

2.00

3.00

4.00

0.00

1.00

2.00

-Vgs (V)

PMOS

3.00

4.00

-Vgs (V)

idvd @ vbs=0V
L=20um
W=20um

PMOS

Gds @ vbs=0V
L=20um
W=20um

1.20E-04

1.60E-04

1.20E-04

Gds (1/ohm)

-Ids (A)

8.00E-05

8.00E-05

4.00E-05

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

4.00E-05

0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 1b: Fitting Id vs. Vg and Vd, transfer and output characteristics of -3.3 V PMOS W/L=20/20. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=-0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 57 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 58 of 105

PMOS

idvg @ low Vds

L=20um
W=0.4um

PMOS

8.00E-08

1.00E-09

idvg @ low Vds

L=20um
W=0.4um

-Ids (A)

1.00E-06

-Ids (A)

1.20E-07

4.00E-08

1.00E-12

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate
1.00E-15
0.00

4.00

1.00

2.00

-Vgs (V)

PMOS

3.00

4.00

-Vgs (V)

idvd @ vbs=0V
L=20um
W=0.4um

PMOS

Gds @ vbs=0V
L=20um
W=0.4um

1.20E-06

1.60E-06

1.20E-06

Gds (1/ohm)

-Ids (A)

8.00E-07

8.00E-07

4.00E-07
4.00E-07

0.00E+00
0.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate
1.00

2.00
-Vds (V)

3.00

4.00

0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 2b: Fitting Id vs. Vg and Vd, transfer and output characteristics of -3.3 V PMOS W/L=0.4/20. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=-0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 58 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 59 of 105

PMOS

idvg @ low Vds

L=20um
W=0.6um

PMOS

2.50E-07

idvg @ low Vds

L=20um
W=0.6um

1.00E-06

2.00E-07

1.00E-09

-Ids (A)

-Ids (A)

1.50E-07

1.00E-07
1.00E-12

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

5.00E-08

0.00E+00
0.00

1.00

2.00

3.00

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate
1.00E-15
0.00

4.00

1.00

2.00

-Vgs (V)

PMOS

3.00

4.00

-Vgs (V)

idvd @ vbs=0V
L=20um
W=0.6um

PMOS

Gds @ vbs=0V
L=20um
W=0.6um

2.50E-06

3.00E-06

2.00E-06

2.00E-06

-Ids (A)

Gds (1/ohm)

1.50E-06

1.00E-06
1.00E-06

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

5.00E-07

0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 3b: Fitting Id vs. Vg and Vd, transfer and output characteristics of -3.3 V PMOS W/L=0.6/20. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=-0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 59 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 60 of 105

PMOS

idvg @ low Vds

L=20um W=0.8um

PMOS
1.00E-06

2.00E-07

1.00E-09

idvg @ low Vds

L=20um W=0.8um

-Ids (A)

-Ids (A)

3.00E-07

1.00E-07

1.00E-12

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate
1.00E-15
0.00

4.00

1.00

2.00

-Vgs (V)

PMOS

3.00

4.00

-Vgs (V)

idvd @ vbs=0V
L=20um
W=0.8um

PMOS

Gds @ vbs=0V
L=20um
W=0.8um

3.00E-06

4.00E-06

3.00E-06

Gds (1/ohm)

-Ids (A)

2.00E-06

2.00E-06

1.00E-06
1.00E-06

0.00E+00
0.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate
1.00

2.00
-Vds (V)

3.00

4.00

0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 4b: Fitting Id vs. Vg and Vd, transfer and output characteristics of -3.3 V PMOS W/L=0.8/20. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=-0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

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0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 61 of 105

PMOS

idvg @ low Vds

L=20um
W=1um

PMOS

5.00E-07

idvg @ low Vds

L=20um
W=1um

1.00E-06

4.00E-07

1.00E-09

-Ids (A)

-Ids (A)

3.00E-07

2.00E-07
1.00E-12

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-07

0.00E+00
0.00

1.00

2.00

3.00

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate
1.00E-15
0.00

4.00

1.00

2.00

-Vgs (V)

PMOS

3.00

4.00

-Vgs (V)

idvd @ vbs=0V
L=20um
W=1um

PMOS

Gds @ vbs=0V
L=20um
W=1um

4.00E-06

6.00E-06

3.00E-06

-Ids (A)

Gds (1/ohm)

4.00E-06

2.00E-06

2.00E-06

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-06

0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 5b: Fitting Id vs. Vg and Vd, transfer and output characteristics of -3.3 V PMOS W/L=1/20. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=-0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 61 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 62 of 105

idvg @ low Vds

L=0.35um
W=20um

PMOS
1.00E-03

3.00E-04

1.00E-06

-Ids (A)

-Ids (A)

PMOS
4.00E-04

2.00E-04

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-04

0.00E+00
0.00

1.00

2.00

3.00

1.00E-09

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

-Vgs (V)

PMOS

idvg @ low Vds

L=0.35um
W=20um

3.00

4.00

-Vgs (V)

idvd @ vbs=0V
L=0.35um
W=20um

PMOS

Gds @ vbs=0V
L=0.35um
W=20um

4.00E-03

6.00E-03

3.00E-03

-Ids (A)

Gds (1/ohm)

4.00E-03

2.00E-03

2.00E-03

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 6b: Fitting Id vs. Vg and Vd, transfer and output characteristics of -3.3 V PMOS W/L=20/0.35. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=-0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 62 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 63 of 105

idvg @ low Vds

L=0.4um W=20um

PMOS
1.00E-03

3.00E-04

1.00E-06

-Ids (A)

-Ids (A)

PMOS
4.00E-04

2.00E-04

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-04

0.00E+00
0.00

1.00

2.00

3.00

1.00E-09

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

-Vgs (V)

PMOS

idvg @ low Vds

L=0.4um W=20um

3.00

4.00

-Vgs (V)

idvd @ vbs=0V
L=0.4um
W=20um

PMOS

6.00E-03

Gds @ vbs=0V
L=0.4um
W=20um

4.00E-03

3.00E-03

-Ids (A)

Gds (1/ohm)

4.00E-03

2.00E-03

2.00E-03

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 7b: Fitting Id vs. Vg and Vd, transfer and output characteristics of -3.3 V PMOS W/L=20/0.4. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=-0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 63 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 64 of 105

idvg @ low Vds

L=0.45um
W=20um

PMOS

4.00E-04

1.00E-03

3.00E-04

1.00E-06

-Ids (A)

-Ids (A)

PMOS

2.00E-04

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-04

0.00E+00
0.00

1.00

2.00

3.00

1.00E-09

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

-Vgs (V)

PMOS

idvg @ low Vds

L=0.45um
W=20um

3.00

4.00

-Vgs (V)

idvd @ vbs=0V
L=0.45um
W=20um

PMOS

Gds @ vbs=0V
L=0.45um
W=20um

6.00E-03

4.00E-03

3.00E-03

-Ids (A)

Gds (1/ohm)

4.00E-03

2.00E-03

2.00E-03

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 8b: Fitting Id vs. Vg and Vd, transfer and output characteristics of -3.3 V PMOS W/L=20/0.45. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=-0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 64 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 65 of 105

idvg @ low Vds

L=0.5um
W=20um

PMOS
1.00E-03

3.00E-04

1.00E-06

-Ids (A)

-Ids (A)

PMOS
4.00E-04

2.00E-04

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-04

0.00E+00
0.00

1.00

2.00

3.00

1.00E-09

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

-Vgs (V)

idvd @ vbs=0V
L=0.5um
W=20um

PMOS

4.00E-03

4.00E-03

3.00E-03

3.00E-03

2.00E-03

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

-Vgs (V)

Gds (1/ohm)

-Ids (A)

PMOS

idvg @ low Vds

L=0.5um
W=20um

3.00

4.00

Gds @ vbs=0V
L=0.5um
W=20um

2.00E-03

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 9b: Fitting Id vs. Vg and Vd, transfer and output characteristics of -3.3 V PMOS W/L=20/0.5. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=-0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 65 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 66 of 105

PMOS

idvg @ low Vds

L=0.6um
W=20um

PMOS

3.00E-04

idvg @ low Vds

L=0.6um
W=20um

1.00E-03

1.00E-06

-Ids (A)

-Ids (A)

2.00E-04

1.00E-09

1.00E-04

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

-Vgs (V)

PMOS

3.00

4.00

-Vgs (V)

idvd @ vbs=0V
L=0.6um
W=20um

PMOS

4.00E-03

Gds @ vbs=0V
L=0.6um
W=20um

3.00E-03

3.00E-03

Gds (1/ohm)

-Ids (A)

2.00E-03

2.00E-03

1.00E-03

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 10b: Fitting Id vs. Vg and Vd, transfer and output characteristics of -3.3 V PMOS W/L=20/0.6. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=-0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 66 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 67 of 105

idvg @ low Vds

L=0.35um
W=0.4um

PMOS
1.00E-03

6.00E-06

1.00E-06

-Ids (A)

-Ids (A)

PMOS
8.00E-06

4.00E-06

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

2.00E-06

0.00E+00
0.00

1.00

2.00

3.00

1.00E-09

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

-Vgs (V)

PMOS

idvg @ low Vds

L=0.35um
W=0.4um

3.00

4.00

-Vgs (V)

idvd @ vbs=0V
L=0.35um
W=0.4um

PMOS

1.00E-04

Gds @ vbs=0V
L=0.35um
W=0.4um

8.00E-05

8.00E-05

6.00E-05

-Ids (A)

Gds (1/ohm)

6.00E-05

4.00E-05

4.00E-05

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

2.00E-05

0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

2.00E-05

0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 11b: Fitting Id vs. Vg and Vd, transfer and output characteristics of -3.3 V PMOS W/L=0.4/0.35. All measurements
and simulations at 27C, Id vs. Vg plots use Vd=-0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 67 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 68 of 105

PMOS

idvg @ low Vds

L=0.35um
W=0.6um

PMOS

1.20E-05

idvg @ low Vds

L=0.35um
W=0.6um

1.00E-03

1.00E-06

-Ids (A)

-Ids (A)

8.00E-06

1.00E-09

4.00E-06

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

-Vgs (V)

PMOS

3.00

4.00

-Vgs (V)

idvd @ vbs=0V
L=0.35um
W=0.6um

PMOS

1.60E-04

Gds @ vbs=0V
L=0.35um
W=0.6um

1.20E-04

1.20E-04

Gds (1/ohm)

-Ids (A)

8.00E-05

8.00E-05

4.00E-05

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

4.00E-05

0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 12b: Fitting Id vs. Vg and Vd, transfer and output characteristics of -3.3 V PMOS W/L=0.6/0.35. All measurements
and simulations at 27C, Id vs. Vg plots use Vd=-0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 68 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 69 of 105

idvg @ low Vds

L=0.35um
W=0.8um

PMOS
1.00E-03

1.20E-05

1.00E-06

-Ids (A)

-Ids (A)

PMOS
1.60E-05

8.00E-06

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

4.00E-06

0.00E+00
0.00

1.00

2.00

3.00

1.00E-09

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

-Vgs (V)

PMOS

idvg @ low Vds

L=0.35um
W=0.8um

3.00

4.00

-Vgs (V)

idvd @ vbs=0V
L=0.35um
W=0.8um

PMOS

2.00E-04

Gds @ vbs=0V
L=0.35um
W=0.8um

1.60E-04

1.60E-04

1.20E-04

-Ids (A)

Gds (1/ohm)

1.20E-04

8.00E-05

8.00E-05

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

4.00E-05

0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

4.00E-05

0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 13b: Fitting Id vs. Vg and Vd, transfer and output characteristics of -3.3 V PMOS W/L=0.8/0.35. All measurements
and simulations at 27C, Id vs. Vg plots use Vd=-0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 69 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 70 of 105

idvg @ low Vds

L=0.35um
W=1um

PMOS

1.60E-05

1.00E-03

1.20E-05

1.00E-06

-Ids (A)

-Ids (A)

PMOS

8.00E-06

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

4.00E-06

0.00E+00
0.00

1.00

2.00

3.00

1.00E-09

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

-Vgs (V)

PMOS

idvg @ low Vds

L=0.35um
W=1um

3.00

4.00

-Vgs (V)

idvd @ vbs=0V
L=0.35um
W=1um

PMOS

2.50E-04

Gds @ vbs=0V
L=0.35um
W=1um

1.60E-04

2.00E-04

1.20E-04

-Ids (A)

Gds (1/ohm)

1.50E-04

8.00E-05

1.00E-04

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

5.00E-05

0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

4.00E-05

0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 14b: Fitting Id vs. Vg and Vd, transfer and output characteristics of -3.3 V PMOS W/L=1/0.35. All measurements and
simulations at 27C, Id vs. Vg plots use Vd=-0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 70 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 71 of 105

Rout @ vbs=0V
L=0.35um
W=20um

PMOS

1.00E+06

1.00E+06

1.00E+05

1.00E+05

Rout (ohm)

Rout (ohm)

PMOS

1.00E+04

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E+03

1.00E+02
0.00

1.00

2.00

3.00

1.00E+04

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E+03

1.00E+02
0.00

4.00

1.00

2.00

3.00

4.00

-Vds (V)

-Vds (V)

PMOS

Rout @ vbs=0V
L=0.4um
W=20um

Rout @ vbs=0V
L=0.45um
W=20um

PMOS

Rout @ vbs=0V
L=0.5um
W=20um

1.00E+06
1.00E+06

1.00E+05

Rout (ohm)

Rout (ohm)

1.00E+05

1.00E+04

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E+03

1.00E+02
0.00

1.00E+04

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E+03

1.00E+02
1.00

2.00

3.00

-Vds (V)

4.00

0.00

1.00

2.00
-Vds (V)

Figure 15b: Fitting of Rout vs. Vds Short devices

MIMOS INTERNAL USE ONLY

Page 71 of 105

3.00

4.00

0.35um CMOS Devices Model Parameters

MYSC02-403

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MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 72 of 105

Rout @ vbs=0V
L=0.35um
W=0.4um

PMOS

1.00E+07

1.00E+07

1.00E+06

1.00E+06

Rout (ohm)

Rout (ohm)

PMOS

1.00E+05

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E+04

1.00E+03

1.00E+05

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E+04

1.00E+03

0.00

1.00

2.00

3.00

4.00

0.00

1.00

2.00

-Vds (V)

PMOS

Rout @ vbs=0V
L=0.35um
W=0.8um

PMOS

1.00E+07

1.00E+07

1.00E+06

1.00E+06

1.00E+05

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E+04

1.00E+03
0.00

3.00

4.00

-Vds (V)

Rout (ohm)

Rout (ohm)

Rout @ vbs=0V
L=0.35um
W=0.6um

Rout @ vbs=0V
L=0.35um
W=1um

1.00E+05

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E+04

1.00E+03
1.00

2.00

3.00

-Vds (V)

4.00

0.00

1.00

2.00
-Vds (V)

Figure 16b: Fitting of Rout vs. Vds Small devices

MIMOS INTERNAL USE ONLY

Page 72 of 105

3.00

4.00

0.35um CMOS Devices Model Parameters

MYSC02-403

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MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 73 of 105

P-type sidewall capacitance

P-type area capacitance

3.00E-11

6.00E-11

AREA
PERIM

= 1.21572E-03
= 0.521306
= 1.073

meas
sim

4.00E-11

CJSW (F)

CJ (F)

CJ
MJ
PB

= 39 200 um^2
= 840 um

= 14 560 um^2
= 7 504 um

CJSW
MJSW
PBSW

= 5.236E-010
= 0.3686
= 0.8500

Meas
Sim

2.00E-11

1.00E-11

2.00E-11
-1

-1

2
Vb (V)

Vb (V)

P-type gate overlap capacitance

4.00E-14
W = 25 um
L = 0.35 um
CGD0 = 2.05E-10
3.00E-14

CGD0 (F)

AREA
PERIM

meas
simu

2.00E-14

1.00E-14

0.00E+00
-4.00

-2.00

0.00

2.00

4.00

Vg (V)

Figure 17b: Area, sidewall and gate overlap capacitances of p-type device (measured vs. simulated)

MIMOS INTERNAL USE ONLY

Page 73 of 105

0.35um CMOS Devices Model Parameters

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Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 74 of 105

idvg @ low Vds

L=0.35um
W=20um

T=70C

PMOS
1.00E-03

3.00E-04

1.00E-06

-Ids (A)

-Ids (A)

PMOS
4.00E-04

2.00E-04

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-04

0.00E+00
0.00

1.00

2.00

3.00

idvd @ vbs=0V
L=0.35um
W=20um

T=70C

1.00E-09

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

-Vgs (V)

PMOS

idvg @ low Vds

L=0.35um
W=20um

3.00

4.00

-Vgs (V)

T=70C

PMOS

5.00E-03

Gds @ vbs=0V
L=0.35um
W=20um

T=70C

4.00E-03

4.00E-03

3.00E-03

-Ids (A)

Gds (1/ohm)

3.00E-03

2.00E-03

2.00E-03

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 18b: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V PMOS W/L=20/0.35. All measurements and
simulations at 70C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 74 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 75 of 105

idvg @ low Vds

L=0.4um
W=20um

T=70C

PMOS

4.00E-04

1.00E-03

3.00E-04

1.00E-06

-Ids (A)

-Ids (A)

PMOS

2.00E-04

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-04

0.00E+00
0.00

idvg @ low Vds

L=0.4um
W=20um

T=70C

1.00E-09

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00E-15

1.00

2.00

3.00

4.00

0.00

1.00

2.00

-Vgs (V)

PMOS

idvd @ vbs=0V
L=0.4um
W=20um

3.00

4.00

-Vgs (V)

T=70C

PMOS

5.00E-03

Gds @ vbs=0V
L=0.4um
W=20um

T=70C

4.00E-03

4.00E-03

3.00E-03

-Ids (A)

Gds (1/ohm)

3.00E-03

2.00E-03

2.00E-03

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 19b: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V PMOS W/L=20/0.4. All measurements and
simulations at 70C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

Page 75 of 105

0.35um CMOS Devices Model Parameters

MYSC02-403

Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 76 of 105

idvg @ low Vds

L=0.45um
W=20um

T=70C

PMOS
1.00E-03

3.00E-04

1.00E-06

-Ids (A)

-Ids (A)

PMOS
4.00E-04

2.00E-04

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-04

0.00E+00
0.00

1.00

2.00

3.00

idvd @ vbs=0V
L=0.45um
W=20um

T=70C

1.00E-09

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

-Vgs (V)

PMOS

idvg @ low Vds

L=0.45um
W=20um

3.00

4.00

-Vgs (V)

T=70C

PMOS

5.00E-03

Gds @ vbs=0V
L=0.45um
W=20um

T=70C

4.00E-03

4.00E-03

3.00E-03

-Ids (A)

Gds (1/ohm)

3.00E-03

2.00E-03

2.00E-03

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 20b: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V PMOS W/L=20/0.45. All measurements and
simulations at 70C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

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0.35um CMOS Devices Model Parameters

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Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 77 of 105

PMOS

idvg @ low Vds

L=0.5um
W=20um

T=70C

PMOS

idvg @ low Vds

L=0.5um
W=20um

T=70C

1.00E-03

3.00E-04

1.00E-06

-Ids (A)

-Ids (A)

2.00E-04

1.00E-09

1.00E-04

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-15
0.00

0.00E+00
0.00

1.00

2.00

3.00

4.00

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00

2.00

PMOS

idvd @ vbs=0V
L=0.5um
W=20um

3.00

4.00

-Vgs (V)

-Vgs (V)

T=70C

PMOS

4.00E-03

Gds @ vbs=0V
L=0.5um
W=20um

T=70C

3.00E-03

3.00E-03

Gds (1/ohm)

-Ids (A)

2.00E-03

2.00E-03

1.00E-03

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 21b: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V PMOS W/L=20/0.5. All measurements and
simulations at 70C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.

MIMOS INTERNAL USE ONLY

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0.35um CMOS Devices Model Parameters

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Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 78 of 105

idvg @ low Vds

L=0.35um
W=20um

T=125C

PMOS
1.00E-03

3.00E-04

1.00E-06

-Ids (A)

-Ids (A)

PMOS
4.00E-04

2.00E-04

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-04

0.00E+00
0.00

1.00

2.00

3.00

idvd @ vbs=0V
L=0.35um
W=20um

T=125C

1.00E-09

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

3.00

4.00

-Vgs (V)

-Vgs (V)

PMOS

idvg @ low Vds

L=0.35um
W=20um

T=125C

PMOS

5.00E-03

Gds @ vbs=0V
L=0.35um
W=20um

T=125C

4.00E-03

4.00E-03

3.00E-03

-Ids (A)

Gds (1/ohm)

3.00E-03

2.00E-03

2.00E-03

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 22b: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V PMOS W/L=20/0.35. All measurements and
simulations at 125C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

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0.35um CMOS Devices Model Parameters

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Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 79 of 105

idvg @ low Vds

L=0.4um
W=20um

T=125C

PMOS
1.00E-03

3.00E-04

1.00E-06

-Ids (A)

-Ids (A)

PMOS
4.00E-04

2.00E-04

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-04

0.00E+00
0.00

1.00

2.00

3.00

idvd @ vbs=0V
L=0.4um
W=20um

T=125C

1.00E-09

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00E-15
0.00

4.00

1.00

2.00

-Vgs (V)

PMOS

idvg @ low Vds

L=0.4um
W=20um

3.00

4.00

-Vgs (V)

T=125C

PMOS

5.00E-03

Gds @ vbs=0V
L=0.4um
W=20um

T=125C

4.00E-03

4.00E-03

3.00E-03

-Ids (A)

Gds (1/ohm)

3.00E-03

2.00E-03

2.00E-03

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 23b: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V PMOS W/L=20/0.4. All measurements and
simulations at 125C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

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0.35um CMOS Devices Model Parameters

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Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 80 of 105

PMOS

idvg @ low Vds

L=0.45um
W=20um

T=125C

PMOS

idvg @ low Vds

L=0.45um
W=20um

T=125C

1.00E-03

3.00E-04

1.00E-06

-Ids (A)

-Ids (A)

2.00E-04

1.00E-09

1.00E-04

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

1.00E-15
0.00

4.00

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00

2.00

PMOS

idvd @ vbs=0V
L=0.45um
W=20um

3.00

4.00

-Vgs (V)

-Vgs (V)

T=125C

PMOS

4.00E-03

Gds @ vbs=0V
L=0.45um
W=20um

T=125C

3.00E-03

3.00E-03

Gds (1/ohm)

-Ids (A)

2.00E-03

2.00E-03

1.00E-03

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 24b: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V PMOS W/L=20/0.45. All measurements and
simulations at 125C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.
MIMOS INTERNAL USE ONLY

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0.35um CMOS Devices Model Parameters

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Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 81 of 105

PMOS

idvg @ low Vds

L=0.5um
W=20um

T=125C

PMOS

3.00E-04

idvg @ low Vds

L=0.5um
W=20um

T=125C

1.00E-03

1.00E-06

-Ids (A)

-Ids (A)

2.00E-04

1.00E-09

1.00E-04

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate
0.00E+00
0.00

Vbs start = 0
Vbs stop = 3.3
Vbs step = 0.55
Vds
= -0.1
measure
simulate

1.00E-12

1.00E-15
1.00

2.00

3.00

4.00

0.00

1.00

2.00

-Vgs (V)

PMOS

idvd @ vbs=0V
L=0.5um
W=20um

3.00

4.00

-Vgs (V)

T=125C
PMOS

4.00E-03

Gds @ vbs=0V
L=0.5um
W=20um

T=125C

3.00E-03

3.00E-03

Gds (1/ohm)

-Ids (A)

2.00E-03

2.00E-03

1.00E-03

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate

1.00E-03

0.00E+00
0.00

1.00

2.00
-Vds (V)

3.00

4.00

Vgs start = -0.8

Vgs stop = -3.3
Vgs step = -0.5
Vbs
=0
measure
simulate
0.00E+00
0.00

1.00

2.00

3.00

4.00

-Vds (V)

Figure 25b: Fitting Id vs. Vg and Vd, transfer and output characteristics of 3.3 V PMOS W/L=20/0.5. All measurements and
simulations at 125C, Id vs. Vg plots use Vd=0.1V and Id vs Vd plots use Vb=0V.

MIMOS INTERNAL USE ONLY

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0.35um CMOS Devices Model Parameters

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Rev 4.0

MIMOS Authorized Recipient Only

Date: 24/02/2011

Page 82 of 105

APPENDIX 2: Fitting Results for BJT Model

Figure 1: Fitting results of vpnp10 parasitic bipolar modeling
Figure 2: Fitting results of vpnp5 parasitic bipolar modeling
Related bipolar transistor characteristics for each figure:
(a) Forward Gummel
(b) Forward BETA
(c) Early Voltage

MIMOS INTERNAL USE ONLY

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0.35um CMOS Devices Model Parameters

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Rev 4.0

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Date: 24/02/2011

Page 83 of 105

Figure 1(a): Fitting results of vpnp10 bipolar modeling (Forward Gummel)

Figure 1(b): Fitting results of vpnp10 bipolar modeling (Forward BETA)

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Figure 1(c): Fitting results of vpnp10 bipolar modeling (Early Voltage)

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Figure 2(a): Fitting results of vpnp5 bipolar modeling (Forward Gummel)

Figure 2(b): Fitting results of vpnp5 bipolar modeling (Forward BETA)

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Figure 2(c): Fitting results of vpnp5 bipolar modeling (Early Voltage)

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APPENDIX 3:
Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Fitting Results for Resistor Model

Fitting of resistance at different temperatures for RPOLYH resistor

a) L=100um, W=2um
b) L=100um, W=5um
c) Fitting of sheet resistance
Fitting of resistance at different temperatures for RPOLY1 resistor
a) L=100um, W=2um
b) L=100um, W=5um
c) Fitting of sheet resistance
Fitting of resistance at different temperatures for RNWELL resistor
a) L=100um, W=4um
b) L=100um, W=5um
c) Fitting of sheet resistance
Fitting of resistance at different temperatures for RNDIFF resistor
a) L=100um, W=4um
b) L=100um, W=5um
c) Fitting of sheet resistance
Fitting of resistance at different temperatures for RPDIFF resistor
a) L=100um, W=4um
b) L=100um, W=5um
c) Fitting of sheet resistance

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Figure 1a: Fitting of resistance at difference temperatures for RPOLYH_L100_W2 (W1)

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Figure 1b: Fitting of resistance at difference temperatures for RPOLYH_L100_W5 (W2)

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Figure 1c: Fitting of sheet resistance at difference temperatures for various RPOLYH

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Figure 2a: Fitting of resistance at difference temperatures for RPOLY1_L100_W2 (W1)

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Figure 2b: Fitting of resistance at difference temperatures for RPOLY1_L100_W5 (W2)

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Figure 2c: Fitting of sheet resistance at difference temperatures for various RPOLY1

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Figure 3a: Fitting of resistance at difference temperatures for RNWELL_L100_W4 (W1)

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Figure 3b: Fitting of resistance at difference temperatures for RNWELL_L100_W5 (W2)

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Figure 3c: Fitting of sheet resistance at difference temperatures for various RNWELL

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Figure 4a: Fitting of resistance at difference temperatures for RNDIFF_L100_W4 (W1)

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Figure 4b: Fitting of resistance at difference temperatures for RNDIFF_L100_W5 (W2)

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Figure 4c: Fitting of sheet resistance at difference temperatures for various RNDIFF

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Figure 5a: Fitting of resistance at difference temperatures for RPDIFF_L100_W4 (W1)

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Figure 5b: Fitting of resistance at difference temperatures for RPDIFF_L100_W5 (W2)

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Figure 5c: Fitting of sheet resistance at difference temperatures for various RPDIFF

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APPENDIX 4:
Figure 1
Figure 2

Fitting Results for Capacitor Model

Fitting of capacitance at different temperatures for PIP 100u x 100u

Fitting of capacitance at different temperatures for PIP 200u x 200u

Figure 1: Fitting of capacitance at different temperatures for PIP 100u x 100u

Figure 2: Fitting of capacitance at different temperatures for PIP 200u x 200u

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