A

MINOR PROJECT REPORT

ON

TO DESIGN 6-T RAM USING VERILOG

Submitted in Partial Fulfilment of Requirements for
the Award of
Degree of Bachelor of Engineering
In
Electronics & Communication Engineering

FET MJPRU

ROHILKHAND

UNIVERSITYBAREILLY
SUBMITTED TO

UNDER THE GUIDENCE OF

Prof. SUMIT SRIVASTAVA

Prof. MANISH RAI

SUBMITTED BY
SHOBHIT SINGH

CONTENTS

1. INTRODUCTION
2. CIRCUIT USED
3. COMPONENTS REQUIRED
4. COMPONENTS DETAIL
5. SOFTWARE REQUIRED
6. SOFTWARE DETAIL
7. APPLICATION OF PROJECT
8. CONCLUSION OF PROJECT
9. FUTURE SCOPE OF PROJECT
10. REFERENCES

ABSTRACT

SRAM is the most widely used embedded memory in modern digital

systems, and their role is preferentially increasing. For all local
storing purposes (registers, cache memory etc.), SRAM is the best
solution because of its high speed since digital design can run at very
high speed as compared to the access time of SRAM. Hence there is
always need of increasing the speed of SRAM. This project design of
6-T SRAM cell for analysis of the Read/ Write timings, a latch-based
Sense Amplifier and other peripheral circuitry in 180nm CMOS
Technology. Based on the need to improve Access time in Read
operation, which takes more time than write operation, a new design
is proposed in which two Sense Amplifiers are used in each column of
SRAM array.
The design was generated using ORCAD tool and the simulation was
done using spice models. . However, there is a marginal increment in
the area due to additional sense amplifiers used in the proposed
design. It has been shown that the proposed design would improve the
time of read operation without compromising with the power.

INTRODUCTION

Modern digital systems require the capability of storing and retrieving

large amounts of information at high speeds. Memories are circuits or
systems that store digital information in large quantity. This chapter
addresses the analysis and design of VLSI memories, commonly
known as semiconductor memories. Today, memory circuits come in
different forms including SRAM, DRAM, ROM, EPROM, E2PROM,
Flash, and FRAM. While each form has a different cell design, the
basic structure, organization, and access mechanisms are largely the
same. In this project we present an analysis of the design of 6T
SRAM Read/ Write timings using 6-T SRAM Cell, a latch-based
Sense Amplifier and other peripheral circuitry in 180nm CMOS
Technology.

CIRCUIT USED

A six-transistor CMOS SRAM CELL

A typical SRAM cell is made up of six MOSFETs. Each bit in an

SRAM is stored on four transistors (M1, M2, M3, M4) that form two
cross-coupled inverters. This storage cell has two stable states which
are used to denote 0 and 1. Two additional access transistors serve to
control the access to a storage cell during read and write operations.
In addition to such six-transistor (6T) SRAM, other kinds of SRAM
chips use 4, 8, 10 (4T, 8T, 10T SRAM), or more transistors per bit.
Four-transistor SRAM is quite common in stand-alone SRAM devices
(as opposed to SRAM used for CPU caches), implemented in special
processes with an extra layer of polysilicon, allowing for very highresistance pull-up resistors. The principal drawback of using 4T

SRAM is increased static power due to the constant current flow

through one of the pull-down transistors.

Four transistor SRAM provides advantages in density at the cost of

manufacturing complexity. The resistors must have small dimensions
and large values.
This is sometimes used to implement more than one (read and/or
write) port, which may be useful in certain types of video memory
and register files implemented with multi-ported SRAM circuitry.
The size of an SRAM with m address lines and n data lines is 2m
words, or 2m n bits. The most common word size is 8 bits, meaning
that a single byte can be read or written to each of 2 m different words
within the SRAM chip. Several common SRAM chips have 11
address lines (thus a capacity of 2m = 2,048 = 2k words) and an 8-bit
word, so they are referred to as "2k 8 SRAM".

OPERATION OF SRAM

An SRAM cell has three different states: standby (the circuit is idle),
reading (the data has been requested) or writing (updating the
contents). SRAM operating in read mode and write modes should
have "readability" and "write stability", respectively. The three
different states work as follows:

Standby
If the word line is not asserted, the access transistors M5 and M6
disconnect the cell from the bit lines. The two cross-coupled inverters
formed by M1 M4 will continue to reinforce each other as long as
they are connected to the supply.

Reading
In theory, reading only requires asserting the word line WL and
reading the SRAM cell state by a single access transistor and bit line,
e.g. M6,

BL. Nevertheless, bit lines are relatively long and have large parasitic
capacitance. To speed up reading, a more complex process is used in
practice: The read cycle is started by pre charging both bit lines BL
and BL, i.e., driving the bit lines to a threshold voltage (midrange
voltage between logical 1 and 0) by an external module (not shown in
the figures). Then asserting the word line WL enables both the access
transistors M5 and M6, which causes the bit line BL voltage to either
slightly drop (bottom NMOS transistor M 3 is ON and top PMOS
transistor M4 is off) or rise (top PMOS transistor M4 is on). It should
be noted that if BL voltage rises, the BL voltage drops, and vice versa.
Then the BL and BL lines will have a small voltage difference
between them. A sense amplifier will sense which line has the higher
voltage and thus determine whether there was 1 or 0 stored. The

higher the sensitivity of the sense amplifier, the faster the read
operation.

Writing
The write cycle begins by applying the value to be written to the bit
lines. If we wish to write a 0, we would apply a 0 to the bit lines, i.e.
setting BL to 1 and BL to 0. This is similar to applying a reset pulse to
an SR-latch, which causes the flip flop to change state. A 1 is written
by inverting the values of the bit lines. WL is then asserted and the
value that is to be stored is latched in. This works because the bit line
input-drivers are designed to be much stronger than the relatively
weak transistors in the cell itself so they can easily override the
previous state of the cross-coupled inverters. In practice, access
NMOS transistors M5 and M6 have to be stronger than either bottom
NMOS (M1, M3) or top PMOS (M2, M4) transistors. This is easily
obtained as PMOS transistors are much weaker than NMOS when
same sized. Consequently when one transistor pair (e.g. M3 and M4) is
only slightly overridden by the write process, the opposite transistors
pair (M1 and M2) gate voltage is also changed. This means that the M 1
and M2 transistors can be easier overridden, and so on. Thus, crosscoupled inverters magnify the writing processed it RAM.

COMPONENTS REQUIRED
There are various type of components used as following.
1. CMOS
2. CMOS INVERTER
3. NAND GATE
4. AND GATE

COMPONENTS DETAILS

1. CMOS
CMOS is also sometimes referred to as complementary-symmetry
metaloxidesemiconductor

(or

COS-MOS).

The

words

"complementary-symmetry" refer to the fact that the typical design

style with CMOS uses complementary and symmetrical pairs of ptype and n-type metal oxide semiconductor field effect transistors
(MOSFETs) for logic functions Complementary metaloxide
semiconductor, abbreviated as CMOS

is a technology for

constructing integrated circuits. CMOS technology is used in

microprocessors, microcontrollers, static RAM, and other digital logic
circuits. CMOS technology is also used for several analog circuits
such as image sensors (CMOS sensor), data converters, and highly
integrated transceivers for many types of communication.

2. CMOS INVERTER
CMOS inverters are some of the most widely used and adaptable
MOSFET inverters used in chip design. They operate with very little
power loss and at relatively high speed.
This short description of CMOS inverters gives a basic understanding
of the how a CMOS inverter works.
A CMOS inverter contains a PMOS and a NMOS transistor connected
at the drain and gate terminals, a supply voltage VDD at the PMOS
source terminal, and a ground connected at the NMOS source

terminal, were VIN is connected to the gate terminals and VOUT is

connected to the drain terminals.

SIMULATION OF CMOS INVERTER

3. NAND GATE
The NAND gate operates as an AND gate followed by a NOT gate. It
acts in the manner of the logical operation "and" followed by
negation. The output is "false" if both inputs are "true." Otherwise, the
output is "true."

NAND GATE
Input 1

Input 2

Output

SIMULATION OF NAND GATE

AND GATE
The AND gate is so named because, if 0 is called "false" and 1 is
called "true," the gate acts in the same way as the logical "and"
operator. The following illustration and table show the circuit symbol
and logic combinations for an AND gate. (In the symbol, the input
terminals are at left and the output terminal is at right.) The output is
"true" when both inputs are "true." Otherwise, the output is "false."

AND GATE
Input 1

Input 2

Output

SIMULATION OF AND GATE

SOFTWARE REQUIRED
In this project mainly two software are used as following.
1. OrCAD
2. MODELSIM

SOFTWARE DETAIL
1.OrCAD

OrCAD is a proprietary software tool suite used primarily for

electronic design automation (EDA). The software is used mainly by
electronic design engineers and electronic technicians to create
electronic schematics and electronic prints for manufacturing printed
circuit boards.Information system) product for component data
management, along with highly OrCAD Capture is one of the most
widely used schematic design solutions for the creation and
documentation of electrical circuits. Coupled with the optional
OrCAD CIS (component integrated flows supporting the engineering
process, OrCAD Capture is one of the most powerful design
environments for taking todays product creation from concept to
production.
OrCAD EE PSpice is a SPICE circuit simulator application for
simulation and verification of analog and mixed-signal circuits.
PSpice is an acronym for Personal Simulation Program with
Integrated Circuit Emphasis.
OrCAD EE typically runs simulations for circuits defined in OrCAD
Capture, and can optionally integrate with MATLAB/Simulink, using
the Simulink to PSpice Interface (SLPS).OrCAD Capture and PSpice
Designer together provide a complete circuit simuation and
verification solution with schematic entry, native analog, mixed
signal, and analysis engines.
2.MODELSIM

ModelSim-Altera Edition software is licensed to support designs

written in 100 percent VHDL and 100 percent Verilog language and
does not support designs that are written in a combination of VHDL
and

Verilog

language,

also

known

as

mixed

HDL.

Mixed HDL support is available in the PE and SE versions of

ModelSim from Mentor Graphics. ModelSim-Altera Edition only
supports Altera gate-level libraries. The ModelSim-Altera Edition
software includes all ModelSim PE features, including behavioral
simulation, HDL testbenches, and Tcl scripting. However, ModelSim
PE optional features are not supported in the ModelSim-Altera
Edition software and the simulation performance of the ModelSimAltera Edition software is slower than that of the ModelSim PE and
SE software.
Example.

Circuit diagram of MUX

Program of multiplexing

SIMULATION OF MUX

APPLICATION OF PROJECT
Static Random access memory (SRAM) are useful building blocks in
many applications such as a data storage embedded applications,
cache memories, microprocessors. Large SRAM arrays that are
widely used as cache memory in microprocessors and applicationspecific integrated circuits can occupy a significant portion of the die
area. For high density circuits such as SRAM arrays.In an attempt to
optimize the performance of such chips, large arrays of fast SRAM
help to boost the system performance. However, the area impact of
incorporating large SRAM arrays into a chip directly translates into a
higher chip cost. Balancing these requirements is driving the effort to
minimize the footprint of SRAM cells. As a result, millions of
minimum-size SRAM cells are tightly packed making SRAM arrays
the densest circuitry on a chip.

CONCLUTION

A 42 bits SRAM was designed and simulated in 180 Nano meter

CMOS technology using cadence OrCAD 16.3 software. The
simulation results indicate that the proposed design of SRAM circuit
has less Read Access Time compared to the conventional SRAM
circuit. The read access time in the proposed design was 52ns which
is reduced by around 34%.
This shows that the proposed design can be very effective for the
applications which needed high speed SRAMs like Cache Memory
but with cost of proposed design do not increase the power
consumption as only one sense amplifier in each column is active
during the Read operation which is controlled by Row Address of
MSB can be further reduced by considering untouched in this design.

FUTURE SCOPE

As the simulation results shows that the Read Access time was not
reduced up to expectation, there is much more left to do with the
design in future like design of Sense amplifier for Fast Read
operation.
Also the design and Simulation was done in 2 m technology which
would have done at sub-micron level using more advanced tools but it
was not possible due to the unavailability of the needed tools. So, the
preferred task in future is to test the proposed design with 32KB
SRAM at 32 nm Technology.

REFERENCES

1. Andrew Carlson, Sriram Balasubramanian, Radu Zlatanovici, TsuJae King Liu, and Borivoje Nikolic, SRAM Read/Write Margin
Enhancements Using FinFETs, IEEE Transactions on VLSI systems,
September, 2009.
2. S. A. Tawfik and V. Kursun, Low power and roubst 7T dual-Vt
SRAM circuit, in Proc.

IEEE Int. Symp. Circ. Sys., ISCAS 2008,

Seatle, WA, USA, 2008, pp. 14521455.

3. M. Pelgrom, A. Duinmaijer, and A. Welbers, Matching properties
of MOS transistors, IEEE J. Solid-State Circuits, vol. 24, no. 5,
pp.14331440, Oct. 1989.
4. H. Pilo, J. Barwin, G. Braceras, C. Browning, S. Burns, J. Gabric,
S.Lamphier, M. Miller, A. Roberts, and F. Towler, An SRAM design
in 65 nm and 45 nm technology nodes featuring read and write-assist
circuits to expand operating voltage, in Proc. VLSI Circuits Symp.,
2006, pp. 1516.
5. K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray,
N.Vallepalli, Y. Wang, B. Zheng, and M. Bohr, A 3 GHz 70 Mb
SRAM in 65 nm CMOS technology with integrated column-based
dynamic power supply, in Proc. ISSCC, 2005, pp. 4745.