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Line transients
Parasitics
Parasitic inductance, resistance, and capacitance in the
line transient setup (Figure 2) limit the ability of the
3V
SOURCE
5V
SOURCE
CBP
Q1
POWER
SUPPLY
INPUT
CBP
CIN
Q2
POWER
SUPPLY
MAX4428
MAX4428
MOSFET DRIVER
PULSE GENERATOR
BODY DIODE
BODY DIODE
CDG
5V
SOURCE
RS
CDG
LS
LMOSFET
Q1
CBP
RDS_ON
RDS_ON
LMOSFET
RS
Q2
CGS
CGS
3V
SOURCE
LS
CBP
LESR_IN
RESR
RESR_IN
RG
DEVICE
UNDER
TEST
RESR
RG
CIN
LESL
LG
LG
LESL
PULSE
GENERATOR
MOSFET DRIVERS
Figure 2. The circuits ability to deliver a clean step-function waveform is limited by parasitic components in the line-transient setup.
Source parasitics
Occasionally, the layout requires that CIN must be placed
directly at the supplys input. This is because the introduction of a MOSFET between the input bypass capacitor
and power-supply input results in unacceptable operation.
If this is the case, the line voltage step must be imposed
across CIN. To change the voltage by VSTEP in time
(t), the CIN must source or sink a current of
I = CIN
VSTEP
t
MOSFET parasitics
FUNCTION GENERATOR
OR MOSFET DRIVER
RG
Load transients
A good method for generating load-transient steps is to use
an n-channel MOSFET to switch between two different
load resistances at the power-supply output. For transient
tests with large output currents, the MOSFET itself can be
the load element (Figure 3). The MOSFET drain in that
configuration connects to the power-supply output, and its
source connects to ground through a current-sense
resistor. The load resistance is adjusted by stepping the
gate-to-source voltage (VGS). As long as the MOSFET
operates outside its saturation region, adjusting VGS will
vary the MOSFET RDS_ON, and thus the load current.
LPARA
LG
LR
RB
RDS_ON
VOUT
RA
COUT
RSENSE
LPARA
VOUT(s) =
The controllers power-filter gain (GVIN(s)) is the smallsignal gain from input to output. The buck converter, for
example, has a power-filter gain of:
VOUT
VIN
D
s2LCOUT + s
RLOAD
+1
VOUT
I OUT
= RLOAD
1
sCOUT
sL
sL =
s2LCOUT +
ZOUT(s) ILOAD(s)
1 + GFB GC(s)
= GVIN(s)
VREF(s) GC(s)
VIN(s) GVIN(s)
+
1 + GFB GC(s)
1 + GFB GC(s)
sL
+1
RLOAD
ILOAD(s)
ZOUT(s)
L
VIN(s)
GVIN(s)
VOUT(s)
DVIN
COUT
RLOAD
CONTROLLER
GAIN
VREF(s)
FEEDBACK
(a)
(b)
Figure 4. A simplified diagram and schematic for a buck converter is illustrated without feedback (a) and with feedback (b).
VOUT
V(t) =
DCGAIN
s
+1
0
1
(1 + GFB GC(s))
V
(1 + DCGAIN e-(0 + 0DCGAIN)t)
1 + DCGAIN
DC GAIN
GAIN
-20dB/DECADE
0/2
fc
VOUT(t)
0dB
-45/DECADE
PHASE MARGIN = 90
PHASE
-90
0
0
FREQUENCY (Hz)
(a)
TIME (s)
(b)
Figure 5. The Bode plot of single-pole loop gain is shown (a), as well as the time-domain response to a step function (b).
7
1.0
0.8
0.6
13
AMPLITUDE
0.4
)(
s +1
1
0.2
90
74
65
30
48
-0.2
-0.4
-0.6
1000
22
s +1
2
-0.8
1
TIME (s)
2
x 10 -4
1
1 + GFB GC(s)
VIN = 5V
VIN = 5V
5.33A/div
ILOAD
100mV/div
VOUT
5.33A/div
ILOAD
100mV/div
VOUT
100s/div
100s/div
(a)
(b)
IOUT = 0A
VIN = 5V
5.33A/div
ILOAD
2V/div
100mV/div
VOUT
100mV/div
100s/div
VIN
VOUT
100s/div
(c)
(d)
Figure 7. EV kit transient responses are shown for: a load step with 2 phase margin (a); a load step with 11 phase margin (b); a load step with 90
phase margin (c); and a line step with 90 phase margin (d).