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ii.Show the changes made for each instructions: (redraw the circuits to show
changes for each instructions)
-controller and datapath circuits
-decoder and conditional logic circuits
-Main decoder circuit and Table
-ALU circuit, ALU decoder circuit and Table
-PC logic
-newly added components
iii. Show the changes made for each instructions by rewriting the System Verilog
and write new one for the new components
Add more design processes and flow charts if needed.
Branch
MemW
RegW
MemtoR
eg
ALUSrc
ImmSrc
RegSrc
Type
Funct0
Funct5
Op
00
DP
Reg
00
XX
00
DP
Imm
X0
00
01
STR
10
01
01
LDR
X0
01
10
X1
10
assign {RegSrc, ImmSrc, ALUSrc, MemtoReg, RegW, MemW, Branch, ALUOp} = controls;
Funct4:1
(cmd)
Funct0
(S)
Notes
ALUControl
FlagW1:
1:0
Not DP
00
00
0100
ADD
00
00
1
0010
11
SUB
01
1
0000
11
AND
10
1
1100
0
1
00
00
10
ORR
11
00
10
Cycle
rese
t
P
C
00
04
08
Instr
SUB R0,
R15, R15
E04F000F
ADD R2,
R0, #5
E2802005
ADD R3,
R0, #12
E280300C
SrcA
Src
B
Branc
h
AluResul
t
Flags3:0
[NZCV
]
CondE
x
WriteDat
a
MemWrit
e
ReadData
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19