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Lewis Sternberg
lewis@qualis.com
Qualis Design Corporation
Three Centerpointe Drive
Suite 250
Lake Oswego, OR 97035 USA
www.qualis.com
ABSTRACT
Cost and time-to-market are the overwhelming predictors of success -- both for your designs
and your career. By learning and using AMS verification techniques you can avoid being a highly
visible project bottleneck and incurring expensive design iterations.
This paper presents a design flow and methodology suited for challenging AMS projects.
Not only is a more successful project (and career) the result, but also you can spend your nights
and weekends away from the office.
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INTRODUCTION
In the past, the focus on producing AMS ICs has been on the technical challenges of
fabricating wafers with differing technologies economically, while maintaining noise immunity
between the digital and analog circuitry. While these issues are perennial, another issue has come
to the forefront: design and verification methodology.
AMS horror stories are common place:
Missed deadlines
DOA chips
Excessive chip turns
Cancelled projects
How can this be? Analog design and verification methodologies have lagged far behind
advances in digital and AMS technologies what once worked for small analog ICs now destroys
large AMS chip projects.
The methodology presented in this paper is based on behavioral models using an AMS
hardware description language (HDL), such as VHDL-AMS and Verilog-AMS.
From the digital side, the methodology looks like structured verification techniques
using behavioral models such as bus functional models (BFMs) to produce test
harnesses.
From the analog side, the methodology looks like top-down design with bottom-up
verification with behavioral modeling.
From the systems side, the methodology is a combination of 1) basic systems design
and simulation resulting in a specification written in an HDL; and 2) systems-level
testing using proven and tested behavioral models.
From the test engineers side, the methodology looks like a virtual test where the
tester program can be developed using behavioral models before first silicon.
From the customers point of view, the process results in known good simulatable
models usable for design many weeks earlier -- without the IC manufacturer having
to worry about losing IP trade secrets.
Finally, from everyones point of view, the methodology results in a 1000x+-simulation
speed-up and more dependable schedules.
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HISTORIC PERSPECTIVE
Over the past two decades, digital methodologies have advanced from gate-level schematic
capture and manual tape-out to widespread use of HDLs, synthesis tools, formal verification, and
more. Meanwhile, even though analog tools have tended to lag behind, analog and AMS HDLs
have existed for over a decade1 and AMS extensions have been added to digital HDLs2. Despite
these advances in analog computer-aided engineering (CAE) tools, analog methodologies have
largely remained unchanged for decades. Typical methodologies go something like this:
1.
2.
Design the circuitry at the transistor level using schematic capture tools.
3.
Verify the design using a transistor-level simulator (e.g. SPICE) until the design is
fully verified or the simulations take so long that it would be faster to just:
4.
5.
This process has proven itself to work well with designs of several dozen transistors
implemented on a small wafer with limited mask costs and quick fab turn-around. This scenario
is common among analog IC manufacturers and in-house (captive) IC units. However, this
process breaks down with larger analog ICs, and it can be disastrous in large AMS ICs. For
example,
If blocks in one domain (digital/analog) are in the feedback loop of another domain,
the circuit can be unverifiable in simulation. The result is excessive chip turns.
Mask charges can be on the order of $100k, while fab turn-around can be many
weeks. Repeated chip turns can destroy any potential profitability of the design.
IEEE 1076_1-1999 (VHDL-AMS standard). AMS extensions to Verilog (IEEE 1364) are being added at this time.
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Prevalent Methodology
Debug
Debugschedule
schedule
cant
cantbe
bepredicted
predicted
reliably.
reliably.
RTL Coding
Spec
VP
TB
Coding
Ship
Synthesis
Top Tests
RTL+TB Debug
Feedback loops
Feedback loops
exist, but are
exist, but are
left off here.
left off here.
Often
Oftenonly
onlyminimal
minimal
verification
verificationpossible.
possible.
System Tests
Impossible
Impossibledue
dueto
to
simulation
times.
simulation times.
VP : Verification Plan
TB : Testbench
Prod Test Dev : Production Test Development
Figure 1 Prevalent methodology makes it hard predict the RTL and TB debug schedule, limits verification of analog
partitions on large systems to minimal levels only, and postpones production test development until after fabrication.
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If behavioral modeling is not available with your analog simulator, the digital portion may be modeled as macromodels or
as a time-averaged analog transfer function.
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Digital
Analog
Analog
Digital
Analog
Analog Simulation
Digital
Digital Simulation
Modeled
Modeled
in
inanalog
analog
Modeled
Modeled
in
indigital
digital
Figure 2 In the Low-Investment Medium-Payoff solution the analog domain models the digital circuitry behaviorally and
the digital domain models the analog circuitry in the digital HDL. This solution is appropriate for circuitry with loose
digital/analog feedback loops.
An advantage of this technique is that the designers can implement it using the tools currently
in use. It requires neither additional CAE license fees nor new tools to learn. A disadvantage of
this technique is that, while it optimizes making the most of available CAE tools, it tends to
minimize the productivity of the engineer.
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Analog
Digital
Very
Veryslow
slow
Extremely
Extremely
slow
slow
Hours-long
Hours-longsimulations
simulationsturn
turn
to
days-long
simulations
to days-long simulations
June
Figure 3 In the High-Investment Low-Payoff solution the digital and analog partitions are simulated together.This
solution often creates untenable simulation times.
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Behavioral
block
Behavioral
block
Beh
block
Behavioral
block
Figure 4 In the High-Investment High-Payoff solution the design is simulated at the highest level using behavioral
blocks
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Bottom-up
Bottom-up
characterization
characterization
Once
Oncebottom-level
bottom-level
works,
works,back-annotate
back-annotate
characteristics.
characteristics.
Figure 5 Once the design is known to work, move to lower levels of abstraction
Multiple design groups can work on individual blocks. Each group designing
their own block to the implementation level, while simulating their portion with
behavioral models of the rest of the design.
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RTL Coding
Synthesis
Top Tests
VP
Ship
Layout
& Fab
RTL Dbg
TB Cdg + Db
Beh
Analog Design and Simulation
Feedback loops
Feedback loops
exist, but are
exist, but are
left off here.
left off here.
VP : Verification Plan
Beh : Behavioral modeling
TB Cdg + Db : Testbench coding and debug
RTL Dbg : RTL debug
Fastest
Fastesttime
timeto
tomaximum
maximumprofit
profit
Prod Test Dev : Production Test Development
Ship : Make money
Figure 6 The High-Investment Maximum-Payoff solution takes full advantage of the power of AMS behavioral
modeling and the resultant IP
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The Virtual Test division of IMS, Inc. supports digital and AMS testers from a number of tester vendors. Teradyne, Inc.
similarly provides virtual test tools for its own AMS testers.
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CONCLUSIONS
One of lifes paradoxes is that it takes more time and money to get things wrong than to get
them right. As with any job, having the right tools is just part of the story. How theyre used
methodology is the determining factor in getting things right. In the case of AMS chip
designs, its also the difference between a functional chip passing spec on time and in budget, and
interminable ulcer-inducing chip turns and lost sleep.
REFERENCES
www.analogy.com Home page of Analogy (Avant!)
www.eda.org/verilog-ams Open Verilog International Verilog Analog Mixed-Signal Group
www.janick.bergeron.com Web page for: Bergeron, Janick, Writing Testbenches: Functional
Verification of HDL Models, Kluwer Academic Publishers
www.janick.bergeron.com/guild Moderated electronic mail forum dedicated to the
verification of electronic designs and the software that runs them
www.mentorg.com/ams Mentor Graphics web page for Analog Mixed Signal news and
events
www.teradyne.com/prods/icd/vx/ Home page of Teradyne VX Software
www.virtualtest.com Home page of IMS Virtual Test Division
http://www.wkap.nl/book.htm/0-7923-9516-6 Web page for: Mantooth, Alan H,
Fiegenbaum, Mike F. Modeling with an Analog Hardware Description Language, Kluwer Academic
Publishers
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