More Flip-Flop Circuits

Because the latch or flip-flop (ff) is one of the most useful

-- and most used -- circuits in the modern computer, we
spent the last lecture discussing and learning about
several types of these circuits.
A flip-flop
flip flop is useful as memory
memory. It can be set to 1 or 0
and retain that value until triggered to the opposite state.
There are many ffs. We will discuss several more in this
lecture, plus devices made from ffs. In the next lecture,
we will discuss even more complicated ff circuits.
First,
First a review of ffs that we discussed in the last lecture.
lecture

Flip-Flop Review
Set

R-S Flip-Flop
Reset

The R-S Flip flop is the simplest example of sequential logic.

Non-clocked; made off cross-connected 2-input
2i
NANDs
A
((or NORs,
O etc.).
)
Output depends on current state as well as the inputs.
Uses negative-true input logic. Outputs Q and Q are always opposite.
When Q=1, Q=0, the R-S FF is set; when Q=0, Q=1, the ff is reset.
Will not change states unless opposite input triggered.
Only opposite state trigger causes state change
change.
Race condition triggered by R=S=0 (outputs cannot be predicted).

The R-S Flip-Flop

Set

Reset

The truth table for the R

R-S
S FF is relatively simple
simple, as shown below:
Inputs

Current Outputs
New Outputs
S
R
Q
Q
Q
Q
1
1
1 or 0
0 or 1
Same
Same
0
1
0
1
1
0
0
1
1
0
Same
Same
1
0
1
0
0
1
1
0
0
1
Same
Same
0*
0*
1 or 0
0 or 1
1*
1*
* This is a race condition and not stable. The S-R input 0-0 is forbidden.

The Clocked R-S Flip-Flop

Set+

Clock+
Reset+

Clocked R-S Flip-Flop

Simplest
p
clocked ff.
Clock input in addition to the set and reset inputs.
When clock is low (0), neither set or reset input affect the circuit.
Set or reset input must be high (1) to set or reset the ff when the clock
goes true (0 1).
Both set and reset true or 1 together is forbidden as in the nonclocked case; simultaneous set and reset true causes a race condition
when clock is high.

The Clocked R-S Flip-Flop (2)

Set+

Clock+
Reset+

Truth Table: Clocked RS Flip-Flop

Clock
0
1
1
1
1
1
1

Inputs
S
X
0
1
1
0
0
1*

R
X
0
0
0
1
1
1*

Current Outputs
Q
Q
1 or 0
0 or 1
1 or 0
0 or 1
0
1
1
0
1
0
0
1
1 or 0
0 or 1

New Outputs
Q
Q
Same
Same
Same
Same
1
0
Same
Same
0
1
Same
Same
1*
1*

* This is a race condition and not stable, as for the non-clocked RS FF.

The D Flip-Flop
D

(S+)

Clock+
D

R
(R+)

Clocked D Flip-Flop

Created by inserting inverted set into reset input.

If D = 1, ff goes set (set = 1, reset = 0) when clock
is high.
high
If D = 0, ff goes reset when clock goes high (set = 0,
reset=1).
No forbidden inputs.

D Flip-Flop Truth Table

D

(S+)

Clock+
D

Inputs

R
(R+)

Clocked D Flip-Flop

Current Outputs

New Outputs

Clock

1 or 0

1 or 0

Same

Same

Same

Same

Same

Same

Timing Diagrams
1
Clock
Time

It is important when designing sequential circuits to understand

the timing relationships between circuit elements.
Normally done by plotting
i the transitions

i i -- the changes between

logic 1 and logic 0 -- of the elements of interest.
All the timing normally related to the clock.
In the fundamental timing diagram, unless specifically instructed
to do otherwise, always start with the clock (it goes best at the
diagram bottom).
Always assume a 50/50 clock, if duty cycle not specified.

Timing Diagrams (Continued)

Q Output
D Input
p
1
Clock

To illustrate D FF timing by plotting the D FF Q output:

Remember that a D FF output is normally triggered when clock = 1.
Assume D FF is originally reset.
reset. Then on the rising edge of the clock, the
D FF output goes to set (1), when the D input is 1.

On successive clock pulses, the D FF Q changes as D changes.

Principle: Output Q
Q of a simple D FF tracks D when the clock ticks!
Note: The clock is shown running continuously. In some cases, the clock may tick only some times.

Exercise 1

The incomplete timing diagram below shows the clock input as the basis
for the diagram and a D FF input, but not the output. In this case, the
clock does not run continuously, but on a sporadic basis. Based on the
discussion so far, plot the timing of the Q output of the D FF (assume the
D FF starts out in the reset condition). Note that you do not need to see
the ff diagram itself to do the plot.

Q
D
1

Clock

Time

Master-Slave, or Delay Flip-Flops

It is often desirable to have a flip-flop whose output does not

change immediately when its internal state is altered from set
(Q=1) to reset (Q=0), or vice-versa.
This sort of ff is called a master-slave or delay ff.
The idea behind the master
slave ff is to have a master
master (i.e.,
master-slave
controlling) ff change states on one edge of a clock pulse (normally
the leading edge) and have a second ff connected to the first
change to the same state as the master on the trailing edge, or
backside of a clock pulse.
In this way, the internal state of the ff changes one-half clock cycle
prior to the time in which the changed state appears on the circuit
outputs.
11

The Master-Slave D Flip-Flop

D

Clock+

Q
Master

Slave

D FF converted to master-slave type.

The slave (basically a clocked RS FF) always mirrors the
state of the master.
The slave circuit changes state 1/2 cycle after the master.
The device still operates as a D FF; no indeterminate state
state.

Timing of Master-Slave D Flip-Flop

D

Clock+

Q
Master

Slave

Slave FF (Q)
M t FF (Q)
Master
D
1
Clock

D Flip-Flop Symbols

Flip-flop detail is not usually shown in diagrams.

D Q
One symbol for a D FF is shown to the right.
C
There is no small circle on either input. Therefore,
1 is the active state (when clock and D = 1, output
Simple D FF
will 1).
D FFs with asynchronous set and reset are also
S
available.
D
Q
Circles on S and R inputs mean that set and reset are
CR Q
negative-true signals (active at level 0).
Q-not output is also available.
D FF With
Set and reset have the same p
problems discussed
Asynchronous S/R
before: If S = R = 0, output may be indeterminate.

The J-K Master-Slave Flip-Flop

It is often useful to have a FF that will not have indeterminate

outputs when S and R inputs are both 1 simultaneously.
The J-K FF, shown above, fits those requirements. The J input
corresponds to Set, while K corresponds to Reset.
The J-K FF is designed so that the condition of J = K = 1 does not
result in an indeterminate output when clocked.
There may still be asynchronous RS inputs with the usual
cautions. However, the J-K inputs are not restricted.
15

Internals of the J-K Flip-Flop

J

OR

Q
Clock
J-K Master-Slave Flip Flop

A master-slave J-K FF can be designed as shown above.

The key states are J=K=1, for either output state (set or reset).
) and
d J = K = 11, output off the
h OR = 00, so the
h ff will
ill reset.
If Q = 1 (S
(Set)
Likewise, if Q = 0 (Reset) and J = K = 1, OR = 1, and the ff will be set.
(For J=1 and K=0, or J=0 and K=1) normal set or reset occurs.)
Then ffor J = K = 11, when the clock ticks
Q the opposite
i
Q
i state.
6

JK Flip Flop Truth Table

1

J
K

Clock
Inputs

Outputs

AND Outputs

OR Outputs

New Outputs

Same

Same

Same

Same

Same

Same

Same

Same

The Toggle Flip-Flop

T

K
Q
Clock
T Master-Slave Flip-Flop

The T FF is like a JK FF with J and K tied together (K input inverted).

Then if T = 1, and clock = 1, the ff toggles to the opposite state.
If T = 0,, the ff does not change
g state on the clock tick.
The T FF is a master-slave ff; output changes on the back edge of the clock.
Set T = 1 permanently, and the T FF toggles on every clock pulse.
Note Q ttied
ed to the
t e K input
put aand
dQ
Q-not
ot ttied
ed to tthee J input.
put. Thiss feedback,
eedbac ,
along with the connected J and K inputs, enables the T FF to work properly.

Toggle Flip Flop Truth Table

1

Clock
Input
T

Outputs

AND
Outputs

OR Outputs

New Outputs

Same

Same

Same

Same

Master-Slave T FF as a Frequency Divider

1
f/8

Clock (at
frequency f)

f/2

f/4

All T FFs
shown are masterslave.

T FF #3
T FF #2
T FF #1
1
Clock

Timing (Continued)
1
Clock

f/8
f/2

f/4

Pulse Out

C
Clock
ffrequency = f

Suppose that we want to decode a state of the frequency divider

circuit seen on the last slide.
When the /8 and /4 and /2 outputs are high, we want to
AND those signals with clock to get a decoded pulse to perform
some operation
p
((see diagram
g
above).
)
How do we show the timing on this sequential decoder?

Timing (Continued)
1
Clock

2
f/2

3
f/4

f/8
Pulse Out

T FF #3
T FF #2
T FF #1
1
0

Clock

We know that the output of FF #1 clocks FF#2, and so-on, for

number 3.
On the first falling edge of the clock,
clock FF #1 toggles.
toggles On the falling
edge of the Q output of FF #1, FF #2 toggles, etc.
22

Timing (Concluded)
1
Clock

2
f/2

3
f/4

f/8
P l Out
Pulse
O t

Pulse
T FF #3
T FF #2
T FF #1
Clock

1
0

With the signals plotted, we look for the time when the output of
clock and the three Qs are high.
We then diagram Pulse Out based on the AND of the 4 signals.

Flip Flop Summary

We have devoted a good deal of time to the study of
the latch, or flip-flop, because it is important in
modern computer circuitry.
The primary uses for latches are:
D FF: ALU registers, input/output buffers, shift registers,
fast memory.
J-K FF: Certain control functions and status indicators.
T FF: Frequency division and counter circuits.

We will studyy more complex

p ff circuits next.

A Simple Binary Counting Circuit

Computer events are timed and synchronized by a clock,
so keeping track of timing becomes important
important.
Computers do not execute an instruction per clock cycle.
Most computer instructions take several clock periods
All instructions do not take the same number of clock periods

Thus counting clock periods as events is important.

Counting
C
ti pulses
l can b
be d
done b
by bi
binary counters,
t
all
ll off
which are made from master-slave T FFs.
pp counter is based on the T FF frequency
q
y
A ripple
divider seen earlier (next slide).

T FF Frequency Divider
T FF as a frequency divider, with decoded state.
1
Clock

2
f/2

3
f/4

f/8
Pulse Out

T FF #3
T FF #2
T FF #1
Clock

1
0
Flip-Flop Circuits

Frequency Divider as Ripple Counter

1
f/2

Clock ((at
frequency f)

f/4

f/8

Count
MSB

LSB

Consider a variation of the T FF frequency divider.

The three Q outputs become counter digits.
digits The f/8 ff is the most
significant bit (MSB), f/2 the least significant bit (LSB).
The outputs of the ffs represent the binary value of the number of
clock pulses up to 77. Every eight pulses
pulses, the counter starts over.
over
This is a ripple counter, since each stage of the counter must
first change to its new state (which takes a small amount of time)
before it can be the clock
clock for the next stage.
stage It counts modulo
modulo8 since it counts 0-7 over and over again.

T FF Counter
1
f/2

f/4

Count
MSB

f/8

Clock (at
frequency f)

T FF #3

000

001

LSB

010

011

100

101

110

111 MSB

T FF #2

LSB

T FF #1
Clock

1
0
Flip-Flop Circuits

Problems with the Binary Ripple Counter

While the so-called ripple counter works well and dependably in

many situations, it has some problems associated with its name.
The chief problem is that the Q output of each T FF acts as the
clock for the next stage of the counter.
This means that there is some delay due to the circuit parameters
after the clock has set and reset the LSB before the output will
change and clock the next stage.
Each
c sstage
ge adds
dds another
o e set
se of
o delays
de ys to
o thee process.
p ocess.
For a very large counter (with many stages), the delays could get
so serious that the final stage was not clocked until after the clock
to the LSB had started the next clock cycle.
y

Actual Counting Cycle with Ripple Counter

T FF #3

000

001

010

011

100

101

110

111 MSB

T FF #2

LSB

T FF #1
Clock

The real-time cycle of a ripple counter is shown above.

Each succeeding stage is further delayed from the input clock.
By the time the counting pulses get to the third T FF, the delay
may be 1/2 of the original clock cycle!
We will see a solution to this ripple problem in the next lecture.
Flip-Flop Circuits

Exercise 2
Least
Significant
Digit

Bit y

Clock

Bit x
Most
Significant
Digit

Reset

There is a simple way to connect the two master-slave

master slave T flip
flip-flops
flops
above so that they make a counter that counts modulo-4 (i.e., 0-3).
Note that clock is connected to BOTH clock inputs. This counter,
when wired properly, makes a parallel
parallel counter that does not
ripple like the one we studied today.
Wire up this counter so that it counts modulo-4 in parallel. Hint:
Use the T inputs to accomplish the toggling of the two flip-flops
flip flops as
the counter counts. Assume Reset is only invoked at startup.

Exercise 2, Concluded
1
Clock
Reset
i

Bit y

Bit x

LSB

MSB

x
0
0
1
1

y*
0
1
0
1



* Digits shown in
order of significance.

Homework
Write down the two or three most important
things you
o learned today
toda and add to your
o r list
list.
Write down two or three things you did not
clearly understand.
understand After finishing the
assigned reading, if you still have questions, see
mee during
du g ooffice
ce hours.
ou s.
Read Tokheim, 9.5-9.8 and 10.1-10.2.
Complete homework #5.