EECS 579 Fall 2016 Homework No.

1
University of Michigan, EECS Department
EECS 579: Digital System Testing
Professor John P. Hayes
Distribution Date:
Due Date:

Wednesday September 14, 2015

Wednesday September 21, 2015 at 5:00pm in 579 dropbox in BBB 1637.

Your Name (Last, First): ________________________________________________

Unique name: ____________________Student ID: ___________________________
Honor Pledge: I am familiar with the College of Engineering Honor Code. I have neither
given nor received aid on this homework, nor have I noticed any violations of the Honor
Code.
Signature: ____________________________________________________________

INSTRUCTIONS:
1. Solutions should be written on a copy of these sheets, with each answer following the corresponding
question. Insert extra pages as needed, but keep your answers with the corresponding questions.
Computer-printed answers are preferred, but not required. Neatness and good clear English are important !
2. Put a copy your solutions in the dropbox marked EECS 579 in BBB 1637 no later than 5:00pm on the due
date. If you have a time conflict with the due date because of other coursework, personal travel, job
interviews, etc., turn in your homework earlier. Late submissions will not be accepted without a valid written
excuse, such as a letter from a doctor in the case of illness.
3. To ease handling, fill in all the requested information in the box above. Print your name clearly since
students may have the same first or last names. Staple all your sheets together and do not fold them.
4. Explain all your reasoning (i.e., show your work) and state any non-obvious assumptions you make. Also
identify any special references you use, such as Internet sites, books or papers.
5. You should not work in groups on the EECS 579 homework; these are all individual assignments.
You should not discuss your solution methods or your answers with other students. You should
not copy solutions from any sources. The solutions you submit must be your own. Any suspected
violation of this instruction will be referred to the CoE Honor Council.
6. Complete solutions to the homework will be provided when the graded homework is returned. Any request
to have your homework regraded must be submitted with a full written explanation within one week from the
date on which the graded homework is returned.

GRADES

P1 ____;

P2 ____; P3 ____;

Max. 100 points

P4 ____;

P5 ____;

P6 ____;

P7 ____;

Your Grade: ____________

1

Problem 1 [10 points] Testing costs

(a) [5 points] New ATE unit U1 is purchased by an IC manufacturer Swintel for $4.5M (four and a half
million dollars). It has an expected lifetime of six years and a residual value of $2M after six years, at
which point it will be sold and replaced. The buyer signs a maintenance contract with the ATE vendor
whose annual cost is 2.0 percent of the purchase price. The additional annual running costs of U1 for
utilities, staffing, etc. are estimated to be $0.15M. Assume that Swintel produces enough ICs to keep U1
busy 90 percent of the time. Stating the key assumptions you make, calculate the cost per IC of testing a
new chip line assuming each IC requires 10 seconds of time on U1.
(b) [5 points] Suppose Swintel finds that it must reduce its testing cost per IC by 50 percent to stay
competitive. It can do so by buying a cheaper, used ATE unit U2 to replace U1. ATE U2 has no further
resale value and no vendors maintenance contract is available for it. Swintel decides to maintain U2 itself,
which will increase its total annual bill for ATE running costs from $0.15M to $0.3M per year. Explaining
your reasoning, calculate how much Swintel should pay for U2.

Problem 2 [10 points] Defect coverage

[Based on Bushnell & Agrawal, Prob. 1.2] Applying the test scenario of Example 1.1 in Chap. 1 of B&A
to VLSI chip testing, Prob(F|FQ) is defined as the defect coverage. It is the probability with which the test
detects any defect that occurs on the chip. Prob(P|FQ) = 1 Prob(F|FQ) is known as the escape
probability, which is the probability of a bad chip escaping (i.e., passing) the test. Keeping all other
probabilities the same as in Example 1.1, find the defect coverage necessary to reduce the defect level to
250 parts per million (ppm). Note: Read Example 1.1 in the textbook carefully and observe that it does not
assume a good chip never fails the test since it states explicitly that Prob(P|PQ) = 0.95.

Problem 3 [10 points] Fault counting

Consider the 2-bit identity comparator COMP whose logic circuit is given below.
A1
B1

c
A0
B0

F
d

(a) [5 points] How many distinct faults involving a single line stuck-at-0 or stuck-at-1 are associated with
COMP? (We refer to these as SAF or SSL faults.)
Ans. (a):

(b) [5 points] How many multiple stuck-line (MSL) faults are associated with COMP, where an MSL fault
involves one or more lines in the stuck state?
Ans. (b):

g
g=0
g=1
Problem 4 [20 points] Transistor-level faults
ON
OFF
N-type
Most ICs consist of CMOS circuits composed of two
s
d
s
d s
transistor types: N-type and P-type. Each acts like a
g
g=1
g=0
switch with its on-off behavior controlled by the voltage
ON
OFF
P-type
applied to input g, as shown (simplified) on the right.
s
d
s
d s
(a) [4 points] Determine the fault-free logical behavior
of the 10-transistor circuit C appearing below.
Give your answer by filling in the given 5-variable K-map for Cs output function z(a,b,c,d,e).

VDD = logic 1

NPU

T1

abc
000 001 011 010 110 111 101 100
00

z
NPD

c
b

T2

de

01
11
10

Fault-free function z

VSS = logic 0

(b) [16 points] Find the faulty function zi realized by C when one of the following faults Fi is present. F1 =
Primary input a stuck-at-1. (The primary input line a feeds both transistors T1 and T2; it is not shown in the
figure.) F2 = Transistor T1 is stuck in the OFF or open state. F3 = Transistor T2 is stuck in the ON or shorted
state; iv) F4 = primary input line a is short-circuited to primary line b.
Give your answers by filling in the K-maps below. Use the symbol Z for a signal that is in the floating or
high impedance state, and use the symbol U (unknown) for a signal state not in the set {0, 1, Z}. State
any non-obvious assumptions you make.

z1

abc
000 001 011 010 110 111 101 100

z2

00

de

00

01

de

11
10

z3

abc
000 001 011 010 110 111 101 100

01
11
10

01
11
10

z4

00

de

abc
000 001 011 010 110 111 101 100

abc
000 001 011 010 110 111 101 100

00

de

01
11
10

Problem 5 [10 points] Logic-level faults

Lets define a new g-fault logical fault model as follows: Any gate with k inputs can produce an
incorrect response to one or more of its 2k possible input patterns. Hence, to detect all possible (single)
g-faults in a circuit, we must exhaustively test every gate G and propagate any faulty response by G to a
primary output of the circuit.
Show that it is impossible to detect all g-faults in COMP (which is copied below) by identifying all gates
Gi that have undetectable g-faults. Assume at most one gate can be faulty at a time. Your answer should
be a list of gate numbers.
A1
B1

5
9

1
6

2
11

A0
B0

7
10

3
8
4

Ans.: __________________________________________________________

Problem 6 [20 points] Circuit testing

Consider once again the COMP circuit repeated below. You may use any reasonable approach, e.g.,
exhaustive analysis of the circuit, to solve this problem.
A1
B1

c
F

A0
B0

(a) [10 points] Consider the stuck-at fault FT1 = line c stuck-at-0 in COMP; this fault is denoted by c/0.
Determine all possible tests that detect the single fault c/0.
(b) [10 points] Determine all tests that detect the single fault FT2 ={d/1}
(c) [10 points] Determine all tests that detect the double fault FT3 ={c/0, d/1}.
(d) [10 points] Determine all tests that distinguish FT1 from FT2, assuming it is known that only one of
the two faults is present.
Give you answers by putting x in all appropriate rows of the following table.
Tests for

A1A0B1B0

FT1

Tests for

Tests for

FT2

FT3

Tests that distinguish

FT1 and FT2

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Problem 7 [20 points] Stuck-at faults

Consider the class of combinational logic circuits composed entirely of elementary gates (AND, OR,
NAND, NOR, or NOT) that realize a single-output Boolean function z(x1,x2,...xn). XOR, XNOR and other
gate types are considered non-elementary gates and so are not allowed in this problem.
(a) Construct a simple example of a redundant circuit C in which some particular single stuck-at fault F
complements (inverts) the circuits output function; that is, if F is present, z changes to its complement z.
(b) Now suppose that redundancy is not allowed (it is undesirable for several reasons) so that all stuck-at
faults are detectable in every circuit C of interest. Prove that it is impossible for any single stuck-at fault in
C to complement the output z. [Hint: Observe that if F is redundant, it has no test vector, whereas if F
complements z, every input vector is a test for F.]

(Seven problems, 100 points total)

Extra Challenge Problem (optional):

This is an optional problem that will not affect your overall grade in the course.
Problem 7(b) becomes much harder if we replace single fault by multiple fault in the problem statement. Since a multiple fault can affect C in more complex ways than a single fault, it might be possible for
a multiple stuck-at fault to complement z in some cases. However, no one has yet discovered whether this
is possible! I conjectured years ago that, like a single fault, a multiple fault cannot complement the output
of a non-redundant C. But nobody has yet come up with a proof or disproof of this conjecture.
I am offering a prize of $100 to anyone in the class who can resolve the problem by constructing a rigorous
proof of either the truth or falsehood of my conjecture. Note that falsehood can be proved rigorously just
by constructing a counterexample. I would also expect a successful answer to this problem to lead to a
small publication in a technical journal, --- a nice bonus! The offer is open until the end of 2016.