EXPERIMENT NO:4

AIM:Write VHDL programs for the following circuits, check the wave forms
and the hardware generated
a. Decoder
b. Encoder
A. DECODER
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DEC2 is
Port ( A : in STD_LOGIC; B : in STD_LOGIC;
W : OUT STD_LOGIC;X : OUT STD_LOGIC;
Y : OUT STD_LOGIC; Z : OUT STD_LOGIC);
end DEC2;
architecture Behavioral of DEC2 is
begin
w <= (not a) and (not b);
x <= (not a) and b;
y <= (a and (not b));
z <= a and b;
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end Behavioral;
ENTITY AND ITS INTERNAL STRUCTURE:

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BEHAVIOURAL SIMULATION:
PROGRAM:
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY DECA_vhd IS
END DECA_vhd;
ARCHITECTURE behavior OF DECA_vhd IS
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COMPONENT DEC1
PORT(A : IN std_logic;
B : IN std_logic;
W : OUT std_logic;
X : OUT std_logic;
Y : OUT std_logic;
Z : OUT std_logic);
END COMPONENT;
SIGNAL A : std_logic := '0';
SIGNAL B : std_logic := '0';
SIGNAL W : std_logic;
SIGNAL X : std_logic;
SIGNAL Y : std_logic;
SIGNAL Z : std_logic;
BEGIN
uut: DEC1 PORT MAP(
A => A,
B => B,
W => W,
X => X,
Y => Y,
Z => Z);
tb : PROCESS
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BEGIN
wait for 100 ns;
wait;
END PROCESS;
A<= NOT A AFTER 10NS;
B<= NOT B AFTER 20 NS;
END;

WAVEFORM:

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B. ENCODER
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PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ENC is
Port ( X : in STD_LOGIC_VECTOR(3 DOWNTO 0);
Y : out STD_LOGIC_VECTOR(1 DOWNTO 0));
end ENC;
architecture Behavioral of ENC is
begin
PROCESS(X)
BEGIN
CASE D_IN IS
when "1000" => Y<= "00";
when "0100" => Y <= "01";
when "0010" => Y <= "10";
when "0001" => Y <= "11";
when others => Y <= "ZZ";
END CASE;
END PROCESS;
end Behavioral;
ENTITY AND ITS INTERNAL STRUCTURE:
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BEHAVIOURAL SIMULATION:
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PROGRAM:
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY ENC2_vhd IS
END ENC2_vhd;
ARCHITECTURE behavior OF ENC2_vhd IS
COMPONENT ENC4
PORT(X : IN std_logic_vector(3 downto 0);
Y : OUT std_logic_vector(1 downto 0));
END COMPONENT;
SIGNAL X : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL Y : std_logic_vector(1 downto 0);
BEGIN
uut: ENC4 PORT MAP(X => X,Y => Y);
tb : PROCESS
BEGIN
X<="1010";
WAIT FOR 15 NS;
X<="0001";
WAIT FOR 20 NS;
X<="0010";
WAIT FOR 25 NS;
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X<="0110";
WAIT;
END PROCESS;
END;

WAVEFORM:
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EXPERIMENT NO:5
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AIM:Write VHDL programs for the following circuits, check the wave forms
and the hardware generated
a. Half subtractor
b. Full subtractor
A. HALF SUBTRACTOR
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity H_SUB is
Port ( A : in STD_LOGIC;B : in STD_LOGIC;
DIFF : out STD_LOGIC;
BORROW : out STD_LOGIC);
end H_SUB;

architecture Behavioral of H_SUB is

begin
DIFF<= A XOR B;
BORROW<= (NOT A) and B;
end Behavioral;

ENTITY AND ITS INTERNAL STRUCTURE:

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BEHAVIOURAL SIMULATION:
PROGRAM:
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY AB_vhd IS
END AB_vhd;
ARCHITECTURE behavior OF AB_vhd IS
PORT(A : IN std_logic;
B : IN std_logic;
DIFF : OUT std_logic;
BORROW : OUT std_logic);
END COMPONENT;
SIGNAL A : std_logic := '0';
SIGNAL B : std_logic := '0';
SIGNAL DIFF : std_logic;
SIGNAL BORROW : std_logic;
BEGIN
uut: HSUB PORT MAP(
A => A,
B => B,
DIFF => DIFF,
BORROW => BORROW);
tb : PROCESS
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BEGIN
wait for 100 ns;
wait; -- will wait forever
END PROCESS;
A<= NOT A AFTER 10NS;
B<= NOT B AFTER 20 NS;
END;

WAVEFORM:

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Aditya Kaushik
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B. FULL SUBTRACTOR
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FSUB is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
DIFF : out STD_LOGIC;
BORROW : out STD_LOGIC);
end FSUB;
architecture Behavioral of FSUB is
begin
DIFF<=((NOT A) AND (NOT B)AND C) OR ((NOT A) AND B AND (NOT C))
OR (A AND (NOT B) AND (NOT C)) OR (A AND B AND C);
BORROW<=((NOT A) AND C) OR ((NOT A ) AND B) OR (B AND C);
end Behavioral;

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ENTITY AND ITS INTERNAL STRUCTURE:

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BEHAVIOURAL SIMULATION:
PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY FSUB1_vhd IS
END FSUB1_vhd;
ARCHITECTURE behavior OF FSUB1_vhd IS

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COMPONENT FSUB
PORT(
A : IN std_logic;
B : IN std_logic;
C: IN std_logic;
DIFF : OUT std_logic;
BORROW : OUT std_logic);
END COMPONENT;
SIGNAL A : std_logic := '0';
SIGNAL B : std_logic := '0';
SIGNAL C : std_logic := '0';
SIGNAL DIFF : std_logic;
SIGNAL BORROW : std_logic;
BEGIN
uut: FSUB PORT MAP(
A => A,
B => B,
C => C,
DIFF => DIFF,
BORROW => BORROW);
tb : PROCESS
BEGIN
wait for 100 ns;
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wait;
END PROCESS;
A<= NOT A AFTER 10 NS;
B<=NOT B AFTER 20NS;
C<= NOT C AFTER 30NS;
END;

WAVEFORM:

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EXPERIMENT NO:6
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AIM: Write a VHDL program for a comparator and check the wave forms
and the hardware generated.
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity COMP_1 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
EQUAL : out STD_LOGIC;
GREATER : out STD_LOGIC;
LESS : out STD_LOGIC);
end COMP_1;
architecture Behavioral of COMP_1 is
begin
equal <= a xnor b;
less <= (not a) and b;
greater <= a and (not b);
end Behavioral;

ENTITY AND ITS INTERNAL STRUCTURE:

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BEHAVIOURAL SIMULATION:
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PROGRAM:
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY COMP_vhd IS
END COMP_vhd;
ARCHITECTURE behavior OF COMP_vhd IS
COMPONENT COMP_1
PORT(A : IN std_logic;
B : IN std_logic;
EQUAL : OUT std_logic;
GREATER : OUT std_logic;
LESS : OUT std_logic);
END COMPONENT;
SIGNAL A : std_logic := '0';
SIGNAL B : std_logic := '0';
SIGNAL EQUAL : std_logic;
SIGNAL GREATER : std_logic;
SIGNAL LESS : std_logic;
BEGIN
uut: COMP_1 PORT MAP(
A => A,
B => B,
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EQUAL => EQUAL,

GREATER => GREATER,
LESS => LESS);
tb : PROCESS
BEGIN
wait for 100 ns;
wait;
END PROCESS;
A<= NOT A AFTER 10 NS;
B<= NOT B AFTER 20 NS;
END;

WAVEFORM:
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Aditya Kaushik
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EXPERIMENT NO:7
AIM: Write a VHDL program for a Binary to Gray code converter and check
the wave forms and the hardware generated.
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BTG is
Port ( D_IN : in STD_LOGIC_VECTOR(3 DOWNTO 0);
D_OUT : out STD_LOGIC_VECTOR(3 DOWNTO 0));
end BTG;
architecture Behavioral of BTG is
begin
D_OUT(3)<=D_IN(3);
D_OUT(2)<=D_IN(3) XOR D_IN(2);
D_OUT(1)<=D_IN(2) XOR D_IN(1);
D_OUT(0)<=D_IN(1) XOR D_IN(0);
end Behavioral;

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ENTITY AND ITS INTERNAL STRUCTURE:

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BEHAVIOURAL SIMULATION:
PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_Binary_to_gray_vhd IS
END tb_Binary_to_gray_vhd;
ARCHITECTURE behavior OF tb_Binary_to_gray_vhd IS
COMPONENT Binary_to_gray
PORT(B : IN std_logic_vector(3 downto 0);
G : OUT std_logic_vector(3 downto 0));
END COMPONENT;
SIGNAL B : std_logic_vector(3 downto 0) := (others=>?0?);
SIGNAL G : std_logic_vector(3 downto 0);
BEGIN
uut: Binary_to_gray PORT MAP(
B => B,
G => G );
B<=1010 after 10ns,1000 after 20ns;

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WAVEFORM:

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EXPERIMENT NO:8
AIM: Write a VHDL program for a FLIP-FLOP and check the wave forms
and the hardware generated .
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity F_F is
Port ( R : in STD_LOGIC;
S : in STD_LOGIC;
CLK:IN STD_LOGIC;
Q : inout STD_LOGIC;
Qbar : inout STD_LOGIC);
end F_F;
architecture Behavioral of F_F is
begin
Q<=((R AND CLK) NOR Qbar);
Qbar<= ((S AND CLK) NOR Q);
end Behavioral;

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ENTITY AND ITS INTERNAL STRUCTURE:

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BEHAVIOURAL SIMULATION:
PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY FF1_vhd IS
END FF1_vhd;
ARCHITECTURE behavior OF FF1_vhd IS
COMPONENT F_F
PORT(R : IN std_logic;
S : IN std_logic;
CLK : IN std_logic;
Q : INOUT std_logic;
Qbar : INOUT std_logic);
END COMPONENT;
SIGNAL R : std_logic := '0';
SIGNAL S : std_logic := '0';
SIGNAL CLK : std_logic := '0';
SIGNAL Q : std_logic;
SIGNAL Qbar : std_logic;
BEGIN
uut: F_F PORT MAP(
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R => R,
S => S,
CLK => CLK,
Q=> Q,
Qbar => Qbar);
tb : PROCESS
BEGIN
wait for 10 ns;
wait;
END PROCESS;
R<= NOT R AFTER 1 NS;
S<= NOT S AFTER 2 NS;
CLK<= NOT CLK AFTER 1 NS;
END;

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WAVEFORM:

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EXPERIMENT NO:9
AIM: Write a VHDL program for a counter and check the wave forms and
the hardware generated.
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity COUNT4 is
Port ( CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(3 DOWNTO 0));
end COUNT4;
architecture Behavioral of COUNT4 is
SIGNAL TMP:std_logic_vector(3 downto 0);
begin
PROCESS(CLK,CLR)
BEGIN
if (CLR='1') then
tmp <= "0000";
elsif (CLK'event and CLK='1') then
TMP<= tmp + 1;
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END if;
end process;
Q <= tmp;
end Behavioral;

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ENTITY AND ITS INTERNAL STRUCTURE:

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BEHAVIOURAL SIMULATION:
PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

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ENTITY CNT_vhd IS
END CNT_vhd;
ARCHITECTURE behavior OF CNT_vhd IS
COMPONENT COUNT4
PORT(
CLK : IN std_logic;
CLR : IN std_logic;
Q : OUT std_logic_vector(3 downto 0));
END COMPONENT;
SIGNAL CLK : std_logic := '0';
SIGNAL CLR : std_logic := '0';
SIGNAL Q : std_logic_vector(3 downto 0);
BEGIN
uut: COUNT4 PORT MAP(
CLK => CLK,
CLR => CLR,
Q => Q);
tb : PROCESS
BEGIN
wait for 100 ns;
wait;
END PROCESS;
CLK <= NOT CLK AFTER 10 NS;
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clr<= not clr after 200 ns;

END;

WAVEFORM:

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Aditya Kaushik
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EXPERIMENT NO:10
AIM: Write a VHDL program for a BCD to Seven Segment code converter
and check the wave forms and the hardware generated.
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCD7 is
Port ( BCD : in STD_LOGIC_VECTOR(3 DOWNTO 0);
SEG7 : out STD_LOGIC_VECTOR(6 DOWNTO 0));
end BCD7;
architecture Behavioral of BCD7 is
begin
PROCESS(BCD)
BEGIN
CASE BCD IS
WHEN "0000"=> SEG7<="1111110";
WHEN "0001"=> SEG7<="0110000";
WHEN "0010"=> SEG7<="1101101";
WHEN "0011"=> SEG7<="1111001";
WHEN "0100"=> SEG7<="0110011";
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WHEN "0101"=> SEG7<="1011011";

WHEN "0110"=> SEG7<="1011111";
WHEN "0111"=> SEG7<="1110000";
WHEN "1000"=> SEG7<="1111111";
WHEN "1001"=> SEG7<="1111011";
WHEN OTHERS=> SEG7<="1111111";
END CASE; END PROCESS;
end Behavioral;

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ENTITY AND ITS INTERNAL STRUCTURE:

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Aditya Kaushik
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WAVEFORM:

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BEHAVIOURAL SIMULATION:
PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY AC_vhd IS
END AC_vhd;
ARCHITECTURE behavior OF AC_vhd IS
COMPONENT BCD7
PORT(BCD : IN std_logic_vector(3 downto 0);
SEG7 : OUT std_logic_vector(6 downto 0));
END COMPONENT;
SIGNAL BCD : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL SEG7 : std_logic_vector(6 downto 0);
BEGIN
uut: BCD7 PORT MAP(
BCD => BCD,
SEG7 => SEG7);
tb : PROCESS
BEGIN
wait for 100 ns;
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wait;
END PROCESS;
BCD(0)<= NOT BCD(0) AFTER 1000000000 NS;
BCD(1)<= NOT BCD(1) AFTER 200 NS;
BCD(2)<= NOT BCD(2) AFTER 300 NS;
BCD(3)<= NOT BCD(3) AFTER 400 NS;
END;

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