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Course Information
Course Name: Digital Electronics
Course Code : UGEA1323
Classification: Engineering Subject
Credit Hour: 3
Trimester and Year offered: Jan Trimester Year 1
Pre-requisite (if any): None
Mode of Delivery:Lectures, Tutorials dan Practicals
Assessment System and Breakdown of Marks:
Continuous Assessment
40%
Final Examination
60%
Total
100%
Name(s) of Academic Staff:
Course Objective:
The objectives of this course are to:
To provide an understanding of the fundamentals of digital logic.
To provide knowledge on the design and analysis of combinational logic circuits and simple
sequential logic circuits.

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Course Learning Outcomes:

On completion of this course, a student shall be able to:
1. Apply the fundamentals of digital logic.
2. Design and analyse combinational logic circuits.
3. Design sequential logic circuits using flip-flops.

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Course Synopsis:
The course covers the principles of digital logic (number systems and codes, Boolean algebra
and minimization techniques), the design and analysis of combinational logic circuits,
synchronous sequential logic and programmable logic.

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Topics and Notional Hours:

Topic 1: Introduction
Digital and analog systems.
Digital system design hierarchy.
Logic levels and gates.
ICs.
Topic 2: Numbers Systems and Codes
Number systems.
Base conversions.
Binary arithmetic.
Signed numbers representation.
Binary codes
Topic 3: Boolean Algebra and Minimization
Boolean expressions and truth table.
Boolean algebra. De Morgans theorem.
Canonical forms.
Minimization using Karnaugh maps: 2, 3, 4 and
5 variable maps.
Minimization using tabular method: QuineMcCluskey.
Dont care states
Topic 4: Combinational Logic
Design and analysis of two-level and multi-level
circuits.
Design using only NAND and NOR gates.

Contact Hours
T
P

Learning
Outcome
1

1, 2

10

SL

TLT

6.5

10.5

14

24

22

36

Gate delays and timing diagrams.

Hazards.
MSI combinational logic circuits: Half and full
adders.
Adder and subtractor circuits. Comparators.
Multipliers.
Multiplexers, decoders, encoders codes.
3

Topic 5: Synchronous Sequential Logic

RS, JK, T and D flip-flops.
Registers and counters.
State machine: Mealey and Moore model.
State diagrams and state tables.
Reduction of state tables.

Topic 6: Programmable Logic

Basic of ROM, RAM, PLA, PAL, CPLD and
3
FPGA.
Application of PLDs in combinational and
sequential circuits.
Assessment methods
Includes Test/Assignments/Lab Assignment/Final actual exam time
Total Notional Hours
Equivalent total lecture hours
Total equivalent lecture hours
Credit Value

10

35
35

5
2.5
42

22

36

8.5

13.5

9
4.5

83
-

132
-

Main Reference:
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1. Roth, Charles H. (2013). Fundamentals of Logic Design. (7 ed.). Nelson Engineering.

Additional Reference(s):
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2. Tocci, Ronald J. (2013). Digital Systems: Principles and Applications. (11 ed.).
Pearson.
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3. Floyd, Thomas. (2015). Digital Fundamentals. (11 ed.). Pearson.
4. Wakerly, John F. (2008). Digital Design: Principles and Practices. (4th ed.). Pearson.
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Date of Senate Approval: 4 August 2016

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