Republic of the Philippines

Mindanao State University - Iligan Institute of Technology

College of Engineering
Tibanga, 9200 Iligan City, P.O. Box No.5644 Tel. Nos. (063) 221-4050 Loc.130
Direct line (063) 2351E-mail:fbalagao@yahoo.com
Homepage: http://www.msuiit.edu.ph/coe

Department of Electrical, Electronics and Computer Engineering

Laboratory No. 1

MOS Inverter Design and

Layout
In partial fulfillment for the course
ECE 135 (CAD Tools and Layout)

Submitted by:
TOLEDO, John Xavier P.

Submitted to:
Prof. Jefrey C. Pasco

March 2016
ABSTRACT

The lay-outing and analysis techniques for inverter are discussed in

this paper. First, the discussion involves on the pre-simulation analysis for
propagation delay and data gathering for the rise/fall time of an inverter
using HSPICE simulations. Second, the discussion involves about the
schematic formation of inverter which uses paired transistors to create
inversion which means pulling up and pulling down of the current input, and
the construction for inverter symbol which will be used in test bench analysis
for propagation delay analysis. Finally, the discussion involves the lay-outing
of the inverter using 0.18um technology and the test analyses -DRC, LVS and
LPE- used for propagation delay and data gathering. The comparison for both
pre-simulation and post-simulation is also discussed in this paper.
INTRODUCTION
An inverter or NOT logic gate, the most basic of all the logical gates
and is sometimes referred to as an Inverting Buffer or simply a Digital
Inverter. It is a single input device which has an output level that is normally
at logic level 1 and goes LOW to a logic level 0 when its single input is
at logic level 1, in other words it complements its input signal.

Figure 1. Graphical Representation or symbol of a NOT gate and its truth

table.
OBJECTIVES
a. To obtain and compare the propagation delay analyses for both presimulation and post-simulation of the CMOS inverter.
b. To have a rise/fall time values of post-simulation which is lesser than
the pre-simulation.
c. To able to lay-out the CMOS inverter in a 0.18um technology.

d. To be able to pass the test analyses for lay-out inverter using DRC and
LVS.
RESULTS and DISCUSSIONS
a. Pre-Simulation

Figure 2. Input and Output Voltages for HSPICE-simulated inverter test

bench.
From the graph presented above, the input voltage is the pulse width
modulator from 0v to 1.8 volts with 10ns rise time, 10ns fall time, 10ns delay
time, 40ns pulse width and 100ns pulse repetition but the custom waveview
input has a 8n rise and fall time, while the output voltage is the inverted

waveform of the input pulse with 4.71ns rise time, 3.73ns fall time, 44ns
pulse width and 99ns pulse width repetition.

b. Post-Simulation

Figure 3. Schematic Diagram for Inverter in Synopsys.

To create the schematic diagram for the inverter, the NMOS and PMOS
transistors are drawn out from analoglib while the Vdd and Gnd are drawn
out from basic lib then, connecting the pins as shown above. The drains of
both transistors are connected along the Vout pin and also, the gate which is
connected to a Vin pin. The substrate for NMOS is connected to ground while
the substrate for PMOS is connected to source voltage.

Figure 4. Test bench schematic for Inverter.

Figure 5. Layout Orientation for PMOS.

Polysilicon gate layer of the PMOS is having a height of 8.88m and a
length of 0.5m with a multiplier equal to 2. The diffusion layer has a height
of 8.40m with a width covering the 2 drain via connected together using
Metal1 layer and 1 source via connected to the guard ring with a metal1 pin

connected to source voltage, vdd!. The guard ring for the PMOS is a N-active
via covering the whole PMOS and the PIMP layer is covering the diffusion
layer. The polysilicon gate layer is bonded together using Metal2 pins and
layer including the polysilicon layer of the NMOS and also, the connected
drain is bonded with the drain of the NMOS using Metal 2 pins and layer. For
the finalization of PMOS, the whole device is covered with minimum amount
of NWELL layer.

Figure 6. Layout Orientation for NMOS.

Polysilicon gate layer has a width of 0.5m and a height of 3.44m
with a multiplier of 2. The diffusion layer has a height of 3.0m covering the
2 polysilicon gate layer, 2 drains via and 1 source via. After the diffusion was
covered, two polysilicon layers are created with minimum width to be used
as dummies outside the diffusion layer with a minimum distance of 0.1m.
By routing, the drains for the NMOS are connected together and a Metal2

pins and layer are used to be connected to the drain of PMOS. The two
polysilicon gate layers are connected together using Metal 1, and another
Metal2 pins and layer are used to be routed in the poly gate of PMOS. To
cover up the device, a NIMP layer is used following the minimum distances to
other layers, and a P-active via is used as a guard ring while the source via is
connected to the guard ring using Metal1 layer and Metal1 pin as a ground,
gnd!. Using Metal 3 pin and layer, the routed poly gate is to be directed as
input voltage while the routed drain is to be directed as output voltage.

Figure 7. Waveform for Input and Output voltages for post-simulation in TT.
According to the graph above, the rise time from 0v to 1.8v is 4.4ns
and the fall time from 1.8v to 0v is 3.51ns using Typical-Typical (TT) setting
for both NMOS and PMOS transistors.

Figure 8. Waveform for Input and Output voltages for post-simulation in SS.
According to the graph above, the rise time from 0v to 1.8v is 5.14ns
and the fall time from 1.8v to 0v is 3.72ns using Slow-Slow (SS) setting for
both NMOS and PMOS transistors.

Figure 9. Waveform for Input and Output voltages for post-simulation in FF.
According to the graph above, the rise time from 0v to 1.8v is 4.28ns
and the fall time from 1.8v to 0v is 3.61ns using Fast-Fast (FF) setting for
both NMOS and PMOS transistors.
CONCLUSION
Two post-simulation processes have a lesser rise and fall times, namely
the TT and FF corner processes. The TT corner process has a 4.4ns and
3.51ns rise time and fall time, respectively and the FF corner process has a
4.28ns and 3.61ns rise time and fall time, simultaneously while the presimulation TT corner process, as a basis, has a 4.71ns and 3.73ns rise/fall

time so it can be concluded that the layout gives a better output voltage as
expected. As for the SS corner process, the 3.72ns fall time is better while
5.14ns is not a good rise time but taking it with considerations for the SS
process, it can be said that the layout process, as an overall, has a good
performance and can be concluded that, it has meet the desired output for
this laboratory activity.