It Digital Electronics Lab Manuel

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LABORATORY REGULATIONS AND SAFETY RULES
The following Regulations and Safety Rules must be observed in all concerned
laboratory location.
It is the duty of all concerned who use any electronics laboratory to take
all reasonable steps to safeguard the HEALTH and SAFETY of themselves
and all other users and visitors.
Be sure that all equipment is properly working before using them for
laboratory
exercises. Any
defective
equipment
must
be
reported
immediately to the Lab. Instructors or Lab. Technical Staff.

Students are allowed to use only the equipment provided in the
experiment manual.
Power supply terminals connected to any circuit are only energized with
the presence of the Instructor or Lab. Staff.
Avoid any part of your body to be connected to the energized circuit and
ground.
Switch off the equipment and disconnect the power supplies from the
circuit before leaving the laboratory.
Observe
cleanliness
and
proper
laboratory
housekeeping
of
the
equipment and other related accessories.

Make sure that the last connection to be made in your circuit is the
power supply and first thing to be disconnected is also the power supply.
Equipment should not be removed, transferred to any location without
permission from the laboratory staff.
Students are not allowed to use any equipment without proper orientation and
actual hands on equipment operation.
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EXTRACT OF ANNA UNIVERSITY SYLLABUS
DIGITAL LABORATORY COMPUTER SCIENCE & ENGINEERING
LIST OF EXPERIMENTS
1. Verification of Boolean theorems using digital logic gates

2. Design and implementation of combinational circuits using basic gates for
arbitrary functions, code converters, etc.
3. Design and implementation of 4-bit binary adder / subtractor using basic
gates and MSI devices
4. Design and implementation of parity generator / checker using basic gates
and MSI devices
5. Design and implementation of magnitude comparator
6. Design and implementation of application using multiplexers/Demultiplexers
7. Design of RS and JK flip flops Using NAND gates
8. Design and implementation of Shift registers
9. Design and implementation of Synchronous counters
10. Design and implementation of Asynchronous counters
11. Simulation
of
combinational
circuits
using
Hardware
Description
Language (VHDL/ Verilog HDL software required)

12. Simulation of sequential circuits using HDL (VHDL/ Verilog HDL
software required)
Lab in- Charge
Bread-Board is used in a laboratory for constructing the different circuits and

testing them. This is very useful since here; we do not have to solder the different
components. Soldering, as you know can be very time consuming. Further, we can reuse the
components again and again, since they are not cut and soldered. Let us learn below how we
can use the breadboard for such applications. The breadboard contains a number of metal
clips aligned beneath the array of holes so that when we insert the lead of a component
(say, resistor) inside a hole, the clip grips the lead tightly. Observe the figure. Fig(a) shows a
metal clip before a component inserted, while Fig(b) shows after the lead inserted. Fig(c)
shows a clip which is beneath an array of 5-holes. All the five holes correspond to one node
since all of them are connected together electrically by the metal clip. That means up to 5
wires can be connected to this single node.
Pin Details of Digital Logic Gates:
Postulates and Theorems of Boolean algebra:
S.
Postulate/Theorem
No
Duality
Remarks
1.
X+0=X
X.1 = X
2.
X + X = 1
X.X = 0
3.
X+X=X
X.X = X
4.
X+1=1
X.0 = 0
5.
(X) = X
6.
X+Y=Y+X
X.Y = Y.X
Commutative
7.
X + (Y + Z) = (X + Y) + Z
X.(Y.Z) = (X.Y).Z
Associative
8.
X.(Y + Z) = X.Y + X.Z
X + (Y.Z) = (X + Y)(X + Z)
Distributive
9.
(X + Y) = XY
(XY) = X + Y
10.
X + XY = X
X.(X + Y) = X
DeMorgans
Theorem
Absorption
Involution
Bit Grouping:
Bit
A single, bivalent unit of binary.

Equivalent to a decimal "digit."
Crumb, Tydbit, or Tayste
Two bits.
Nibble or Nybble
Four bits.
Nickle
Five bits.
Byte
Eight bits.
Deckle
Ten bits.
Playte
Sixteen bits.
Dynner
Thirty-two bits.
Word
(system dependent).
Arithmetic Notations:
Augend
Addend
Sum
Minuend
Subtrahend
Difference
Multiplicand
Multiplier
Product
Dividend
Divisor
Quotient
Verification of Logic Gates:
EXP. NO : 1
DATE
VERIFICATION OF BOOLEAN THEOREMS USING DIGITAL LOGIC GATES

---------------------------------------------------------------------------------------Aim:
To verify the truth table of basic Boolean algebric laws by using logic gates.
Components Required:
S.NO
1
COMPONENTS
Digital IC trainer kit
IC
3
4
Bread board
Connecting wires
RANGE
7400
7402
7404
7408
7432
7486
-
QUANTITY
1
1
1
1
1
1
1
1
As required
Theory:
Demorgans Theorems
First Theorem:
It states that the complement of a product is equal to the sum of the

complements.
(AB) =A +B
Second Theorem:
It states that the complement of a sum is equal to the product of the
complements.
(A+B) =A.B
Boolean Laws:
Boolean algebra is a mathematical system consisting of a set of two or more
distinct elements, two binary operators denoted by the symbols (+) and (.) and one
unary operator denoted by the symbol either bar (-) or prime (). They satisfy the
commutative, associative, distributive and absorption properties of the Boolean algebra.
Commutative Property:
Boolean addition is commutative, given
by A+B=B+A
Boolean algebra is also commutative over multiplication, given
by A.B=B.A
De-Morgans Theorem: 1
De-Morgans Theorem: 2
Associative Property:
The associative property of addition is given
by A+ (B+C) = (A+B) +C
The associative law of multiplication is given
by A. (B.C) = (A.B).C
Distributive Property:
The Boolean addition is distributive over Boolean multiplication, given
by A+BC = (A+B) (A+C)
Boolean multiplication is also distributive over Boolean addition given
by A. (B+C) = A.B+A.C
Realization of circuits for Boolean expression after simplification:
A binary variable can take the value of 0 or 1. A Boolean function is an
expression formed with binary operator OR, AND and a unary operator NOT,
parenthesis function can be 0 or 1.
For example, consider the function
The prime implicants are found by using the elimination of complementary function. The
circuit diagram for the function is drawn using AND.OR and NOT gates. The output for
the corresponding input of A1, A0, B1, BO is calculated and the truth table is drawn.
Procedure:
1. Test the individual ICs with its specified verification table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and
ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.
5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.
Commutative Law:
Truth Table:
Input
Output
A+B
B+A
Associative Law:
Truth Table:
Input
Output
A+B
(A+B)+C
B+C
A+(B+C)
Distributive Law:
Truth Table:
Input
Output
B+C
A.(B+C)
A.B
A.C
A.B+A.C
Description
Max.
Marks
Marks
Secured
Preparation
30
Performance
40
Viva Voce
10
Record
20
Total
100
Staff Signature
Result:
Thus the verification of Boolean laws and theorems using digital logic gates
were performed.
Truth Table for Arbitrary Function:
Input
Output
A1
A0
B1
B0
Realization of simplified Boolean
expression using K-Map:
EXP. NO: 2
DATE
DESIGN AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS USING

BASIC GATES FOR ARBITRARY FUNCTIONS AND CODE CONVERTERS
---------------------------------------------------------------------------------------------------
Aim:
To design and implement a combinational circuit to convert gray code to Binary
and BCD to Excess-3 vice versa.
S.NO
1
COMPONENTS
Digital IC Trainer kit
IC
3
4
Connecting wires
Bread board
RANGE
7404
7408
7432
7486
-
QUANTITY
1
1
2
1
1
As required
1
Theory:
Binary to Gray Vice versa:
The binary coded decimal (BCD) code is one of the early computer codes. Each
decimal digit is independently converted to a 4 bit binary number. A binary code will
have some unassigned bit combinations if the number of elements in the set is not a
multiple power of 2. The 10 decimal digits form such a set. A binary code that
distinguishes among 10 elements must contain at least four bits, but 6 out of the 16
possible combinations remain unassigned. Different binary codes can be obtained by
arranging four bits in 10 distinct combinations. The code most commonly used for the
decimal digits is the straight binary assignment. This is called binary coded decimal.
The gray code is used in applications where the normal sequence of binary
numbers may produce an error or ambiguity during the transition from one number to
the next. If binary numbers are used, a change from 0111 to 1100 may produce an
intermediate erroneous number 1001 if the rightmost bit takes longer to change in
value than the other three bits. The gray code eliminates this problem since only one bit
changes in value during any transition between two numbers.
Truth Table (Binary to Gray):
Binary (Input)
Gray (Output)
B3
0
B2
0
B1
0
B0
0
G3
0
G2
0
G1
0
G0
0
BCD to Excess 3 Vice versa:
Excess 3 code is a modified form of a BCD number. The excess 3 code can be
derived from the natural BCD code by adding 3 to each coded number. For example,
decimal 6 can be represented in BCD as 0110. Now adding 3 to the given number yield
equivalent excess 3 code i.e., 6 + 3 = 9 0110 + 0011 = 1001. Thus for the entire
sequence of BCD value (i.e., 0 to 9) excess 3 equivalent table should be made so that
the realization of Boolean expression for the circuit implementation is feasible. In the
reverse process of designing a code converter from excess 3 to BCD the same
procedure is followed. Here are the general steps to be followed while going for a code
converter design,
start with the specification of the circuit to be designed.
Identify the inputs and outputs
Derive truth table
Obtain simplified Boolean equations
Draw the logic diagram
Check the design to verify correctness with the truth/verification table.
Logic Diagram:
Pin Diagram:
Procedure:
3. Make sure that the ICs are enabled by giving the suitable Vcc and
ground connections.
Verify the observed logic output with the verification/truth table given.
Truth Table (Gray to Binary):
G3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Gray (Input)
G2
G1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
G0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Binary (Output)
B2
B1
B0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
1
0
1
0
0
1
0
1
1
1
1
1
1
0
1
0
0
1
0
1
0
0
0
0
0
1
0
1
1
0
1
0
Logic Diagram:
Truth Table:
BCD Input
Excess 3 output
Decimal
Value
Realization of Boolean Expression for BCD to Excess 3 Converter:
Circuit Diagram:
Truth Table:
Decimal
Value
Excess 3 Input
BCD Output
Realization of Boolean Expression for Excess 3 to BCD Converter:
Circuit Diagram:
Description
Max.
Marks
Marks
Secured
Preparation
30
Performance
40
Viva Voce
10
Record
20
Total
100
Staff Signature
Result:
Thus the combinational circuit for an arbitrary function, code converter using
logic gates was designed, implemented and tested its performance with truth table.
Logic Diagram:
Pin Diagram:
EXP. NO : 3
DATE
DESIGN AND IMPLEMENTATION OF 4 BIT BINARY ADDER / SUBTRACTOR

USING MSI DEVICES
-----------------------------------------------------------------------------------------------Aim:
To design and implement a four bit binary adder / subtractor using MSI devices.
Apparatus Required:
S.NO
COMPONENTS
IC trainer kit
ICs
Connecting wires
RANGE
QUANTITY
7483
7486
Theory:
Digital computers perform a variety of information processing tasks. Among the
functions encountered are the various arithmetic operations. The most basic arithmetic
operation is the addition of two binary digits. This simple addition consists of four
possible elementary operations: 0+0=0, 0+1=1, 1+0=0 and 1+1=10.
A binary adder-subtractor is a combinational circuit that performs the arithmetic
operations of addition and subtraction with binary numbers. A combinational circuit that
performs the addition of two bits is called half adder. One that performs the addition of
three bits is a full adder. A binary adder is a digital circuit that produces the arithmetic
sum of two binary numbers.
Procedure:
1. Connect the circuit as per the circuit diagram.
2. Power supply is switched ON and a voltage of 5v is maintained.
3. Four bit binary number is given and verifies the sum result.
4. If the adder or subtractor signal is low addition is performed.
5. If the adder or subtractor signal is high subtractor result is verified.
Verification Table:
Terminology
Input Variables
Augend
A3
A2
A1
A0
Addend
B3
B2
B1
B0
Results
Cin
Cout
Addition
Subtraction
Binary inputs
Description
Max.
Marks
Preparation
30
Performance
40
Viva Voce
10
Record
20
Total
Marks
Secured
100
Staff Signature
Result:
Thus the 4 bit parallel adder/subtractor was implemented and tested using the
MSI device IC 7483.
Truth Table (Even and odd parity generator):
D1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Data Inputs
D2
D3
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
D4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Parity Bit
Even Odd
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
EXP. NO : 4
DATE
DESIGN AND IMPLEMENTATION OF PARITY GENERATOR AND CHECKER

---------------------------------------------------------------------------------------------------
Aim:
To design and implement the parity generator and checker using logic gates
and verify its performance with the verification table.
S.NO
1
COMPONENTS
Digital IC Trainer kit
IC
3
4
Connecting wires
Bread board
RANGE
7486
7474
7404
-
QUANTITY
1
1
2
1
As required
1
Theory:
Parity generator:
A parity bit is a scheme of detecting error during transmitting of binary
information. A parity bit is an extra bit included with a binary message to make the
number of 1s either odd or even.
Parity generators are used in digital transmission system for the errorless
transmission of digital data. A parity bit is added to the data before the transmission
and it will be checked for the correctness at the receiver end. There are two types of
parity systems, even parity and odd parity. In the even parity system if the number of
1s in the data word is odd, a 1 will be added as a parity bit to the data to make total
number of 1s even. If the number of 1s even, a 0 bit will be added. In the odd parity
system if the number of 1s in the data word is odd, a 0 will be added to make the
number of 1s odd. Otherwise, a 1 is added to make it odd. The circuit shown in the
figure is used as a parity generator as well as a checker. ABCD is the 4-bit data word. Pi
and Po are the parity input and parity output respectively.
The working of the circuit can be concluded as follows,
Work as a Parity generator:
To generate an odd parity bit for ABCD, Pi must be made 0. To
generate an even parity bit for ABCD, Pi must be made1.
Work as a parity checker:

If the parity of ABCD Pi is odd, Po will be 0.
If the parity of ABCD Pi is even, Po will be 1.
Circuit Diagram:
Pin Diagrams:
The message, including the parity bit, is transmitted and then checked at the
receiving end for errors. An error detected if the checked parity does not correspond
with the one transmitted. The circuit that generates the parity bit in the transmitter is
called a parity generator. The circuit that checks the parity in the receiver is called
parity checker. In even parity the added parity bit will make the total number of 1s an
even amount. In odd parity the added parity bit will make the total number of 1s an odd
amount.
Procedure:
3. Make sure that the ICs are enabled by giving the suitable Vcc and ground
connections.
Truth Table for Even Parity Checker
4 BIT DATA RECEIVED

A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PARITY ERROR
CHECK
PEC
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
Circuit Diagram:
K-Map Simplication for Even Parity Checker
Description
Max.
Marks
Marks
Secured
Preparation
30
Performance
40
Viva Voce
10
Record
20
Total
100
Staff Signature
Result:
Thus the Parity Generator was designed, implemented using logic gates and
its performance was verified.
EXP. NO: 5
DATE
DESIGN AND IMPLEMENTATION OF 2 BIT MAGNITUDE COMPARATOR

-----------------------------------------------------------------------------------------------AIM:
To design and implement a 2-bit magnitude comparator using logic gates.
COMPONENTS REQUIRED:
S.NO
1
3
4.
COMPONENTS
Digital Trainer Kit
ICs
RANGE
7404
7486
7408
7432
QUANTITY
1
1
1
3
1
As required
Connecting Wires /
Patch Cords
Bread board
THEORY:
The comparison of two numbers is an operation that determines if one number is greater
than, less than, or equal to the other number. A magnitude comparator is a combinational circuit
that compares the two numbers, A and B, and determines their relative magnitude.
n
The circuit for comparing two n-bit numbers has 2 entries in the truth table and becomes
too cumbersome even with n=3. On the other hand comparator circuits possess a certain
amount of regularity. The algorithm is a direct application of the procedure a person uses to
compare the relative magnitudes of two numbers. Consider two numbers, A and B, with four
digits each consider
A=A3A2A1A0
B=B3B2B1B0
The two numbers are equal if all pairs of significant digits are equal: A 3=B3, A2=B2, A1=B1 and
A0=B0. When the numbers are binary, the digits are either 0 or 1, and the equality relation of
each pair of bits can be expressed logically with an EX-OR function
xi =Ai Bi + Ai Bi for i=0,1,2,3 The

binary variables A=B=X1X0 =1.
A>B= Ai Bi + X1 A0 B0 A<B = Ai
Bi + X 1 A 0 B0
Truth Table (2 Bit magnitude Comparator):
Input
Output
A1
0
A0
0
B1
0
B0
0
Ai = Bi
1
Ai > Bi
0
Ai < Bi
0
Procedure:
connections.
Description
Max.
Marks
Preparation
30
Performance
40
Viva Voce
10
Record
20
Total
Marks
Secured
100
Staff Signature
RESULT:
Thus the 2 bit magnitude comparator was constructed using logic gates and verified with
its truth table.
Implementation of the following Boolean function F= m (1, 3, 5 6) using multiplexer

Truth table
Minterm
0
1
2
3
4
5
6
7
Inputs
Output
(F)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
Logic diagram:
EXP. NO : 6
DATE
DESIGN AND IMPLEMENTATION OF APPLICATION USING MULTIPLEXERS

----------------------------------------------------------------------------------------------
Aim:
To design and implement the combinational logic using multiplexers
Components required:
S.
No
1
Components Name
Range
Type
Quantity
IC
7408
IC
7404
IC
7432
Bread Board
Connecting wires
As required
Theory:
The Block diagram shows the implementation of Boolean function using 4:1 multiplexer.
The implementation table is nothing but the list of the inputs of the multiplexer and under them
list of all the minterms in two columns. The first column lists all the minterms where least
significant variable is complemented (C), and the second column lists all the minterms with
least significant variable is un-complemented (C). The minterms given in the function are
circled and then each row is inspected separately as follows.
If the two minterms in a row are not circled, 0 is applied to corresponding
multiplexer input.
If the two minterms in a row are circled, 1 is applied to corresponding multiplexer
input.
If the minterm in the column 1 is circled, least significant variable is complemented
(C) and applied to the corresponding multiplexer input.
If the minterm in the column 2 is circled, least significant variable is uncomplemented (C) and applied to the corresponding multiplexer input.
Procedure:
connections.
Description
Max.
Marks
Preparation
30
Performance
40
Viva Voce
10
Record
20
Total
Marks
Secured
100
Staff Signature
Result:
Thus the implementation of the given Boolean function using multiplexer was designed,
implemented and verified with its truth table.
Realization of RS flip-flop using NAND gates:
Characteristic Table:
Qn(P.S)
Qn+1(N.S)
Invalid
Invalid
Truth Table:
Qn+1
Qn(N.C)
Invalid
Note: N.C No Change; N.S Next State; P.S Present State
EXP. NO : 7
DATE
:
DESIGN OF RS AND JK FLIP FLOPS USING NAND GATES
----------------------------------------------------------------------------------------------
Aim:
To design and implement RS and JK flip-flop using NAND gates.
S.NO
1
2
3
4
COMPONENTS
ICs
Connecting wires
Bread Board
RANGE
QUANTITY
7400
-
1
1
As required
1
Theory:
Flip-flop:
The memory cell has only two states. It can be either 0 or 1. Such two state sequential
circuits are called flip-flops, because they flip from one state to another and then flop back. A
flip-flop is also known as bistable multivibrator, latch or toggle.
Types of flip-flop:
There are four different (basic) types of flip-flop. They are
1. SR flip-flop
2. JK flip-flop
3. D flip-flop and
4. T flip-flop.
Set-Reset (S-R) Flip-Flop:
The S-R flip-flop has two inputs, namely SET and RESET and two outputs Q and Q . The
two outputs are complement to each other. The S-R flip-flop can be easily implemented using
NAND gates. The operation of NAND S-R flip-flop can be analyzed in the same manner employed
for the NOR flip-flop. If any one of the inputs is low for the NAND gate then it will force the
output high. This flip-flop is called as S-R flip-flop, i.e., here S=0 and R=1 will set the flip-flop.
J-K Flip-Flop:
A J-K flip-flop has a characteristic similar to that of an S-R flip-flop. In addition, the
indeterminate condition of the S-R flip-flop is permitted in it. Inputs J and K behave like inputs S
and R to set and reset the flip-flop respectively. When J=K=1, the flip-flop output toggles, i.e.,
switches to its complement state. If q=0, it switches to Q=1 and vice versa.
Realization of JK flip-flop using NAND gates:
Characteristic Table:
Qn(P.S)
Qn+1(N.S)
Truth Table:
Qn+1
Qn(N.C)
Note: N.C No Change; N.S Next State; P.S Present State
Procedure:
connections.
Description
Max.
Marks
Preparation
30
Performance
40
Viva Voce
10
Record
20
Total
Marks
Secured
100
Staff Signature
Result:
Thus the flip-flops RS and JK were designed and implemented using NAND gates and
verified with their truth tables.
Circuit Diagram: Serial IN Serial OUT shift Register
Circuit Diagram: Serial IN Parallel OUT shift Register
EXP. NO : 8
DATE
:
DESIGN AND IMPLEMENTATION OF SHIFT REGISTERS
-----------------------------------------------------------------------------------------------Aim:
To design, implement and verify the functioning of shift right registers (all types) using D
flip-flop.
S.NO
1
COMPONENTS
ICs
3
4
Connecting wires
Bread Board
RANGE
7474
7408
7404
7432
-
QUANTITY
1
2
2
1
1
1
Theory:
A register that is used to store binary information is known as a memory register. A
register capable of shifting binary information either to the right or the left is called a shift
register. Shift registers are classified into four types,
1. Serial-in Serial-out (SISO)
2. Serial-in Parallel-out (SIPO)
3. Parallel-in Serial-out (PISO)
4.
Parallel-in
Parallel-out
(PIPO)
Serial-in Serial-out (SISO):

This type of shift registers accepts data serially, i.e., one bit at a time on a single input
line. It produces the stored information on its single output and the output also in serial form.
Data may be shifted left (from low to high order bits) using shift-left register or shifted right
(from high to low order bits) using shift-right register.
Serial-in Parallel-out (SIPO):
It consists of one serial input, and outputs are taken from all the flip-flop simultaneously
in parallel. In this register, data is shifted in serially but shifted out in parallel. In order to shift
the data out in parallel, it is necessary to have all the data available at the outputs at the same
time. Once the data is stored, each bit appears on its respective output line and all the bits are
available simultaneously, rather than on a bit by bit basis as with the serial output.
Parallel-in Serial-out (PISO):
This type of shift register accepts data parallel, i.e., the bits are entered simultaneously
into their respective flip-flops rather than a bit-by-bit basis on one line.
Circuit Diagram: Parallel-in Serial-out shift Register
Circuit Diagram: Parallel IN Parallel OUT shift Register
Parallel-in Parallel-out (PIPO):

In this type of register, data inputs can be shifted either in or out of the register in
parallel.
Procedure:
3. Make sure that the ICs are enabled by giving the suitable Vcc and ground connections.
Verification Table:
Pin Diagram:
Description
Max.
Marks
Preparation
30
Performance
40
Viva Voce
10
Record
20
Total
Marks
Secured
100
Staff Signature
Result:
Thus the shift registers using D flip-flop were implemented and studied their operation in
4 different modes.
State Table (3 bit synchronous binary UP counter)

Present State
A
B
C
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Next State
A+
0
0
0
1
1
1
1
0
B+
JK Flip-Flop Inputs
C+
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
JA
0
0
0
1
X
X
X
X
KA
X
X
X
X
0
0
0
1
JB
0
1
X
X
0
1
X
X
JK Excitation Table:
Qn
0
0
1
1
Qn+1
0
1
0
1
J
0
1
X
X
K
X
X
1
0
KB
X
X
0
1
X
X
0
1
JC
1
X
1
X
1
X
1
X
KC
X
1
X
1
X
1
X
1
EXP. NO : 9
DATE
:
DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTER
----------------------------------------------------------------------------------------------
Aim:
To design and implement a 3-bit synchronous binary up and down counter using JK flipflop.
S.NO
1
COMPONENTS
Digital Trainer Kit
ICs
3
4
Connecting wires
Bread Board
RANGE
7476
7408
7432
-
QUANTITY
1
2
1
1
As required
1
Theory:
A Synchronous counter is also called parallel counter. In this counter the clock inputs of
all the flip-flops are connected together so that the input clock signal is applied simultaneously to
each flip-flop. Also, only the LSB flip-flop C has its J and K inputs connected permanently to Vcc
while the J and K inputs of the other flip-flops are driven by some combination of flip-flop
outputs.
3 Bit Synchronous Binary UP Counter:
The J and K inputs of the flip-flop B are connected to with QC. The J and K inputs of the
flip-flop A, are connected with AND operated output of QC and QB. The flip-flop C changes its
state when with the occurrence of negative transition at each clock pulse. The flip-flop B changes
its state when QC = 1 and when there is negative transition at clock input. Flip-flop A changes its
state when QC = QB = 1 and when there is negative transition at clock input.
3 Bit Synchronous Binary DOWN Counter:
The J and K inputs of the flip-flop B are connected to with QC . The J and K inputs of the
flip-flop A, are connected with AND operated output of QC and QB. The flip-flop C changes its
state when with the occurrence of negative transition at each clock pulse. The flip-flop B changes
its state when QC = 1 and when there is negative transition at clock input. Flip-flop A changes
its state when QC = QB = 1 and when there is negative transition at clock input.
Circuit Diagram:
Procedure:
connections.
Pin Diagram:
State Table (3 bit synchronous binary DOWN counter)

Present State
A
B
C
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
A
1
0
0
0
0
1
1
1
Next State
+
B
1
0
0
1
1
0
0
1
C
1
0
1
0
1
0
1
0
JA
1
0
0
0
X
X
X
X
JK Flip-Flop Inputs
KA
JB
KB
JC
X
1
X
1
X
0
X
X
X
X
1
1
X
X
0
X
1
1
X
1
0
0
X
X
0
X
1
1
0
X
0
X
JK Excitation Table:
Qn
0
0
1
1
Qn+1
0
1
0
1
J
0
1
X
X
K
X
X
1
0
Circuit Diagram:
KC
X
1
X
1
X
1
X
1
State Table:
Present State
Next State
+
T input
A
TD
TC
TB
TA
Realization of T flip-flop input using K- Map:
T flip-flop Excitation Table:

Qn
0
0
1
1
Qn+1
0
1
0
1
T
0
1
1
0
Circuit Diagram:
Description
Max.
Marks
Preparation
30
Performance
40
Viva Voce
10
Record
20
Total
Marks
Secured
100
Staff Signature
Result:
Thus the synchronous up, down and BCD counters were designed using JK flip-flop and
verified with their state table.
Verification Table (4 bit binary ripple up counter):

Clock
Pulse
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Q3
Q2
Q1
Q0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Circuit Diagram:
EXP. NO : 10
DATE
:
DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS COUNTER
----------------------------------------------------------------------------------------------
Aim:
To design and implement a 4-bit asynchronous binary up and down counter using JK flipflop.
S.NO
1
2
3
4
5
6
COMPONENTS
IC
Bread board
Connecting wires
RANGE
7476
7400
-
QUANTITY
1
2
1
1
1
As required
Theory:
A counter, by function, is a sequential circuit consisting of a set of flip-flops connected in
a suitable manner to count the sequence of the input pulses presented to it digital form. An
asynchronous counter, each flip-flop is triggered by the output from the previous flip-flop which
limits its speed of operation. The settling time in asynchronous counters, is the cumulative sum
of the individual settling times of flip-flops. It is also called a serial counter.
The asynchronous counter is the simplest in terms of logical operations, and is therefore
the easiest to design. In this counter, all the flip-flops are not under the control of a single clock.
Here, the clock pulse is applied to the first flip-flop, i.e. the least significant bit stage of the
counter, and the successive flip-flop is triggered by the output is constructed using clocked JK
flip-flops. The system clock, a square wave, drives flip-flop A (LSB). The output of A drives flipflop B, the output of B drives flip-flop C. all the J and K inputs connected to Vcc (High (1)), which
means that each flip-flop toggles on the edge (-ve) clock pulse.
Consider initially all flip-flops to be in the logical 0 state (i.e. Q A=QB=QC=QD=0). A negative
transition in the clock input which drives flip-flop A causes QA to change from 0 to 1. Flip-flop B
doesnt change its state since it is also requires negative transition at its clock input, i.e. it requires
its clock input (QA) to change from 1 to 0. With arrival of second clock pulse to flip-flop A, QA goes
from 1 to 0. This change of state creates the negative going edge needed to trigger flip-flop B, and
thus QB goes from 0 to 1. Before the arrival of the 16
th
clock pulse, all the flip-flops are in the logical
1 state. Clock pulse 16 causes QA, QB, QC and QD to go logical 0 state in turn.
Verification Table (4 bit binary ripple down counter):

Clock
Pulse
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Q3
Q2
Q1
Q0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Circuit Diagram:
Procedure:
connections.
Pin Diagram:
Verification Table (BCD ripple up counter):

Clock
Pulse
0
1
2
3
4
5
6
7
8
9
10
Q3
Q2
Q1
Q0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
Circuit Diagram:
Description
Max.
Marks
Preparation
30
Performance
40
Viva Voce
10
Record
20
Total
Marks
Secured
100
Staff Signature
Result:
Thus the asynchronous up, down and BCD counters were constructed and tested the
operations with the help of their verification tables.
HDL for combinational logic

VHDL code for logic gates OR gate
library ieee;
use ieee.std_logic_1164.all;
entity gor is port(a,b: in
std_logic;
c:out std_logic); end
gor;
architecture arc_gor of gor is begin
c <= a or b; end
arc_gor;
VHDL code for logic gates NAND gate

library ieee;
entity nandg is port(a,b: in
std_logic;
nandg;
architecture arc_ nandg of nandg is begin

c <= a nand b; end arc_
nandg;
VHDL code for logic gates Ex-OR gate

library ieee;
entity gxor is port(a,b: in
std_logic;
gxor;
architecture arc_gxor of gxor is begin

c <= a xor b; end
arc_gxor;
EXP. NO : 11
DATE
:
HDL FOR COMBINATIONAL LOGIC
Aim:
To write a VHDL code for the combinational circuits given below and simulate the result
using EDA tool.
1. Logic Gates (OR , NAND and EX-OR)
2. Half adder and Full adder
Components Required
S.No
Component Name
Range / Type
Quantity
Personal Computer
EDA Tool
(ModelSim 5.5e)
Theory:
The basic steps involved in the Digital System Design are,
1. Specify the desired behavior of the circuit.
2. Synthesize the circuit.
3. Implement the circuit.

4. Test the circuit to check whether the desired specifications meet.
But as the size and complexity of digital system increase, they cannot be designed manually
because their design becomes highly complex. At their most detailed level, they may consist of
millions of elements (Transistors or logic gates). So, Computer aided design (CAD) tools are used in
design of digital systems. One such a tool is a Hardware Description Language (HDL).
HDL describes the hardware of digital systems. This description is in textual form. The
Boolean expressions, logic diagrams and digital circuits (Simple and Complex) can be
represented using HDL.
The HDL provides the digital designer with a means of describing a digital system at a wide
range of levels of abstraction and at the same time, provides access to computer aided design
tools to aid in the design process at these levels.
The HDL represents digital systems in the form of documentation which can understand
by human as well as computers.
It allows hardware designers to express their design with behavioral constructs. An
abstract representation helps the designer explore architectural alternatives through
simulations and to detect design bottlenecks before detailed design begins.
The HDL makes it easy to exchange the ideas between the designers.
It resembles a programming language, but the orientation of the HDL is specifically
towards describing hardware structures and behavior. The storage, retrieval and
processing of programs written using HDL can be performed easily and efficiently.
HDLs are used to describe hardware for the purpose of simulation, modelling, testing and
documentation.
VHDL for full adder Structural Model

-- Library Declaration library
ieee;
use
ieee.std_logic_1164.all;
use
work.all;
-- Entity Declaration entity fa
is
port (a,b,c:in std_logic; sum,cout: out
std_logic);
end fa;
-- Architecture Declaration
architecture arc_fa of fa is
Structural
Model
component ha port(a,b:in
std_logic;
component;
s,c:out std_logic); end
component gor port(a,b:in

std_logic;
component;
signal s1,c1,c2:std_logic; begin

ha1:ha port map(a,b,s1,c1); ha2:ha port
map(s1,c,sum,c2); or1:gor port
map(c1,c2,cout); end arc_fa;
VHDL for half adder Data Flow Model

library ieee;
entity ha is
port ( a,b: in std_logic; s,c: out
std_logic);
end ha;
architecture arc_ha of ha is begin
s <= a xor b; c <= a
and b; end arc_ha;
Procedure:
1. Click the ModelSim SE 5.5e icon to start the simulation of VHDL code.
2. Select create a project options given on the welcome screen in order to create a new
project otherwise choose open a project to open the existing project.
3. Proper project name should be given along with the location to save the project in the
create project window.
4. In the main window go to file New Source VHDL to get in to the source editor
window.
5. Enter the VHDL source code on that source editor window and save with the extension
.vhd in the project (project created) folder and location specified previously.
6. Select file compile in the source editor window for compiling the written code. If there
is an error debug the error, save and compile again.
7. Load the design by selecting Design load design in the main window after successful
compilation of the VHDL codes.
8. Select signals from the view menu of the main window for selecting the signals.
9. In signal window, choose edit force / clock for applying the appropriate input levels for
the signals selected.
10. Select view wave signals in design to view the response of the design (Wave form)
with the help of run option from the signal window.
11. Continue the simulation for different input levels with the procedure stated above.
Description
Max.
Marks
Marks
Secured
Preparation
30
Performance
40
Viva Voce
10
Record
20
Total
100
Staff Signature
Result:
Thus the VHDL Code for the Combinational circuits was developed and simulated using
Electronic Design Automation tool.
HDL FOR SEQUENTIAL LOGIC

VHDL code for flip-flops (D)
library ieee;
entity dff is
port(clr,d : in std_logic;
clk: in std_logic; q : out
std_logic);
end dff;
architecture arc_dff of dff is begin
process(clk) begin
if(clr = '0')then q <= '0';
elsif (clk = '1' and clk'event) then q <= d;

end
if;
end
process; end arc_dff;
VHDL for Synchronous UP/DOWN counter

Library ieee;
use ieee.std_logic_1164.all; use
ieee.std_logic_unsigned.all; entity
synudcounter is
port( clk: in std_logic;

clr: in std_logic; ud: in
std_logic;
end synudcounter;
cout: inout std_logic_vector(3 downto 0));
architecture arc_synudcounter of synudcounter is begin

process(clk) begin
if (clk = '0' and clk'event) then if(clr =

'0') then
cout <= "0000"; else

if(clr = '1' and ud = '0') then cout <=
cout + 1;
elsif(clr = '1' and ud = '1') then cout

<= cout - 1;
end if;
end process;
end if;
end if;
end arc_synudcounter;
EXP. NO : 12
DATE
HDL FOR SEQUENTIAL LOGIC
Aim:
To write a VHDL code for the sequential circuits given below and simulate the result
using EDA tool.
1. D flip flop
2. Synchronous UP / DOWN Counter
Components Required
S.No
Component Name
Range / Type
Quantity
Personal Computer
EDA Tool
(ModelSim 5.5e)
Theory:
The basic steps involved in the Digital System Design are,
1. Specify the desired behavior of the circuit.
2. Synthesize the circuit.
3. Implement the circuit.
4. Test the circuit to check whether the desired specifications meet.
But as the size and complexity of digital system increase, they cannot be designed manually
because their design becomes highly complex. At their most detailed level, they may consist of
millions of elements (Transistors or logic gates). So, Computer aided design (CAD) tools are used in
design of digital systems. One such a tool is a Hardware Description Language (HDL).
HDL describes the hardware of digital systems. This description is in textual form. The
Boolean expressions, logic diagrams and digital circuits (Simple and Complex) can be
represented using HDL.
The HDL provides the digital designer with a means of describing a digital system at a wide
range of levels of abstraction and at the same time, provides access to computer aided design
tools to aid in the design process at these levels.
The HDL represents digital systems in the form of documentation which can understand
by human as well as computers.
It allows hardware designers to express their design with behavioral constructs. An
abstract representation helps the designer explore architectural alternatives through
simulations and to detect design bottlenecks before detailed design begins.
The HDL makes it easy to exchange the ideas between the designers.
It resembles a programming language, but the orientation of the HDL is specifically
towards describing hardware structures and behavior. The storage, retrieval and
processing of programs written using HDL can be performed easily and efficiently. HDLs
are used to describe hardware for the purpose of simulation, modelling, testing and
documentation.
Procedure:
1. Click the ModelSim SE 5.5e icon to start the simulation of VHDL code.
2. Select create a project options given on the welcome screen in order to create a new
project otherwise choose open a project to open the existing project.
3. Proper project name should be given along with the location to save the project in the
create project window.
4. In the main window go to file New Source VHDL to get in to the source editor
window.
5. Enter the VHDL source code on that source editor window and save with the extension
.vhd in the project (project created) folder and location specified previously.
6. Select file compile in the source editor window for compiling the written code. If there
is an error debug the error, save and compile again.
7. Load the design by selecting Design load design in the main window after successful
compilation of the VHDL codes.
8. Select signals from the view menu of the main window for selecting the signals.
9. In signal window, choose edit force / clock for applying the appropriate input levels for
the signals selected.
10. Select view wave signals in design to view the response of the design (Wave form)
with the help of run option from the signal window.
11. Continue the simulation for different input levels with the procedure stated above.
Description
Max.
Marks
Marks
Secured
Preparation
30
Performance
40
Viva Voce
10
Record
20
Total
100
Staff Signature
Result:
Thus the VHDL Code for the Sequential circuits was developed and simulated using
Electronic Design Automation tool.

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www.Vidyarthiplus.

immediately to the Lab. Instructors or Lab. Technical Staff.

equipment and other related accessories.

1. Verification of Boolean theorems using digital logic gates

Language (VHDL/ Verilog HDL software required)

Lab in- Charge

Bread-Board is used in a laboratory for constructing the different circuits and

X.(Y + Z) = X.Y + X.Z

A single, bivalent unit of binary.

Crumb, Tydbit, or Tayste

VERIFICATION OF BOOLEAN THEOREMS USING DIGITAL LOGIC GATES

It states that the complement of a product is equal to the sum of the

Realization of simplified Boolean

expression using K-Map:

DESIGN AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS USING

Realization of Boolean Expression for BCD to Excess 3 Converter:

Realization of Boolean Expression for Excess 3 to BCD Converter:

DESIGN AND IMPLEMENTATION OF 4 BIT BINARY ADDER / SUBTRACTOR

DESIGN AND IMPLEMENTATION OF PARITY GENERATOR AND CHECKER

Work as a parity checker:

Truth Table for Even Parity Checker

4 BIT DATA RECEIVED

K-Map Simplication for Even Parity Checker

DESIGN AND IMPLEMENTATION OF 2 BIT MAGNITUDE COMPARATOR

xi =Ai Bi + Ai Bi for i=0,1,2,3 The

Truth Table (2 Bit magnitude Comparator):

Implementation of the following Boolean function F= m (1, 3, 5 6) using multiplexer

DESIGN AND IMPLEMENTATION OF APPLICATION USING MULTIPLEXERS

To design and implement the combinational logic using multiplexers

Digital IC trainer kit

Realization of RS flip-flop using NAND gates:

Note: N.C No Change; N.S Next State; P.S Present State

Realization of JK flip-flop using NAND gates:

Note: N.C No Change; N.S Next State; P.S Present State

Circuit Diagram: Serial IN Serial OUT shift Register

Circuit Diagram: Serial IN Parallel OUT shift Register

Serial-in Serial-out (SISO):

Circuit Diagram: Parallel-in Serial-out shift Register

Circuit Diagram: Parallel IN Parallel OUT shift Register

Parallel-in Parallel-out (PIPO):

State Table (3 bit synchronous binary UP counter)

State Table (3 bit synchronous binary DOWN counter)

Realization of T flip-flop input using K- Map:

T flip-flop Excitation Table:

Verification Table (4 bit binary ripple up counter):

clock pulse, all the flip-flops are in the logical

Verification Table (4 bit binary ripple down counter):

Verification Table (BCD ripple up counter):

HDL for combinational logic

VHDL code for logic gates NAND gate

c:out std_logic); end

architecture arc_ nandg of nandg is begin

VHDL code for logic gates Ex-OR gate

c:out std_logic); end

architecture arc_gxor of gxor is begin

2. Synthesize the circuit.

3. Implement the circuit.

VHDL for full adder Structural Model

s,c:out std_logic); end

component gor port(a,b:in

c:out std_logic); end

signal s1,c1,c2:std_logic; begin

VHDL for half adder Data Flow Model