Fabrication and Electrical Characteristics of Self-aligned (SA)

Gate-All-Around (GAA) Si NanoWire MOSFETs (SNWFET)

Dong-Won Kim, Kyoung Hwan Yeo, Sung Dae Suk, Ming Li, Yun Young Yeoh,
Dong Kyun Sohn and Chilhee Chung
Semiconductor R&D Center, Samsung Electronics Co.
San 24, Nongseo-Dong, Kiheung-Gu, Yongin-City, Kyungki-Do, Korea, 449-711
Phone: 82-31-208-0212, E-mail : timo.kim@samsung.com
Abstract
In this paper, excellent electrical properties of self
aligned (SA) SNWFET with various gate lengths down to
sub-10nm will be discussed with advantages of SNWFET
process compatible with conventional CMOS process.
Nanowire size dependency of electrical characteristics, such
as threshold voltage, driving current and etc., are investigated
as well. In addition, random telegraph noise (RTN) of GAA
SNWFETs will be investigated as an item to be studied [14].

We have proposed gate-all-around Silicon nanowire

MOSFET (SNWFET) on bulk Si as an ultimate transistor.
Well controlled processes are used to achieve gate length (LG)
of sub-10nm and narrow nanowire widths. Excellent
performance with reasonable VTH and short channel
immunity are achieved owing to thin nanowire channel, selfaligned gate, and GAA structure. Transistor performance with
gate length of 10nm has been demonstrated and nanowire
size (DNW) dependency of various electrical characteristics
has been investigated. Random telegraph noise (RTN) in
SNWFET is studied as well.

Device fabrication
4 key processes, SiGe/Si epi-growth, McFET process,
damascene gate, and selective SiGe etch, are applied to make
SNWFET as shown in Fig. 1. . First of all, SiGe and Si layers
are grown on bulk Si wafer to form single crystal Si. Second
one is SiN trim process after trench etch. This process makes
nanowire uniform and narrow because nanowire widths are
controlled not by photo lithography but by etched SiN
amount. Third one is self-aligned damascene process. The
process that form gate at one time makes it possible to obtain
a device free from misaligns. The last one is selective SiGe
etch. To make gate-all-around (GAA) structure SiGe layer
should be removed selectively. After nanowire formation,
gate trim process is followed by TiN deposition to get
reasonable threshold voltages of n/p-FET and minimize gate
length.
To obtain gate length of sub-10nm and various nanowire
widths precisely controlled etching processes are used after
TiN deposition and trench etch [9]. SNWFET with 10nm top
gate and 5nm bottom gate is confirmed by vertical SEM and
TEM as shown in Fig. 2. Various DNW of ~3nm to 11nm are
prepared to estimate nanowire size dependency as shown in Fig.
3.

Introduction
As semiconductor devices have been scaled down rapidly
and continuously into the nanometer regime, short channel
effects have become more and more serious problems. To
overcome them, many device architectures, such as multi-gate
structures and thin body channel devices, are proposed and
studied as candidates for future devices [1-7]. As an ultimate
transistor structure, gate-all-around (GAA) structures with
nanowire channels have been focused on because of their
high immunity to short channel effects and high performance
even in the ultimately scaled regime. [1, 2, 4]. Some nanowire
transistor which was formed with bottom-up process showed
poor compatibility with conventional CMOS process [7].
Nanowire transistors with top-down process have been
proposed by several research groups. Among them, Silicon
nanowire MOSFET (SNWFET) on bulk Si wafer shows
excellent gate control and electrical properties.

a)

SiN

Si

b)

c)

Twin nanowire

d)

Gate

SiGe
Si

SiO2
Fig. 1. Key processes and schematic diagrams of GAA TSNWFET fabricated on bulk Si wafer. Process results after (a) active
SiN trimming after trench etch, (b) damascene pattern (c) field oxide recess and SiGe removal in channel region, and (d) S/D
dummy layer removal following gate oxide and gate material deposition.

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ICICDT-10

DNW=13nm

Top TiN Gate

DNW=11nm

10nm

20nm

Fig. 2. VSEM image of SA GAA structure (a). TEM images

of 10nm top gate/5nm bottom gate (b) and 13-nm-diameter
silicon nanowire as well as 25 ISSG gate oxide (c).

Fig. 3. Top view SEM images of twin silicon nanowires after removing
SiGe layer. Different nanowire sizes from ~3 nm to 11 nm are obtained
by trimming amount of active SiN.

Device Performance : Lg of 10nm

-1

10

Fig. 4 shows threshold voltages (VTH) and sub-threshold

swings (SS) of SA GAA SNWFET with DNW=13nm.
SNWFETs control channels until LG=10nm for NMOS and
15nm for PMOS, respectively. SNWFET with LG of 15nm for
NMOS and 20nm for PMOS meet the criteria, VTH difference
between threshold voltages of long LG and short LG, SS and
DIBL <100mV. Due to better SCE immunity than PMOS
SNWFET, electrical characteristic with DNW of 13nm and
16nm for NMOS and PMOS, respectively, are summarized.
The on-off relationships of 10nm and 84nm for NMOS and
PMOS SNWFET are plotted in Fig. 5 to show the
performance boosted by scaling down LG. Fig. 6 shows that
the ID-VG and ID-VD characteristics of typical SNWFETs. Oncurrent (ION) of 1494 and 1054A/m at off-current (IOFF) of
102 and 6.44nA/m are obtained for NMOS and PMOS,
respectively. Excellent PMOS performance comparable to
that of NMOS is explained by uniaxial compressive stress on
Si nanowire channel [11].
Other device parameters are summarized in Table.1 with
comparison with the reported results [4, 11, 12, 13] and
ITRS2007 prediction. Thanks to quasi-ballistic transport in
the ultra-thin channel, the intrinsic gate delay of 0.11ps,
superior to the prediction of ITRS 2007 for 10nm double-gate
devices, is obtained with consideration of 20% more parasitic
gate capacitance although the parasitic S/D resistance (RSD) is
about 38% larger than ITRS2007.

|VD|=50mV,1.0V

-3

NFET
2.0 PFET
|VG|=0.6,0.8,1.0,1.2V
1.5

ID [mA/Pm]

ID [A/Pm]

10

-5

10 PFET
-7

10

-9

NFET

LG=10nm

LG=10nm

DNW=13nm

DNW=16nm

1.0
0.5

10

-11

10

0.0
-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2
VD [V]

-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2

VG [V]

Fig. 6 ID-VG and ID-VD characteristics of 10nm SNWFETs with

DNW=16nm and 13nm for NMOS and PMOS, respectively.
Table. 1. Device parameters of this work compared to other published
results and ITRS 2007 prediction
Recent

Previous

Omega

GAA SOI

GAA

ITRS 2007

SNWFET [9]
NFET
PFET

NWFET [11]
NFET
PFET

SOI NW [4]
NFET PFET

NW [12]
NFET

NW [13]
PFET
NFET

(DG)
NFET

Poly Si

Poly Si

Gate
Lg (nm)

TiN
10/5

TiN
10

15

15

10

TaN/HK(Hf)

35

25

10

Dnw (nm)

16

13

10

10

13.3*20.4

9*13.9

TOX or EOT (nm)

2.5

2.5

3.5

3.5

1.9

1.9

4.0

1.5 #

1.5 #

1.0

VDD (V)

1.0

1.0

1.0

1.0

1.0

1.0

1.2

1.0

1.0

0.9

Vtsat (V)

0.15

-0.23

0.30

-0.31

0.35*

-0.22*

-0.25*

0.27

~-0.33

0.111

SS (mV/dec.)

89

86

72

71

75

63

75

85

85

<100

DIBL (mV)

88

133

50

43

80

14

22

65

105

<100

Ion (uA/um)

1494

1054

1440

1940

522

115

3740

2592

2985

2295

Ioff (nA/um)

102

6.44

2.0

1.0

10

0.5

15

15

380

Rsd (um)

220

148

~450

~350

160

Gate delay (ps)

0.13**

0.17**

0.42

0.39

0.22

0.48

0.18

Ballistic Factor

0.66

0.70

0.53

-2

10

0.6
0.3

Solid: VTH,lin

0.0

Open:VTH,sat

NFET
PFET

100

-8

10

-12

60 80 100 120
LG [nm]

Fig. 4 Short channel effect of

SNWFET with Tox of 25 and
DNW of 13nm.

* : estimated value, ** : 20% more parasitic gate capacitance consideration, # : EOT

-6

-10

40

84nm
10nm

10

10

80
20

84nm

10

-0.3
120

10nm

-4

IOFF [A/Pm]

VTH [V]

DNW=3nm

GAA TiN Gate

5nm
Bottom
Gate
20nmG

Bottom TiN Gate

SS [mV/dec.]

DNW=6nm

Top
Gate

NW

60
0

DNW=8nm

10

Nanowire Size Dependency

100nA/Pm

TOX=22A
DNW=15nm
PFET

-2000 -1000

NFET
1000 2000

ION [PA/Pm]
Fig. 5 ION-IOFF correlation of
10nm and 84nm N/MOS and
PMOS SNWFETs.

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Fig. 7 shows ID-VG curves and threshold voltages of NMOS

and PMOS SNWFET with different DNW. As DNW decreases,
increase of VTH and decrease of on-current (ION) can be easily
observed as shown in Fig. 7 (a) and (b). Fig. 7 (c) shows VTH
trends as a function of DNW. VTH increases with smaller
nanowire due to quantum confinement effect.

ICICDT-10

-4

a)

10
DNW [nm]
1~2
2~3
4~5
8~9

10

-6

10

b)
DNW [nm]
9~10
8~9
4~5
1~2
<1~2

-5

10

-6

10

ION [A]

-5

ION [A]

Fig. 9 shows ID-VD curves, total resistance (RTOTAL) and

channel resistance (RCH) of n-TSNWFET with different
DNW and gate length. ID-VD curves are measures at various
gate length and DNW as shown in Fig. 9 (a). Total resistance
of SNWFET is extracted from the linear region of ID-VD
curves. And, channel resistance and source/drain resistance
are estimated from the relation between total resistance and
gate length as shown in Fig. 9 (b). S/D resistance shows
~1.45 K: while channel resistance is lager than 20 K:. The
relation between DNW and channel resistance is plotted in
Fig. 9 (c). Channel resistance increases as nanowire size
decreases.

-4

10

-7

10

-7

10

-8

10

NMOS
LG = 30 nm
VD = 1 V

-8

10

-9

10
-0.5

-9

10

-10

0.0

0.5

1.0

VG [ V ]

1.5

2.0

10

PMOS
LG = 30 nm
VD = 1 V

-1.5 -1.0 -0.5

0.0

0.5

1.0

VG [V]
G

1.2

c)

1.0
G

0.8

a)
50 VG-VTH = 1.0 V

LG ~ 30 nm

40

ION [uA]

VT [V]

60

nMOS
pMOS

LG = 52 nm
62 nm

DNW 9~10 nm

87 nm

30

0.6

20

0.4
0.2

DNW 1~2 nm

10

0
0.0

10

Nanowire size [ nm ]

62 nm

0.4

0.8
VD [ V ]

RTOTAL [K:]

40

ION versus DNW graphs of NMOS and PMOS SNWFET

are shown in Fig. 8. Because of the reduced cross-sectional
area, ION decreases continuously as shown in Fig. 8 (a).
More rapid decrease can be observed near DNW below 4 nm.
However, ION normalized by circumference show peaks at
DNW of ~4 nm due to volume inversion effect. And then it
decreases rapidly with decrease of DNW resulted from
various scattering effect as shown in Fig. 8 (b).

1.8
a)
LG ~ 30 nm

ION @VG-VT=1V [mA/um]

ION @VG-VT=1V [uA]

60

0
0

Nanowire size [ nm ]

10

0.6
0

nMOS
pMOS

0
0

0.8

60

80

0
0

100

10

DNW [nm]

LG ~ 30 nm

1.0

nMOS
pMOS

40

50

Gate length [ nm ]

1.2

20

NMOS

RTN in SNWFET

b)

1.4

40

100

RSD ~ 1.45 K:
'L = 19.7 nm
20

LG = 60 nm
VG-VTH = 0.9 V

Fig. 9. ID-VD, total resistance and channel resistance of NMOS

SNWFET. S/D resistance shows ~1.45 K: while channel
resistance is lager than 20 K:. Channel resistance increases as
nanowire size decreases.

1.6

VG - VT
0.9 V
1.1 V
1.3 V

80

20

c)

b)
Nanowire size ~ 10 nm

10

30

1.2

150

RCH [K:]

50

Fig. 7. ID-VG curves as a function of DNW. At both cases of NMOS

and PMOS SNWFET, VTH increases and ION decreases as DNW
decreases. VTH increases due to conduction band increase in
limited dimension of nanowire channel.

LG = 32 nm
42 nm

10

Nanowire size [ nm ]

Fig. 8. ION and normalized ION with different DNW. Due to the
reduced cross-sectional area, ION decreases steadily as DNW
decreases. However, ION normalized by circumference reaches
peaks at DNW of ~4 nm.

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65

As devices scaled down, RTN by defect in gate oxide

becomes more important. In case of SNWFET, channel area
is very small and drain current can be affected by a single
trap. Fig. 10 shows RTN characteristics and Power Spectral
Density (PSD) of SNWFETs. 2 levels of drain current
which indicate existence of an active trap in gate oxide are
observed as shown in Fig. 10 (a) ~ (b). Fig. 10 (c) and (d)
show that corresponding PSD show close to Lorentzian
shape with a corner frequency fc. Fig. 11 shows multilevel
RTN, which mean more than 1 trap in the channel. 4 current
levels which signify 2 independent traps, a slow trap and a
fast trap, are observed as shown Fig. 11 (a) and (b).
Relationship between two traps is studied with current
difference at high level (empty slow trap) and low level
(filled slow trap) as shown in Fig. 12. Device A shows

ICICDT-10

different current as a function of gate voltage (VGS) while

device B shows almost same current. It means that traps of
device A are electrically separated and those of device B
affect each other.

Conclusions
GAA SNWFET on bulk Si is demonstrated as an ultimate
transistor and short gate length of sub 10nm and narrow width
of sub 5nm are achieved with fine-tuned process. SNWFET
with gate length of ~10nm effectively controls channel with
excellent electrical characteristic due to gate all structure.
nanowire size (DNW) dependency of various electrical
properties is investigated to understand overall performance
of nanowire transistor deeply. RTN characteristic is measured
and studied to understand issues at nano-scale devices.

0.7

a)

0.75

N-FET, L = 40 nm

0.70

ID n w [P A ]

I D nw [ P A ]

0.6

P-FET, L = 40 nm

b)

0.5

0.65

0.60

at slow RTN high level

0.4

Vgs= 0.54V, Vds= 0.05V

0.3
0.40

0.41

0.42

0.55

0.43

0.44

Vgs= - 0.56V, Vds= - 0.05V

40

0.45

42

44

46

Time [sec]

48

References

50

52

54

Time [sec]

[1] S. D. Suk et al., High performance 5 nm radius twin silicon

nanowire MOSFET (TSNWFET): Fabrication on bulk Si wafer,
characteristics, and reliability, IEDM Tech., p. 717, 2005.

1E-14

P-FET, L = 40 nm

1E-15

N-FET, L = 40 nm

fc

1E-17

P S D [A 2 / H z ]

P S D [A 2 / H z ]

1E-17

1E-16

1E-18

1/f

1E-19

1E-20

Vgs= - 0.56V, Vds= - 0.05V

1E-21
1E-22
0.1

10

1E-18

fc

1E-19

1/f

1E-20

1E-21

Vgs= 0.54V, Vds= 0.05V

1E-22

100

10

Frequency [Hz]

100

1000

10000

Frequency [Hz]

Fig. 10. RTN characteristics and Power Spectral Density (PSD) of

SNWFETs.
0.44

a)
Device B

0.40

Vgs = 0.52 V
Vds = 0.05 V

0.40

Vds = 0.05 V

0.36

ID P A

0.35

ID P A

Vgs = 0.52 V

b)
Device B

0.30

0.25

0.32
0.28
0.24
0.20

Slow RTN

0.20
0.0

0.2

0.4

0.6

0.350

0.355

0.360

Time [sec]

0.365

0.370

0.375

0.380

Time [sec]

Fig. 11. RTN characteristics with 4 current levels which mean 2

independent trap.
0.14
0.12

At slow RTN high level

At slow RTN low level

0.12

~8% decrease

0.10

Vds = 0.05 V

0.09

0.11

Device A
0.10

PA

Vds = 0.05 V

Device B
0.11

' ID

' ID

PA

0.13

0.52

0.54

At slow RTN high level

At slow RTN low level

0.08

0.56

0.58

0.60

0.46

0.48

Vgs [V]

0.50

0.52

0.54

0.56

0.58

Vgs [V]

Fig. 12. Current differences as a function of gate voltage. Traps of

device A are electrically separated and those of device B affect
each other.

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66

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