Central Processing Unit

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CentralprocessingunitWikipedia
Centralprocessingunit
FromWikipedia,thefreeencyclopedia
Acentralprocessingunit(CPU)istheelectroniccircuitrywithina
computerthatcarriesouttheinstructionsofacomputerprogramby
performingthebasicarithmetic,logical,controlandinput/output(I/O)
operationsspecifiedbytheinstructions.Thecomputerindustryhasused
theterm"centralprocessingunit"atleastsincetheearly1960s.[1]
Traditionally,theterm"CPU"referstoaprocessor,morespecificallytoits
processingunitandcontrolunit(CU),distinguishingthesecoreelements
ofacomputerfromexternalcomponentssuchasmainmemoryandI/O
circuitry.[2]
Theform,designandimplementationofCPUshavechangedoverthe
courseoftheirhistory,buttheirfundamentaloperationremainsalmost
unchanged.PrincipalcomponentsofaCPUincludethearithmeticlogic
unit(ALU)thatperformsarithmeticandlogicoperations,processor
registersthatsupplyoperandstotheALUandstoretheresultsofALU
operations,andacontrolunitthatorchestratesthefetching(frommemory)
andexecutionofinstructionsbydirectingthecoordinatedoperationsofthe
ALU,registersandothercomponents.
AnIntel80486DX2CPU,asseen
fromabove.
MostmodernCPUsaremicroprocessors,meaningtheyarecontainedona
singleintegratedcircuit(IC)chip.AnICthatcontainsaCPUmayalso
containmemory,peripheralinterfaces,andothercomponentsofa
computersuchintegrateddevicesarevariouslycalledmicrocontrollersor
BottomsideofanIntel80486DX2,
systemsonachip(SoC).Somecomputersemployamulticoreprocessor,
showingitspins.
whichisasinglechipcontainingtwoormoreCPUscalled"cores"inthat
context,onecanspeakofsuchsinglechipsas"sockets".[3]Array
processorsorvectorprocessorshavemultipleprocessorsthatoperateinparallel,withnounitconsideredcentral.
TherealsoexiststheconceptofvirtualCPUswhichareanabstractionofdynamicalaggregatedcomputational
resources.[4]
Contents
1 History
1.1 TransistorCPUs
1.2 SmallscaleintegrationCPUs
1.3 LargescaleintegrationCPUs
1.4 Microprocessors
2 Operation
2.1 Fetch
2.2 Decode
2.3 Execute
3 Structureandimplementation
3.1 Controlunit
3.2 Arithmeticlogicunit
3.3 Memorymanagementunit
https://en.wikipedia.org/wiki/Central_processing_unit
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3.3
3.4
3.5
3.6
4
5
6
7
8
Memorymanagementunit
Clockrate
Integerrange
Parallelism
3.6.1 Instructionlevelparallelism
3.6.2 Tasklevelparallelism
3.6.3 Dataparallelism
3.7 VirtualCPUs
Performance
Seealso
Notes
References
Externallinks
History
EarlycomputerssuchastheENIAChadtobephysicallyrewiredto
performdifferenttasks,whichcausedthesemachinestobecalled"fixed
programcomputers".[5]Sincetheterm"CPU"isgenerallydefinedasa
deviceforsoftware(computerprogram)execution,theearliestdevicesthat
couldrightlybecalledCPUscamewiththeadventofthestoredprogram
computer.
Theideaofastoredprogramcomputerwasalreadypresentinthedesignof
J.PresperEckertandJohnWilliamMauchly'sENIAC,butwasinitially
omittedsothatitcouldbefinishedsooner.[6]OnJune30,1945,before
ENIACwasmade,mathematicianJohnvonNeumanndistributedthepaper
entitledFirstDraftofaReportontheEDVAC.Itwastheoutlineofa
storedprogramcomputerthatwouldeventuallybecompletedinAugust
1949.[7]EDVACwasdesignedtoperformacertainnumberofinstructions
(oroperations)ofvarioustypes.Significantly,theprogramswrittenfor
EDVACweretobestoredinhighspeedcomputermemoryratherthan
EDVAC,oneofthefirststored
specifiedbythephysicalwiringofthecomputer.[8]Thisovercameasevere
programcomputers
limitationofENIAC,whichwastheconsiderabletimeandeffortrequired
toreconfigurethecomputertoperformanewtask.WithvonNeumann's
design,theprogramthatEDVACrancouldbechangedsimplybychangingthecontentsofthememory.EDVAC,
however,wasnotthefirststoredprogramcomputertheManchesterSmallScaleExperimentalMachine,asmall
prototypestoredprogramcomputer,ranitsfirstprogramon21June1948[9]andtheManchesterMark1ranits
firstprogramduringthenightof1617June1949.[10]
EarlyCPUswerecustomdesignsusedaspartofalargerandsometimesdistinctivecomputer.[11]However,this
methodofdesigningcustomCPUsforaparticularapplicationhaslargelygivenwaytothedevelopmentofmulti
purposeprocessorsproducedinlargequantities.Thisstandardizationbeganintheeraofdiscretetransistor
mainframesandminicomputersandhasrapidlyacceleratedwiththepopularizationoftheintegratedcircuit(IC).
TheIChasallowedincreasinglycomplexCPUstobedesignedandmanufacturedtotolerancesontheorderof
nanometers.[12]BoththeminiaturizationandstandardizationofCPUshaveincreasedthepresenceofdigital
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devicesinmodernlifefarbeyondthelimitedapplicationofdedicatedcomputingmachines.Modern
microprocessorsappearinelectronicdevicesrangingfromautomobiles[13]tocellphones,[14]andsometimeseven
intoys.[15]
WhilevonNeumannismostoftencreditedwiththedesignofthestoredprogramcomputerbecauseofhisdesign
ofEDVAC,andthedesignbecameknownasthevonNeumannarchitecture,othersbeforehim,suchasKonrad
Zuse,hadsuggestedandimplementedsimilarideas.[16]ThesocalledHarvardarchitectureoftheHarvardMarkI,
whichwascompletedbeforeEDVAC,[17][18]alsoutilizedastoredprogramdesignusingpunchedpapertaperather
thanelectronicmemory.[19]ThekeydifferencebetweenthevonNeumannandHarvardarchitecturesisthatthe
latterseparatesthestorageandtreatmentofCPUinstructionsanddata,whiletheformerusesthesamememory
spaceforboth.[20]MostmodernCPUsareprimarilyvonNeumannindesign,butCPUswiththeHarvard
architectureareseenaswell,especiallyinembeddedapplicationsforinstance,theAtmelAVRmicrocontrollers
areHarvardarchitectureprocessors.[21]
Relaysandvacuumtubes(thermionictubes)werecommonlyusedasswitchingelements[22][23]ausefulcomputer
requiresthousandsortensofthousandsofswitchingdevices.Theoverallspeedofasystemisdependentonthe
speedoftheswitches.TubecomputerslikeEDVACtendedtoaverageeighthoursbetweenfailures,whereasrelay
computerslikethe(slower,butearlier)HarvardMarkIfailedveryrarely.[1]Intheend,tubebasedCPUsbecame
dominantbecausethesignificantspeedadvantagesaffordedgenerallyoutweighedthereliabilityproblems.Mostof
theseearlysynchronousCPUsranatlowclockratescomparedtomodernmicroelectronicdesigns.Clocksignal
frequenciesrangingfrom100kHzto4MHzwereverycommonatthistime,limitedlargelybythespeedofthe
switchingdevicestheywerebuiltwith.[24]
TransistorCPUs
ThedesigncomplexityofCPUsincreasedasvarioustechnologies
facilitatedbuildingsmallerandmorereliableelectronicdevices.Thefirst
suchimprovementcamewiththeadventofthetransistor.Transistorized
CPUsduringthe1950sand1960snolongerhadtobebuiltoutofbulky,
unreliable,andfragileswitchingelementslikevacuumtubesandrelays.[25]
WiththisimprovementmorecomplexandreliableCPUswerebuiltonto
oneorseveralprintedcircuitboardscontainingdiscrete(individual)
components.
In1964,IBMintroduceditsSystem/360computerarchitecturethatwas
usedinaseriesofcomputerscapableofrunningthesameprogramswith
differentspeedandperformance.[26]Thiswassignificantatatimewhen
mostelectroniccomputerswereincompatiblewithoneanother,eventhose
IBMPowerPC604eprocessor
madebythesamemanufacturer.Tofacilitatethisimprovement,IBM
utilizedtheconceptofamicroprogram(oftencalled"microcode"),which
stillseeswidespreadusageinmodernCPUs.[27]TheSystem/360architecturewassopopularthatitdominatedthe
mainframecomputermarketfordecadesandleftalegacythatisstillcontinuedbysimilarmoderncomputerslike
theIBMzSeries.[28][29]In1965,DigitalEquipmentCorporation(DEC)introducedanotherinfluentialcomputer
aimedatthescientificandresearchmarkets,thePDP8.[30]
Transistorbasedcomputershadseveraldistinctadvantagesovertheirpredecessors.Asidefromfacilitating
increasedreliabilityandlowerpowerconsumption,transistorsalsoallowedCPUstooperateatmuchhigherspeeds
becauseoftheshortswitchingtimeofatransistorincomparisontoatubeorrelay.[31]Theincreasedreliabilityand
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dramaticallyincreasedspeedoftheswitchingelements(whichwerealmost
exclusivelytransistorsbythistime),CPUclockratesinthetensof
megahertzwereeasilyobtainedduringthisperiod.[32]Additionallywhile
discretetransistorandICCPUswereinheavyusage,newhigh
performancedesignslikeSIMD(SingleInstructionMultipleData)vector
processorsbegantoappear.[33]Theseearlyexperimentaldesignslatergave
risetotheeraofspecializedsupercomputerslikethosemadebyCrayInc
andFujitsuLtd.
SmallscaleintegrationCPUs
Duringthisperiod,amethodofmanufacturingmanyinterconnected
transistorsinacompactspacewasdeveloped.Theintegratedcircuit(IC)
allowedalargenumberoftransistorstobemanufacturedonasingle
semiconductorbaseddie,or"chip".Atfirstonlyverybasicnonspecialized
digitalcircuitssuchasNORgateswereminiaturizedintoICs.CPUsbased
uponthese"buildingblock"ICsaregenerallyreferredtoas"smallscale
integration"(SSI)devices.SSIICs,suchastheonesusedintheApollo
guidancecomputer,usuallycontaineduptoafewscoretransistors.To
buildanentireCPUoutofSSIICsrequiredthousandsofindividualchips,
butstillconsumedmuchlessspaceandpowerthanearlierdiscrete
transistordesigns.
IBM'sSystem/370followontotheSystem/360usedSSIICsratherthan
SolidLogicTechnologydiscretetransistormodules.DEC'sPDP8/Iand
KI10PDP10alsoswitchedfromtheindividualtransistorsusedbythe
PDP8andPDP10toSSIICs,andtheirextremelypopularPDP11line
wasoriginallybuiltwithSSIICsbutwaseventuallyimplementedwithLSI
componentsoncethesebecamepractical.
LargescaleintegrationCPUs
FujitsuboardwithSPARC64VIIIfx
processors
CPU,corememory,andexternalbus
interfaceofaDECPDP8/I.Madeof
mediumscaleintegratedcircuits.
LeeBoyselpublishedinfluentialarticles,includinga1967"manifesto",
whichdescribedhowtobuildtheequivalentofa32bitmainframecomputerfromarelativelysmallnumberof
largescaleintegrationcircuits(LSI).[34][35]Atthetime,theonlywaytobuildLSIchips,whicharechipswitha
hundredormoregates,wastobuildthemusingaMOSprocess(i.e.,PMOSlogic,NMOSlogic,orCMOSlogic).
However,somecompaniescontinuedtobuildprocessorsoutofbipolarchipsbecausebipolarjunctiontransistors
weresomuchfasterthanMOSchipsforexample,DatapointbuiltprocessorsoutofTTLchipsuntiltheearly
1980s.[35]
Peoplebuildinghighspeedcomputerswantedthemtobefast,sointhe1970stheybuilttheCPUsfromsmall
scaleintegration(SSI)andmediumscaleintegration(MSI)7400seriesTTLgates.Atthetime,MOSICswereso
slowthattheywereconsideredusefulonlyinafewnicheapplicationsthatrequiredlowpower.[36][37]
Asthemicroelectronictechnologyadvanced,anincreasingnumberoftransistorswereplacedonICs,decreasing
thequantityofindividualICsneededforacompleteCPU.MSIandLSIICsincreasedtransistorcountsto
hundreds,andthenthousands.By1968,thenumberofICsrequiredtobuildacompleteCPUhadbeenreducedto
24ICsofeightdifferenttypes,witheachICcontainingroughly1000MOSFETs.[38]InstarkcontrastwithitsSSI
andMSIpredecessors,thefirstLSIimplementationofthePDP11containedaCPUcomposedofonlyfourLSI
integratedcircuits.[39]
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Microprocessors
Inthe1970s,thefundamentalinventionsbyFedericoFaggin(SiliconGate
MOSICswithselfalignedgatesalongwithhisnewrandomlogicdesign
methodology)changedthedesignandimplementationofCPUsforever.
Sincetheintroductionofthefirstcommerciallyavailablemicroprocessor
(theIntel4004)in1970,andthefirstwidelyusedmicroprocessor(theIntel
8080)in1974,thisclassofCPUshasalmostcompletelyovertakenall
othercentralprocessingunitimplementationmethods.Mainframeand
minicomputermanufacturersofthetimelaunchedproprietaryIC
developmentprogramstoupgradetheiroldercomputerarchitectures,and
eventuallyproducedinstructionsetcompatiblemicroprocessorsthatwere
backwardcompatiblewiththeirolderhardwareandsoftware.Combined
withtheadventandeventualsuccessoftheubiquitouspersonalcomputer,
thetermCPUisnowappliedalmostexclusively[a]tomicroprocessors.
SeveralCPUs(denotedcores)canbecombinedinasingleprocessing
chip.[40]
DieofanIntel80486DX2
microprocessor(actualsize:
126.75mm)initspackaging
PreviousgenerationsofCPUswereimplementedasdiscretecomponents
andnumeroussmallintegratedcircuits(ICs)ononeormorecircuit
boards.[41]Microprocessors,ontheotherhand,areCPUsmanufacturedon
averysmallnumberofICsusuallyjustone.[42]TheoverallsmallerCPU
size,asaresultofbeingimplementedonasingledie,meansfaster
switchingtimebecauseofphysicalfactorslikedecreasedgateparasitic
IntelCorei5CPUonaVaioEseries
capacitance.[43][44]Thishasallowedsynchronousmicroprocessorstohave
laptopmotherboard(ontheright,
clockratesrangingfromtensofmegahertztoseveralgigahertz.
beneaththeheatpipe)
Additionally,astheabilitytoconstructexceedinglysmalltransistorsonan
IChasincreased,thecomplexityandnumberoftransistorsinasingleCPU
hasincreasedmanyfold.ThiswidelyobservedtrendisdescribedbyMoore'slaw,whichhasproventobeafairly
accuratepredictorofthegrowthofCPU(andotherIC)complexity.[45]
Whilethecomplexity,size,construction,andgeneralformofCPUshavechangedenormouslysince1950,[46]itis
notablethatthebasicdesignandfunctionhasnotchangedmuchatall.AlmostallcommonCPUstodaycanbe
veryaccuratelydescribedasvonNeumannstoredprogrammachines.[b]AstheaforementionedMoore'slaw
continuestoholdtrue,[45]concernshavearisenaboutthelimitsofintegratedcircuittransistortechnology.Extreme
miniaturizationofelectronicgatesiscausingtheeffectsofphenomenalikeelectromigrationandsubthreshold
leakagetobecomemuchmoresignificant.Thesenewerconcernsareamongthemanyfactorscausingresearchers
toinvestigatenewmethodsofcomputingsuchasthequantumcomputer,aswellastoexpandtheusageof
parallelismandothermethodsthatextendtheusefulnessoftheclassicalvonNeumannmodel.
Operation
ThefundamentaloperationofmostCPUs,regardlessofthephysicalformtheytake,istoexecuteasequenceof
storedinstructionsthatiscalledaprogram.Theinstructionstobeexecutedarekeptinsomekindofcomputer
memory.NearlyallCPUsfollowthefetch,decodeandexecutestepsintheiroperation,whicharecollectively
knownastheinstructioncycle.
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Aftertheexecutionofaninstruction,theentireprocessrepeats,withthenextinstructioncyclenormallyfetching
thenextinsequenceinstructionbecauseoftheincrementedvalueintheprogramcounter.Ifajumpinstruction
wasexecuted,theprogramcounterwillbemodifiedtocontaintheaddressoftheinstructionthatwasjumpedto
andprogramexecutioncontinuesnormally.InmorecomplexCPUs,multipleinstructionscanbefetched,decoded,
andexecutedsimultaneously.Thissectiondescribeswhatisgenerallyreferredtoasthe"classicRISCpipeline",
whichisquitecommonamongthesimpleCPUsusedinmanyelectronicdevices(oftencalledmicrocontroller).It
largelyignorestheimportantroleofCPUcache,andthereforetheaccessstageofthepipeline.
Someinstructionsmanipulatetheprogramcounterratherthanproducingresultdatadirectlysuchinstructionsare
generallycalled"jumps"andfacilitateprogrambehaviorlikeloops,conditionalprogramexecution(throughthe
useofaconditionaljump),andexistenceoffunctions.[c]Insomeprocessors,someotherinstructionschangethe
stateofbitsina"flags"register.Theseflagscanbeusedtoinfluencehowaprogrambehaves,sincetheyoften
indicatetheoutcomeofvariousoperations.Forexample,insuchprocessorsa"compare"instructionevaluatestwo
valuesandsetsorclearsbitsintheflagsregistertoindicatewhichoneisgreaterorwhethertheyareequaloneof
theseflagscouldthenbeusedbyalaterjumpinstructiontodetermineprogramflow.
Fetch
Thefirststep,fetch,involvesretrievinganinstruction(whichisrepresentedbyanumberorsequenceofnumbers)
fromprogrammemory.Theinstruction'slocation(address)inprogrammemoryisdeterminedbyaprogram
counter(PC),whichstoresanumberthatidentifiestheaddressofthenextinstructiontobefetched.Afteran
instructionisfetched,thePCisincrementedbythelengthoftheinstructionsothatitwillcontaintheaddressof
thenextinstructioninthesequence.[d]Often,theinstructiontobefetchedmustberetrievedfromrelativelyslow
memory,causingtheCPUtostallwhilewaitingfortheinstructiontobereturned.Thisissueislargelyaddressedin
modernprocessorsbycachesandpipelinearchitectures(seebelow).
Decode
TheinstructionthattheCPUfetchesfrommemorydetermineswhattheCPUwilldo.Inthedecodestep,
performedbythecircuitryknownastheinstructiondecoder,theinstructionisconvertedintosignalsthatcontrol
otherpartsoftheCPU.
ThewayinwhichtheinstructionisinterpretedisdefinedbytheCPU'sinstructionsetarchitecture(ISA).[e]Often,
onegroupofbits(thatis,a"field")withintheinstruction,calledtheopcode,indicateswhichoperationistobe
performed,whiletheremainingfieldsusuallyprovidesupplementalinformationrequiredfortheoperation,suchas
theoperands.Thoseoperandsmaybespecifiedasaconstantvalue(calledanimmediatevalue),orasthelocation
ofavaluethatmaybeaprocessorregisteroramemoryaddress,asdeterminedbysomeaddressingmode.
InsomeCPUdesignstheinstructiondecoderisimplementedasahardwired,unchangeablecircuit.Inothers,a
microprogramisusedtotranslateinstructionsintosetsofCPUconfigurationsignalsthatareappliedsequentially
overmultipleclockpulses.Insomecasesthememorythatstoresthemicroprogramisrewritable,makingit
possibletochangethewayinwhichtheCPUdecodesinstructions.
Execute
Afterthefetchanddecodesteps,theexecutestepisperformed.DependingontheCPUarchitecture,thismay
consistofasingleactionorasequenceofactions.Duringeachaction,variouspartsoftheCPUareelectrically
connectedsotheycanperformallorpartofthedesiredoperationandthentheactioniscompleted,typicallyin
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responsetoaclockpulse.VeryoftentheresultsarewrittentoaninternalCPUregisterforquickaccessby
subsequentinstructions.Inothercasesresultsmaybewrittentoslower,butlessexpensiveandhighercapacity
mainmemory.
Forexample,ifanadditioninstructionistobeexecuted,thearithmeticlogicunit(ALU)inputsareconnectedtoa
pairofoperandsources(numberstobesummed),theALUisconfiguredtoperformanadditionoperationsothat
thesumofitsoperandinputswillappearatitsoutput,andtheALUoutputisconnectedtostorage(e.g.,aregister
ormemory)thatwillreceivethesum.Whentheclockpulseoccurs,thesumwillbetransferredtostorageand,if
theresultingsumistoolarge(i.e.,itislargerthantheALU'soutputwordsize),anarithmeticoverflowflagwillbe
set.
Structureandimplementation
HardwiredintoaCPU'scircuitryisasetofbasic
operationsitcanperform,calledaninstructionset.
Suchoperationsmayinvolve,forexample,adding
orsubtractingtwonumbers,comparingtwo
numbers,orjumpingtoadifferentpartofa
program.Eachbasicoperationisrepresentedbya
particularcombinationofbits,knownasthe
machinelanguageopcodewhileexecuting
instructionsinamachinelanguageprogram,the
CPUdecideswhichoperationtoperformby
"decoding"theopcode.Acompletemachine
languageinstructionconsistsofanopcodeand,in
manycases,additionalbitsthatspecifyarguments
fortheoperation(forexample,thenumberstobe
summedinthecaseofanadditionoperation).Going
upthecomplexityscale,amachinelanguage
programisacollectionofmachinelanguage
instructionsthattheCPUexecutes.
BlockdiagramofabasicuniprocessorCPUcomputer.Black
linesindicatedataflow,whereasredlinesindicatecontrolflow
arrowsindicateflowdirections.
Theactualmathematicaloperationforeach
instructionisperformedbyacombinationallogic
circuitwithintheCPU'sprocessorknownasthearithmeticlogicunitorALU.Ingeneral,aCPUexecutesan
instructionbyfetchingitfrommemory,usingitsALUtoperformanoperation,andthenstoringtheresultto
memory.Besidetheinstructionsforintegermathematicsandlogicoperations,variousothermachineinstructions
exist,suchasthoseforloadingdatafrommemoryandstoringitback,branchingoperations,andmathematical
operationsonfloatingpointnumbersperformedbytheCPU'sfloatingpointunit(FPU).[48]
Controlunit
ThecontrolunitoftheCPUcontainscircuitrythatuseselectricalsignalstodirecttheentirecomputersystemto
carryoutstoredprograminstructions.Thecontrolunitdoesnotexecuteprograminstructionsrather,itdirects
otherpartsofthesystemtodoso.ThecontrolunitcommunicateswithboththeALUandmemory.
Arithmeticlogicunit
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Thearithmeticlogicunit(ALU)isadigitalcircuitwithinthe
processorthatperformsintegerarithmeticandbitwiselogic
operations.TheinputstotheALUarethedatawordstobe
operatedon(calledoperands),statusinformationfromprevious
operations,andacodefromthecontrolunitindicatingwhich
operationtoperform.Dependingontheinstructionbeing
executed,theoperandsmaycomefrominternalCPUregistersor
externalmemory,ortheymaybeconstantsgeneratedbythe
ALUitself.
SymbolicrepresentationofanALUanditsinput
Whenallinputsignalshavesettledandpropagatedthroughthe
andoutputsignals
ALUcircuitry,theresultoftheperformedoperationappearsat
theALU'soutputs.Theresultconsistsofbothadataword,
whichmaybestoredinaregisterormemory,andstatusinformationthatistypicallystoredinaspecial,internal
CPUregisterreservedforthispurpose.
Memorymanagementunit
Mosthighendmicroprocessors(indesktop,laptop,servercomputers)haveamemorymanagementunit,
translatinglogicaladdressesintophysicalRAMaddresses,providingmemoryprotectionandpagingabilities,
usefulforvirtualmemory.Simplerprocessors,especiallymicrocontrollersusuallydon'tincludeanMMU.
Clockrate
MostCPUsaresynchronouscircuits,whichmeanstheyemployaclocksignaltopacetheirsequentialoperations.
Theclocksignalisproducedbyanexternaloscillatorcircuitthatgeneratesaconsistentnumberofpulseseach
secondintheformofaperiodicsquarewave.Thefrequencyoftheclockpulsesdeterminestherateatwhicha
CPUexecutesinstructionsand,consequently,thefastertheclock,themoreinstructionstheCPUwillexecuteeach
second.
ToensureproperoperationoftheCPU,theclockperiodislongerthanthemaximumtimeneededforallsignalsto
propagate(move)throughtheCPU.Insettingtheclockperiodtoavaluewellabovetheworstcasepropagation
delay,itispossibletodesigntheentireCPUandthewayitmovesdataaroundthe"edges"oftherisingandfalling
clocksignal.ThishastheadvantageofsimplifyingtheCPUsignificantly,bothfromadesignperspectiveanda
componentcountperspective.However,italsocarriesthedisadvantagethattheentireCPUmustwaitonits
slowestelements,eventhoughsomeportionsofitaremuchfaster.Thislimitationhaslargelybeencompensated
forbyvariousmethodsofincreasingCPUparallelism(seebelow).
However,architecturalimprovementsalonedonotsolveallofthedrawbacksofgloballysynchronousCPUs.For
example,aclocksignalissubjecttothedelaysofanyotherelectricalsignal.Higherclockratesinincreasingly
complexCPUsmakeitmoredifficulttokeeptheclocksignalinphase(synchronized)throughouttheentireunit.
ThishasledmanymodernCPUstorequiremultipleidenticalclocksignalstobeprovidedtoavoiddelayinga
singlesignalsignificantlyenoughtocausetheCPUtomalfunction.Anothermajorissue,asclockratesincrease
dramatically,istheamountofheatthatisdissipatedbytheCPU.Theconstantlychangingclockcausesmany
componentstoswitchregardlessofwhethertheyarebeingusedatthattime.Ingeneral,acomponentthatis
switchingusesmoreenergythananelementinastaticstate.Therefore,asclockrateincreases,sodoesenergy
consumption,causingtheCPUtorequiremoreheatdissipationintheformofCPUcoolingsolutions.
Onemethodofdealingwiththeswitchingofunneededcomponentsiscalledclockgating,whichinvolvesturning
offtheclocksignaltounneededcomponents(effectivelydisablingthem).However,thisisoftenregardedas
difficulttoimplementandthereforedoesnotseecommonusageoutsideofverylowpowerdesigns.Onenotable
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recentCPUdesignthatusesextensiveclockgatingistheIBMPowerPCbasedXenonusedintheXbox360that
way,powerrequirementsoftheXbox360aregreatlyreduced.[49]Anothermethodofaddressingsomeofthe
problemswithaglobalclocksignalistheremovaloftheclocksignalaltogether.Whileremovingtheglobalclock
signalmakesthedesignprocessconsiderablymorecomplexinmanyways,asynchronous(orclockless)designs
carrymarkedadvantagesinpowerconsumptionandheatdissipationincomparisonwithsimilarsynchronous
designs.Whilesomewhatuncommon,entireasynchronousCPUshavebeenbuiltwithoututilizingaglobalclock
signal.TwonotableexamplesofthisaretheARMcompliantAMULETandtheMIPSR3000compatible
MiniMIPS.
Ratherthantotallyremovingtheclocksignal,someCPUdesignsallowcertainportionsofthedevicetobe
asynchronous,suchasusingasynchronousALUsinconjunctionwithsuperscalarpipeliningtoachievesome
arithmeticperformancegains.Whileitisnotaltogetherclearwhethertotallyasynchronousdesignscanperformat
acomparableorbetterlevelthantheirsynchronouscounterparts,itisevidentthattheydoatleastexcelinsimpler
mathoperations.This,combinedwiththeirexcellentpowerconsumptionandheatdissipationproperties,makes
themverysuitableforembeddedcomputers.[50]
Integerrange
EveryCPUrepresentsnumericalvaluesinaspecificway.Forexample,someearlydigitalcomputersrepresented
numbersasfamiliardecimal(base10)numeralsystemvalues,andothershaveemployedmoreunusual
representationssuchasternary(basethree).NearlyallmodernCPUsrepresentnumbersinbinaryform,witheach
digitbeingrepresentedbysometwovaluedphysicalquantitysuchasa"high"or"low"voltage.[f]
Asixbitwordcontainingthebinary
encodedrepresentationofdecimal
value40.MostmodernCPUsemploy
wordsizesthatareapoweroftwo,
forexample8,16,32or64bits.
Relatedtonumericrepresentationisthesizeandprecisionofinteger
numbersthataCPUcanrepresent.InthecaseofabinaryCPU,thisis
measuredbythenumberofbits(significantdigitsofabinaryencoded
integer)thattheCPUcanprocessinoneoperation,whichiscommonly
called"wordsize","bitwidth","datapathwidth","integerprecision",or
"integersize".ACPU'sintegersizedeterminestherangeofintegervalues
itcandirectlyoperateon.[g]Forexample,an8bitCPUcandirectly
manipulateintegersrepresentedbyeightbits,whichhavearangeof256
(28)discreteintegervalues.
IntegerrangecanalsoaffectthenumberofmemorylocationstheCPUcandirectlyaddress(anaddressisan
integervaluerepresentingaspecificmemorylocation).Forexample,ifabinaryCPUuses32bitstorepresenta
memoryaddressthenitcandirectlyaddress232memorylocations.Tocircumventthislimitationandforvarious
otherreasons,someCPUsusemechanisms(suchasbankswitching)thatallowadditionalmemorytobeaddressed.
CPUswithlargerwordsizesrequiremorecircuitryandconsequentlyarephysicallylarger,costmore,andconsume
morepower(andthereforegeneratemoreheat).Asaresult,smaller4or8bitmicrocontrollersarecommonly
usedinmodernapplicationseventhoughCPUswithmuchlargerwordsizes(suchas16,32,64,even128bit)are
available.Whenhigherperformanceisrequired,however,thebenefitsofalargerwordsize(largerdatarangesand
addressspaces)mayoutweighthedisadvantages.ACPUcanhaveinternaldatapathsshorterthanthewordsizeto
reducesizeandcost.Forexample,eventhoughtheIBMSystem/360instructionsetwasa32bitinstructionset,the
System/360Model30andModel40had8bitdatapathsinthearithmeticlogicalunit,sothata32bitaddrequired
fourcycles,oneforeach8bitsoftheoperands,and,eventhoughtheMotorola68kinstructionsetwasa32bit
instructionset,theMotorola68000andMotorola68010had16bitdatapathsinthearithmeticlogicalunit,sothat
a32bitaddrequiredtwocycles.
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Togainsomeoftheadvantagesaffordedbybothlowerandhigherbitlengths,manyinstructionsetshavedifferent
bitwidthsforintegerandfloatingpointdata,allowingCPUsimplementingthatinstructionsettohavedifferentbit
widthsfordifferentportionsofthedevice.Forexample,theIBMSystem/360instructionsetwasprimarily32bit,
butsupported64bitfloatingpointvaluestofacilitategreateraccuracyandrangeinfloatingpointnumbers.[27]The
System/360Model65hadan8bitadderfordecimalandfixedpointbinaryarithmeticanda60bitadderfor
floatingpointarithmetic.[51]ManylaterCPUdesignsusesimilarmixedbitwidth,especiallywhentheprocessoris
meantforgeneralpurposeusagewhereareasonablebalanceofintegerandfloatingpointcapabilityisrequired.
Parallelism
Thedescriptionofthebasicoperationof
aCPUofferedintheprevioussection
describesthesimplestformthataCPU
cantake.ThistypeofCPU,usually
referredtoassubscalar,operatesonand
executesoneinstructionononeortwo
piecesofdataatatime,thatislessthan
oneinstructionperclockcycle(IPC<1).
ModelofasubscalarCPU,inwhichittakesfifteenclockcyclestocomplete
threeinstructions.
ThisprocessgivesrisetoaninherentinefficiencyinsubscalarCPUs.Sinceonlyoneinstructionisexecutedata
time,theentireCPUmustwaitforthatinstructiontocompletebeforeproceedingtothenextinstruction.Asa
result,thesubscalarCPUgets"hungup"oninstructionswhichtakemorethanoneclockcycletocomplete
execution.Evenaddingasecondexecutionunit(seebelow)doesnotimproveperformancemuchratherthanone
pathwaybeinghungup,nowtwopathwaysarehungupandthenumberofunusedtransistorsisincreased.This
design,whereintheCPU'sexecutionresourcescanoperateononlyoneinstructionatatime,canonlypossibly
reachscalarperformance(oneinstructionperclockcycle,IPC=1).However,theperformanceisnearlyalways
subscalar(lessthanoneinstructionperclockcycle,IPC<1).
Attemptstoachievescalarandbetterperformancehaveresultedinavarietyofdesignmethodologiesthatcausethe
CPUtobehavelesslinearlyandmoreinparallel.WhenreferringtoparallelisminCPUs,twotermsaregenerally
usedtoclassifythesedesigntechniques:
instructionlevelparallelism(ILP),whichseekstoincreasetherateatwhichinstructionsareexecutedwithin
aCPU(thatis,toincreasetheutilizationofondieexecutionresources)
tasklevelparallelism(TLP),whichpurposestoincreasethenumberofthreadsorprocessesthataCPUcan
executesimultaneously.
Eachmethodologydiffersbothinthewaysinwhichtheyareimplemented,aswellastherelativeeffectiveness
theyaffordinincreasingtheCPU'sperformanceforanapplication.[h]
Instructionlevelparallelism
Oneofthesimplestmethodsusedtoaccomplishincreasedparallelismistobeginthefirststepsofinstruction
fetchinganddecodingbeforethepriorinstructionfinishesexecuting.Thisisthesimplestformofatechnique
knownasinstructionpipelining,andisutilizedinalmostallmoderngeneralpurposeCPUs.Pipeliningallows
morethanoneinstructiontobeexecutedatanygiventimebybreakingdowntheexecutionpathwayintodiscrete
stages.Thisseparationcanbecomparedtoanassemblyline,inwhichaninstructionismademorecompleteat
eachstageuntilitexitstheexecutionpipelineandisretired.
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Pipeliningdoes,however,introducethepossibilityfora
situationwheretheresultofthepreviousoperationis
neededtocompletethenextoperationaconditionoften
termeddatadependencyconflict.Tocopewiththis,
additionalcaremustbetakentocheckforthesesortsof
conditionsanddelayaportionoftheinstructionpipelineif
Basicfivestagepipeline.Inthebestcasescenario,this
thisoccurs.Naturally,accomplishingthisrequires
pipelinecansustainacompletionrateofoneinstruction
additionalcircuitry,sopipelinedprocessorsaremore
perclockcycle.
complexthansubscalarones(thoughnotvery
significantlyso).Apipelinedprocessorcanbecomevery
nearlyscalar,inhibitedonlybypipelinestalls(aninstructionspendingmorethanoneclockcycleinastage).
Furtherimprovementupontheideaofinstruction
pipeliningledtothedevelopmentofamethodthat
decreasestheidletimeofCPUcomponentsevenfurther.
Designsthataresaidtobesuperscalarincludealong
instructionpipelineandmultipleidenticalexecution
units.[52]Inasuperscalarpipeline,multipleinstructions
arereadandpassedtoadispatcher,whichdecideswhether
ornottheinstructionscanbeexecutedinparallel
(simultaneously).Ifsotheyaredispatchedtoavailable
executionunits,resultingintheabilityforseveral
instructionstobeexecutedsimultaneously.Ingeneral,the
moreinstructionsasuperscalarCPUisabletodispatch
simultaneouslytowaitingexecutionunits,themore
instructionswillbecompletedinagivencycle.
Asimplesuperscalarpipeline.Byfetchingand
dispatchingtwoinstructionsatatime,amaximumof
twoinstructionsperclockcyclecanbecompleted.
MostofthedifficultyinthedesignofasuperscalarCPU
architectureliesincreatinganeffectivedispatcher.Thedispatcherneedstobeabletoquicklyandcorrectly
determinewhetherinstructionscanbeexecutedinparallel,aswellasdispatchtheminsuchawayastokeepas
manyexecutionunitsbusyaspossible.Thisrequiresthattheinstructionpipelineisfilledasoftenaspossibleand
givesrisetotheneedinsuperscalararchitecturesforsignificantamountsofCPUcache.Italsomakeshazard
avoidingtechniqueslikebranchprediction,speculativeexecution,andoutoforderexecutioncrucialto
maintaininghighlevelsofperformance.Byattemptingtopredictwhichbranch(orpath)aconditionalinstruction
willtake,theCPUcanminimizethenumberoftimesthattheentirepipelinemustwaituntilaconditional
instructioniscompleted.Speculativeexecutionoftenprovidesmodestperformanceincreasesbyexecutingportions
ofcodethatmaynotbeneededafteraconditionaloperationcompletes.Outoforderexecutionsomewhat
rearrangestheorderinwhichinstructionsareexecutedtoreducedelaysduetodatadependencies.Alsoincaseof
singleinstructionstream,multipledatastreamacasewhenalotofdatafromthesametypehastobeprocessed
,modernprocessorscandisablepartsofthepipelinesothatwhenasingleinstructionisexecutedmanytimes,
theCPUskipsthefetchanddecodephasesandthusgreatlyincreasesperformanceoncertainoccasions,especially
inhighlymonotonousprogramenginessuchasvideocreationsoftwareandphotoprocessing.
InthecasewhereaportionoftheCPUissuperscalarandpartisnot,thepartwhichisnotsuffersaperformance
penaltyduetoschedulingstalls.TheIntelP5PentiumhadtwosuperscalarALUswhichcouldacceptone
instructionperclockcycleeach,butitsFPUcouldnotacceptoneinstructionperclockcycle.ThustheP5was
integersuperscalarbutnotfloatingpointsuperscalar.Intel'ssuccessortotheP5architecture,P6,addedsuperscalar
capabilitiestoitsfloatingpointfeatures,andthereforeaffordedasignificantincreaseinfloatingpointinstruction
performance.
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BothsimplepipeliningandsuperscalardesignincreaseaCPU'sILPbyallowingasingleprocessortocomplete
executionofinstructionsatratessurpassingoneinstructionperclockcycle.[i]MostmodernCPUdesignsareat
leastsomewhatsuperscalar,andnearlyallgeneralpurposeCPUsdesignedinthelastdecadearesuperscalar.In
lateryearssomeoftheemphasisindesigninghighILPcomputershasbeenmovedoutoftheCPU'shardwareand
intoitssoftwareinterface,orISA.Thestrategyoftheverylonginstructionword(VLIW)causessomeILPto
becomeimplieddirectlybythesoftware,reducingtheamountofworktheCPUmustperformtoboostILPand
therebyreducingthedesign'scomplexity.
Tasklevelparallelism
Anotherstrategyofachievingperformanceistoexecutemultiplethreadsorprocessesinparallel.Thisareaof
researchisknownasparallelcomputing.[53]InFlynn'staxonomy,thisstrategyisknownasmultipleinstruction
stream,multipledatastream(MIMD).[54]
Onetechnologyusedforthispurposewasmultiprocessing(MP).[55]Theinitialflavorofthistechnologyisknown
assymmetricmultiprocessing(SMP),whereasmallnumberofCPUsshareacoherentviewoftheirmemory
system.Inthisscheme,eachCPUhasadditionalhardwaretomaintainaconstantlyuptodateviewofmemory.By
avoidingstaleviewsofmemory,theCPUscancooperateonthesameprogramandprogramscanmigratefromone
CPUtoanother.ToincreasethenumberofcooperatingCPUsbeyondahandful,schemessuchasnonuniform
memoryaccess(NUMA)anddirectorybasedcoherenceprotocolswereintroducedinthe1990s.SMPsystemsare
limitedtoasmallnumberofCPUswhileNUMAsystemshavebeenbuiltwiththousandsofprocessors.Initially,
multiprocessingwasbuiltusingmultiplediscreteCPUsandboardstoimplementtheinterconnectbetweenthe
processors.Whentheprocessorsandtheirinterconnectareallimplementedonasinglechip,thetechnologyis
knownaschiplevelmultiprocessing(CMP)andthesinglechipasamulticoreprocessor.
Itwaslaterrecognizedthatfinergrainparallelismexistedwithasingleprogram.Asingleprogrammighthave
severalthreads(orfunctions)thatcouldbeexecutedseparatelyorinparallel.Someoftheearliestexamplesofthis
technologyimplementedinput/outputprocessingsuchasdirectmemoryaccessasaseparatethreadfromthe
computationthread.Amoregeneralapproachtothistechnologywasintroducedinthe1970swhensystemswere
designedtorunmultiplecomputationthreadsinparallel.Thistechnologyisknownasmultithreading(MT).This
approachisconsideredmorecosteffectivethanmultiprocessing,asonlyasmallnumberofcomponentswithina
CPUisreplicatedtosupportMTasopposedtotheentireCPUinthecaseofMP.InMT,theexecutionunitsand
thememorysystemincludingthecachesaresharedamongmultiplethreads.ThedownsideofMTisthatthe
hardwaresupportformultithreadingismorevisibletosoftwarethanthatofMPandthussupervisorsoftwarelike
operatingsystemshavetoundergolargerchangestosupportMT.OnetypeofMTthatwasimplementedisknown
astemporalmultithreading,whereonethreadisexecuteduntilitisstalledwaitingfordatatoreturnfromexternal
memory.Inthisscheme,theCPUwouldthenquicklycontextswitchtoanotherthreadwhichisreadytorun,the
switchoftendoneinoneCPUclockcycle,suchastheUltraSPARCT1.AnothertypeofMTissimultaneous
multithreading,whereinstructionsfrommultiplethreadsareexecutedinparallelwithinoneCPUclockcycle.
Forseveraldecadesfromthe1970stoearly2000s,thefocusindesigninghighperformancegeneralpurposeCPUs
waslargelyonachievinghighILPthroughtechnologiessuchaspipelining,caches,superscalarexecution,outof
orderexecution,etc.Thistrendculminatedinlarge,powerhungryCPUssuchastheIntelPentium4.Bytheearly
2000s,CPUdesignerswerethwartedfromachievinghigherperformancefromILPtechniquesduetothegrowing
disparitybetweenCPUoperatingfrequenciesandmainmemoryoperatingfrequenciesaswellasescalatingCPU
powerdissipationowingtomoreesotericILPtechniques.
CPUdesignersthenborrowedideasfromcommercialcomputingmarketssuchastransactionprocessing,wherethe
aggregateperformanceofmultipleprograms,alsoknownasthroughputcomputing,wasmoreimportantthanthe
performanceofasinglethreadorprocess.
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Thisreversalofemphasisisevidencedbytheproliferationofdualandmorecoreprocessordesignsandnotably,
Intel'snewerdesignsresemblingitslesssuperscalarP6architecture.Latedesignsinseveralprocessorfamilies
exhibitCMP,includingthex8664OpteronandAthlon64X2,theSPARCUltraSPARCT1,IBMPOWER4and
POWER5,aswellasseveralvideogameconsoleCPUsliketheXbox360'striplecorePowerPCdesign,andthe
PS3's7coreCellmicroprocessor.
Dataparallelism
Alesscommonbutincreasinglyimportantparadigmofprocessors(andindeed,computingingeneral)dealswith
dataparallelism.Theprocessorsdiscussedearlierareallreferredtoassometypeofscalardevice.[j]Asthename
implies,vectorprocessorsdealwithmultiplepiecesofdatainthecontextofoneinstruction.Thiscontrastswith
scalarprocessors,whichdealwithonepieceofdataforeveryinstruction.UsingFlynn'staxonomy,thesetwo
schemesofdealingwithdataaregenerallyreferredtoassingleinstructionstream,multipledatastream(SIMD)
andsingleinstructionstream,singledatastream(SISD),respectively.Thegreatutilityincreatingprocessorsthat
dealwithvectorsofdataliesinoptimizingtasksthattendtorequirethesameoperation(forexample,asumora
dotproduct)tobeperformedonalargesetofdata.Someclassicexamplesofthesetypesoftasksinclude
multimediaapplications(images,video,andsound),aswellasmanytypesofscientificandengineeringtasks.
Whereasascalarprocessormustcompletetheentireprocessoffetching,decoding,andexecutingeachinstruction
andvalueinasetofdata,avectorprocessorcanperformasingleoperationonacomparativelylargesetofdata
withoneinstruction.Ofcourse,thisisonlypossiblewhentheapplicationtendstorequiremanystepswhichapply
oneoperationtoalargesetofdata.
Mostearlyvectorprocessors,suchastheCray1,wereassociatedalmostexclusivelywithscientificresearchand
cryptographyapplications.However,asmultimediahaslargelyshiftedtodigitalmedia,theneedforsomeformof
SIMDingeneralpurposeprocessorshasbecomesignificant.Shortlyafterinclusionoffloatingpointunitsstarted
tobecomecommonplaceingeneralpurposeprocessors,specificationsforandimplementationsofSIMDexecution
unitsalsobegantoappearforgeneralpurposeprocessors.SomeoftheseearlySIMDspecificationslikeHP's
MultimediaAccelerationeXtensions(MAX)andIntel'sMMXwereintegeronly.Thisprovedtobeasignificant
impedimentforsomesoftwaredevelopers,sincemanyoftheapplicationsthatbenefitfromSIMDprimarilydeal
withfloatingpointnumbers.Progressively,developersrefinedandremadetheseearlydesignsintosomeofthe
commonmodernSIMDspecifications,whichareusuallyassociatedwithoneISA.Somenotablemodernexamples
includeIntel'sSSEandthePowerPCrelatedAltiVec(alsoknownasVMX).[k]
VirtualCPUs
CloudcomputingcaninvolvesubdividingCPUoperationintovirtualcentralprocessingunits[56](vCPUs[57]).
Ahostisthevirtualequivalentofaphysicalmachine,onwhichavirtualsystemisoperating.[58]Whenthereare
severalphysicalmachinesoperatingintandemandmanagedasawhole,thegroupedcomputingandmemory
resourcesformacluster.Insomesystemsitispossibletodynamicallyaddandremovefromacluster.Resources
availableatahostandclusterlevelcanbepartitionedoutintoresourcespoolswithfinegranularity.
Performance
Theperformanceorspeedofaprocessordependson,amongmanyotherfactors,theclockrate(generallygivenin
multiplesofhertz)andtheinstructionsperclock(IPC),whichtogetherarethefactorsfortheinstructionsper
second(IPS)thattheCPUcanperform.[59]ManyreportedIPSvalueshaverepresented"peak"executionrateson
artificialinstructionsequenceswithfewbranches,whereasrealisticworkloadsconsistofamixofinstructionsand
applications,someofwhichtakelongertoexecutethanothers.Theperformanceofthememoryhierarchyalso
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greatlyaffectsprocessorperformance,anissuebarelyconsideredinMIPScalculations.Becauseoftheseproblems,
variousstandardizedtests,oftencalled"benchmarks"forthispurposesuchasSPECinthavebeendevelopedto
attempttomeasuretherealeffectiveperformanceincommonlyusedapplications.
Processingperformanceofcomputersisincreasedbyusingmulticoreprocessors,whichessentiallyisplugging
twoormoreindividualprocessors(calledcoresinthissense)intooneintegratedcircuit.[60]Ideally,adualcore
processorwouldbenearlytwiceaspowerfulasasinglecoreprocessor.Inpractice,theperformancegainisfar
smaller,onlyabout50%,duetoimperfectsoftwarealgorithmsandimplementation.[61]Increasingthenumberof
coresinaprocessor(i.e.dualcore,quadcore,etc.)increasestheworkloadthatcanbehandled.Thismeansthat
theprocessorcannowhandlenumerousasynchronousevents,interrupts,etc.whichcantakeatollontheCPU
whenoverwhelmed.Thesecorescanbethoughtofasdifferentfloorsinaprocessingplant,witheachfloor
handlingadifferenttask.Sometimes,thesecoreswillhandlethesametasksascoresadjacenttothemifasingle
coreisnotenoughtohandletheinformation.
DuetospecificcapabilitiesofmodernCPUs,suchashyperthreadinganduncore,whichinvolvesharingofactual
CPUresourceswhileaimingatincreasedutilization,monitoringperformancelevelsandhardwareutilization
graduallybecameamorecomplextask.[62]Asaresponse,someCPUsimplementadditionalhardwarelogicthat
monitorsactualutilizationofvariouspartsofaCPUandprovidesvariouscountersaccessibletosoftwarean
exampleisIntel'sPerformanceCounterMonitortechnology.[3]
Seealso
Addressingmode
AMDAcceleratedProcessingUnit
CISC
Computerbus
Computerengineering
CPUcorevoltage
CPUsocket
Digitalsignalprocessor
Hyperthreading
ListofCPUarchitectures
ListofCPUarchitectures
Microprocessor
Multicoreprocessor
Protectionring
RISC
Streamprocessing
TruePerformanceIndex
Waitstate
Notes
a.IntegratedcircuitsarenowusedtoimplementallCPUs,exceptforafewmachinesdesignedtowithstandlarge
electromagneticpulses,sayfromanuclearweapon.
b.Thesocalled"vonNeumann"memoexpoundedtheideaofstoredprograms,[47]whichforexamplemaybestoredon
punchedcards,papertape,ormagnetictape.
c.SomeearlycomputersliketheHarvardMarkIdidnotsupportanykindof"jump"instruction,effectivelylimitingthe
complexityoftheprogramstheycouldrun.Itislargelyforthisreasonthatthesecomputersareoftennotconsideredto
containaproperCPU,despitetheirclosesimilaritytostoredprogramcomputers.
d.Sincetheprogramcountercountsmemoryaddressesandnotinstructions,itisincrementedbythenumberofmemory
unitsthattheinstructionwordcontains.InthecaseofsimplefixedlengthinstructionwordISAs,thisisalwaysthesame
number.Forexample,afixedlength32bitinstructionwordISAthatuses8bitmemorywordswouldalwaysincrement
thePCbyfour(exceptinthecaseofjumps).ISAsthatusevariablelengthinstructionwordsincrementthePCbythe
numberofmemorywordscorrespondingtothelastinstruction'slength.
e.BecausetheinstructionsetarchitectureofaCPUisfundamentaltoitsinterfaceandusage,itisoftenusedasa
classificationofthe"type"ofCPU.Forexample,a"PowerPCCPU"usessomevariantofthePowerPCISA.Asystem
canexecuteadifferentISAbyrunninganemulator.
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f.Thephysicalconceptofvoltageisananalogonebynature,practicallyhavinganinfiniterangeofpossiblevalues.Forthe
purposeofphysicalrepresentationofbinarynumbers,twospecificrangesofvoltagesaredefined,oneforlogic'0'and
anotherforlogic'1'.Theserangesaredictatedbydesignconsiderationssuchasnoisemarginsandcharacteristicsofthe
devicesusedtocreatetheCPU.
g.WhileaCPU'sintegersizesetsalimitonintegerranges,thiscan(andoftenis)overcomeusingacombinationof
softwareandhardwaretechniques.Byusingadditionalmemory,softwarecanrepresentintegersmanymagnitudeslarger
thantheCPUcan.SometimestheCPU'sinstructionsetwillevenfacilitateoperationsonintegerslargerthanitcan
nativelyrepresentbyprovidinginstructionstomakelargeintegerarithmeticrelativelyquick.Thismethodofdealingwith
largeintegersisslowerthanutilizingaCPUwithhigherintegersize,butisareasonabletradeoffincaseswherenatively
supportingthefullintegerrangeneededwouldbecostprohibitive.SeeArbitraryprecisionarithmeticformoredetailson
purelysoftwaresupportedarbitrarysizedintegers.
h.NeitherILPnorTLPisinherentlysuperiorovertheothertheyaresimplydifferentmeansbywhichtoincreaseCPU
parallelism.Assuch,theybothhaveadvantagesanddisadvantages,whichareoftendeterminedbythetypeofsoftware
thattheprocessorisintendedtorun.HighTLPCPUsareoftenusedinapplicationsthatlendthemselveswelltobeing
splitupintonumeroussmallerapplications,socalled"embarrassinglyparallelproblems".Frequently,acomputational
problemthatcanbesolvedquicklywithhighTLPdesignstrategieslikesymmetricmultiprocessingtakessignificantly
moretimeonhighILPdeviceslikesuperscalarCPUs,andviceversa.
i.Bestcasescenario(orpeak)IPCratesinverysuperscalararchitecturesaredifficulttomaintainsinceitisimpossibleto
keeptheinstructionpipelinefilledallthetime.Therefore,inhighlysuperscalarCPUs,averagesustainedIPCisoften
discussedratherthanpeakIPC.
j.EarlierthetermscalarwasusedtocomparetheIPCcountaffordedbyvariousILPmethods.Herethetermisusedinthe
strictlymathematicalsensetocontrastwithvectors.Seescalar(mathematics)andVector(geometric).
k.AlthoughSSE/SSE2/SSE3havesupersededMMXinIntel'sgeneralpurposeprocessors,laterIA32designsstillsupport
MMX.ThisisusuallyaccomplishedbyprovidingmostoftheMMXfunctionalitywiththesamehardwarethatsupports
themuchmoreexpansiveSSEinstructionsets.
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