A VHDL Design of A JPEG Still Image Compression Standard Decoder

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8-1-1994
A VHDL design of a JPEG still image compression

standard decoder
Douglas Carpenter
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Carpenter, Douglas, "A VHDL design of a JPEG still image compression standard decoder" (1994). Thesis. Rochester Institute of
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A VHDL Design of a JPEG Still Image

Compression Standard Decoder
by
Douglas A. Carpenter
A Thesis Submitted
ill
Partial Fulfillment of the

Requirements for the Degree of
MASTER OF SCIENCE
ill
Computer Engineering
--_
Approved by:
Graduate Advisor - Prof. George A. Brown
Committee Member - Dr. Ronald G. Matteson
Department Head - Dr. Roy S. Czemikowski
DEPARTMENT OF COMPUTER ENGINEERING

COLLEGE OF ENGINEERING
ROCHESTER INSTITUTE OF TECHNOLOGY
ROCHESTER, NEW YORK
August, 1994
THESIS RELEASE PERMISSION FORM

ROCHESTER INSTITUTE OF TECHNOLOGY
Title: A VHDL Design of a JPEG Still Image Compression Standard Decoder
I, Douglas A. Carpenter, hereby grant permission to the Wallace Memorial Library ofRIT
to reproduce my thesis in whole or in part.
Signature:
Date:
/5 S e f
q~
11
ABSTRACT
Digital images
JPEG
require
large
amounts of
memory to be
compression standard allows the amount of
image to be
reduced with
design
ASIC that implements
of an
little to
decoder
implements the baseline decoder defined

most notable
the speed of
being that
only
decompressing
writing VHDL
source
code,
grayscale
of
by the
images
memory
loss
no perceptible
JPEG
JPEG
can
stored
of
in
a computer system.
storage required
image
quality.
compressed
in turn was
cells.
in
digital
This thesis is
standard with a
few exceptions, the
be decompressed. With
used
images. The decoder
images is greatly increased. The decoder
which
by
The
such an
was
ASIC,
designed
by
to synthesize the ASIC using standard
TABLE OF CONTENTS
ABSTRACT
iii
LIST OF FIGURES
vi
LIST OF TABLES
GLOSSARY OF TERMS
xii
1.0 INTRODUCTION
1-1
1.1 OVERVIEW
1-1
1.2 IMAGES
1-1
1.3 DIGITAL IMAGING
1-2
1.4 JPEG
1-3
1.5 TYPES OF JPEG IMPLEMENTATIONS
1-6
1.6 VHDL
1-8
1.7 DESIGN BRIEF
1-10
1.8 SOFTWARE USED
1-11
2.0 CONCEPTS
2-1
2-1
2.1 JPEG
2.1.1 JPEG BRIEF
2-1
2. 1.2 HUFFMAN CODING
2-7
2. 1.3 DISCRETE COSINE TRANSFORM
2-12
2.2 A JPEG ENCODER AND DECODER
2-13
2.3 INTERCHANGE FORMAT
2-20
2.4 VHDL
2-21
2.4.1 BEHAVIORAL MODELING
2-21
2.4.2 STRUCTURAL MODELING
2-23
3.0 IMPLEMENTATION
3-1
3.1 C PROGRAM BEHAVIORAL MODEL
3-1
3.2 LIMITATIONS OF STRUCTURAL MODEL
3-1
3.3 VHDL STRUCTURAL MODEL
3-2
3.3.1 VHDL TEST BENCH
3-2
3.3.2 CONTROL SIGNALS
3-5
3.3.3 DECODER MODULE
3-7
3.3.4 DECODING A SCAN
3-35
3.3.5 MISCELLANEOUS MODULES
3-43
IV
4-1
4.0 RESULTS
4.1 TIMING DIAGRAMS
4-1
4.1 DECODED IMAGES
4-9
4.2 SYNTHESIS OF A MODULE
4-14
5.0 CONCLUSION
5-1
5.1 ACCOMPLISHMENTS
5-1
5.2 IMPROVEMENTS
5-1
5.3 LESSONS LEARNED
5-4
BIBLIOGRAPHY
APPENDIX A
VHDL SOURCE CODE
A-l
APPENDIX B
STATE TABLES AND ESPRESSO RESULTS
B-l
APPENDIX C
SUPPORT CODE
C-l
LIST OF FIGURES
Figure 1-1
Example Compressed Images
1-5
Figure 1-2
Overview
1-10
Figure 2-1
Encoder Overview
2-2
Figure 2-2
Decoder Overview
2-3
Figure 2-3
Interchange Format
2-4
Figure 2-4
JPEG
2-5
Figure 2-5
DPCM Model for
Figure 2-6
Example Quantization
2-15
Figure 2-7
Zig Zag Ordering
2-17
Figure 2-8
Encoding Flow
2-18
Figure 2-9
Decoding Flow
2-19
of Design
Test Flow
hierarchy
2-8
Encoding
Figure 2-10 Typical Compressed Image Data Format
2-20
Figure 2-11 A Decoder Circuit
2-22
Figure 2-12 Example VHDL Circuit
2-22
Figure 2-13 Example VHDL Behavioral Model
2-23
Figure 2-14 Example VHDL Structural Model
2-24
Figure 3-1
VHDL Test Bench
3-2
Figure 3-2
VHDL Test Bench Basic Structure
3-4
Figure 3-3
Control Signals Example Schematic
3-5
Figure 3-4
Example Control Signals
3-7
Timing
VI
Figure 3-5
Major Components
Figure 3-6
Layout
Figure 3-7
Controller Symbol
3-10
Figure 3-8
NextByte Symbol
3-15
Figure 3-9
NextByte Espresso Input
3-17
of Decoder
of Decoder
Module
VHDL Source Code
3-8
3-9
Figure 3-10 NextByte Espresso Output File
3-18
Figure 3-11 VHDL Source Code From Espresso Output
3-19
Figure 3-12 ISR Symbol
3-19
Figure 3-13 FindSOI Symbol
3-21
Figure 3-14 Example Wired Or Schematic
3-22
Figure 3-15 FindSOF Symbol
3-23
Figure 3-16 Frame Header Syntax
3-24
Figure 3-17 FrHeader Symbol
3-25
Figure 3-18 FindEOI Symbol
3-27
Figure 3-19 dec_frame
symbol
3-28
Figure 3-20 Find_SOS
symbol
3-29
Figure 3-21 Decode_Scan Symbol

Figure 3-22
Differing Uses
of else
3-30
Clause
3-32
Figure 3-23 Example VHDL Direct Coded State Machine
3-33
Figure 3-33 dec_scan_header Symbol
3-34
Figure 3-25 Compute_MCUs Symbol
3-35
Figure 3-26 Example Pipelined
Figure 3-27 Scan
and
Non-pipelined Systems
Decoding Modules
3-36
3-37
vn
Figure 3-28 load_coeff Symbol
3-38
Figure 3-29 dequantcoeff Symbol
3-39
Figure 3-30 idct_coeff Symbol
3-40
Figure 3-31
unloadcoeff
3-40
Figure 3-32
mem64x8
Figure 4-1
Decoding Timing Diagram
4-2
Figure 4-2
Decoding Timing Diagram, Expanded
4-3
Figure 4-3
Test
Figure 4-4
Test Image
Figure 4-5
Independent JPEG
Group
Software Decompression Result
Figure 4-6
Independent JPEG
Group
Software Decompression Result, Values
Figure 4-7
XV Decompression
Result, Image
4-11
Figure 4-8
XV Decompression
Result, Values
4-11
Figure 4-9
XV Decompression
Result,
Symbol
3-41
Symbol
Image-
4-9
Original
Original,
4-9
Values
Difference Tables
4-10
...
10
4-11
Figure 4-10 Dec.c Decompression Result, Image
4-12
Figure 4-11 Dec.c Decompression Result, Values
4-12
Figure 4-12 Dec.c Decompression Result, Difference Tables
4-12
Figure 4-13 VHDL Decompression Result, Image
4-13
Figure 4-14 VHDL Decompression Result, Values
4-13
Figure 4-15 VHDL Decompression
Result,
Difference Tables
4-13
Figure 4-16 Controller Symbol
4-14
Figure 4-17 Controller Schematic
4-15
vm
Figure 4-18 Controller with I/O Pads
4-16
Figure 4-19 Controller Layout
4-18
Figure 5-1
5-3
Two Types
of
Buffering in Pipelines
IX
LIST OF TABLES
Table 1-1
Examples
Table 1-2
Advantages
Table 1-3
Functionality ofPrograms
Table 2-1
Levels
Table 2-2
SSSS Values for DC coding
2-9
Table 2-3
Additional bits for DC
2-9
Table 2-4
Example DC Huffman coding
2-10
Table 2-5
SSSS Symbols for AC Huffman coding
2-11
Table 2-6
Example AC Huffman coding
2-11
Table 2-7
JPEG Markers
2-21
Table 3-1
VHDL Test Bench Modules
3-3
Table 3-2
VHDL Test Bench
Table 3-3
Controller Signals
3-11
Table 3-4
Work Request Codes
3-11
Table 3-5
NextByte Signals
3-15
Table 3-6
NextByte State Table
3-16
Table 3-7
ISR Signal Definitions
3-20
Table 3-8
ISR Codes
3-20
Table 3-9
FindSOI Signal Defintions
3-21
Table 3-10
FindSOF Signal Definitions
3-24
1-5
of Compression
and
of JPEG
Disadvantages
of
Differing Implementations
1-11
2-5
implementation
and
1-8
AC coding
Interconnecting
Signals
3-3
Table 3-11
Frame Header Descriptors
3-25
Table 3-12
FrHeader Signal Defintions
3-26
Table 3-13
dec frame Interface Defintions
3-28
Table 3-14
FindSOS Signal Defintions
3-29
Table 3-15
Decode_Scan Signal Defintions
3-31
XI
GLOSSARY OF TERMS
ASIC
Application Specific Integrated Circuit
bit
A binary digit
chrominance
The difference between
a color and a reference white at the same
luminance.
CMY
Cyan, Magenta,
CMYK
Cyan, Magenta, Yellow and blacK:
CODEC
Combined
continuous tone
An image
DCT
Discrete Cosine Transform
DIS
Draft International Standard
DPCM
Differential Pulsed Code Modulation
DOD
Department Of Defense
DSP
Digital Signal
EDIF
Electronic Design Interchange Format
GJF
Graphics Interchange Format
IEEE
Institute
JPEG
Joint Photographic Experts
luminance
Provides
relative,
pixel
and
Yellow:
encoder and
have
whose components
used
in
a subtractive color
device
more than one
bit
per sample
Processing
of Electrical and
Electronics Engineers
Group
a grayscale version of an
amount of light
array
device
a subtractive color
decoder
from
Picture Element. Sample in

of an
in
used
image. The absolute,
each
primary
digital image. A digital image is
of pixels.
Blue:
RGB
Red, Green,
RTL
Register Transfer Language
and
used
xn
rather
in
than
color source.
an additive color
device
made
up
VHDL
VHSIC Hardware Description Language
VHSIC
Very High Speed
VLSI
Very Large
YCbCr
color
transformation,
related to
YUV
YIQ
color
transformation,
related to
YUV
YUV
color
transformation, Y is
Integrated Circuits
Scale Integration
chrominance.
xm
the
luminance,
and
U, V make up the
1. Introduction
1.1
Overview
This thesis is divided into 5 chapters,
plus appendices.
Chapter
introduction to images, the JPEG (Joint Photographic Experts Group)

compression
standard
Description Language). A
decompressing images,
implementation
of
VHDL
and
(Very
in depth
more
is found in
chapter
high
coverage
of
still
brief
image
Hardware
circuits
especially relating to
JPEG,
two. Chapter three covers the design and
the JPEG decoder in VHDL. The
the decoder are described in chapter four. The last
for future work,
integrated
speed
is
one
results
chapter
from the implementation
of
is conclusions, containing ideas
learned from this thesis.
and reflections of lessons
1.2 Images
What is
definition
likeness
an
of an
an
image? Webster's Third New International
image
as
"a thing actually
[Web86]. When
most
would
refer
to
traditional
the
processes to store representations of an
use of
taken
as
one
any
photographic-material"
image,
needed,
seemingly reproducing another,
of an object produced on
photographic paper or a color negative.
the
or
Dictionary has
by
analog
circuits
brief discussion
creating
associated
Traditional photography
image. This
To
method of
why digital
in
electronics.
of
traditional photographs
a negative of
picture, the image is
image
relate
is
used.
1-1
with
still
think
piece
of
of
relies upon chemical
image
similar
to
compression
is
A traditional
image
storing images is
the image on filmbase called a
enlarged and printed as a positive
people
photograph
"negative"
To
is
view a
on photographic paper.
If
the image is enlarged too much, the picture
be thought
of as a compressed
image
distorted due to the negative,

opposite case
from
the compressing
in depth
of
digital
of
different
exist
cameras.
With the
seen
the loss
the human
and
and
storing images has
methods.
facsimile
in
section
of
data
not
This is the
1.3. With digital
images, it is
For
and picture quality.
system
visual
another
Some digital images

These
machines.
refer
form. Another
in the
methods of using
digital images that
method
compression scheme was
The basic
needed,
element of a
digital image. Pixels
can
be
a more
to Digital Image
facsimile
A Bi-level
image,
image
have typically 8-bits
such as a
differing
will
per pixel.
1-2
be
capturing,
created
number of
was
copies of
To
precision
pixel
is the
and
more precise
images
number
the size
understand
why
smallest sample
of
digital image is
depending upon the

per pixel.
use of
digital format.
increase in the
of what comprises a
a pixel.
digital images
developed.
by
the use of scanners,
only in
comes an
only have 1 bit

For
can
essentially creating
created and exists
digital image is
by
of
for creating digital images is the
brief discussion
samples of
are created
digital images
scheme
compression
Digital images
methods are
With this method, the image is
expansion
will
in
is
picture.
enlarging the
expanded.
digital images. It is due to the increase in the
required.
the image quality
the electronic information age, the methods
advent of
copiers or
images that
be
as will
causes
a result of
But,
negative can
1 to 4 [Pra91].
displaying
a number of
it is
blurry. The
Imaging
With the
transferring,
image,
images
of
chapters
1.3 Digital
digital
and
of the enlarged picture.
rather
the image that
coverage
Processing
digital
be distorted
will
in
application.
monochrome still
such as
digitized
X-
bits
additional
rays,
Color
be
can
number of
per pixel are used.
by
represented
(Cyan, Magenta, Yellow),

level,
U,V
related to
V),
to U and V). To
and
JPEG
color per
standard
previously
pixels
space.
disk
not
of
film,
Storing
space.
very
is readily
specify the
the
image
24 images
method
cost effective.
apparent
display
are needed.
to
The
level,
of
method
requires
this
used.
RGB
Since
data from
image
each pixel
It
made
be
images;
up
of
levels
related
the
for the red,
have 8-bits
noted
any
640
is 3 bytes (1 byte
of space
levels
elements
should
color
luminance
each part of
will
to be stored.
22,118,400 (approx. 22
CMY
chrominance
chrominance
image, data
into
that the
one of
pixels
per
by
8-bits,
the
480
each
Relating
this
MB) bytes
of
film"
would
problem
other method
that some means
Cb,Cr
each pixel.
color
size would need
this
level, I,Q
for representing
color value
YUV (Y
A typical RGB image
for
per pixel.
(Red, Green, Blue),
pixel needs
921,600 bytes
"digital
avoid
are needed
may be
multiple rolls of
One
luminance
of 307,200 pixels.
total
8-bits),
color needs
to a roll
not
mentioned methods
requires a
For example, to
pixel, thus 24-bits
does
RGB
luminance
image in color, every
blue primary levels
green and
examples are
levels), YIQ (Y
an
the
(Cyan, Magenta, Yellow, blacK),
YCbCr (Y
display
color representation.
primary
CMYK
chrominance
and
Some
bits
addition of color adds more
a number of methods which separate
color values.
primary
The
is to
is
quickly
use most computer systems
to purchase more
compress
of compression
is
the
disk space, but that is
images. With this
example
it
needed.
1.4 JPEG
JPEG
international
stands
for Joint Photographic Experts Group. JPEG was formed to
standard
for
a compression technique
1-3
for
create an
color and grayscale continuous
tone
still
images. The
Level standard,
should
be
fill
standard was to
JBIG,
noted that
gap in
the future digital
and
JPEG is designed for
will not perform well on non-continuous
further introduction
For
on
in depth
a more
JPEG
refer
coverage of
images
tone
to references
JPEG,
of the
JPEG standard,
An
125
125
pixel grayscale
bits
number of
bytes. A
visual example of
1-1. Picture A is the
was noted
image
original
format found
well,
and can
reduce
This
the
can
for those
who are
per
pixel, the
for images C
be
seen
by
is
uncompressed
shown
image
file
using
would
the image
store
size
image. Table 1-1
and
and
image E
shows
is 15,722
workstation
was
the file size
display,
8-bits
image
today. Its drawbacks are that
per pixel.
data, but
comparing the
Note, for
will
small
of each
very
images,
it does
the GJF
a popular
not compress
format
will not
take up more space than the original
sizes of
slight
very distorted. Picture F is the
in Graphics Interchange Format (GIF). GIF format is
use
amount of
standard.
capable of
involved to
draft copy
the effects of data compression on an image is shown in figure
on computer systems
only
This book
also contains a
the number of colors, the actual
original uncompressed
saved
[Wal92].
and
recommended.
that JPEG is
It
Joan Mitchell's book
implementing this
some additional overhead
per pixel and
and
It
of users.
the amount of compression done. On a
and
distortion
levels
image. With 8-bits
bytes. With
storage
size, the
image
useful
all
photographs.
Bi-level images. For
such as
[Pen93] is
Bi-
MPEG. It
standard
like those in
William Pennebaker
for
between the
[Leg91], [Mit91], [Mit92],
example of the amount of compression
15,625
need
is
which
much
images,
JPEG Still Image Data Compression Standard

contains an excellent overview of JPEG
compression
motion
still
techniques
compression
image.
image A to image F in table 1-1. For larger
1-4
images,
GIF
image will
will compress
still
take up
the amount of data used to a size
more space than a
less
than the original. A GIF
JPEG compressed image.
Figure
File Size fbytes^
A CoriginaD
15722
3676
C
D
3225
77
79
2041
87
1006
94
18158
Table 1-1 Examples
of compression
Picture A
Picture B
Picture C
Picture D
Picture E
Picture F
Figure 1-1 Example
compressed
1-5
images
Compression
0
(%)
1.5 Types
of
JPEG implementations
Various factors
Factors include cost,
changes
and
speed of
design
other
discussed in this section,

popular method
be found
is the
which offers
in
Another
has
also
Three
for
on
that it
A downside to
are compressed or
for
implement the JPEG
how to
can
low
be easily
cost
implementing
[Ram93] for
obtain
and
project,
processing tasks. It
standard,
is
an
sets.
An
example
a mix of a
provided
should
they only provide
be
it
and
method can
can
digital
and manipulate
Refer to
be
can
used
Group,
page
Implementing
quickly created, it
the JPEG still
to
such
hardware
noted
allow
image
example of such a
of a
280
JPEG in
be easily
across
many
slow speed
of
DSP is the DSP96002
The DSP chip
image processing functions.
designer to implement
complex
directly implement
a set of hardware/software tools that can
1-6
use
DSP implementation. A DSP
used
that DSPs do not
is the
standard
and a software solution.
is designed specifically to implement commonly

software
This
Independent JPEG
this software.
One
use are noted.
standard.
are
decompressed.
Refer to
Specialized
by the
making
JPEG
implementing
display
that
systems.
ease of
implementing the project in software is the
processor.
implementation is
of
non-commercial and commercial use.
information
method
implementation,
methods
been implemented
image processing DSP chip
set
ease of
is implemented in
the factors that drive their
to
specialized
processor
standard
commercial software programs
features, it is
computer platforms.
images
use of software
advantages
updated with new
at which
and some of
software
more
has the
processing needed,
considerations.
standard
free C
for
[Pen93]
software
in
embedded
images. The JPEG
determine how the JPEG
will
be
used
to
image
the JPEG
implement
the standard.
Also
speeds.
and
making
Advantages
one
implementation is
not
The last
The
occupy
be
DSP
as viable as a
method of
are
The disadvantages
This may
processor.
total
implementing
standard can
less
not
is
be found in [Jai92],
focus
creating
disadvantage, if
the
concern, the DSP
a major
speed.
The
VLSI integrated
the
and
second advantage
or a computer
factors that
hardware design.
a pure
[Leo91], [Oga92],
DSP set,
are some of
is
a single
that a VLSI design is harder to implement
space and market
be
ease of
implementation is
are that the
the JPEG standard
be implemented into
space than a
compression/decompression
hardware implementation.
VLSI implementation is
much
disadvantages
speed,
specific
faster
is implemented using software, the
also an advantage.
examples of this can
advantage of a
will
solution are much
to be embedded into a product. If space
JPEG
complete
Some
is
changes
may
DSP
since the actual standard
limited only to
solution
of a
circuit.
[Rue93]. The
is
size.
main
single
chip
that runs software. The
and
will
to make changes.
determine
Cost,
which of
the
three methods are chosen to implement the standard. Another factor is how much of the
standard
portion,
is to be implemented. Requirements may

such as
just the decoder. Table 1-2
call
outlines
each method.
1-7
for the
complete
standard,
the advantages and
or
only
disadvantages
of
Need
Software
DSP
Hardware
Cost
low
medium
high
Speed
slow
fast
fastest
Ease
of
complex
requires
medium,
easy
implementation
knowledge
of
specialized software
Ease to
easy, but
change
must
be
easy, but
distributed
Cross Platform
Yes
Size
No,
large
Table 1-2 Advantages
Disadvantages
and
requires
complex,
distribution
specific to
only
No,
requires
device
new
specific to
only
that DSP set
that VLSI chip
medium
small
of
Differing Implementations
1.6 VHDL
VHDL
stands
for VHSIC Hardware Description Language,
Very
High Speed Integrated Circuits. VHDL is
such
as
or
specifically be
have
one
different
language
FORTRAN,
used
except
that it
was
some
to design digital circuits. VHDL is
hardware description language for

vendors
has
to
be
able
use
like
much
VHSIC meaning
typical software
concurrent
a result of a
by vendors.
with
One
constructs
DOD
common
language,
that
can
requirement to
language
allows
to share and connect designs. Due to increased needs, the
transferred to the IEEE for standardization. Since then
the latest
numerous reviews and changes and
official version
it has
undergone
has been documented in the
VHDL 1993 Language Reference Manual.
"Why
function?"
is
use
VHDL
when
current
a question often asked.
One
schematic
reason
1-8
capture
programs
do the
same
to use VHDL over traditional schematic
capture
is that VHDL is
a recognized
No
companies and vendors.
source code should
fact comply
circuit
with
diagram
be
the IEEE VHDL standard. This is
often can not
Format (EDIF). Another
be
similar
is the
structural
model,
schematic
abstraction,
each
from high
model
is
abstraction and
layouts
the
model
[Bha92]
[Leu89] incorporate the
models
can
design
and
is
not
vendor
"C"
or
be
synthesized.
without
[Coe89]
cycle of an
circuit.
Thus
an
having
of
and
the design that is very
of
data in
model
design in
of abstraction
design. This is
concurrent.
much
Events
can
is the
like
occur
From the lower levels
ASIC
to
to a low level for
Pascal. The data flow
the flow
in
than
behavioral, data flow
sequential, but
they do in
as
designed using VHDL
references
does in
different levels
can model
a sequential model of
it
easier
level, for behavioral,
a model of a set of interconnects
level,
is
type format. The lowest level
(RTL)
other, just
circuits and
simulated and
VHDL
is
layout. At this
concurrently to
on
which
using different
parties
models of abstraction are
of abstraction goes
Register Transfer Language
compiler
not so with schematic capture.
is that VHDL
additional reason
level down in
that the
source code
to a high level programming language such as
next
between
interchanged using the Electronic Design Interchange
is that changing the
the structural model. A behavioral
exchanged
VHDL compiler, the VHDL
assumes
between two
exchanged
design. The different
The level
structural.
reason
diagrams. An
abstraction of a
Note this
acceptable and usable.
be
and thus can
matter what vendor creates a
schematic capture software unless
edit circuit
IEEE standard,
of
be entirely written,
the need for schematics. For further reading
are recommended.
ASIC
1-9
with
VHDL.
References
[Hub91]
and
1.7 Design Brief

This design
of
the JPEG
decoder. The behavioral
do the behavioral
this thesis
was accomplished
model over
was started.
baseline decoder. This

only does
grayscale
in the design
design
of
the
model was
VHDL due to
Appendix C
program
parts.
contains
implements
structural model.
The first
part was a
done in C. AC
a change
in the
color
Figure 1-2
images,
computer systems at
whereas
model would
to
the time
the design in VHDL
be done in VHDL, to
shows an overview of
compare
results
1
ong.pgm
displ.pgm
vhdl.pgm
Figure 1-2 Overview
model
program was chosen
decoding JPEG compressed images.
difference
behavioral
the C program dec.c that implements the
images. Ideally the behavioral
model simulates
ong-JPg
in two
of design
1-10
test flow
help
how the VHDL
Table 1-3 defines the
functionality of each block in the
above
Block
figure.
Definition
Original,
on
&JEE.
Converts the
conv
textio
raw
raw
data JPEG
JPEG file into
functions
available
ASCII JPEG file that
vhdl.dat
VHDL test bench
will
an
ASCII file. This is due to the
in VHDL
be
Simulation
in
read
Converts the
display
output
which
from blocks
of
only
read
ASCII.
by the VHDL test bench
of VHDL
Output from VHDL
vhdl.pg:;m
image
compressed grayscale
design.
simulator
8x8 to line
by line for proper
display
ong.pgm
original uncompressed
Compares
compare
results
notes
any
original
pixel
XV
1.8 Software
was
Quicksim
and
to
it
II,
of time and
Bradley was
The tools
and
was used
disk
used on
space.
used
by +/-
entire
the HP
software tools on
package were:
contains
HP
Design
System 1076
the VHDL source code. Quicksim U is the digital
to simulate the
To
from the Mentor
Autologic. Design Architecture
write and compile
using the Autologic tool. The
lack
original
Functionality of programs
designed using Mentor Graphics Corporation
series workstations.
which was used
simulator,
that differs from the
image
used
This thesis
Architecture,
uncompressed
Display program
Table 1-3
9000/700
image to the
image
design
design. The design
was not synthesized
was
partially
synthesized
due to its large size,
and a
display the decompressed images the XV program by John
workstations.
This thesis
6.0.
1-11
was written
using Microsoft Word
2. Concepts
This
chapter
what comprises
section of
Also the
If any discrepancies
correct source.
methods
The first
is
a condensed overview of
in
presented
Joan Mitchell is
and
actual standard
some
detail in the first
second part of
highly
recommended
for
a more in-
is very useful in understanding how JPEG works.
between this thesis
are noted
The
part
the book JPEG Still Image Data Compression Standard
Again,
William Pennebaker
coverage.
parts.
this thesis. The JPEG decoder is
this chapter.
[Pen93] by
depth
is divided into two
and
this chapter is
for modeling designs in VHDL. Behavioral
is the
the standard, the standard
a short
introduction to two
and structural
modeling
of
the
examples are
given and contrasted.
2.1 JPEG
2.1.1 JPEG Brief
There
are
are
three
decoder
the encoder, the
compresses
images,
major parts
and
to the JPEG
the decoder takes
are
decoder designed
discussed in
The
JPEG,
some
encoder's
and compress
compression scheme.
by
any
detail in the
a compressed
are passed
Lossy
compression standard.
image
along
and expands
with
it for
They
the compressed
viewing.
image that
party to decompress that image. The three
second
parts
following three paragraphs.
function is to take
it into
image
the interchange format. The encoder is the part that
The interchange format is the data that
allows a
still
smaller
refers
a raw
size.
image,
whose
format is
The JPEG baseline
to the fact that data will be
2-1
not specified
encoder uses
lost
when
by
lossy
the image is
This is usually
compressed.
will
be
some
Users
can
values
in
data
trade
loss,
off
not a problem with still
but the image quality
source
grayscale
or
it
per pixel are used.
Huffman tables
image
set
being
into the
encoder
is
can
little
and
other
encoder.
or
they
can
JPEG does
the compressed
to the encoder
be
to
by
obtain
can
be
modifying
as
much
quality.
encoder are
can
the
be just
baseline encoder, only 8-bits
is table specifications,
a set of standard
JPEG There
digital image data
data. In
tables. These tables
and quantization
compressed,
planes of color
input
JPEG, is
the encoder. The inputs to the
table specifications. The
be different
The
of
of
loss in visual image
or no perceptible
basic layout
shows a
image data
data,
by
the same to the viewer's eye.
will remain
table". The major purpose
compression as possible with
digital
compressed
the the amount of compression against degredation
'quantization
Figure 2-1
images
optimized
which are
from the
the
current
(hard coded) tables permanently
not require which method
is
used.
The
output of
the
image data.
7|
Encoder
Compressed Image Data
7Tn
Source Image Data
Table Specifications
Figure 2-1 Encoder
The decoder is the
compressed
image data
second major part of
and
structure of the uncompressed
uncompresses
image data is
the JPEG standard. The decoder takes
that data in some usable form.
not
2-2
dependent
upon
The final
the JPEG standard. The
input
to the
decoder is
specifications, Huffman
a system
present
would
and
quantization, may be
that has advance knowledge
in the
be
image data. From the
compressed
compressed
a system
Figure 2-2
data, but
of
will
obtained.
the contents
already be
of
shows the
layout
of the
data the table
Note, if the decoder is

these
available
that transits image data from point to
compressed
tables, they
need not
in the decoder. An
point
that is built
by
part of
be
example
one vendor.
JPEG decoder.
Compressed Image Data
Decoder
Reconstructed
Image Data
Table Specifications
Figure 2-2 Decoder

The third
major portion
interchange format is the

encoding
image
and
decoding
can cross
environment
the
of an
is
data
and all other associated
image. The interchange format

between
associates
shows an example of what
the JPEG standard is the interchange
compressed
boundary
internally
of
application
tables
meant
regardless of
how
each
images [IS093 J. Figure 2-3
by the interchange format.
2-3
data involved in the
guarantees that a compressed
environments,
with compressed
format. The
Application Environment A
Compressed
Data, included tables
specs.
Application Environment B
Figure 2-3 Interchange format

There
contains all
format for
tables
at
three types
information
compressed
used
known
are
by
the
needed
to decode
decoder. This
would
an
image. The
be
used
in
interchange format
type is
second
format does
abbreviated
of
an abbreviated
not need
applications where
to include
all
the tables were
the decoder beforehand. The third type of interchange format is abbreviated
specification
the
data. This
be
interchange format. The first type
image data. The
format for table

compressed
images
of
would not
of the second
There
data. With this
would
be
used
format,
to set up the
have to carry the table data (Note:
all
decoder,
so
are contained
that the
images using this
in
following
method would
type of interchange format).
are
four different levels
at which the
JPEG
The first is the baseline level. All encoders, decoders
implement this lowest level. The
(DCT) based,
only the table data
lossless
and
other
and codecs except
three levels are extended
hierarchical. Figure 2-4
2-4
be implemented.
standard can
shows
the
discrete
the
lossless,
cosine
hierarchy
of
must
transform
the JPEG
Table 2-1 lists the four levels
standard.
of
implementation,
the
and
major
differences
between them.
\ Prnarpssi ve
Sequential DCT
DCT
Sequential
Baseline
Lossless
\/
Hierarchical
Figure 2-4 JPEG hierarchy

Baseline
sequential
DCT
based
DCT based
8-bits
process
per pixel
Sequential coding
Huffman coding, 2 AC tables and 2 DC tables
Decoders shall process scans with 1,2,3 and 4
Extended DCT based
process
Interleaved
and non-interleaved scans
DCT based
process
per pixel
or
12-bits
Sequential
Huffman
or progressive
or arithmetic
Decoders
processing
coding, 4 AC and 4 DC tables
shall process scans with
Interleaved
Lossless
components
1,2,3
and
components
components
Predictive process, not DCT based

2 to 16 bits per pixel
Sequential processing
Huffman
or arithmetic
Decoders
4 DC tables
Interleaved
Hierarchical
coding
Multiple frames (non-differential

Uses
extended
Decoders
Table 2-1 Levels
DCT based
or
and
and
differential)
lossless
Interleaved
1,2,3
1,2,3
of JPEG
2-5
implementation
process
and
components
The
detail
on
following
is
the other three
DCT based:
list
term used to define the baseline system. For more
of each
levels
to the standard.
refer
Encoders
decoders
and
Refer to
cosine transform.
the
8-bits
per pixel:
sequential coding:
For
discrete
each
Image is
cosine
coded
This is done
all
Huffman
coding:
progressively
in
or
components:
2. 1.3 for
An image
the use of the discrete
2.1.2 for
information
more
on
are used
The
better;
other method
much
one
8 blocks.
is progressive,
which
like
focusing
lens.
to code the coefficients. Refer to
information
have
by
the picture quality starts out very low
not used
more
can
component
upon
left to the lower right in 8
which
gets
Arithmetic coding is
section
1,2,3,
upper
one scan.
uses multiple scans
and
section
bits only
from
in
based
transform.
eight
scan,
are
on
Huffman
coding.
to four components. Examples are 1
for grayscale, 3 for RGB
and
components
for
CMYK.
interleaved
or non-interleaved:
For
color
images
only.
An interleaved
scan
is
one where
the components are intercoded into the compressed data.
An
example would
green and
(each
set
then a 8x8
code a
blue. As
has the three primary
decoded that
color.
be to
part of
With
2-6
the
image
non-interleaved,
8x8
red
unit, then
each set
color
can
of
8x8
8x8 blocks
components)
are
be displayed in full
each
color
is
coded
separately in the
finally the blue.

displayed
will
All
scan.
of the red
When this
look
not
method
correct
is
done,
the green and
is decoded, the image
until
the final color
is
decoded.
2.1.2 Huffman
This
standard.
Coding
section explains
For
a complete
Huffman coding is
transformed
by
decorrelated,
correlation
the discrete
thus
between
modulation
AC
in
theory
of
in the JPEG image
Huffman coding,
(DPCM)
model.
be 'bompressed
The DC
A DPCM
independently
without
coefficients are coded
coefficient
model
is
is
one
coded
in
the runs
of zeros
advantage.
2-7
using
which
its difference from the last DC
which uses
refer
it has been
after
compression
to
[Huf62].
quantized and
transform. Once the data has been transformed it is
[Pen93]. The
coefficients.
manner
the
the compressed data
cosine
can
on
used
coefficients"
coded with respect to
coded
background
performed on
and
coefficient and
how Huffman coding is
concern
about
in two parts, the DC
differential
pulse code
the current DC coefficient is
coefficient.
created
by
AC
coefficients
zigzag ordering to
are
an
DC coding is done
by
following
using the
steps.
A step
by
step
example
is
included.
1. Find difference: DIFF
DC
value
value
to
is
also called
zero.
Current DC
the
Figure 2-5
value
value.
The Last
(PRED). Initialize last DC
predictor value
shows a
Last DC
diagram
of
the DPCM
model
encoding.
Figure 2-5 DPCM Model for
Example, Step
Current DC
PRED
Diff
2. Look up SSSS (SSSS is
SSSS according to the
(Initial
value of the
2-8
Value)
-8
variable) code,
Example, Step 2
SSSS
Encoding
see
table 2-2 below. Select
DPCM difference.
for
3. Select
and a
additional
leading 0
bits. Note:
means
the
leading
difference is
means
the difference is positive,
negative.
See table 2-3
Example, Step 3
Additional Bits
0111
SSSS
DPCM difference
-1,1
-3,-2,2,3
-7,...,-4,4,...,7
-15,...,-8,8,...,15
-31,...-16,16,...,31
-63,.
..,-32,32,.
-127,..
.,-64,64,.
..63
..,127
-255,.
..,-128,128,.
..,255
-511,.
..,-256,256,.
..,511
10
-1023,.
11
-2047,.
Table 2-2 SSSS
values
..,-512,512,.. .,1023
..,-1024,1024,. ..,2047
for DC coding
SSSS
DPCM Difference
-1,1
0,1
-3,-2,2,3
00,01,10,11
-7,...,-4,4,...,7
-15,...,-8,8,...,15
-31,...-16,16,...,31
-63,.
-127,.
..,-32,32,.
..,-64,64,..
000,.
0000,.
00000,.
oooooo,.
..63
0000000,.
.,127
-255,.
..,255
..,-128,128,.
-511,.
..,-256,256,.
..,511
..,-512,512,.
..,1023
10
11
-1023,.
-2047,. ..,-1024,
(binary)
Additional bits
1024,.
..,2047
00000000,.
000000000,.
0000000000,.
..,011,100,.
..,111
..,0111,1000,.
..,1111
..,01111,10000,. ..,11111
..,011111,100000,.
,.,n
mi
..,0111111,1000000,.. .,1111111
..,01111111,10000000,..
.,11111111
..,011111111,100000000,.
..,111111111
..,0111111111,1000000000,.
..,1111111111
ooooooooooo,...,oiiiiiiiii 1,10000000000,.
Table 2-3
additional
2-9
bits for DC
and
AC coding
..,1111111
mi
4. Concatenate the
binary
This becomes the

will
vary for
each
value of
code used
SSSS
for the DC
the
and
additional
coefficient.
The
bits together.
size of the code
DPCM difference.
Example, Step 4
code
(binary)
Table 2-4 illustrates

coefficients.
1000111
Note,
an
the
example
first
Huffman
of
is from the
column
of
coding
DC
example used
previously.
Quantized DC
PRED
-6
-8
-3
-6
-8
-3
-8
-1
-14
-2
0111
0001
00
101
110
1000111
11
10
100001
1000
11101
11110
value
value
DPCM difference
SSSS
Additional bits
code
(binary)
Table 2-4 Example DC Huffman coding
AC Huffman coding is
1
accomplished
by using the following
Calculate RRRR. RRRR is the
before
a non-zero coefficient.
coded as
buffer is
(end
of
number of
If there
using the ZRL (zero
run
are
repeating
16
length)
steps:
zeros
symbol.
reached and no non-zero coefficients are
buffer)
code
is
used.
2-10
in
zeros
row,
If the
in
a row
they
are
end of the
reached, the EOB
2. Calculate SSSS. SSSS is derived from the
determining RRRR.
Use table 2-5 to
non-zero number reached when
SSSS.
calculate
SSSS
non-zero coefficient value
-1,1
-3,-2,2,3
-7,...,-4,4,...,7
-15
15
-8,8
-31,...-16,16,...,31
-63,..
-127,..
-255,.
-511,
10
.,-64,64,.
..,127
..,-128,128,.
..,255
...,-256,256,.. .,511
-1023,.
11
.,-32,32,. ..63
..,-512,512,..
-2047,. ..,-1024,
.,1023
1024,.
..,2047
Table 2-5 SSSS Symbols for AC Huffman coding

3. Calculate RUN-SIZE. RUN-SIZE is
4. Add
on additional
value
in the
of 0001
code
the
RUN- SIZE symbol.
determine the
bits
bits to
additional
equal
to
(16xRRRR)
SSSS.
sign and magnitude of
Use the
non-zero value and
bits. For example,
(see table 2-3: for SSSS
the non-zero
4,
-15
-14
table 2-3 to
would need additional
is 0000,
-14
is 0001
and
8 is 0111).
See
appendix
F1.2 in the draft international
how Huffman coding for the JPEG
[Pen93]
which
is
an example of AC
standard
is
standard
Huffman
[IS093]
accomplished.
for
specific
information
on
Shown below is table 2-6
coding.
Zigzag index
10
11
AC descriptor
-14
!<-
2->|
|<-
RRRR
SSSS
RUN-SIZE
Additional bits
Huffman
code
->|
|<-
EOB
0
0
68
33
0001
10001000001
1000011
Table 2-6 Example AC Huffman

2-11
Coding
63
0
~
_>|
2.1.3 Discrete Cosine Transform
The two dimensional discrete

that allows compression to be
cosine
in the JPEG
possible
actually do any compression, but it transforms

compression can
be done. For
book Discrete Cosine Transform

chapter
of Pennebaker and
in-depth
an
is
transform
one of
into
coefficients
P.
Yip is
[Rao90] by
K.R. Rao
and
Mitchell's book
[Pen93] is
a good source
'
1
Cu Cv
J,
>
>
^-i^-L
format
the discrete cosine
to the transform The 2-D forward discrete cosine transform
Suv
major components
The transform does
standard.
coverage of
the
l)n
used
that
so
the
transform,
Also
recommended.
for
not
an
introduction
by JPEG is defined by
+
_(2y
l)vn
COS
Syx COS
16
16
x=0y=0
where
û an<^ ^v
~T=
for u>
^' ^"' Cv
otherwise
v/2
One
of
the properties
two dimensional DCT is that it
of
can
be broken down into
two 1 -dimensional transforms. The one dimensional transform that applies to JPEG
defined
as :
Su
J^,
C>
This thesis
were
is
to be
Another
constructed
option
is to
in
VLSI,
transform, if implemented
computational
power
approach
as
to
model
then the most
use a commercial
defined,
l)uU
16
n
x=0
the two 1-D DCT
uses
(2x
SxCOS-
the Inverse DCT. If an actual design
appropriate
DCT
method would
be
used.
chip that is designed for the DCT. The DCT

would
to implement. Thus
require
simplification
2-12
large
exists
amount
of
time
for the discrete
and
cosine
transform to reduce the time to
perform.
the number of multiplications
and/or
Most
multiplications and
[Fei92] has
number
reduced the
Other
arithmetic shifts.
DCT. Different implementations

A
platform
technique
that
do fast
can
which reduces
2.2 A JPEG
description
of
but
1-D
to 54
method
approaches
developed
464
with
(FFT)
additions
by Feig
and
to implement the
to speed up the transform.
slow multiplications should use an algorithmic
number of multiplications.
encoder and
coverage of
additions.
different
to reduce
the DCT using separable
the fast fourier transform
will use
additions
encoder and
The JPEG
step-by-step
the
896
of multiplications
methods use
simplifications attempt
Doing
additions.
transforms results in 1,024
these
of
decoder
decoder
are covered
how the JPEG
its functions. Take
section.
The
functions. Each step
encoder
note of where
in this
the
actual
data loss
following is
contains a
brief
and compression
occur.
1. Level
For
shift
an
to a signed representation. For P
8 bit mode, the level
unsigned
8 bit
127). This step
2. Image
number
can
shift
(0 to
be done
unit
that
is
255)
and create a signed
as part of step
called the
from
each pixel
system
8 bit
this
will
number
2^-1.
take an
(-128 to
2.
into 8x8 blocks. A 8x8 block
of pixels
is
compressed.
3. Each block is transformed

64 values,
subtract
is 128. For the baseline
component samples are grouped
the basic data
bits,
by the forward
DCT
coefficients.
2-13
discrete
One
cosine transform
coefficient
(upper
(FDCT)
left)
into
is the DC
coefficient, the
at
original
loss due to rounding

purpose
of
frequency points.
eliminate some
is to
The
highly
points without
For
input
of
11 -bit two's
8-bit
(note
upper
left
of
group
no
a slight
are
corner are
data
other
(FDCT)
data
used
the higher
able
the JPEG
the FDCT transform
12-bit inputs
require
to
The
points.
by
and
the lower
data is to be
the
(baseline)
output.
may be
corner
lower right
cosine transform
complement
is
were performed
: there
correlated
adversely affecting
precision
there
point operations with cosines).
decorrelating
of
purpose
standard.
an
floating
coefficients towards the
is the forward discrete
require
recovered
towards the
following
an
of
take a
coefficients
data
be
would
Note,
standard.
for
algorithm
specific
If an inverse transform
step.
accuracy
the JPEG
by
specified
data
and
The
points.
the AC coefficients. No
from this
this step
decorrelate it. The
frequency
are
is
or compression
this point, the
The
63
the DCT
implementing
data loss
other
will
15 -bit
an
output.
FDCT
Suv
ivv
Cu Cv > > Syx
(2x+i)n
COS-
(2V + i)vn
COS-^
*'*-'
16
16
x=0y=0
Cu
and
4. The 64
Cv
= =
/^
where
for u, v
coefficients are quantized
quantization
table.
using
one of
Quantization is done
2-14
0; Cu, Cv
1 otherwise
64 corresponding
by dividing
each
values
from
coefficient
by
corresponding
nearest
in the
number
integer. Figure 2-6
Results
quantization array.
to the
are rounded
shows an example.
low freq
160
-10
16
-12
12
20
26
30
156
-12
-14
10
13
29
30
28
-56
24
20
12
20
29
35
28
21
-27
-11
15
11
15
26
44
40
31
33
-28
divide
11
19
28
34
55
52
39
-12
-18
by
12
18
28
32
41
52
57
46
25
32
39
44
52
61
60
51
36
46
48
49
56
50
52
50
8x8 data
high freq
quantization table
'
20
-2
-i
26
-2
-2
-8
-3
-1
-1
-1
-1
result
Figure 2-6 Example

No default table is
example
specified
by
quantization
the JPEG standard. The table
is the default table from the Independent JPEG
also the same table specified
by
Group
the draft ISO compliance
2-15
used
in this
software.
It is
testing document.
There is
no compression at
this step data loss
will
this stage,
The lower
occur.
important in reconstructing
image,
an
least important in reconstructing

divided down to
coefficients are
high
frequency
in the
points are
quantization
divided
points are quantized
All
numbers
quantization
by
placed
same
table,
and
zero
in the
reconstructed
is
coefficient
encoded
image
the
zeroes as
to
in
will
be
can
be
the
frequency
possible, hence the
The
values
to maximize the
The low
frequency
to prevent them from
zero
most
points are
higher
able
a row.
the
are
quantization coefficients.
together
not quantize
points
frequency
Thus
restored
by
becoming
a reverse
thus have no loss. All numbers in the 8x8
cannot
be recovered,
too many numbers, especially in the lower
will result
5. The DC
large
many
much smaller numbers
that do
using the
be
data block that do divide to
Dividing
image.
obtain as
by
the high
while
an
frequency
table are selected so that step 6
number of zeroes that can
zero.
there are still 64 coefficients. But at
as
and
frequency
thus are lost.
range, to
zero
being distorted.
using the difference
with respect
to the last DC
coefficient.
coded
This
DC term
preserves the
Present Quantized DC
DC
coefficient with a
quantization error.
2-16
Last Quantized DC
lossless coding scheme,
except
for
6. The
coefficients are ordered with a
many
in
zeros
DC
zigzag
ordering.
AC(01)
AC(07)
AC(77)
Figure 2-7
Entropy
encode
Zig Zag Ordering
the coefficients using Huffman coding. Tables must be supplied
to the encoder. The DC coefficient is Huffman coded using the DC
the
AC
coefficients
are
compression will occur.
Figure 2-9
place as
a row as possible.
AC(70)
7.
This is done to
shows
coded
With
the complete
using the
more zero
overall
2-17
AC tables.
runs,
At this
tables,
and
stage
the
more compression will occur.
encoding flow.
Source Image
Level Shift
8x8 blocks
Compressed Data
Entropy
Zig Zag
Encoder
<r
Quantizer
7T\
Table Specs
Table Specs
Encoding flow
Figure 2-8
Decoding
is essentially the
decoder has only the

steps
done to decode
1.
essential
Entropy decoding,
result will
information
compressed
be 64
of
reverse
encoding, therefore this
its function. The
on
image data. Figure 2-9
using Huffman
coefficients
in
coding.
shows
following
the
The tables
overall
coefficient.
B. Decode the AC
DC
value
coefficients
2. Undo the zigzag
reordering.
3. De-quantize the
coefficients.
be
2-18
list
of
the
decoding flow.
The
and predictor
from
array.
Last DC
value +
decode
using the AC Huffman table.
Table(s)
is
the
on
supplied.
must
A. Decode the DC coefficient, using DC Huffman table

last DC
section
must
be
supplied.
value.
4. Run the
coefficients through the
Syx
inverse discrete
(2x + l)uII
^V^c
> >
CuCvSvuCOS-
(^4an^ G
5. Level shift; for

6. Data
will
be
an
an
= -j=
8 bit
image,
16
add
0,Cu,G
128 to
Compressed
Entropy
Decoding
l otherwise
each pixel.
8x8 block. Reconstruct the image
Data
(2y + l)vn
16
foru,v
(JDCT).
cos^^
4^*
where
cosine transform
^Zig-Zag
with
8x8 blocks.
Dequantize
7F
3Z
^L
Table
Table
Specifications
Specifications
Reconstructed
Image
Figure 2-9
The JPEG
standard
specifies what comprises
software and
hardware,
does
not
Decoding Flow
specify how to implement the
the encoder and
would
implement
decoder. Different
each
respective technologies.
2-19
above
steps, it only
implementations,
block using the strong
such as
points of their
2.3 Interchange Format
This
compressed
exhaustive
For the
section contains a
image
denotes
of the complete
description
marker, table data
data. An
that can be decoded
description
complete
brief description
and the
refer
the interchange format found in a
this project. This is
interchange format
specified
image data. Markers denote
to be an
meant
by the JPEG standard.
specific sections
in the
is the Define Huffman Table(s), DHT,
Huffman table data
are
defined. Table data
or quantization
tables. Figure 2-10 shows a typical format
For
description
a complete
not
to the standard. The interchange format consists of
example of such a marker
a section where
by
of
of each part of
of
are
the
compressed
marker.
actual
It
Huffman
the compressed image data.
the compressed data
refer
to
section
of
the
DIS [IS094].
SOI
multi-scan
^ tables
.S
misc
leader
tables
,,
"7
Figure 2-10 Typical
and
markers
APP.
found in the
They
EOI
frame
ymisc
The
>
are
compressed
compressed
data
are
defined in table 2-7 along
SOI, EOI, SOF, SOS, DQT, DHT,
with
2-20
image data format.
their codes.
COM
Marker
Definition
SOI
Start Of Image
FFD8
EOI
End Of Image
FFD9
SOF
Start Of Frame
FFCO
Start Of Scan
FFDA
SOS
DQT
Code
Define Quantization
FFDB
Table(s)
Define Huffman Table(s)
DHT
COM
FFC4
COMment
APP
Application
(hex)
FFFE
FFEO-FFEF
specific
information
Table 2-7 JPEG Markers
The SOF
marker
is found
the SOS marker
quantization
preceded
of the
frame header. At
header,
the start of the scan
be found. In the tables/misc. boxes there may be Huffman tables,
will
tables,
the start
at
comments
or
application
specific
information. These
will
all
be
by their appropriate markers.
2.4 VHDL
2.4.1 Behavioral modeling
"A behavioral
test"
under
inputs
box
and outputs to this
need not
implement the
designs,
will work.
is
be the
use
system.
black
box, but
what
how
designers
model
implements the
Behavioral modeling is
Behavioral modeling
behavioral
describes the behavior
of
the hardware entity
test can be thought of as a black
understand
and thus can give
Once
under
actual circuitry.
is to
that
a model
[Fan94]. The entity
down design. Its
level
model
a system
can
2-21
functionality
used as
be implemented
the
at
are
black
of a
not
much quicker
early look
and approved
of
the start
is going to operate,
and customers an
is functional
box. There
top
how to
than lower
how
a system
by both the designers
and
customers, then
that will
can
be done. Figure 2-1 l[Bha92]
behavioral
model and a structural model
lower level design
be designed
as
both
shows a schematic
(section 2.4.2).
OZ(0
A O
r
-OZ(
B O
I )
OZ(2
ozo:
IABLE L>
Figure 2-1 1 A Decoder Circuit
Below is the entity that implements the interconnections for the decoder
common
to both the behavioral
the
to the outside stays the same, but what goes
view
entity DECODER2x4 is
port (A,B, ENABLE
end
and structural models.
in BIT; Z:
out
on
Thus the analogy to
inside
changes.
BIT_VECTOR(0 to
DECODER2x4;
Figure 2-12 Example VHDL
2-22
Entity
3));
circuit.
black
It is
box,
The
code
that
implements this entity
architecture
as a
DECSEQUENTIAL
behavioral
of
model
is
shown
below.
DECODER2x4 is
begin
process
(AB,ENABLE)
variable
ABAR, BBAR: BIT;
begin
ABAR
BBAR
:=
not
:=
not
B;
if(ENABLE='l')then
Z(3) <= not

Z(0) <= not
Z(2) <= not
Z(l) <= not
(A
B);
and
(ABAR
BBAR);
(A and BBAR);
(ABAR and B);
and
else
Z<="1111";
if;
end
end
process;
end;
Figure 2-13 Example VHDL Behavioral Model
Chapter two
of
A VHDL Primer
by
Jayaram Bhasker
[Bha92] has
a more
in depth
coverage of this and other types of VHDL modeling.
2.4.2 Structural
Modeling
Structural modeling is
model as a set of
inverters
and
at a
interconnected components,
NAND
gates
that
implements the decoder, inverters

gates are
the
the lowest level
structural portion of
section
lower level than behavioral
devices,
are
and
like
interconnected.
NAND
each
much
have
gates are
2.4.1.
2-23
a schematic.
In the
It describes the
Figure 2-10
structural
uses
that
model
interconnected. The inverters
behavioral
the VHDL code that
modeling.
model
and
format. Shown below is
implements the decoder
example
from
architecture
DEC STR
of
DECODER2x4 is
component INV
port
end
(A: in BIT; Z:
out
BIT);
component;
component NAND3
port
end
(AB,C: in BIT; Z:
out
BIT);
component;
signal
ABAR,
BBAR:
BIT;
begin
10
INV
(AABAR);
(B,BBAR);
NO : NAND3 port map (ABARBBAR,ENABLE,Z(0));
Nl ; NAND3 port map (ABAR,B,ENABLE,Z(1));
N2 : NAND3 port map (ABBAR,ENABLE,Z(2));
II: INV
N3
end
dec
port
map
port
map
NAND3
port
map (A,B,ENABLE,Z(3));
str
Figure 2-14 Example VHDL Structural Model
2-24
3. Implementation
3.1
C program behavioral
The C program, dec.c
Its
main purpose was
be
meant to
input,
only
was written
to be able to
an exact match
used
for
an
source code to the
of
1 The VHDL decoder

.
period.
2. The
list
add
cases
reset
of
of
images
functions that
not
and
not
as
Refer to
It
was not
have the
same
program was
of
part
appendix
the
A for the
in the decoder. For
are not available
is
stated.
images. This
work on grayscale
also reduces
extra
capability for
compress
the
(MCU)
are compressed
decoding
errors are
design. It does
structural
how JPEG works,
only
markers were not
the
worked.
was
done to limit
the design to a level that could be implemented in a reasonable time
that do not
3. Restart
JPEG decoder
JPEG decoder.
VHDL implementation has. Since the C
minimum coded unit
in the
standard requirement
will
This limitation
grayscale
how
model of the
Structural Model
omission, the JPEG baseline
of
behavioral
program.
section contains a
the size
design, it will not be discussed in detail.
dec.c
3.2 Limitations
This
understand
understanding
of the
to be
to the VHDL
output or modules that the
implementation
each
model
simulation
size was
times to a manageable level.
limited to
one
in this manner; therefore, it
more
than one 8x8
block in
8x8 block. Most
was
decided
not to
MCU for the few
this way.
included in the design
of a scan to an
introduced into the
initial
state at set
compressed
3-1
of the
decoder. Restart
markers
intervals. This is helpful if
image data. With restarts, only the
section
in
a given
image
entire
after
3.3 VHDL Structural

This
designed
was
and
engine.
level
will
error will
be
be
affected
by
Without restarts, the
error.
model
structural model will
top down
and works
abstract
the
affected.
describes how the VHDL behavioral
using
blocks
an upper
the
implemented. The
designed,
abstract
into
section
interval
block
of a
These lower levels may be
detailed
specific
car,
abstract
small
was
same manner
starts with
blocks. An
lower levels
with some
JPEG decoder
be described in the
A top down design
approach.
down to
model of the
high level
example would
being brakes,
it
be
tires and
can
be broken down
the VHDL design
is the test bench.
blocks themselves that
blocks.
smaller
3.3.1 VHDL Test Bench
As
seen
in figure 1-2, the
This top level block is
upper most
expanded to the next
level
lower level
rmpr<:<:pH_riata
/nptljiyt _""!
Memory
of
and
is
shown
rpcnlt
data
rcglllt
data
ualiri
"""lit
data
arlf
in figure 3-1.
Display
Decoder
npytjiytpjirlf
rpari
rnmplptp
firr
>
_cliu_
intr
fPSPt
tart
decoding
decade
isr data
nnmplptp_arlf
Figure 3-1 VHDL Test Bench
3-2
*>
The three
parts
that
make
blocks. These blocks

three
blocks
are
are
up the VHDL test bench
defined in table 3-1. The
defined in table 3-2. The
the
are
interconnecting
behavior
exact
decoder,
memory
between the
signals
is
of these signals
display
and
shown
in
more
detail in the decoder section, 3.3.2.

A VHDL behavioral
Memory
compressed
image data.
data from
file.
Decoder
The JPEG
Display
A VHDL behavioral
accepts
memory that
the
of
model
stores
the
This module reads the compressed image
decoder, described in detail in section 3.3.2

model of a display module. This
the decompressed image and
writes
module
the data to a file.
Table 3-1 VHDL Test Bench Modules

clock
system clock
reset
Resets the decoder to
initial
an
state.
Initial
state
is awaiting
signal
to begin decoding. Reset has precedence
over all other signals.
start_decode
Signals the decoder to
a compressed
decoding
When on, signifies that the decoder is decompressing

When off, decoder is awaiting a start decode signal.
complete
Signals that the decoder has
completed
Signals the decoder that the
complete signal was seen.
decoder looks for
complete
ack
intr
Signals that
decoding
start
rising
edge on
image. The
this signal.
an error occurred while
an
image.
decompressing data.
the decoder
was
decompressing
data.
Interrupt data from which the
isr data
cmprssed
next
data
byte req
next_byte_ack
Compressed data that is input into the decoder

A request from the decoder for the
Acknowledgment
compressed
Data
en-
read
result
data
result
result
cause of an error can
that
data is
could not
Decompressed
be
the
next
next
valid on cmprssed
obtained
data,
output
from
byte
byte
request
from the decoder
data
data
ack
Decompressed data has been delivered to
3-3
at a time.
was
data.
signaled,
memory.
Decompressed data is
Table 3-2 VHDL Test Bench
byte
of compressed
data line.
valid
valid on
be determined.
the result
byte
at a time.
data line.
display module.
Interconnecting Signals
To implement the VHDL test

needed.
This file
startdecode,
and
and completeack.
bench,
It
file that
stimulus
also checks
structure of
refer
a source
the
provides
also
isrdata. The basic
complete test
bench,
to
connects
the
inputs signals;
the output signals
the VHDL test
to the JPEG source file in
the modules together
bench is
appendix
decoding,
shown
A.
entity jpeg is
end jpeg;
architecture
jpeg_arch
end
jpeg
is
declarations
component
component
of
definitions
constant
memory
component;
component
end
decoder
component;
component
end
display
component;
define
signals
signal
clock
std_ulogic;
signal
result_data_ack
std_ulogic;
begin
components
connect
mem
memory
map (
port
signals
decoder
map (
port
signals
)
dis
display
map {
port
signals
)
process
MAIN
begin
control
end
end
process
signals
MAIN;
jpeg_arch;
Figure 3-2 VHDL Test Bench Basic Structure
3-4
clock,
is
reset,
complete, intr
in figure 3-2. For the
3.3.2 Control Signals
Throughout
section
the design
describes how
modules, A
two
control
B,
is
modules
methodology is
and
the JPEG decoder many
control signals are used
Control between different
handshaking
of
shown
which need
to
to
communicate
accomplished
in the
These two
communicate some
example,
module
schematic
layout
control
will need
lines
using
following
lines between the modules, REQ
acknowledged).
are used
control signals are used.
handshaking
example.
This
modules.
The
scheme.
example
has two
task between themselves. There are
(request)
in
between two
This
and
REQ_ACK
conjunction with a
(request
data line. In this
to request data from module B. Figure 3-3 shows the
of the modules.
DATA
START
in
out
in
REQ
in
out
REQ ACK
in
DUt
Figure 3-3 Control Signals Example Schematic
The
REQ line is used by module
the data are
requesting
valid on
and
the DATA line
acknowledging is
1. Reset state, both

Module A
change
A to
waits
as
REQ
to
request
by
data from
using the
module
B. Module B
REQ ACK line. The
signals that
exact syntax
for
follows:
and
REQACK
do work,
to 1. The DATA line
are set
and module
starts
3-5
in
to 0. This
waits
is the initial
for the
an unknown state.
REQ
state.
signal
to
2. Module A
receives an external signal
from 0 to 1
to start work, it then
REQ line
3 Module A waits for REQ_ACK line to

.
4. Module B
data for
changes
REQ
receives
module
change
change
from 0 to 1
from 0 to 1. Does internal
work
to
obtain
A.
5. Module B
puts
6. Module B
changes
7. Module B
waits
8. Module A
receives
9. Module A
returns
data
onto
DATA line.
REQACK line from 0 to 1.
for
REQ line to
change
REQ_ACK line
REQ line
to 0.
from 1 to 0.
change
from 0 to 1
(Note, it
would
be
an
improvement to take
the data from B at this point.)
10. Module A waits for REQACK line to
return
11. Module B
back to 0. Module B
receives
REQ
signal change
state, restoring REQ_ACK
signal
to 0.
returns
to initial
to 0. Data line is not changed in the initial
state.
12. Module A
receives
the DATA line and
line
until
talk to
with
REQ_ACK
continue with work.
the next request.
each other.
signal change
Note, in
Thus the data
the current data and make a
to 0. It
Module B
take data from
will not change
the data
this design only these two modules may
will remain valid until module
new request.
3-6
will now
A is done
Note that this is

clock.
In
design,
a synchronous
all modules used
in the design
An
used with control signals.
example
and all actions occur with an edge of a
of
the JPEG decoder this is the
timing diagram is
Figure 3-4 Example Control Signals
shown
method
below in figure 3-4
Timing
3.3.3 Decoder Module

The decoder
module
seven major components

main unit
is the
that control and handle the
in the decoder is the
ISR (Interrupt Status
(Find Start
of
shows
complete
sections
The
the JPEG decoder. It consists of
decompressing
other major units are
module, FindSOI (Find Start
FrHeader (Frame
module, FindSOS (Find Start

3-5
controller.
Register)
Frame),
structural model of
of
Scan)
Header)
and
of
in this
of
the
decoder, it
chapter cover
the
only
Image)
remaining
the
Scan)
of
Image)
module.
Figure
Note,
major control and
modules and signals.
3-7
module, FindSOF
module, FindEOI (Find End
DecodeScan (Decode
shows
image data. The
the NextByte module,
the major components that that make up the decoder.
diagram
of
data
this is not a
signals.
Later
s
/
Next
-> Byte
DecodeFrame
-*
FrHeader
FindSOS
DecodeScan
->
->
FindSOF
/
\
FindSOI
Controller
v.
y
ISR
*
Figure 3-5 Major Components
The decoder
module
actual source code
accomplish
made
up
appendix
no
complete
only
shows the
decoder
Module
between many
functionality, it
decoding. Figure 3-6
A for the
\/
of Decoder
of interconnections
for the decoder has
decoder
Name
is
the parts of the
See
module.
->
The
submodules.
connects modules
basic
structure of the
that
decoding
source code.
entity
Purpose
JPEG baseline decoder
Author
Douglas
Created
12-Mar-1994
A.
Carpenter
Revised
library and
library ieee;
use
clauses
use
ieee.
std_logic_1164
use
ieee
std_logic_1164_extensions
library
use
all ;
all ;
my__components;
all
entity decoder
--
all;
huff_acdcsel6. all;
is
control
inputs/outputs
in
clock
start
isr
components
my_components
port
all;
.package_l
my_components
include
use
my_packages;
my_packages
library
use
decode
decoding
in
std
std
ulogic;
start
ulogic;
decoding
out
std
ulogic;
acknowledge
out
std
ulogic;
in
std
ulogic;
decoding
decoding
intr
out
std
ulogic;
interrupt
isr data
out
std
logic
complete
complete
ack
:>r(7
3-8
downto
compressed
start
decode
data
in
memory
signal
complete
complete
0);
acknowledge
flag
interrupt
status
register
reset
in
--
std
compressed data
flag
reset
ulogic;
in
vector (7
cmprssed_data
in
std
ulogic
downto
0);
next_byte
out
std
ulogic;
--
request
for
inc_data_ack
in
std
ulogic;
--
next
readêrr
in
std
ulogic;
--
error
req
result_data_valid
out
std
result_data
out
std
result_data_ack
in
std
byte
input
--
next
is
reading
byte
valid
next
for
byte
ulogic;
vector(7
ulogic
downto
0);
ulogic);
decoder;
end
Name
Purpose
decoder
arch
decoder
module
Author
Douglas A.
Created
12-Mar-1994
Revised
--
decoder
architecture
of
arch
DAC
decoder
is
isr
component
port
Carpenter
reset
in
std
ulogic;
std
ulogic
interconnections
clock
*
end
component;
define
do
component
port
components
unload
clock
in
std
ulogic;
interconnections
--
result
end
in
data
in
ack
std
ulogic);
component;
work
signal
--
define
do
signal
req
internal
unload
std
ulogic
vector
(2
downto
0);
signals
ack
std
ulogic;
begin
ISReg
isr
port
map
reset,
interconnecting
signals
clock) ;
Instantiate
Dollnload
do
components
unload
port
map
clock,
--
Interconnecting
result
end
decoder
data
signals
ack);
arch;
Figure 3-6 Layout
of Decoder
3-9
VHDL Source Code
compressed
of
compressed
read
data
data
Controller Module
The
controller module
outputs to the
decoder
that signal
in the decoder
which sub-module
shows the
is the brains
symbol
for the
when
will
controller.
of
to start decoding. The controller determines
be working
A feature
Corporation System 1076 VHDL is that
definitions. Source
code
a r
for the
e c o
controller
omp I
the compressed data. Figure 3-7
on
designing
of
be
can
symbols
wor
2: 0 )
q (
(UT
r r
et e_oc
with
clock
dec
ack
co
od
mp I
i ng
e
CUT
(U
3-10
Mentor Graphic's
created
is found in Appendix A.
reset
r e
the decoder. It has the external inputs and
from the entity
The
signals used
by the controller are defined
Signal
follows in table 3-4
Definition
clock
reset
decode
System
clock
System
reset
External
signal
decoding
External
output to
complete
External
output
completeack
External input to
intr
External output,
start
as
decoding compressed data.

signal that decoding is in process.
signal that decoding is complete.
to start
to
signal
that
complete
has been
received.
compressed
Internal
workreq
bus to
has
an error
data. Check ISR
control
occurred
register
bus. Different
for
error cause.
requests are put on
request a module perform
table 3-4 for
decoding the
its
operation.
See
work request codes.
is
ack
Work
requested
req_err
Work
requested can not
complete
be completed,
an error
occurred
Table 3-3 Controller Signals
work
req
000
definition
code
No request,
also signals
that the last ACK was
received.
001
Request that FindSOI
module perform
its
operation
010
Request that FindSOF
its
module perform
operation
011
Request that FrHeader
module perform
its
operation
100
Request that decframe
110
Request that FindEOI
module perform
its
operation
module perform
operation
all others
not used
Table 3-4 Work Request Codes
3-11
its
the
For the remaining modules, the flow
corresponding
Step
VHDL
state table or
1. Reset state,
be
will not
The flow
source code.
set all outputs
See the
shown.
appropriate module's
of the controller
is
as
follows:
to their initial state. Wait for startdecode
signal.
Step
2.
Received
Send
startdecode signal.
out
workreq
code
to find start of
image (SOI).
Step
3.
Wait for
found. If a
Step
4.
from FindSOI
acknowledgment
is returned,
req_err
Received ACK from
that SOI marker
module
was
go to error step.
FindSOI,
send out
workreq
code to
find
start of
frame (SOF).
Step
5.
Wait for
acknowledgment
found. If a
Step
Step
7.
to perform
Wait for
8.
FindSOF,
its
read
in
go
module
that SOF marker was
to error step.
send out work request
to the frame header
operation.
acknowledgment
data were
Step
is returned,
req_err
6. Received ACK from
module
from FindSOF
correctly.
from FrHeader
If a
req_err
module
is returned,
Received ACK from FrHeader module,
that the frame header
go
to
error step.
send out work request code
to
the DecFrame module.
Step
9.
Wait for
decoded
Step
acknowledgment
properly.
If a
from DecFrame
req_err
is returned,
10. Received ACK from DecFrame module,

the module to find the end of image
3-12
go
module
that the frame was
to error step.
send out work request code
(EOI) marker.
to
11. Wait for
Step
found. If a
was
from FindEOI
acknowledgment
req_err
is returned,
12. Received ACK from FindEOI
Step
proper sequence of signals that
Error
Step
Send
an
design
were used.
controller
interrupt. Once
not
be
The first
for the
shown
it is
is
Send
complete.
decoding is complete.
controller.
for the
design
difficult to do
process.
Since the
module.
is that it is very
difficult
state machines.
controller
The ISR
use
a state
without
method,
is
will
to use and
Most
for
and
rather
only be
large
modules
designing
it
process of
module will cover
this method
cumbersome
methods
The basic
time consuming process.
and
Two
using the INTR line to
table. The steps
only
an
few
on a
this first method
will
in depth discussion
be
will
this method in detail later in the
noted.
The downfall
necessary
understanding the
in the
in the decoder
state machines
was used
when changes are
Also,
alert
to step 1.
a state machine.
method was not an efficient
thesis. All other modules that
method
decoding
that
module
complete return
is implemented using
modules at the start of the
explained
marker
go to error step.
proper sequence of control signals
implemented using
are
that the EOI
13. Return to step 1.
Step
The
module
process
to
of this
first
on a module
source code
is very
implement the
state
machine are:
1. Design
a state
2. Code the
3. Run the
the
state
state
table into
an espresso program
espresso
controller
for the
table. The
program,
is found in
table
obtain
appendix
controller
is found in
appendix
B.
input.
the espresso output. The espresso output for
B.
3-13
4. Use the
minterms.
espresso
output
Minterms
are
labeled AO to A30 for

(D3 to
DO)
the sums used.
Usually
this method
implementing
of
first
method will
The
second method
be
the VHDL code.
write
found
as the rows
in the
derived using
written
espresso output.
method results
in
major changes
state machines was abandoned
They
are
is
to all the minterms and
required.
for the
For this reason,
second method.
to as the espresso method throughout the rest
is the direct
using
sums.
a complete rewrite of the source code
referred
Code is
the controller. With these minterms, the state variables
and outputs are
Making improvements using this
to
method and
it
will
be
covered
in the first
of
The
this thesis.
module used.
NextByte Module
The NextByte
data
memory.
If changes
module needs to
method used
method
is
module
be
used
are made
changed.
in the design
shown
is
was
of
common
interface to the
compressed
to the way the compressed data is accessed, only this
The NextByte
module was
designed
as a state machine.
the espresso method. A detailed description
for the NextByte
3-8 is the interface
to supply one
module
following
The
of the espresso
the symbol and signal tables. Figure
the NextByte module. All compressed data are read from memory
sequentially.
3-14
IN
cmprssed_dato(7:0
nex
reset
t b y t
dotaôi
OUT
r ead_er r
next
n c
nex
eq
o
nex
ou
clock
err
Figure 3-8 NextByte Symbol
Table 3-5 defines the
signals used
by the NextByte module.
Signal
Definition
clock
System
clock
reset
System
reset
byte req
inc_data_ack
Request to memory for next byte of data.

ACK from memory, data is valid on
next
cmprssed
read
err
cmprsseddata
Error
at
data line.
memory providing
Compressed data from
next
memory.
byte
of data
Input
byte
at a
time.
next
req
nextack
for
Internal
request
Internal
response
are valid on
next
byte
of data.
to nextreq. Will
signal
that data
data line.
data
Internal data line. The
en-
Internal
error
reading from
size
is
byte.
line. Signals that there

memory.
Table 3-5 NextByte Signals
3-15
was an error
The
following is a step-by-step description of the espresso method for coding state tables.
1: Create
Step
a state
functionality needed for the
table of the
the state table for the NextByte
module.
Table 3-6 is
module.
J*
o
CO
I
CD
*-
CD
1
CO
-o
o-
CD
OS
CO
cu
er
cu
Q2 Q1 QO
rr
D2 D1
DO
-a
X
CD
CD
CD
Comment
0 Wait for
1 Got next request, send
wait
err on
got
wait
next request
for inc
memory req
inc
ack
no err
0 inc
wait
next
err state, wait
err state, next
0 Not Used
0 Not Used
0 Not Used
to memory a request
ack
out
for inc
ack
ack returned
for
to
0, send
next ack
req to return to 0
next
req
to return to 0
returned
for
to
0, go to 000
next
req
req to
returned
return
to 0
to 0
Table 3-6 NextByte State Table
Step 2.
Create
an espresso
input file. The

states needed
are
#
.
in the
state
espresso
module.
table. Figure 3-9
type
.phase
espresso
#
#
The data in the
input
number
of
inputs
number
of
outputs
fr
#non inverted
111111
outputs
#
#
#
The
first
The
second
six
six
columns
are
columns
3-16
are
is the
espresso
input file define the inputs
the same as the state table.
.06
comments
for the NextByte
NextByte
input file from the
inputs
outputs
espresso
and
input file
#
#
#
#
#
#
#
#
#
#
The
are
columns
defined
as
follows,
from left
to
right
Q2
Ql
QO
next
inc
req
data
read
ack
err
D2
Dl
# DO
next
#
#
#
#
err
next
000
byt e
req
for
stands
000
ack
don't
000
000
001
001
001
-00
001
001
001
001
111
010
001
-10
011
000
011
000
010
100
100
011
-1-
011
-0-
010
010
010
000
000
111
111
010
111
000
000
care,
same
as
in
state
table
end
Figure 3-9 NextByte Espresso Input File
Step
3. Run the
#
.i
.o
#.
input file through the Espresso
espresso
file. Figure 3-10
espresso
output
NextByte
module.
NextByte
esp
6
phase
resso
6
six
six
shows
program.
the espresso
It
will create an
output
output
inputs
outputs
111111
#
# The columns are defined the same as in the input file
#
# The first size columns of each row defines a minterm
#
P
-01--1
0-1-1-01-00
-101--
111010
A0
011000
Al
001001
001001
# A2
# A3
# A4
# A5
010100
111010
010100
-001
Oil-O
ft
#
Example
A6
3-17
for the
#
#
#
#
.
AO
'0'
(DO
and
1'
(read
and
err
1'
is
D2
output
(Dl
is
minterm AO
A3
or
Figure 3-10 NextByte Espresso Output File

3: Create the VHDL
Step
VHDL
--
--
--
--
Name
nextbyte
Purpose
Douglas
Created
Revised
architecture
std
from
espresso.
Carpenter
DAC
of
arch
ulogic
aO
std
ulogic;
signal
al
std
ulogic;
signal
a2
std
ulogic;
signal
a3
std
ulogic;
signal
a4
std
ulogic;
signal
a5
std
ulogic;
signal
a6
std
ulogic;
signal
idata
std
is
nextbyte
vector)
signal
results
Figure 3-11 Shows the
module
A.
30-Mar-1994
nextbyte
implements the
espresso results.
arch
nextbyte
Author
signal
code that
from the
code
ulogic
downto
vector!
0)
downto
0);
begin
next
process
process
( reset, clock)
begin
if
(reset
<=
D
aO
<=
al
<=
a2
<=
<=
<=
<=
<=
((
clock'
<=
<(D(1)
al
<=
((D(2)
a2
<=
((D(l)
a3
<=
((D(2)
a4
<=
((D(l)
a5
<=
((D(l)
a6
<=
((D(2)
D(2)
<=
((aO
D(l)
<=
((aO
D(0) <= ((aO

if (inc data
<=
idata
'1')
'1')
'1')
ack
cmprssed
(clock
and
and
(D(0)
(D(0)
(D(0)
and
(next
and
and
and
and
and
or
(a3
or
(al
or
(al
'1')
I'.'J
'1')
and
(clock'last
and
and
( inc data
ack
'1')
and
( inc data
ack
req
(D(0)
(D(0)
(D(l)
=
'!')
err
read
'0')
and
(next
req
'0')
'
1')
and
(next
and
(D(0)
req
=
'1
'1'));
'1')
'1')
or
(a3
or
(a2
'!'
'1'
'
assign
next
'1'
or
(a6
<=
'1'
when
'0'
next
byte
((aO
'!')
or
(a3
req
<=
when
( (a2
'1')
'1'
'1'))
or
and
(read
) )
3-18
'
) )
) )
err
'0
and
inc
data
ack
'1
or
(a6
'1
or
(a5
else
'1'
'
el se
(a5
'1
(a3
;
'1'
));
(a4
'0';
err
'
or
then
'1')
'
or
data;
((a4
then
) )
values
when
) )
process;
output
<~
ack
'
'
if;
process
'1')) ;
'
'0'
= --
value
if;
end
--
)
'0')
'0't
'0')
'!')
'1')
'0')
'0')
event
aO
end
next
then
'0';
<=
"00000000";
idata
elsif
a4
end
'0'
"000";
) }
else
'0') );
1'));
1'
) );
) );
data
end
<-
'0';
idata;
nextbyte
arch;
Figure 3-11 VHDL Source Code From Espresso Output

The VHDL
implements the
source code
are modified
in the
main
process; the
results
sum of
from
espresso
directly. Minterms
these minterms are used for
each
outputs.
ISR Module
The ISR Module is the interrupt
decoding process,
reason
holds
for the interrupt
codes
for
(figure 3-12),
codes
the intr
will
be
line
will
placed
table
of signal
Only
for future
few
be
Shown below
have been
3-7)
are
and a
used as of
the
an
s r
i n
( 7: 0)
isr
reset
isr
isr_l
q-t
that
symbol
3-19
register
for the ISR
module
table of the current in use
the current
( 7: 0
OUT
ch_ack(frj
Figure 3-12 ISR Symbol
in the
bit
an eight
clock
occurs
the
g p
d
error
Along with this line,
enhancements.
+r
from 0 to 1.
changed
definitions (table
codes
When
into the ISR. The ISR is
various error conditions.
(table 3-8).
extra codes are
signal
status register.
error
implementation. All
Signal
Definition
clock
System
clock
reset
System
reset
isr latch
Input from modules to latch isr data in.
isrlatchack
Output to
modules
that
data have been
latched.
isr data in
Interrupt
isr data
External
code
data from internal
modules
output of interrupt code.
Table 3-7 ISR Signal Definitions
Code
Definition
00000001
Error
finding SOI marker

Error loading quantization table
Error loading Huffman table
Error finding SOF marker
Error finding EOI marker
00000011
00000100
00000101
00000111
Table 3-8 ISR Codes

The ISR
contains
was
the
implemented
state
table
and
as a state machine
using the
Appendix B
espresso method.
the espresso results.
FindSOI Module
The
marker
of
purpose of the
FindSOI
is found. Once the SOI
the compressed
data
module
marker
FindSOI interface.
Following that,
is
FindSOI
module
appendix
B for the
is found
are searched and no
from memory, then the REQ_ERR is
is to
an
SOI
returned
read
in
ACK is
marker
to the
compressed
is found
controller.
designed using the
state table and espresso output.
3-20
until
the SOI
returned to the controller.
or
there
is
by
If all
a read error
Figure 3-13
table 3-9 defines the signals used
a state machine and was
data
shows the
the module. The
espresso method.
See
dot
nrrl
7=
0)
FindSOI
:
eq ( 2 0)
work_r
<>TN
s r
1-
o_i n
r e
0)
(UT
reset
next
tn i
ack
s r
r r
next
q (W
err
s r
(>UT
(W
ack
clock
(UT
Figure 3-13 FindSOI Symbol

Signal
Definition
clock
System
clock
reset
System
reset
work_req
Request line from controller, when equal to

the FindSOI request number, begin search
for SOI
marker.
Output to NextByte
nextreq
compressed
module
Input from NextByte
nextack
for
next
byte
of
data.
module that
data
are
valid.
Compressed data
data
Error reading next byte.

Work request could not be
err
req
received a
err
Work
ack
SOI
time
completed.
request was completed
was
at a
successfully,
found.
Output to ISR to latch isr data in.
isr latch
isr latch
byte
Input from ISR that data
ack
isr data in
Interrupt
code
were
latched in.
data to ISR.
Table 3-9 7indSOI Signal Definitions
Some
modules.
One
of
such example
requests use the
module
the signals
ACK
is working
at
signal.
any
used
in the design
is the ACK
Multiple
one time.
signal.
of
All
modules can
To
code such a
3-21
the
of
drive
line,
decoder
are
shared
by
multiple
the modules that receive
a common signal since
a wired or resolution
work
only
one
function is
used.
signal.
or
resolution
As the
name
function takes
gate.
The
function is
implies,
all of
signal will
design,
only
be
OR
off.
one module
ACK line. Figure 3-14
in VHDL
when
there are multiple
the function will resolve
what
the modules signals for the one
output of the
off, the
used
gate
If any
is the
resolved
at
any
on
driving on,
shows an example of the wired or
them through
when all of
the
time, thus only
signal will
same
wired
an
OR
the lines are
be
on.
as a schematic
In this
drive the
one module will
function
correct output.
and puts
function. Thus
of the modules are
is working
line
is the
inputs to the
diagram.
Figure 3-14 Example Wired Or Schematic

FindSOF Module
FindSOF
found
an
reads compressed
ACK is
returned
marker, if any DHT

are called.
A DHT
or
DQT
data until the SOF
to the controller.
markers are
marker will result
causes a quantization
marker
As the
is found. Once the
module
marker
is searching for the SOF
found then the corresponding table load
in the
loading
of a
table to be read. The modules that accomplish the
marker.
3-22
modules
Huffman table. The DQT
tables are covered later in this section. Figure 3-15 shows the
is
interface
loading
of
marker
of
these
the FindSOF
dot
7:
work_r
ob
0)
FindSOF
2- 0)
eq (
isr
e_err
1-
0)
o_i n
r e
b I
(fU
n e x
(UT
(UT
eq
(fur
(UT
reset
qt
nex
b I
t
sr
ht
e_o c
ab
ch_oc
e_oc
qt
k
s r
ht
err
b I
e_r
clock
ac
(UT
k our
Figure 3-15 FindSOF Module

The definitions
of
interface to the FindSOF
the signals used to
module
described in table 3-10.

Signal
Definition
clock
System
clock
reset
System
reset
workreq
Work
request
waits until
line from
controller.
FindSOF
workreq line has data that

SOF req value.
matches the
ack
Acknowledgment back to
work
is complete, SOF
controller
was
that
found
successfully.
req_err
An
attempting to
See ISR register for
error occurred when
locate the SOF
marker.
the cause.
nextreq
Request from NextByte for

compressed
nextack
byte
of
data.
Acknowledgment from NextByte that byte

on
data line is
valid.
data
Error obtaining a byte from memory

Compressed data, size is byte.
isr latch
Message to ISR to latch in data.
isrlatchack
Return
err
message
from ISR that the data was
latched in.
isr data in
Data to be latched into ISR
3-23
register.
are
qtable
Request to load
req
a quantization table.
Acknowledgment from
qtable_ack
loader
quantization
module that table was
table
loaded
successfully.
htable req
htableack
Request to load
Huffman table.
Acknowledgment from Huffman table

loader
module
that table
was
loaded
successfully.
Error
tableerr
loading a table.
Huffman loaders
Since only
they
used
the
table is
one
can share
Both
quantization and
same signal.
loading
at a
time,
the line.
Table 3-10 FindSOF Signal Definitions

Fr Header Module
The FrHeader
SOF
marker.
This
module was
header
decompressed. Figure 3-16
designed to
contains
shows
the
read
important
makeup
of the
in the data that
data
related
to
are
located
the
after
image
the
being
frame header.
Frame Header
SOF
Lf
Frame
Component-spec.
Nf
parameters
Tq
component-specific parameters
Figure 3-16 Frame Header Syntax

For
a grayscale
image,
what each parameter
complete
most of the parameters are will
is,
and
frame header
the
refer
only be
possible or preset values.
to
section
For
B.2.2 in the
3-24
one value.
Table 3-11 lists
detailed description
draft international
of the
standard.
SOF
Start
Lf
Length
of Frame
of the
marker,
read
in
header, excludes the SOF marker. Lf is the

including the two byte length parameter.
frame
number of bytes
Sample precision, for baseline

Number of lines.
Nf
to 8 bits.
set
Number
of sample per
Number
of image components
grayscale
by FindSOF module.
line.
in
frame. Set to
one
for
images.
Component identifier. Used for
multiple component
frames. Set
to 1 for grayscale images.
Horizontal sampling factor. Set to one for this thesis.

Vertical sampling factor. Set to one.
Tq
Quantization table
for
component
selector
a grayscale
for the
image,
component.
the
Tq
Since only
parameter
is
set
one
to
one.
Table 3-11 Frame Header Descriptors
Figure 3-17
describes the
shows
interface
of the
FrHeader module,
and
following that table 3-12
signals used.
do t
wor
7:
0)
xy_dota(
Fr
next
s r
o_i n
7-
0)
(iDT
(TOT
x_l a
ch
(iUT
(fDT
(fur
(fur
a c
(fur
Heade
r e
next
IN
+r
(lUT
15=0)
:
eq ( 2 0)
reset
s r
err
clock
sr
Figure 3-17 FrHeader Symbol
3-25
clock
System
clock
reset
System
reset
workreq
Work
from the
request
for the
waits
Acknowledgment to
ack
read
in
Signal
req_err
controller.
Frame header
module
correct code.
controller
that frame header
was
correctly.
controller
that
an error occurred
reading in frame
header data.
nextreq
Request to NextByte
nextack
Return
module
for
next
byte
of compressed
data.
line is
en-
signal
module
module signals that an error occurred
data
Compressed data from

Return
ack
isr data in
message
register.
Signal to X
register
to latch in data.
y latch
Signal to Y
register
to latch in data.
xy_data
or
reading
from ISR that data were latched in.
Data to be latched into ISR
latch
data
memory.
latch
on
memory.
isr latch
isr latch
that byte
valid.
NextByte
from
from NextByte
Y dimension
signal
data, fed into both registers.
determines
which register
or
latches data.
Table 3-12 FrHeader Signal Definitions
The frame header
appendix
B for the
state
module was
designed using the
espresso
method.
Refer to
table and espresso results.
FindEOI Module
The FindEOI
requests compressed
acknowledgment
controller
is
module
data
has
until
one
purpose,
and
that is to find the EOI marker. It
the EOI marker is found. When
to the controller. If an error occurs
notified.
3-26
when
found,
it
returns an
searching for the marker, the
TN dato(7:0)
/or
FindEO
k_r eq ( 2 : 0)
i
sr
1-
0)
o_i n
r e
r r
nex
(lUT
reset
next
sr
k
i
er r
+r
sr
ock
clock
dUT
OUT
Figure 3-18 FindEOI Symbol

The FindEOI
B for the
state
table
module was
designed using the
espresso method.
Refer to
appendix
and espresso results.
dec_frame
The decode frame module,
from the
main controller
code on the
first
workreq
requests
found,
decframe, is
to decode a frame. When this request
line,
marker
the module requests that the
Since there is only

multiple scans.
defines the
receives a request
is received, in the form
scan
be found. Once the
of a
Figure 3-19
in
frame in
shows
start of scan marker
be decoded. Once both these
main controller signals
one scan
signals used
It
the module sends requests to two sub-modules. The module
that the start of scan
performed, in order, the
a mini controller.
that the frame
a grayscale
the interface
by the module.
3-27
image,
used
by
was
decoded
no extra code
requests
is
are
successfully.
is
needed
for
the decmodule. Table 3-13
2- 0!
eq (
IN work_r
frame
dec
reset
f i
f i
nd_s os_ock
dec
d
r r
o s
r eq_er r
find
ode_sca n_er r
e c o
c o n
decode_scon
ock
clock
(fur
o s (fur
(fur
(fur
Figure 3-19 decframe Symbol
clock
System
clock
reset
System
reset
workreq
Work
from the
request
module waits
for the
Acknowledgment to
ack
Signal
Frame header
controller
that frame header
inconectly.
was read
req_err
controller.
conect code.
controller
that
an enor occuned
reading in
frame header data.

findsos
Request that the findsos
findsosack
Return
findsoserr
An
decode
Request that the
find the SOS
module
marker.
SOS
signal
that the findsos module found the
marker successfully.
enor
attempting to find the SOS
occuned
marker.
scan
decodescanack
Return
signal
scan
that
be decoded.
the
scan
was
successfully
decoded.
decode
en-
scan
An
enor occuned
decoding the
scan.
Table 3-13 dec frame interface definitions
Find SOS
The FindSOS
finds the SOS

are called to
module
marker.
has the
If any DHT
same
or
DQT
load the tables. Figure 3-20
Table 3-14 has the definitions for the
function
as
the FindSOF module, except that it
markers are
shows
the interface used
signals used
3-28
found,
by the module.
their respective modules
by the FindSOS
module.
data(7:0)
FindSOS
t
ob
e_err
reset
qt
b I
a c
sr
isr
ht
ab
f i
b I
next
qt
atch_ack
isr
e_ack
O)
("
next
7:
a_i n
o s
ht
er r
f i
clock
find
ab
ot ch
I e_req
nd_s os_er r
(fUr
r*
HU
(fur0
(Hir0
ock
sos
Figure 3-20 Find_SOS Symbol

Signal
Definition
clock
System
clock
reset
System
reset
find
sos
req
find_sos_ack
Request that this
next
marker.
module that
Enor
to
signal
decodeframe
compressed
module that
SOS
Request from NextByte for
ack
Acknowledgement from NextByte that byte
byte from
byte
en
Enor obtaining
data
Compressed
isr latch

ack
Return
data,
message
marker was not
of compressed
on
data.
data line is
valid.
memory.
is byte.
size
from ISR that data were latched in
isr data in
Data to be latched into ISR register.
qtable
Request to load
req
marker
data.
req
isr latch
SOS
found.
found in
next
find the SOS
Acknowledgement to decode frame

was
find_sos_en
module
a quantization
qtableack
Acknowledgement from
htable req
htableack
Request to load
table_en
Enor
table.
quantization
table loader
module
that
table was loaded successfully.

a
Huffman table.
Acknowledgement from Huffman table loader

was
loaded
module
that table
successfully.
loading a table.
used
the
they
can share
same signal.
Both
quantization and
Since only
one table
is
the line.
Table 3-14 FindSOS Signal Definitions
3-29
Huffman loaders
loading at a time,
The FindSOS
Appendix B
module uses
the
for
espresso method
implementing
a state machine.
contains the state table and espresso results.
DecodeScan
The DecodeScan
a scan.
module controls
It has three functions that it
completed, the decodescan
functions
module
the actual
decoding
that it is complete.
The three
sequential
are:
1 Request
and wait
for the
scan
2. Request
and wait
for the
number of MCU
3. Request
and wait
for the
header to be
scan
read
in.
to be computed.
be decoded. This
will
be done
by
modules.
scancomplete
DecodeScan
reset
decode_scon_heoder_err
decode_scon_header_ock
decode
decode_scon
c o
+i
data for
Once these three have been
performs sequentially.
signals
of the compressed
mp
e n u mmc u s o c
clock
or
(fur
can
decode
can
omp
s c a n (fur
can
decode
Figure 3-21 DecodeScan Symbol
3-30
(fur
c
e nu mmc us
(far
fur
a pipeline of
clock
reset
decode
System
clock
System
reset
Signal for this
scan
decodescan
Return
ack
Return
header
scan
ack
Return
decodescanheader
err
Return
decframe
module that the scan
to the decframe
decoding the
Signal to the
decodescanheader
to start.
has been
successfully.
signal
occuned
decode
to
signal
decoded
decodescanen
module
from the
signal
that an
enor
scan.
header
scan
module
module
scan
to read in the header
header
module
that it was
successful.
from the
signal
header
scan
module
that
an enor
occuned.
computenummcus
Signal to
computenummcusack
Return
its
compute number of
MCUs
module to perform
operation.
that the
signal
MCUs
number of
was
successfully
computed.
start
scan
Signal to the
scan
complete
Return
scan pipeline
signal
from the
to start.
scan pipeline
that it is complete.
Table 3-15 DecodeScan Signal Definitions

The decode
state
to
machine; instead it
implement the
code.
scan module
direct
state machine.
Refer to the
method.
uses a
does
source code
The
in
not use
approach.
appendix
is very
state, only the
code associated with that state
Two
notes on
1 Code
.
all
coding this way
states,
simple.
are:
even unused ones.
3-31
is
implementing
module
directly into
to see
When design
All
the
source
an example of
high level language
affected.
tables or programs are needed
is implemented
like
much
and
method.
outside
A for this
very readable,
changes
No
state machine
This method, the direct method, is

making
the espresso method for
program.
this
It is
changes are needed on a
modules
here
after use
this
2. Use
caution when
using
else clauses.
If
they
be
unknown states can cause the else statement to
is
shown
if
method
decode
state
the
if
scan
be
will
next
(decode
state
executed.
An
example of this
in figure 3-22.
Improper
--
to be used, ensure that no
are
next;
ack
but
value
Thus
be
will
head er
scan
same;
coding
is any
ack
reached.
state
0,
the
decode
if
scan
next
ack
XU'
reached.
*0'
then
else
state
if;
end
Proper
--
--
if
method
Only
when
next
state
decode
state
of
state
be
reached
scan
next;
same;
coding
next
header
ack
ack
is
VI*
to
equal
wilJ
the
then
else
state
if ;
end
Figure 3-22
An
example state machine coded
has four states,

on
the
rising
uses a synchronous
edge of the
possible state
each
Differing uses
clock,
is covered,
in VHDL is
clock,
and
has
of else clause
shown
an asynchronous reset.
any time. In the
and resets can occur at
including
any
Only
unknown states.
time the process is entered for a
clock
in figure 3-23. The
cycle.
The
module
Actions
occur
clock section each
one state will
state machine
be
executed
is designed
as
follows:
1. State 0 is the
equal
state, the
state machine will remain
to 1 When this occurs it

.
2. State 1
state
reset
waits until
inputl
will go
returns to
2.
3-32
to
state
in this
state until
input 1 is
0. When this occurs, the
state changes to
3. State 2
be
state
watches the signal
is
0,
the
of the states
any
process
1,
the next state
to 0. When input2 returns to
of
values
(reset,
may be
changed as needed.
the four steps noted above. That
implementing
process
returns
the output
direct implementation
to
0,
(reset
<=
is
--
if
set
state machines.
clock)
(D
if
"00")
(inputl
<=
(clock'
and
states
last
value
>0'
and
(clock'
event
then
'1'
then
to
state
state
change
*1'
initial
to
outputs
=
"01";
else
--
end
elsif
if
at
remain
Q <= "00";
if;
(D
"01")
=
(inputl
--
change
<=
then
0'
then
to
state
state
"10";
else
remain
at
Q <= "01";
end if;
elsif
(D
"10") then
if (input2
*1') then
=
change
<=
to
state
state
"11";
else
remain
<=
(D
"11")
(input2
if
at
"10";
if;
end
elsif
<=
then
to
state
state
change
then
'0'
"00";
else
--
end
at
remain
Q <= "11";
if;
else
<=
end
if
end
end
D
--
unknown
states
if
process
<=
"00"
example
process
Q;
assign
output
state
the reason
'0') then
"00";
((clock
elsif
the
Notice how
begin
if
will
reset state.
the name direct approach for
example
input2
waits until
returns to
the code
changes
3.
4. State 3
During
input2. When input2
values
Figure 3-23 Example VHDL direct
3-33
coded state machine
) )
then
for
dec_scan_header
The
decscanheader
purpose of the
header data. The header data

this
design. Refer to
code
for this
section
must
B.2.3
be
of
module
checked so
that
is to
they
be
and
of
the
check
scan
to the restrictions of
conform
the DIS for the syntax
module contains the preset values that must
in
read
header. The
the
source
in the header.
present
dato(7:0)
reset
nex
s r
sr
a_i n
i
con
7-
next
err
decode
e a
e r
clock
decode
can
decode
scan
Figure 3-24 decscanheader
s r
0)
OUT
eq
OUT
(fur
(JUT
header
ack
(fur
symbol
ComputeMCUs
The ComputeMCUs
decoded in
a scan.
module takes
and then
number.
For this thesis
in the
x and
divides that
When
dimension to
an
module computes
a minimum coded unit
y dimensions
result
by
eight.
of
The
image is compressed,
computation
source
image,
is
(MCU)
multiples
blocks that
is
These
rounded upwards
is done.
3-34
for
the
symbol
are
to
be
8x8 block. The
together,
to the nearest whole
to either the
additional pixels can
shows
code
one
the two values
additional pixels are added
make them multiples of eight.
Refer to the VHDL
the
result
the image is decompressed. Figure 3-25
module.
the number of 8x8
x or
be discarded
when
for the ComputeMCUs
on
how the
[ I 5= 0J
IN yjatol
15^0)
i
( 31
n u mmc u s
_
0)
OUT
reset
IN c o
Tn"
mp
e n u mmc u s
clock
omp
mc us
enu mmc u soc
Figure 3-25 Compute_MCUs Symbol
3.3.4
Decoding
The
actual
Scan
decoding
modules were used to
blocks
a pipeline can
break up the
be
is
of a scan
created.
decoding
With
process
pipeline, data
parts.
The four
dequantization, inverse discrete

The
This
are:
set
smaller
of modules.
Several
blocks. With
smaller
be decompressed
by breaking up
loading
an
the
at a
be
latency
pipelined
in the
pipeline that
implementation
when one stage must wait until
advantage of a pipeline can
be
other
shown
image is to be decoded. The 64x64

Figure 3-26
of an
data to
display
to the slowest module
in the
memory.
8x8 blocks
pipeline.
of
There
is due to waiting for the first block to be decoded.
uses a single
the
rate
8x8 block from memory,
transform and unloading
be limited
speed of the pipeline will
faster
decoding
loading module involves Huffman decoding of the compressed data into
data. The
will
cosine
parts
into
can
than a system without a pipeline. The pipeline is created
8x8 block into four
by
accomplished
buffering
is done
by
pixel
with
scheme.
the
buffer before it
a simple example.
In this
image has 64 blocks
shows the two methods which are
3-35
to be
Single
used
can
be
example a
of size
to
buffering
occurs
used.
64x64
The
pixel
8x8 to be decoded.
decode this image. Each
block has
total time
it takes to
time associated
with
it that
process a given number of blocks
Ttotai
and
With larger
non-pipelined method.
load
8ns
blocks in the image
in
the time to
(p) is
one.
a pipeline
load the
The
pipeline.
pipelined method
has
are:
2048ns
non-pipelined
Ttotai
670ns
pipelined
blocks,
For
the pipelined method
a more
Programs for the Transputer
will
excludes
Ttotai
numbers of
to the pipeline
Ttotai
: number of stages
stage the number of stages
The total times
to process data. The
is defined by:
number of 8x8 pixel
N
P
For the non-pipelined
long it takes
(N+(P-1)) X T^weststage [Cok91]
where
of four.
how
represents
detailed
by Ronald
be discussed in the
method,
method,
have
will
analysis refer
to
Tsiowest
Tsi0west
even
chapter
10ns
faster times
four
dequantize
idct
8ns
10ns
pipe
unload
6ns
noti-pipelined
32ns
and
3-36
can
thesis.
ined
Figure 3-26 Example Pipelined
versus
the
of Parallel
S. Cok [Cok91]. Improvements that
conclusions section of this
32ns
Non-pipelined Systems
be
made
The
modules used to
3-27. Each
implement the
is
module
rnmplntP
explained
decoding of a scan process are
in
mem
64x8
following this figure.
IL
Hde"Uant
r64xmi6
in figure
nnmplptfl
IL
mem
idct
|-64x8
ZE
ZE
start
detail
rnmplpfp
IL
7 coeff
greater
shown
unload
"?
scan
snannnmplptR
dec
scan
Figure 3-27 Scan

load
coeff
The loadcoeff module is that

the
loading
of
module reads
decoded,
buffer,
data from the
in the
number of MCUs
a complete signal
related
to
dequantization
this
module
for the detailed
The Huffman
decoded;
controls
part of the pipeline that
is
is
sent
module,
ready.
syntax of
decoding is
data
compressed
to
stream
decodes the
scan.
It
controls
into 8x8 blocks. The loadcoeff
be decoded. Once this
number of MCUs
has been
to the dequantize module. Control of the memory
is done
Using
aemptyright and afullright.
code
Decoding Modules
by
the
use
two
of
handshaking
these two signals data is only
Thus data
are not overwritten at
this handshaking.
steps.
when
any time. See the
Loading is done by
using two
accomplished
loaded
signals,
the
source
Huffman decoding.
First the DC
coefficient
is
then the remaining 63 AC coefficients are done. The module doloadcoeff
the Huffman
symbol of the
decoding process
for
each
loadcoeff module.
3-37
8x8 block
of
data. Figure 3-28
shows the
( 31
IN nu-mmc u s ou t
o a
s
a r
coeff
s c o n
reset
o o
o a
oef
omp I
do
clock
y_r
gh
I I
et e
(fur
oa
d ur
gh
_emp
ur
Figure 3-28 loadcoeff symbol
dequantcoeff
The dequantcoeff
dequantizing
done
by the
is done
module controls
by the dequantize
the
module.
dequantizing
1. Check for
full
symbol
signal on
the input buffer. When
and signal
buffers is
for the interface
used
that buffer is
full,
go
to unload step.
unloaded.
data, done by calling the dequantize module.
4. Check if output buffer is
empty.
When empty, load data to the
5. Goto step 1.
See the
and output
actual
steps of this module are:
2. Unload input buffer

3. Dequantize
8x8 blocks. The
Access to the input
dequantizecoeff module. Figure 3-29 is the
this module. The simplified
of
source code
for
3-38
of this process.
output
buffer.
by
^tnI
or
s c a n
equant
reset
o q
oef
et e
_comp
do_dequant_unload_ac
^tn d
ua n
do_dequant
dequont
clock
<yTn
4-
Jul I
IN a
mp I
eft
ight
mp t y
I I
UT
(fur
i ght
9ht(fur
mp t y
eft
ur
Figure 3-29 dequantcoeff symbol
idct
coeff
The idctcoeff
transform is done
idctcoeff
module
controls
by the idct module.
module.
Figure 3-30
the
dequantizing
Access to the input
shows
the
symbol
of
8x8 blocks.
and output
The
buffers is done
for the idctcoeff
actual
by the
module.
simplified steps of this module are:
1. Check for
full
signal on
2. Unload input buffer
the input buffer. When full go to
and signal
3. Do the inverse discrete
cosine
4. Check if output buffer is
that buffer is unloaded.
transform on the
empty.
data,
calling the idct
When empty, load data to the
5. Go to step 1.
See the
source code
for
unload step.
3-39
of this process.
module.
output
buffer.
The
a r
s c o n
idct
reset
i d
do
o a
coeff
i dc t
rnp I e t e
do i dc t
idct_coeff
dequant_coeff_complete
clock
Jul I
o
_emp
eft
t y
gh
I I
a
_emp
t y
gh
OUT
ef
(fur
Figure 3-30 idctcoeff symbol

unload
coeff
The
memory.
purpose of this module
This
module to
is to
control
module controls the access to the
do the
actual unloading.
interface
source code
of this module
a r
for
in
is
signal
symbol
input
buffer,
and calls
When the idctcoeffcomplete
the final buffer is unloaded, the scancomplete
Refer to the
the unloading of image data to the
of
signal
s c a n
o_u n
oef
oad_a c
omp I
coeff
et e
scancomplete OUT
do
clock
4-
full
left
Figure 3-31
unload
mp t y
unloadcoeff symbol
3-40
is
received and
this module. Figure 3-31 shows the
reset
i d
the dounload
to the decodescan module.
sent
format.
unload
display
ef
(fUT
t (fur
mem64x8 and mem64xl6
The
mem64x8 module
is the
mem64xl6 module
mem64x8 symbol.
memory
of the
64
element register
it has 16 bits
same except
Change the
modules are used
the output
is
dequantize module,
IN
TFT
per element.
each element.
Figure 3-32
data lines to 16 bits for the
size of the
in between
that has 8 bits for
stages
which
in the
pipeline.
Most data
shows
mem64x8.
are
bits,
The
the
These
except at
has 16 bit data.
dinl(7=0)
radrl(5:0)
wadr
me m64x
I (5:0)
we
mempr es e
4t
Idl
Figure 3-32
The
following is
description is
source code
list
given
in
of
for
appendix
dout 1(7:0)
mem64x8
Symbol
the remaining components that make up the pipeline. A short
each module.
For the
actual
interface used,
refer
to the VHDL
and
do loadAC
A.
do Ioad_coeff
The
modules.
dodecodecoeff
It has two basic
steps.
module
controls
The first is to
the
signal
do loadDC
do loadDC to operate,
and when
that step is complete the do loadAC module is signaled. When both steps have been
completed
in order,
a complete ack
is
returned
to the loadcoeff module.
3-41
do loadDC
and
These two
do load_AC
data. The do loadDC

block. Do loadAC
block. These
decode,
receive,
section
controls the
controls the
the 8x8
DIS
Huffman
Huffman
extend and nextbit.
The
in
section
of
of the
following
of the compressed
the DC
coefficient
remaining 63 AC
modules
to
3.3.5
by
of this
can
in
image
an
8x8
coefficients
accomplish
functionality of these routines
are also modules used
are mentioned
decoding
decoding
decoding
two routines use the
F.2.2. There
tables. These
Huffman
modules control the actual
in
their tasks:
be found in the
these routines to access the Huffman
thesis.
dequantize
The dequantize
it using the
module
quantization
takes the data that
were
Huffman decoded
and
dequantizes
table.
idct
The idct
module
is
behavioral
synthesis would
floating
point
does the
module
actual
model of
require
numbers.
rather
inverse transform
on
the dequantized data. This
the inverse discrete cosine transform.
complex
The transform
design considering the
was
split
into the
Coding
use
separable
this for
of cosines
and
one-dimensional
transform. Once the transform is complete, the data are sent to the unload
buffer.
dounload
The dounload
to the
display
module.
module
It is
then sends the data out to the
is
responsible
very
for unloading the decompressed image data
simple module
display module.
3-42
that first reads in the
input buffer;
and
3.3.5 Miscellaneous Modules
The
for
following is an abbreviated list of the remaining modules;
each module.
No
Quantization table
The
symbols or
interconnections
only the
purpose
is
stated
are given.
modules
following
for the
modules are used
loading
the
and storage of
quantization
table:
defineqtable : This
qaddr:
qmem:
The
module controls
the
address that accesses the
by this
inefficient
method of accessing
Qmem is the
very
actual
Huffman table
memory
implementation
poor
memory.
module.
register
used
the
where
of a
quantization
table is loaded
the
and was used
quantization
memory
banks for
stores
table
module.
better
upon
reset.
This is
table can be eliminated.
only
data
of
It is
of
the
implementing
is included in this
useful
very
once.
are stored.
Thus the
data is
was a
Refer to any
example
simulations
data.
quantization
only for writing data. This
memory,
A feature for speeding up
predetermined
of the quantization
memory that
It is
controlled
loading
module.
loading
when
of
testing
the
the
pipelined stages.
Huffman decoder loader

The
modules
following routines are used for the loading,
tables. There are two Huffman
The
tables,
one
for the DC
storage and access
data,
and
to the Huffman
the other for the AC data.
routines are :
1. definehtable
Controls the
following
tables.
3-43
routines
that read in and load Huffman
Routines
huffacdcsel,
and
huff_reg256by8,
,huff_read_in,
two modules of each
preset
they
huffbitsloader,
loader,
huff_reg256by8,
huffên.
huff2_256by8,
huff_reg256byl6,
huff_regl6by8: These
3.
huffcontroller
huffloadcode,
huffloadsize,
huff_reg256byl6,
data. These
huffJen
huffacdcreg,
huffvals loader,
modules are used
type;
one
and
tables, it
data. This is
useful when
can
be decoded
testing
the
other
feature for speeding up
are preloaded with a standard set of tables.
of
huff_regl6byl6
and
to store the Huffman tables. There are
is for the DC table
registers contain a special
the same set
is
are
load, huff_bits_addr, huff_bits, huff_vals_addr, huff_vals, huffjencntr,
huff
2.
definehtable
by
controlled
without
the pipeline
simulations.
Upon
Thus, if a test image
the need
stages.
is for AC table
for
uses
including the table
The time to load the tables
eliminated.
huffacdcsel,
which
huffacdcsel 16
table, DC
or
AC,
and
provide
huffacdcsel6: These
modules are used
input to the Huffman decoder
to select
modules
decode
and receive.
Miscellaneous
regl6
and reg32
These
are general purpose registers of size
respectively.
3-44
16
and
32 bits
4. Results
4.1
Timing Diagrams
Figure 4-1
shows a
expanded view of figure
using the
structural
timing diagram from
4-1 is
VHDL
shown
model.
a simulation of the
in figure 4-2. A 16x16
Using a
clock with a
decoding of the compressed data took 450,898 ns.

quantization
data. The
dojdct
seen
table,
DC huffrnan table,
operation of the pipeline can
and
downloading
signals.
that this module has the
be
The
10
image
nanosecond
compressed
AC hufffnan table
seen
pixel
VHDL decoder. An
and
execution
pipeline.
4-1
decoded
period, the
data
contained one
the compressed image
by examining the do load, dodequant,
By examining the doJdct transform
longest
was
time,
and
signal, it
can
thus controls the speed
be
of the
4-
4-
4-
4-
4-
+>
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-4
4-4-4-
4-
4-
4-
4-
4-
4-
1*
4-
4-
h
4
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
4-
Z!_
4-
4-
4-
4-
4-
4-
I
4
4-
3c
4-
4-
4-
4-
1.
i
r-f
r-H
XJ
lH
Figure 4-1
Decoding Timing Diagram
4-2
4-44-4-4-
4.
444-
4i.,l
4-
44444
4-
-fc
4-
4-
444444-4-444444444
444-44444
444
444-44-4-4-4-444-4-4-44-4
4-
44
44
444444-44444-44-44-4
4444444444444-444
4444444
444
4444
4-
4444
44
4-
44
444
71
j_>
4->
Ifl
Figure 4-2
Decoding Timing Diagram, Expanded
4-3
a.
i->
(>
01
[)
Figure 4-2
Timing Diagram,
4-4
Expanded
Continued
?o
01
Figure 4-2
r-<
Timing Diagram,
4-5
Expanded
Continued
Figure 4-2
Timing Diagram,
4-6
Expanded
Continued
Figure 4-2
Timing Diagram,
4-7
Expanded
Continued
4>
"eT
><
Figure 4-2
Timing Diagram,
4-8
Expanded
Continued
4.2 Decoded Images

A 16x16
image
was chosen to
chosen
because it
or column.
shown
pixel
The
image
was used
limit the time
to test the
needed
8x8
contained more than one
image is
original
in figure 4-4. For
all
shown
images
to
decoder implemented in VHDL. A
the simulations. The 16x16 size
run
block,
and
had data in
in figure 4-3. The
shwon
data
black,
values are
and
white.
Original
106
106
106
106
106
106
106
106
109
115
107
94
117
129
161
149
147
157
142
150
148
137
155
147
160
160
160
160
160
160
160
160
160
157
161
163
156
188
173
163
177
174
172
174
177
177
175
172
196
185
174
172
179
184
182
177
171
184
174
191
187
150
156
158
163
155
148
149
106
106
106
106
106
106
106
106
109
115
107
94
in
129
161
149
147
157
142
150
148
137
155
147
160
160
160
160
160
160
160
160
160
157
161
163
156
188
173
163
177
174
172
174
177
175
172
196
185
174
172
179
184
182
177
171
184
174
191
187
150
156
158
163
155
14 8
149
106
106
106
106
106
106
106
106
109
115
107
94
117
129
161
149
147
106
106
106
106
106
106
106
106
109
115
107
94
117
129
161
149
147
157
142
150
148
137
155
147
160
160
160
160
160
160
160
160
160
157
161
163
156
188
173
163
177
174
172
174
177
177
175
172
196
185
174
172
179
184
182
177
171
184
174
191
187
150
156
158
163
155
148
149
157
142
150
148
137
155
147
160
160
160
160
160
160
160
160
160
157
161
163
156
188
173
163
177
174
172
174
177
177
175
172
196
185
174
156
Figure 4-4 Test Image
4-9
Original,
Values
was
more than one row
actual pixel
in this chapter, 0 is for
Figure 4-3 Test Image
small
255 is for
The
original
image
compression software.
methods.
The
The
was
standard,
methods are.
data
and the
compressed
a standard.
difference images
data
the VHDL
The three
Group
decompressed using four different
Group
decompression routine, the
implementation. The Independent JPEG

other methods were compared
showing how
were created
Figure 4-5 through figure 4-15
difference data for
was then
Independent JPEG
program and
then used as
and
then compressed using the Independent JPEG
methods used are: the
XV software, the dec.c
Group
was
show the
accurate the
decompressed
to this
decompressing
images,
the actual
all methods.
Figure 4-5 Independent JPEG
Group
Software Decompression Result, Image
97
106
114
114
106
100
100
103
104
117
106
90
112
146
154
147
161
154
145
141
143
150
158
162
163
168
158
150
157
162
161
164
159
155
153
160
170
172
164
155
171
172
172
180
183
169
164
179
195
187
179
177
181
187
189
188
178
179
179
185
184
164
151
161
162
160
152
136
117
104
100
100
101
110
108
108
114
109
98
96
113
129
149
158
155
149
148
150
131
146
146
142
156
168
164
159
166
165
162
158
155
155
158
161
170
184
180
168
172
177
174
173
173
171
174
182
191
191
182
172
169
182
182
176
177
177
179
190
189
161
152
161
161
156
154
149
120
103
96
106
109
101
100
109
109
103
103
106
112
132
154
162
132
118
110
113
115
108
104
106
104
115
116
100
96
115
138
146
152
148
144
143
147
149
149
148
145
163
166
156
155
160
166
171
156
162
163
156
157
168
175
175
161
170
170
174
185
177
165
168
180
190
190
176
168
176
185
187
179
183
172
175
192
181
161
165
155
162
161
150
142
146
151
152
136
155
146
140
162
164
151
158
162
161
159
160
163
164
159
154
153
190
184
162
176
181
169
172
182
173
170
179
189
186
171
158
Figure 4-6 Indepenent JPEG
Group
Software Decompression
4-10
Result,
Values
Figure 4-7 XV Result, Image

97
106
114
114
106
100
100
103
104
117
106
90
112
146
154
147
161
154
145
141
143
150
158
162
163
168
158
150
157
162
161
164
159
155
153
160
170
172
164
155
171
172
172
180
183
169
164
179
195
187
179
177
181
187
189
188
178
179
179
185
184
164
151
161
162
160
152
136
117
104
100
100
101
110
108
108
114
109
98
96
113
129
149
158
155
149
148
150
131
146
146
142
156
168
164
159
166
165
162
158
155
155
158
161
170
184
180
168
172
177
174
173
173
171
174
182
191
191
182
172
169
182
182
176
177
177
179
190
189
161
152
161
161
156
154
149
120
103
96
106
109
101
100
109
109
103
103
106
112
132
154
162
132
118
110
113
115
108
104
106
104
115
116
100
96
115
138
146
152
148
144
143
147
149
149
148
145
163
166
156
155
160
166
171
156
162
163
156
157
168
175
175
161
170
170
174
185
177
165
168
180
190
190
176
168
176
185
187
179
183
172
175
192
181
161
165
155
162
161
150
142
146
151
152
136
155
146
140
162
164
151
158
162
161
159
160
163
164
159
154
153
190
184
162
176
181
169
172
182
173
170
179
189
186
171
158
Figure 4-8 XV Decompression Result
Values
Figure 4-9 XV Difference Table
4-11
Figure 4-10 Dec.c
Result, Image
97
106
115
115
107
101
101
104
104
118
106
91
113
145
153
147
161
153
145
140
143
150
157
162
162
167
158
149
157
162
161
164
159
154
153
160
169
172
164
154
171
172
172
179
183
169
163
178
194
186
178
176
180
186
188
187
178
178
179
184
184
163
150
160
161
159
151
135
118
105
100
101
102
111
109
108
115
110
99
97
113
129
149
157
154
148
147
149
130
146
146
142
155
167
164
158
166
165
161
157
155
154
157
160
169
183
179
168
171
176
173
172
172
171
173
182
191
191
182
172
168
181
181
176
177
176
179
190
188
160
152
160
160
156
153
149
121
104
97
107
110
101
100
109
110
104
104
107
113
132
153
161
131
118
110
114
115
109
105
107
105
116
116
101
97
116
138
146
151
147
143
143
146
148
148
147
144
162
165
155
154
160
166
170
155
162
162
156
157
167
174
174
160
170
170
173
184
177
164
167
180
189
189
175
167
175
184
186
179
183
172
174
191
180
160
165
155
162
161
149
142
145
151
151
135
155
146
140
162
163
150
157
161
160
159
160
163
163
159
153
153
190
183
162
176
181
168
171
182
173
170
179
188
185
170
157
Figure 4-11 Dec.c Result, Values

0
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
Figure 4-12 Dec.c Difference Table
4-12
Figure 4-13 VHDL
Result, Image
97
106
114
114
106
100
100
103
104
117
106
90
112
146
154
147
161
154
145
141
143
150
158
162
163
168
158
150
157
162
161
164
159
155
153
161
170
172
165
155
171
172
172
180
183
169
164
178
195
187
179
177
181
187
189
188
178
179
179
185
184
164
151
161
162
160
152
136
118
105
100
100
101
110
109
108
114
109
98
96
113
130
149
158
155
149
148
150
131
146
146
142
156
168
165
159
166
165
162
158
155
155
158
161
170
184
179
168
172
176
173
173
173
171
174
182
191
192
182
172
169
182
182
176
177
177
179
190
189
161
152
161
161
156
154
149
121
103
96
106
109
101
100
109
109
103
103
106
112
132
154
162
132
118
110
113
115
108
104
106
104
115
116
101
96
115
138
146
152
148
143
143
147
150
149
148
145
162
166
156
154
160
166
171
156
163
163
157
157
168
175
175
161
171
171
174
185
177
165
168
180
190
190
176
168
175
185
187
179
183
172
175
192
181
161
165
156
162
161
150
142
146
151
152
136
155
146
140
162
164
151
158
162
161
159
160
163
164
159
153
153
190
184
162
176
181
169
172
182
173
170
179
189
185
171
157
Figure 4-14 VHDL Result, Values

0
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
Figure 4-15 VHDL Difference Table
From the
results
it
can
Independent JPEG Groups

errors
that
were
only
be
seen that the
software.
XV
The dec.c
plus or minus one
from the
4-13
program was a perfect match to
program and
standard.
The
the VHDL software
reason
the
had
for the differences
is
most
use
likely due
to
Independent JPEG group
4.3 Synthesis
manuals
synthesis
for
the IDCT. The dec.c and VHDL code
use other methods
IDCT,
the XV software and
while
for the IDCT.
of a module
section contains an example synthesis of one module used
decoder. The
step in the
of
1-D transforms to implement the
separable
This
implementations
differing
be
controller module will
as the example module.
be
synthesis of the module will
information
more
is to
on
run the compiled
produce a symbol
how to
VHDL
for the module,
Only
The first step
Autologic
through the
and a schematic of
the results
of the
of each
Refer to the Mentor Graphics
presented.
perform the synthesis.
code
in the design
software.
of the
This
will
the circuitry needed to implement
the module. Figure 4-16 shows the symbol created, figure 4-17 and shows the circuit
diagram.
or
t Jecode
reset
i/cr
k_r eq ( 2- 0)
r eq_er r
omp I
e_o c
oc
(fur
od
(fur
omp I
e (fur
dec
clock
4-14
Figure 4-17 Controller Schematic
4-15
Once the
be
constructed
before the
only for
from
be designed
have been created, the
Input,
standard cells.
circuit can
the standard cells.
with
larger module, the
pads would not
be
circuit must
be
prepared to
be
power and ground pads must
output,
an example of the synthesis of a complete
as part of a
of
schematic and symbol
Note,
the pads
design. If module
needed.
was
Figure 4-18
the pads to the controller circuit. The schematic symbol
is
used
added
here
to be synthesized
shows
the
used on a sheet
addition
to add the
pads.
-OW-i
^^
XI2IPD
control
st q r
er
All
e cod e
2'
resel
req
t o
work_req(
e I e
' n
0PADI2
t r
decDd i ng
[lock
XI2IPD
W>-J_]
0)
err
mp I
k
c o
mp I
e1 e
iii
-i>j>-a
0PADI2
Al.
XI2IPD
0PADI2
OUU
D-i^t
X I 2 I PD
All
^>i>HD
0PADI2
UL
D-
Al.
-JH>-D
QPADI2
QUI
04J4-
XI2IPD
Al.
0PADI2
Figure 4-18 Controller with I/O Pads
4-16
are
Once the
called
pads
have been added,
IC. In IC the
resulting layout is
complete
design,
model), to
the circuit can
standard cells can
shown
except
be
create a complete
module
decoder chip
in Mentor Graphics layout tool
be automatically
in figure 4-19. This
for the IDCT
opened
at
the
4-17
placed and routed.
whole procedure could
(the IDCT
cell
level.
module
The final
be done
is only
on
the
behavioral
Figure
4-
1 9 Controller Layout
4-18
5. Conclusion
5.1 Accomplishments
This thesis
was able to produce a
VHDL design
of a
JPEG decoder. The
major
accomplishments that were achieved are:
1 A
"C"
program that was used as a pseudo
the JPEG decompression standard
2. A VHDL
This
structural
excludes the
design
IDCT
of a
behavioral
model
to
understand
how
worked.
baseline JPEG decoder that
module which
is only
can
behavioral
be
synthesized.
model and
is
not
synthesizable.
3. A test
output
4. The
bench,
plus additional software
from the decoder
that can provide stimulus and receive
during a simulation.
successful simulation of
the decompression of a 16x16 image using the
decoder designed in VHDL.

5. The
synthesis
of
modules,
see
lessons learned for
more
comments
on
this
achievement.
5.2 Improvements
Improved IDCT: The
of
computations
implementing
and
current
time.
IDCT
used
complete
in the VHDL design is very inefficient in terms

investigation
the discrete cosine transform should
consumes
available
methods
method
for
for
Since this
stage
is the
most
critical,
it may
even
have to be
custom
the greatest amount of time in the pipeline;
5-1
the
be done. Then the best
implementing the DCT in hardware should be selected.

it
of
designed. Note,
layout
design
a custom
of the circuits at
the
silicon
Interface: If the decoder device

output modules can
the
decoder is
changed
be
for any input
Testability: One
in.
be done
by hand,
by a synthesis unit.
not
to be used in a system, changes to the
be
should
input
and
changed to meet the need of the system
and
DoUnload
modules would need to
be
and/or output requirements.
of corrupt
proper
that
would need
to be added would be to
the only method to test this
image. The few ISR (interrupt
in the design for
would
were
major requirement
only indicators
involve using VHDL for simulation, but the
Only the NextByte
testability features. Currently
are
level
They
changed.
being used
would still
status
register)
errors
data. The design
fabricated is very time inefficient. To
include
full
a complete
that have been included in the design
should
Running
operation.
device is to decode
incorporate
methods to test submodules
test on every device
operational
avoid this method
testing,
of
some method
of
designing for testability should be included.

Baseline: The decoder
would
would
involve
be
should
incorporating
added
be improved
the
this
would necessitate
blocks in
each
MCU
for
it
meets all
baseline
now used
would
(As
an
the addition of multiscan
have to become
example,
a variable
RGB MCU
will
have
controls
images
at
of
circuitry
would need
images. Also the
size, instead
This
requirements.
improvements. Additional
to allow for the restart marker to be used. Color
decoded;
8x8 block
following
until
the
to
number of
hardcoded
least three 8x8
be
blocks,
one
one
each color).
Pipeline: Two improvements
improvement is
can
be
made
to change the pipeline from
5-2
to the pipelining
single-buffered
to
of
the decoder.
One
doubled-buffered. A
double buffered pipeline

for the
allows each stage of the pipeline to work on
stage to unload the
next
methods used
in
load
buffer. Figure 5-1
shows the
data without waiting
two type of
buffering
a pipeline.
dequant
uffer
Duffer
unload
luffer
IDCT
Single Buffered
uffer
load
lequant
unload
IDCT
luffer
Double Buffered
Figure 5-1 Two Types
of
Buffering in Pipelines
In the double buffered pipeline, the load

the dequant module is unloading buffer
buffer has been
filled,
and
module can then switch
back to
separate
other
modules
that
implemented
as two
transform is
being
each
other modules work
pipeline
implement
1-D transforms in
performed at
any
by the deqaunt
while
module, the load
the A buffer. This continues until the
filling
improvement to the
first fill buffer A. Then
the load module can fill buffer B. Once the B
the A buffer has been emptied
been completely decoded. The

The
module will
in the
fashion.
is to divided the IDCT

1-D
one time.
With this
module
Currently
transform.
one module.
5-3
same
image has
the
implementation,
By separating
into two
IDCT
only
is
one
the transform into two
separate
modules,
Combining
1-D
each
transform
be operating
can
this with a double buffered pipeline
on
data
simultaneously.
further increase the
will
speed of the
IDCT.
To increase the
must
any
speed of the
be improved. Since the IDCT
other module.
Using
choosing the
improvements
that
module
the module that
is the slowest, it
is
the slowest
in the
pipeline
be improved first before
must
double buffered pipelined, splitting the transform into two
modules and
decoder,
most efficient method
will speed
for
implementing
the transform are
up the decoder.
5.3 Lessons learned

The
following
Anyone just starting

1
paragraph contains
VHDL design for the first time
Designing with VHDL using
the abstract
modeling to
useful.
top down design
during
should
the course
this thesis.
find this information helpful.

does
approach
of
work.
The ability to
mix
the design (behavioral model) with lower levels (structural
upper part of
models) is very
lessons learned
To be
fully understand
able to write the
how the device
design
operates
as an abstraction
is extremely
useful.
using behavioral
Then to be
able
to substitute in structural parts and still have a complete working device is an even greater
advantage.
operates
of
Throughout the
properly
behavioral
would
2. The
complete structural
as a whole.
models and a
have benefited greatly
Simulation time
few
synthesized.
can also
models
one
be
is
modules,
such as
As the design
5-4
able
to ensure that the
reduced
by using
that need to
by the use of the complete top
use of more medium size
design to be
structural
design
the
stands
number
be tested. This design
down design in VHDL.
load_htable module,
now,
large
device
most
of
the
will allow
the
modules
are
interconnected in
the decoder
module.
This
creates one
disk
synthesized with the current system power and
by the
needed
create a
grouped
into
design that
can
be synthesized, many
a small number of medium sized
purposes, these
medium sized modules can
module
not
would
could
be
determines the
for
used
be hand
sized modules as small as
experience.
Rather,
synthesis.
connected at
one
modules are collections of small modules
that
3. The
use of medium and small
modules
is very quick,
the small modules
modules and
to let a
4. Two
keep
of
is run,
have been tested, they
having
test
track
of all
interconnect to
in the
benches
can
on
be
can
be
For
simulation
one module.
This large
used.
sized
modules,
once
the number of medium
be too tedious. What
the system in
use and some
size of a small state machine.
that it performs. Medium
one another.
device.
Testing
small
there are few
signals.
Once
medium
sized
simulation of the
since
be interconnected into
these small and medium modules is very
to check the results and force the proper inputs each time a
bench,
program remember all
additional
help
on
"tasks"
be done very thoroughly
tested. The use of test
helpful. Instead
simulation
and can
blocks
depends
two
or
be
should not
is typically the
a small module
module will
should
to be
would
which
modules,
By keeping
possible, the interconnection
I have found that
small
big
into the days. Thus to
the medium
the chip level.
size of a small or medium module
small
modules,
that is too
Also the time that
be interconnected in
have only
Usually
space.
module
current system to synthesize this module would run
actually
synthesized,
large
written
in VHDL
can
be
written one
time. It
is
lot
easier
the details that need to be checked.
hints for coding in VHDL
are
to use as many variables as possible and
the interconnects. With a large module,
5-5
such
as
the decoder that
connected
The
signals.
be
small
many
modules, it
was
simulator whenever
are
only
events could
are
event
any
be
analyzed
for
they
simulation
track of all the
possible
times.
are changed.
have
in
must
interconnecting
Variables
be
shows
should
checked
very time
are
A tool that
By
a simulation
cutting down
the activity
is reduced,
on
and
by
the
consuming.
of each
high transaction traffic, but few
improvements.
checked
Signals
them, thus they
on
that
signals
it is
number of times
up
occurs
used whenever
be helpful. The
signal would
signal, the
keep
use of more medium sized modules will solve this problem.
used whenever possible to speed
Variables
difficult to
actual
the events on a
thus simulations
faster.
5. The design
design
was
of the scan
decoder
broken down into
with a pipeline was
smaller parts
product of the pipeline was that the
in the improvements to the
Adding
very
useful.
By using
pipeline, the
that could be tested individually. The
device
was able
pipeline
other
by
to process compressed data faster.
from the
previous section will
increase the
speed of the pipeline even more.
6. One
additional
lesson learned from programming in VHDL is it
programming language.
designing
circuits.
VHDL
state machines.
It is
as a
Early
This is
very difficult
programming
when old methods
and
on
in the design, the
an old method
inefficient
language,
is
used
state machines
on new ones.
5-6
be thought
of as
espresso method was used
to design state
method when used
coding
have to be traded in
that
should
in VHDL.
is very
simple,
for
machines with
By thinking
of
there are times
Bibliography
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Acoustics, Speech,
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vol. 30, no. 7 (July 1991), pp.
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Pennebaker, William B., "Understanding
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Inform,
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Kato, S., A "Single Chip Compression/Decompression LSI Based on
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Anvantages, Applications. Academic Press, Inc. London, 1990.
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Miller, G. D., "Multiprocessor DSP Architectures
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1993)
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and
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pp. xviii
Merriam- Webster
Inc.,
xxiv.
1986.
Gersho, Allen, "Improved Decoder for Transform Coding
Application to the JPEG Baseline

vol.
1 (Feb
Standard,"
no.
System,"
2, (Feb 1992)
pp.
IEEE Transactions
251-254.
on
Appendix A
VHDL Source Code
jpeg
DESCRIPTION:
Test bench for JPEG decoder
(entity)
result_data_ack
jpeg_entity
Purpose
bench
test
end
for
jpeg
port
Author
Douglas A.
Created
12-Mar-1994
Revised
Carpenter
library
library ieee;
ieee.
ieee.
use
library
use
use
use
display
result_data
all;
.package_l
end
all;
std_
my_components;
.decoder
my_components
.memory.
use
my_components
all;
compare. all;
is
jpeg;
Jpeg
DESCRIPTION:
Test bench for JPEG decoder
Name
(architecture)
std
jpeg_arch
Purpose
bench
test
decoder/encoder
Author
for
jpeg
std_
architecture
Douglas A.
Carpenter
12-Mar-1994
Created
in
0);
result_data_ack
out
complete
in
component;
byte
signal
next
signal
cmprssed
ulogic
vector
signal
inc data
signal
read
(7
reg
data
downto
decode
signal
start
decoding
signal
complete
signal
complete
signal
intr
signal
isr
logic
ulogic
std
ulogic
std_
ulogic
std
ulogic
std
ulogic
std
ulogic
0)
ack
err
signal
std
:
all;
COMPONENT:
--
.all;
myjpackages;
jpeg
downto
(7
std_ulogic) ;
use
end
in
std_ulogic;
DAC
clauses
std_logic_1164
my_coraponents
entity
std_ulogic);
std_ulogic;
my_packages
library
in
(result_data_valid
std_ulogic_vector
and
0);
component;
component
decoder/ encoder
std_ulogic;
out
downto
std_ulogic_vector (7
Name
std_ulogic;
out
result_data_valid:
result_data
use
in
read_err
COMPONENT;
ulogic
ack
ulogic
data
vector
downto
(7
3);
std
signal
reset
signal
clock
signal
result
data
signal
result
data
ulogic
vector
signal
result
ulogic
ulogic
(7
downto
data
ulogic
val id:
0)
ack
std_
ulogic
DAC
begin
Revised
architecture
jpeg_arch
is
jpeg
of
constant
CLOCK_CYCLE
time
:=
constant
WAIT_TIME
time
:=
memory
port
5ns;
map
next_byte_req,
cmprssed_data,
inc_data_ack,
15ns;
read
err) ;
component
port
memory
(next_byte_req:
in
cmprssed_data :
std_ulogic_vector
end
(7
dec
std_ulogic;
decoder
out
downto
port
0);
map
(clock,
inc_data_ack
out
std_ulogic;
start_decode,
read_err
out
std_ulogic);
decoding,
complete,
component;
complete_ack,
component
intr,
isr_data,
decoder
control
port)
inputs/outputs
reset,
clock
in
std_ulogic;
start_decode
in
std_ulogic;
cmprssed_data,
decoding
out
std_ulogic;
next_byte_req,
complete
out
std_ulogic;
inc_data_ack,
complete_ack
in
std_ulogic;
read_err,
intr
out
std_ulogic;
result_data_valid,
isr data
out
std_logic_vector
(7
in
reset
result_data,
result data ack) ;
0);
downto
std_ulogic;
compressed
cmprssed_data
std_ulogic_vector
(7
next_byte_req
inc data ack
TheDisplay
display
in
port
in
downto
data
map
result_data_valid,
result_data,
0);
out
std_ulogic;
result_data_ack,
in
std_ulogic;
complete) ;
A-l
out
std_ulogic_vector
inc_data_ack
out
std_ulogic;
readerr
out
std_ulogic);
cmprssed_data
clk_process
begin
<=
clock
for CLOCK_CYCLE ;
wait
<=
clock
'
01
end
process
memory;
for CLOCK_CYCLE ;
wait
end
"l
(7
0) ;
downto
process
clk_process;
COMPONENT:
memory
DESCRIPTION:
compressed
data memory, test bench (architecture)
process
begin
Name
FALSE
assert
Purpose
severity NOTE;
<=
reset
start_decode
'0';
complete_ack
<=
'
'
<=
USE
<=
file
reset
wait
for
30ns;
'
'
'
<=
'
until
wait
for WAITJTIME;
<=
'1');
0';
(complete
wait
until
wait
for WAIT_TIME;
'
<=
/home/ stul/dac4 927/ jpg/vhdl.dat";

time
WAIT_DELAY
15ns;
until
wait
for WAITJTIME;
<=
variable
linel
line;
variable
d_string
string (1
variable
good
boolean;
variable
d_byte
downto
=
'1');
to
60);
std_ulogic_vector
0) ;
variable
integer;
variable
d_char
character;
begin
1';
(complete
wait
complete_ack
memory is
process
(decoding
wait
complete_ack
of
in
is
TEXT
begin
30ns;
start_decode
memory_arch
IN_FILE:
constant
start_decode
std.textio. all;
architecture
'0';
"
for
wait
DAC
12-Mar-1994
Revised
for WAIT_TIME;
reset
Created
'1';
memory module
Author
<=
wait
memory_arch
"Started"
report
'0');
<=
'
'0';
<=
cmprssed_data
for WAIT_TIME;
assert FALSE
'
<=
inc_data_ack
read_err
'0';
"00000000";
wait
report
"Decoding
wait
end
(not
while
ENDFILE
READLINE(IN_FILE,
process;
jpeg_arch;
for WAIT_DELAY;
READ
(linel,d_string,
(good)
not
report
memory
data memory, test bench
good) ;
then
FALSE
assert
compressed
'1');
(IN_FILE) ) loop
linel);
wait
if
COMPONENT:
DESCRIPTION:
complete
severity ERROR;
end
( next_byte_req
until
"bad
read
to
string"
severity NOTE;
(entity)
read_err
'1'
<=
after
WAIT_DELAY;
else
j
Name
Purpose
time when
memory module,
provides
byte
at
case
Douglas A.
Created
Revised
1;
(j
d_char
requested.
Author
:=
while
memory_entity
Carpenter
loop
d_string(j);
:=
d_char
when
12-Mar-1994
<61)
'0'
is
=>
d_byte(7
downto
4)
=>
d_byte ( 7
downto
4 )
=>
d_byte(7
downto
4)
=>
d_byte ( 7
downto
4 )
=>
d_byte ( 7
downto
4 )
=>
d_byte ( 7
downto
4 )
=>
d_byte ( 7
downto
4 )
=>
d_byte(7
downto
4)
"0000";
when
'1'
"0001";
library and
library ieee;
use
clauses
when
when
use
use
ieee.
ieee.
'2'
"0010";
std_logic_1164
'3'
"0011";
all;
std_logic_1164_extensions.
all;
when
'4
'
"0100";
use
when
std.textio. all;
'5'
"0101";
library
use
when
my_packages;
my_packages
.package_l
"0110";
all;
when
"0111";
entity memory is
port
(next_byte_req
in
'6'
std_ulogic;
A-2
'7
'
8'
when
=>
d_byte(7
downto
4)
=>
d_byte ( 7
downto
4 )
=>
d_byte(7
downto
4)
=>
d_byte(7
downto
4)
=>
d_byte(7
downto
4)
=>
d_byte ( 7
downto
4 )
=>
d_byte ( 7
downto
4 )
=>
d_byte(7
downto
4)
=>
d_byte(7
downto
4)
end
memory_arch;
"1000";
191
when
COMPONENT:
DESCRIPTION:
"1001";
'A'
when
decoder
decoder module(entity)
"1010";
'B'
when
Name
"1011";
'C
when
Purpose
"1100";
'D'
when
Author
'E'
JPEG baseline
:
Douglas A.
Created
"1101";
when
decoder_entity
decoder
Carpenter
12-Mar-1994
Revised
"1110";
'F'
when
library and
library ieee;
"1111";
when
oth
others
"0000";
end
d_string( j+1)
:=
d_char
case
=>
1'
when
d_byte(3
downto
use
std.textio. all;
library
0)
use
=>
d_byte ( 3 downto
0)
=>
d_byte(3 downto
0)
'2'
when
"0010";
'3'
when
=>
d_byte(3 downto
0)
=>
d_byte ( 3 downto
0)
"0011";
'4
when
'
"0100";
'5'
when
=>
d_byte ( 3
downto
0)
"0101";
'6'
when
=>
d_byte ( 3 downto
0)
"0110";
'7'
when
=>
d_byte(3 downto
=>
d_byte(3 downto
0)
"0111";
'8'
when
0)
"1000";
.9.
when
=>
d_byte ( 3 downto
0)
d_byte(3 downto
0)
"1001";
'A'
when
=>
"1010";
B1
when
=>
d_byte(3 downto
=>
d_byte(3 downto
0)
"1011";
'C
when
0)
"1100";
'D'
when
=>
d_byte(3 downto
0)
"1101";
'E'
when
=>
d_byte ( 3 downto
0)
"1110";
F1
when
=>
d_byte(3 downto
0)
"1111";
when
2;
<=
cmprssed_data
d_byte
for
PROP_DELAY;
inc_data_ack <= '1'
wait
after
WAIT_DELAY;
'0');
inc_data_ack <= '0' after WAIT_DELAY;
wait until
'1');
(next_byte_req
end loop;
wait
( next_byte_req
until
my_compon ents;
isr. all;
use
my_components
.nextbyte.
use
my_components
use
my_components
use
my_components
use
my_components
use
my_components
.dec_frame.
use
my_components
use
my_components
.define_htable.
all;
use
my_components
.define_qtable.
all;
use
my_components
qaddr
use
my_components
qmem. all;
use
my_components
.dequantize.
use
my_components
find_soi
fr_header
f ind_eoi
inc_data_ack
end
all;
all;
all;
all;
all;
regl6. all;
my_components
.reg32.all;
my_components
use
my_components
.dec_scan.
use
my_components
.dec_scan_header.
use
my_components
.huff_reg256byl6.all;
use
my_components
use
my_components
use
my_components
.huff_regl6byl6.all;
use
my_components
huf f_regl6by8
use
my_components
compute_MCUs
find_sos. all;
all;
huff_reg256by8
huf f 2_reg256by8
all;
all ;
.
all;
all ;
all;
use
my_components
.mem64by8.
use
my_components
.mem64byl6.
use
my_components
use
my_components
.dequant_coef
use
my_components
use
my_components
.idct.
use
my_components
use
my_components
.do_unload.
use
my_components
.do_load_coef
use
my_components
.do_loadDC.all;
use
my_components
.do_loadAC.all;
use
my_components
.decode.
use
my_components
.receive.
use
my_components
use
my_components
.nextbit.
use
my_components
.huf
use
my_components
.huf
use
my_components
.huff
all;
load_coef f
idct_coef f
all;
.
all;
all;
all;
all;
unload_coef f
all;
all;
all;
all;
all;
extend. all;
all;
f_acdcsel
all;
f_acdcsell6. all;
acdcsel6. all;
entity decoder is
loop;
read_err
all;
use
port
end
f ind_sof all;
use
if;
all;
controller. all;
end
all;
my_components
after
WAIT_DELAY;
use
case;
all;
.package_l
othe
"0000";
==
my_packages;
my_packages
library
"0001";
ieee.std_logic_1164_extensions.all;
"0000";
end
ieee. std_logic_1164
use
is
'0'
when
clauses
use
case;
d_char
use
<=
'
<=
'
'
'
A-3
inputs/outputs
in
std_ulogic;
start_decode
in
std_ulogic;
decoding
process;
control
clock
compressed
data
in memory
start
decoding
decode
out
std_ulogic;
ack
start
signal
complete
out
decoding
std_ulogic;
complete
complete_ack
complete
in
decoding
std_ulogic;
acknowledge
intr
out
std
interupt
ulogic;
flag
isr_data
0);
intr
stat
out
std_logic_vector (7
in
std_ulogic;
compressed
cmprssed_data
0);
for
of
next
read_err
error
compressed
port
data
std_ulogic;
reset
in
std_ulogic;
decoding
out
std_ulogic;
complete
out
std_ulogic;
intr
out
std_ulogic;
ack
in
std_ulogic;
req_err
in
std_ulogic;
out
find_soi
:
in
std_ulogic;
reset
in
std_ulogic;
work_req
in
(2
result_data
out
std
ulogic;
in
std
ulogic;
in
std
ulogic;
out
std
ulogic;
out
std
ulogic;
out
std
result_data_ack
0);
in
ulogic;
out
std
ulogic;
out
std
logic
(clock
in
std
ulogic;
reset
in
std
ulogic;
in
std
ulogic;
in
std
ulogic;
in
std
ulogic;
ulogic;
isr
latch
req
err
next
isr
std_ulogic);
decoder;
req
latch
in
isr data
downto
COMPONENT:
DESCRIPTION:
end
decoder
decoder module
port
decoder_arch
find
work
sof
decoder
module
Douglas
A.
Created
12-Mar-1994
in
req
std_ulogic_vector
Purpose
(2
downto
data
Carpenter
std_ulogic_vector
DAC
next
Revised
(7
decoder_arch
reset
isr
reset
to
output
0);
incoming
isr_data
downto
0);
outgoing
:
isr_latch
latch
the
is
incoming
acknowledge
the
clock
out
std
htable
ack
in
std
ulogic;
in
std
ulogic;
out
std
ulogic;
out
std
ulogic;
out
std
ulogic;
out
std
ulogic;
out
std
logic
isr
std_logic_vector (7
std_ulogic;
out
std_ulogic;
data
end
latch
in
qtable
req
out
std
ulogic;
htable
req
out
std
ulogic) ;
(clock
in
std
ulogic;
reset
in
std
ulogic;
component;
fr header
component
port
component;
work
component
nextbyte
clock
in
std
ulogic;
reset
in
std
ulogic;
inc_data_ack
in
std
ulogic;
cmprssed_data
in
in
req
std_ulogic_vector
port
downto
(2
data
std_ulogic_vector
(7
downto
0);
read_err
in
std
ulogic;
next_req
in
std
ulogic;
next_byte_req
data
out
std
ulogic;
downto
(7
std_ulogic_vector
(7
downto
std_ulogic;
std_ulogic;
in
std_ulogic;
out
std_ulogic;
out
std_ulogic;
out
std_ulogic;
out
std_ulogic;
out
std_logic_vector
latch
out
std_ulogic;
y latch
xy data
out
std_ulogic;
isr
latch
req
err
next_ack
err
next
isr
0);
std_ulogic;
out
std
downto
ulogic
component;
std
component
ulogic
vector
controller
end
port(
clock
std
ulogic;
A-4
in
0) ;
x
Ir
ene!
ack
req
latch
isr data
out
0),
in
ack
ack
out
0),
in
in
next
err
std_ulogic_vector
vector (7
0) ;
std_ulogic
);
end
req
latch
isr data
downto
in
err
err
next
ISR data
in
in
ack
std_logic_vector (7
ISR data
incoming
ack
req
zeroes
in
ack
0);
qtable
std_ulogic;
data
isr_latch_ack
latch
table
in
all
isr_data_in
downto
decoder
isr
component
port
of
isr
0),
in
downto
ack
err
architecture
(7
component;
(architecture)
Author
vector
0) ) ;
component
Name
ack
ack
out
downto
0),
in
ack
next
std_ulogic;
in
downto
(7
std_ulogic_vector
0),
downto
data
err
0));
downto
(clock
std_ulogic_vector
std_ulogic;
std_ulogic;
result_data_valid
end
(7
byte
next
reading
std_ulogic;
in
component;
std_ulogic;
in
end
data
compressed
inc_data_ack
:
in
byte is valid for read
in
component
std_ulogic_vector
out
byte
next
flag
in
in
input
next_byte_req
request
data
reset
complete_ack
work_req
reg
reset
downto
downto
start_decode
component;
out
(15
do\ mto
0 ) ),
(1
dec_frame
(clock
component
port
std
ulogic;
reset
in
std
ulogic;
work_req
in
end
downto
req_err
out
ack
out
find_sos
out
decode_scan
out
find
in
downto
ulogic;
std_ulogic;
in
std_ulogic;
err
in
std_ulogic;
qdata_in
out
std_ulogic_vector
ulogic;
qload
out
std_ulogic;
std
ulogic;
qload_ack
in
std_ulogic);
end
ulogic;
std
ulogic;
std
ulogic)
port
reset
in
std
ulogic;
work_req
in
downto
downto
qaddr
in
std_ulogic;
inc
in
std_ulogic;
clock
in
std_ulogic;
qtable_addr
out
std_ulogic_vector
out
std_ulogic);
(qreset
0)
component;
0) ;
in
downt o
component
0);
port
qmem
in
std
ulogic;
clock
in
std_ulogic;
in
std
ulogic;
reset
in
std_ulogic;
in
std
ulogic;
qdata_in
in
req_err
out
std
ulogic;
ack
out
std
ulogic;
qload
in
std_ulogic;
next_req
isr_latch
out
std
ulogic;
qload_ack
out
std_ulogic;
out
std
ulogic;
qdata_out
out
out
std
logic
qreq
in
std_ulogic;
qreq_ack
out
std_ulogic;
qtable_addr
in
std_ulogic_vector
(5
in
std
vector
(5
isr_data
ack
ck
in
downto
vector
(7
downto
0) ;
0) ;
0) ) ;
component;
def ine_htable
component
(clock
in
std_ulogic;
reset
in
std_ulogic;
table_err
out
std_ulogic;
htable_req
in
std_ulogic;
htable_ack
out
std_ulogic;
out
std_ulogic;
next_req
err
in
std_ulogic;
data
in
std_ulogic_vector
0) ;
DCmin_WEl
out
std_
ulogic;
std
ulogic;
DCmax_WEl
out
out
DCval_WEl
out
std
ulogic;
out
std^
ulogic;
std
ulogic;
ACmax_WEl
out
ACvalptr_WEl
out
ulogic;
ACval_WEl
out
ulogic;
huff_DIN
out
reset
(7
downto
in
do_dequant_ack
qdata_out
std_ulogic_vector
(7
downto
0)
qreq_ack
std_ulogic;
val_DINl
out
std_ulogic_vector
(3
std_ulogic_vector
std_ulogic_vector
(7
downto
out
in
out
in
out
out
in
out
0);
(5 downto
0);
LoadToDeqDOUTl
std_ulogic_vector
out
(5
LoadToDeqRADRl
std_ulogic_vector
std_ulogic;
qtable_raddr
out
out
0);
qreq
out
std_ulogic;
val_LDl
in
std_ulogic;
0) ;
huff_LDl
val_RWADR
std_ulogic;
do_dequant_unload_ack
std_ulogic_vector
0) ;
in
std_ulogic;
out
downto
std_ulogic;
0) ;
deguantize
(clock
std_ulogic;
ulogic;
ACmin_WEl
(7
downto
0);
DeqToIDCT_DINl
std_logic) ;
std_ulogic_vector
component;
(15 downto
0);
DeqToIDCT_WADRl
component
downto
define_qtable
std_ulogic_vector
(clock
in
std_ulogic;
reset
in
std_ulogic;
table_err
out
std_ulogic;
qtable_req
in
std_ulogic;
qtable_ack
out
std_ulogic;
qreset
out
std_ulogic;
inc
out
std_ulogic;
qtable_addr
in
std_ulogic_vector
0 )I;
inc
ack
ulogic
component;
do_dequant
DCvalptr_WEl
downto
0) ) ;
port
std_ulogic;
(15
downto
component
in
huff_WADR
0) ;
end
std_ulogic_vector
downto
qtable_raddr
next_ack
port
(5
inc_ack
end
(7
component;
component
ulogic;
(7
0) ;
std
ulogic;
isr_latch_
port
out
next_ack
in
std
err
downto
next_req
in
in
next_ack
end
ulogic;
(clock
data
downto
std
eoi
std_ulogic_vector I
std_ulogic_vector
0) ;
in
std_ulogic_vector I
downto
downto
component;
port
end
find_sos_ack
decode_scan_ack
find_sos_err
decode__scan err
component
in
data
in
(5
downto
DeqToIDCT_LDl
out
0);
.
out
std_ulogic;
DeqToIDCT_WEl
out
std_ulogic) ;
end
component;
component
(5
port
std_ulogic;
A-5
regl6
(reset
in
std_ulogic;
clock
in
std_ulogic;
in_data
downto
downto
end
in
std_ulogic_vector
(15
next_ack
0) ;
std_ulogic;
in_latch
in
std_ulogic;
out_data
out
std
ulogic_vector
in
err
(15
std_ulogic;
0) ) ;
in
isr_latch_ack
component;
std_ulogic;
out
next_req
component
port
reg32
std_ulogic;
(reset
in
std_ulogic;
clock
in
std_ulogic;
in
std_ulogic_vector
in_data
downto
std_logic_vector
in_latch
end
in
std_ulogic;
out
std
ulogic_vector
out
isr_data_in
(31
0) ;
out_data
downto
isr_latch
std_ulogic;
(7
out
downto
0);
in
decode_scan_header
(31
std_ulogic;
0) ) ;
decode_scan_header_ack
component;
decode_scan_header_err
find_sos
component
port
end
out
std_ulogic) ;
(clock
in
std_ulogic;
reset
in
std_ulogic;
find_sos_req
in
std
data
in
downto
out
std_ulogic;
downto
end
component;
component
ulogic;
huf f_reg256byl6
in
std_ulogic_vector
(15 downto
RADR1
in
std_ulogic_vector
(7
downto
WADR1
in
std_ulogic_vector
(7
downto
DOUT1
out
std_ulogic_vector
(15 downto
port(DINl
0);
next_ack
in
std_ulogic;
err
in
std_ulogic;
isr_latch_ack
in
std_ulogic;
qtable_ack
in
std_ulogic;
htable_ack
in
std_ulogic;
table_err
in
std_ulogic;
find_sos_ack
out
std_ulogic;
LD1
in
std_ulogic;
find_sos_err
out
std_ulogic;
WEI
in
std
next_req
isr_latch
out
std_ulogic;
out
std_ulogic;
isr_data_in
out
std_logic_vector
end
(7
component
0) ;
huff_reg256by8
in
std_ulogic_vector
(7
downto
RADR1
in
std_ulogic_vector
(7
downto
WADR1
in
std_ulogic_vector
(7
downto
DOUT1
out
downto
LD1
in
std_ulogic;
WEI
in
std_ulogic);
port(DINl
qtable_req
out
std_ulogic;
htable_req
out
std
ulogic) ;
component;
ulogic) ;
component;
component
port
dec_scan
(clock
std_ulogic;
reset
in
std_ulogic;
decode_scan
in
end
out
component
component;
std_ulogic;
decode_scan_ack
std_ulogic;
port
decode_scan_err
huf f 2_reg256by8
in
std_ulogic_vector
(7
downto
RADR1
in
std_ulogic_vector
(7
downto
WADR1
in
downto
DOUT1
out
downto
( DIN1
out
std_ulogic;
computeNumMCUs
out
std_ulogic;
in
computeNumMCUs ack
std_ulogic;
startscan
out
std_ulogic;
in
scancomplete
std_ulogic;
decode_scan_header
out
end
std_ulogic;
LD1
in
std_ulogic;
WEI
in
std_ulogic;
reset
in
std_ulogic;
acdc
in
std_ulogic);
component;
in
component
std_ulogic;
huf f_regl6byl6
:
in
RADR1
in
std_ulogic_vector
(3
downto
WADR1
in
std_ulogic_vector
(3
downto
D0UT1
out
std_ulogic_vector
(15 downto
port(DINl
downto
std_ulogic) ;
end
component;
component
port
dec_scan_header
(
clock
std_ulogic;
LD1
reset
std_ulogic;
data
std_ulogic_vector
(7
downto
0);
A-6
in
std_ulogic;
WEI
in
std_ulogic;
reset
in
std_ulogic;
acdc
in
std_ulogic;
minmax
in
std_ulogic);
end
component;
ulogic;
downto
std
ulogic;
(3 downto
std
ulogic;
huf f_regl6by8
component
in
reset
std
in
startscan
in
RADR1
in
std_ulogic_vector
WADR1
in
downto
std
ulogic;
DOUT1
out
downto
std
ulogic;
LD1
in
std_ulogic;
std
ulogic;
WEI
in
std_ulogic;
reset
in
std_ulogic;
std
ulogic;
acdc
in
std_ulogic);
std
ulogic;
std
ulogic;
std
ulogic;
std
ulogic) ;
port(DINl
0)
load
0)
coeff
dequant
0)
in
complete
coeff
in
empty left
out
full
out
in
out
in
a_full_left
0)
end
component;
right
right
empty
do dequant
component
port
compute_MCUs
(clock
in
std_ulogic;
reset
in
std_ulogic;
computeNumMCUs
in
std_ulogic;
computeNumMCUs ack
out
std_ulogic;
data
downto
y_data
downto
numMCUs_in
downto
latchMCUs
end
unload
do dequant
end
in
ack
in
ack
component;
port
out
0);
:
idct
component
0);
:
(31
dequant
0);
:
std_ulogic_vector
do
in
out
complete
out
coeff
in
(clock
reset
in
startscan
in
deguant
std_ulogic);
idct
component;
in
complete
coeff
complete
coeff
port
downto
downto
downto
downto
mem64by8
(DIN1
0)
in
std_ulogic_vector
(5
WADR1
in
std_ulogic_vector
(5
DOUT1
out
end
LD1
in
std_ulogic;
component
WEI
in
std_ulogic;
in
std_ulogic);
0
0)
do
IDCT
unload
do
IDCT
done
ack
ulogic
ulogic
std
ulogic
out
ulogic
in
ulogic
in
ack
component;
port
component;
mem64byl6
idct
(clock
in
reset
in
std_ulogic;
do_idct
in
std_ulogic;
do_idct_unload_ack
out
std_ulogic;
do_idct_done_ack
out
std_ulogic;
DeqToIDCT_RADRl
out
std_ulogic;
in
std_ulogic_vector
(15
in
std_ulogic_vector
(5
in
std_ulogic_vector
(5
out
std_ulogic_vector
(15
LD1
in
std_ulogic;
IDCT_ToUnload_LDl
out
std_ulogic;
WEI
in
std_ulogic;
IDCT_ToUnload_WEl
out
std_ulogic)
mempreset
in
std_ulogic);
( DIN1
0);
std_ulogic_vector
(5
downto
0)
DeqToIDCT_DOUTl
0);
std_ulogic_vector
(15
downto
0);
IDCT_ToUnload_DINl
0);
std_ulogic_vector
(7
downto
0)
IDCT_ToUnload_WADRl
0);
std_ulogic_vector
end
(5
downto
0)
component;
component;
component
component
port
load_coeff
port
(clock
in
std_ulogic;
reset
in
std_ulogic;
startscan
in
std_ulogic;
(31
downto
std_ulogic;
in
startscan
in
scancomplete
out
idct_coef f_complete
in
d_full_left
in
a_empty_left
out
do_unload
out
std_ulogic;
out
std_ulogic;
a_full_right
out
std_ulogic;
a_empty_right
in
std_ulogic;
do_load
out
std_ulogic;
do_load_ack
in
std_ulogic);
std_ulogic;
std_ulogic;
std_ulogic;
component;
port
reset
std_ulogic;
0)
load_coef f_complete
component
unload_coeff
(clock
in
numMCUsout
std_ulogic_vector
end
ulogic
std
0)
DOUT1
end
ulogic
out
in
ulogic
std_ulogic) ;
WADR1
downto
out
right
empty
do_IDCT
RADR1
downto
RADR1
port
downto
(7
component
downto
std_ulogic_vector
mempreset
end
in
ulogic
std
in
empty left
full right
ulogic
ulogic
out
a_full_left
component
std
dequant_coef f
std_ulogic;
(clock
std_ulogic;
std_ulogic;
A-7
do_unload_ack
end
out
value
std_ulogic) ;
std
vector
ulogic
component ;
nextbit
(7
downto
port
do
load
nextbit
data
(clock
in
std_ulogic;
nextbit
err
reset
in
std_ulogic;
huff_RADR
in
std_ulogic;
out
std_ulogic;
out
std_ulogic;
do
load
do
load
coeff
ack
loadDC
loadDC
ack
loadAC
loadAC
end
ack
in
std_ulogic;
out
std_ulogic;
in
std_ulogic) ;
std
vector
ulogic
ulogic
std
ulogic
std
ulogic
port
do
std
ulogic
(clock
in
std_ulogic;
reset
in
std_ulogic;
vector
vector
vector
loadDC
in
std_ulogic;
loadDC_ack
out
std_ulogic;
decode
out
std_ulogic;
in
std_ulogic;
out
decode
ack
receive
receive
ack
extend
extend
ack
Tdecode
downto
downto
downto
0);
downto
0);
downto
0);
LoadDINl
component
(7
downto
0);
out
(7
(7
receive
ulogic;
std
ulogic;
in
std_ulogic;
receive
std_ulogic;
receive
in
std_ulogic;
SSSS
in
downto
0) ;
Vout
in
std_ulogic_vector
(7
downto
0) ;
in
std_ulogic_vector
(7
std_ulogic_vector
LoadWEl
out
std_ulogic) ;
std_ulogic;
reset
in
std_ulogic;
loadAC
in
std_ulogic;
downto
downto
port
downto
std_ulogic;
std_ulogic_vector
(0
out
std_ulogic_vector
(7
out
std_ulogic_vector
(5
ulogic
vector
(7
out
std
ulogic
vector
(7
ulogic;
req
out
std
nextbit
ack
in
std
ulogic;
nextbit
data
in
std
ulogic;
nextbit
err
in
std
ulogic) ;
extend
(clock
in
std
ulogic;
reset
in
std
ulogic;
extend
in
std
ulogic;
out
std
ulogic;
ack
in
std
ulogic
vector
(7
in
std
ulogic
vector
(7
downto
0) ;
RetV
out
std
ulogic
vector(7
downto
0) )
component;
port
nextbit
(clock
reset
in
std
ulogic;
in
std
ulogic;
ulogic;
LoadLDl
out
std_ulogic;
nextbit
req
in
std
LoadWEl
out
std_ulogic;
nextbit
ack
out
std
ulogic;
decode
out
std_ulogic;
nextbit
data
out
std
ulogic;
in
std_ulogic;
nextbit
err
in
data
ack
downto
0);
receive
ack
extend
extend
ack
recSSSS
downto
0);
downto
0);
std
ulogic;
in
std
ulogic
vector
std_ulogic;
next
req
out
std
ulogic;
in
std_ulogic;
next
ack
in
std
ulogic;
out
std_ulogic;
err
in
std
ulogic) ;
in
std_ulogic;
out
in
std_ulogic_vector
end
(7
(7
component;
huff
acdcisel
port(IN0
in
std_ ulogic
vector
(7
downto
INI
in
std_ ulogic
vector (7
downto
SEL
in
std_ ulogic
vector
DOUT
out
std_ ulogic
vector (7
0);
in
Eval
std_ulogic_vector
(7
0);
mempreset
std_ulogic) ;
out
0));
decode
(clock
in
std_ulogic;
reset
in
std_ulogic;
in
std_ulogic;
out
std_ulogic;
decode
decode
(0 downto
0);
component;
component
out
0) ;
component
RecV
:
:
out
0);
port
std
0) ;
T
0);
receive
end
ulogic;
in
nextbit
component
Tdecode
downto
out
out
0);
decode
downto
ulogic;
downto
end
LoadWADR2
std
std
(5
0);
LoadDIN2
in
out
component;
loadAC
in
:
ack
:
extend
ack
in
0));
std
component
outSEL
downto
0);
in
std_ulogic;
loadAC
in
in
out
huff
downto
LoadLDl
do
in
0);
std_ulogic_vector
(clock
(15
0);
downto
(15
in
downto
reset
component;
port
ulogic;
std_ulogic;
out
component
ulogic;
std
(clock
port
end
LoadWADRl
vector
out
out
std
in
component;
0);
RetV
end
end
0);
DIFF
vector
ulogic
in
0);
huffmax_DOUT
std
downto
huffvalptr_DOUT
loadDC
ulogic;
(3
huffmin_DOUT
component
ulogic;
std
out
huffval_DOUT
component;
std
in
RADR
val
std
out
:
req
nextbit_ack
component
0);
ack
end
component;
component
A-8
huf f_acdcsell6
downto
in
port(INO
std_ulogic_vector
(15
downto
signal
std
INI
in
std_ulogic_vector
SEL
in
DOUT
out
(15
downto
signal
std
downto
std
downto
std
component;
huf f_acdcsel6
component
in
port(IN0
vector
(5 downto
std
0)
downto
std
0)
SEL
std_ulogic_vector
(0 downto
std
qload
out
std_ulogic_vector
(5 downto
std
0) );
component;
std
qreq
port
do_unload
std
clock
in
in
std_ulogic;
do_unload
in
std_ulogic;
do_unload_ack
out
std_ulogic;
out
reset
IDCT_ToUnload_RADRl
std_ulogic_vector (5 downto 0);
IDCT_ToUnload_DOUTl
downto
y latch
ulogic;
out
std
std
std_ulogic) ;
end
signal
std
work_req
(2 downto
std_ulogic_vector
signal
signal
downto
signal
std
0);
std
std_ulogic;
std
signal
std
std_ulogic_wired_or
signal
std
std_ulogic;
next_ack
signal
std
ack
std_ulogic_vector
signal
(7
downto
std
std_ulogic;
std
std_ulogic;
vector
ulogic
downto
(15
0);
vector
downto
(15
0);
huf fDCmax_DOUT
vector
ulogic
(15 downto
huffDCvalptr
ulogic
vector
(7
0);
DOUT
downto
0);
huf fACmin_DOUT
vector
ulogic
downto
(15
0);
huf fACmax_DOUT
vector
ulogic
(15 downto
0);
huf fACvalptr_DOUT
vector
ulogic
(7
huffmin
ulogic
vector
downto
0);
DOUT
downto
(15
0);
huffmax_DOUT
vector
ulogic
(15 downto
0);
huf fvalptr_DOUT
ulogic
vector
(7
downto
0);
huffval_DOUT
ulogic
vector
huff
ulogic
signal
std_ulogic;
(7
downto
0);
outSEL
vector
downto
0);
(3 downto
0);
(0
signal
std_ulogic;
huff_RADR
(3 downto
huff_LDl
std_ulogic;
qreset
signal
inc
DCmin_WEl
std_ulogic;
signal
inc_ack
DCmax_WEl
std_ulogic;
signal
std_ulogic;
(5
downto
DCvalptr_WEl
std_ulogic;
qtable_raddr
ulogic_vector
huff_WADR
std_ulogic_vector
qtable_ack
std_ulogic;
std
err
huff DCmin_DOUT
std_ulogic_vector
std_ulogic;
signal
scan
huffJDIN
ulogic
signal
std_ulogic;
htable_ack
signal
signal
err
qtable_req
std_ulogic_wired_or
signal
sos
decode
signal
htable_req
std_ulogic_wired_or
signal
std
ack
scan
ulogic;
signal
std_ulogic_wired_or
signal
0);
reg_err
std_ulogic_wired_or
signal
find
signal
std_ulogic_wired_or
signal
std
std_ulogic;
data
ack
ulogic;
signal
std_ulogic_wired_or
signal
std
std_ulogic;
table_err
sos
decode
signal
std_ulogic_wired_or
signal
std
std_ulogic;
err
scan
ulogic;
signal
std_ulogic_wired_or
signal
find
signal
std_ulogic;
0);
req
ulogic;
signal
next_req
downto
(15
sos
decode
signal
std_ulogic;
0);
ulogic;
signal
isr_latch_ack
(15 downto
ulogic;
signal
isr_latch
std_ulogic_wired_or
find
signal
0);
isr_data_in
std_logic_vector (7
vector
ulogic
signal
component;
0);
y data
signal
:
(15 downto
data
vector
ulogic
signal
std_ulogic;
out
0);
result_data_ack
vector
x
signal
std
xy data
ulogic
signal
0);
result_data
downto
std
(7
latch
ulogic;
signal
std
result_data_valid
std
out
vector
signal
std_ulogic;
0);
ack
qdata
ulogic
signal
component
downto
ack
ulogic;
signal
end
0);
qreq
signal
DOUT
downto
ulogic;
signal
0)
(7
ulogic;
signal
INI
0);
ulogic;
signal
std_ulogic_vector
downto
gload
signal
std
(5
in
qdata
signal
0) tr
end
vector
ulogic
signal
addr
qtable
ulogic
0);
A-9
0);
signal
DCval_WEl
signal
std_ulogic;
signal
ACmin_WEl
std_ulogic;
signal
signal
ACmax_WEl
signal
ACvalptr_WEl
std_ulogic;
decode_ack
std_ulogic;
std_ulogic;
signal
ddecode
std_ulogic_wired_or
std_ulogic;
signal
loadAC_ack
std_ulogic;
signal
ACval_WEl
rreceive
std_ulogic;
std_ulogic;
signal
receive_ack
std_ulogic;
signal
val_DIN
signal
signal
0);
std_ulogic;
downto
0);
std_ulogic;
downto
0);
std_ulogic;
0);
std_ulogic;
0);
std_ulogic;
val_WADR
signal
downto
signal
valACval_DOUT
signal
signal
valDCval_DOUT
signal
signal
val_RADR
signal
downto
signal
val_LDl
signal
std_ulogic;
signal
extend_ack
acrreceive
acreceive_ack
aceextend
acextend_ack
std_ulogic;
computeNumMCUs
signal
std_ulogic;
signal
eextend
downto
Tdecode
std_ulogic_vector
std_ulogic;
signal
(31
downto
0);
signal
numMCUs_out
std_ulogic_vector
signal
(31
downto
downto
0);
(7
downto
0);
0);
latchMCUs
signal
nextbit_req
std_ulogic_wired_or
signal
startscan
std_ulogic;
nextbit_ack
std_ulogic;
signal
std_ulogic;
signal
(7
RetV
std_ulogic_vector
std_ulogic;
signal
0);
numMCUs_in
std_ulogic_vector
signal
downto
RecVal
std_ulogic_vector
signal
(7
computeNumMCUsack
scancomplete
nextbit_data
std_ulogic;
signal
std_ulogic;
nextbit_err
std_ulogic;
signal
signal
std_ulogic;
signal
loadtodeq_a_full
signal
std_ulogic;
signal
decode_scan_header
std_ulogic;
loadtodeq_a_empty
std_ulogic;
signal
std_ulogic;
std_ulogic;
signal
dequant_coef f_complete
signal
std_ulogic;
LoadToDeqDINl
std_ulogic_vector
signal
deqtoidct_a_full
signal
std_ulogic_vector
std_ulogic;
signal
signal
deqtoidct_a_empty
signal
signal
idcttounload_a_full
signal
signal
idcttounload_a_empty
signal
signal
signal
signal
(5 downto
(5
(5
signal
0);
downto
0);
0);
(7
downto
0);
std_ulogic;
LoadToDeqWEl
signal
std_ulogic;
DeqToIDCT_DINl
std_ulogic_vector
loadDC_ack
signal
std_ulogic;
signal
0);
loadDC
std_ulogic;
signal
0);
LoadToDeqLDl
std_ulogic_wired_or
signal
downto
(5 downto
std_ulogic_wired_or
do_load_ack
std_ulogic;
downto
LoadToDeqDOUTl
std_ulogic_vector
do_load
std_ulogic;
0);
LoadToDeqWADR2
std_ulogic_vector
std_ulogic;
downto
LoadToDeqWADRl
std_ulogic_vector
std_ulogic;
signal
(7
LoadToDeqWADR
std_ulogic_vector
signal
0);
LoadToDegRADRl
std_ulogic_vector
std_ulogic;
downto
LoadToDeqDIN
std_ulogic;
signal
(7
LoadToDeqDIN2
std_ulogic_vector
loadAC
std_ulogic;
A-10
(15 downto
0);
DeqToIDCT_RADRl
(5
downto
0);
signal
DeqToIDCT_WADRl
downto 0);
DeqToIDCT_DOUTl
signal
DeqToIDCT_LDl
NB
signal
std_ulogic_wired_or
nextbyte
port
clock,
map
reset,
inc_data_ack,
std_ulogic;
"~
signal
DeqToIDCT_WEl
std_ulogic_wired_or
cmprssed_data,
read_err,
std_ulogic;
next_req,
signal
IDCT_ToUnload_DINl
downto 0)
IDCT_ToUnload_RADRl
next_byte_req,
signal
data,
next_ack,
downto
0),
IDCT_ToUnload_WADRl
std_ulogic_vector (5 downto 0)
signal
IDCT_ToUnload_DOUTl
err) ;
signal
signal
controller
0),
port
clock,
map
IDCT_ToUnload_LDl
std_ulogic_wired_or
signal
downto
Cont
start_decode,
complete_ack,
std_ulogic;
IDCT_ToUnload_WEl
std_ulogic_wired_or
std
reset,
decoding,
ulogic;
complete,
signal
intr,
sel_min
std_ulogic;
signal
ack,
sel_max
req_err,
std_ulogic;
signal
work_req) ;
sel_dc
fSOI
std_ulogic;
signal
find_soi
sel_ac
std_ulogic;
port
map
clock,
reset,
signal
recSSSS
signal
downto
0)
downto
0)
downto
0)
data,
RecV
next_ack,
signal
work_req,
err,
Eval
isr_latch_ack,
req_err,
ack,
signal
mempreset
next_req,
isr_latch,
isr data in)
std_ulogic;
signal
do_dequant
std_ulogic;
signal
do_dequant_ack
fSOF
signal
find_sof
std_ulogic;
do_deguant_unload_ack
port
map
std_ulogic;
clock,
reset,
work_req,
signal
do_IDCT
data,
next_ack,
std_ulogic;
signal
do_IDCT_done_ack
err,
isr_latch_ack,
std_ulogic;
signal
do_IDCT_unload_ack
qtable_ack,
htable_ack,
table_err,
std_ulogic;
signal
do_unloading
req_err,
ack,
std_ulogic;
signal
do_unload_ack
next_req,
std_ulogic;
isr_latch,
isr_data_in,
begin
qtable_req
htable_req)
sel
min
<=
sel
max
<=
sel
dc
<=
sel
ac
<=
frame_header
fr_header
port
map
clock,
reset,
ISReg
work_req,
data,
isr
port
map
reset,
next_ack,
isr_data_in,
isr_data,
isr_latch,
isr_latch_ack,
err,
clock) ;
next_req,
isr_latch_ack,
req_err,
ack,
A-ll
err,
isr_latch,
isr_data_in,
qdata_in,
qload,
x_latch,
qload_ack) ;
y_latch,
xy_data) ;
QA
decode_frame
dec_f rame
port
qaddr
port
map
map
qreset,
inc,
clock,
reset,
clock,
work_req,
qtable_addr,
find_sos_ack,
decode_scan_ack,
f ind_sos_err,
decode_scan_err,
inc
ack) ;
QM
qmem
port
req_err,
clock,
map
reset,
ack,
f ind_sos_req,
qdata_in,
decode
qload,
scan) ;
qload_ack,
fEOI
qdata_out,
find_eoi
port
qreq,
map
clock,
qreq_ack,
reset,
qtable_addr,
qtable_raddr
work_req,
data,
DEQ
next_ack,
dequantize
err,
port
isr_latch_ack,
clock,
map
reset,
req_err,
ack,
do_dequant,
next_req,
do_dequant_unload_ack,
isr_latch,
isr data in)
do_dequant_ack,
qdata_out,
qreq,
qreq_ack,
DH
qt abl e_r addr ,
define_htable
port
map
clock,
reset,
LoadToDeqRADRl
LoadToDeqDOUTl
DeqToIDCT_DINl,
table_err,
htable_req
htable_ack,
DeqToIDCT_WADRl,
DeqToIDCT_LDl,
DeqToIDCT_WEl) ;
next_req,
next_ack,
Xreg
err,
regl6
data,
port
DCmin_WEl,
DCmax_WEl
reset,
map
clock,
xy_data,
DCvalptr_WEl,
DCval_WEl,
ACmin_WEl,
ACmax_WEl,
ACvalptr_WEl,
ACval_WEl,
huff_DIN,
huff_WADR,
huff_LDl,
x_latch,
x
Yreg
port
reset,
map
clock,
xy_data,
y_latch,
y_data) ;
val_WADR,
LD1)
regl6
val_DIN,
val
data)
NumMCUs
reg32
DQ
port
def ine_qtable
port
map
map
reset,
clock,
clock,
reset,
numMCUs_in,
latchMCUs,
table_err,
qtable_req
numMCUs
out
qtable_ack,
FStOfSc
qreset,
find_sos
inc,
port
qtable_addr,
map
clock,
reset,
inc_ack,
data,
find_sos_ req,
next_req,
data,
next
next
ack,
A-12
ack,
err,
reset,
isr_latch_ack,
sel_dc,
qtable_ack,
sel
max) ;
htable_ack,
huffDCvalptr
table_err,
huff_regl6by8
find_sos_ack,
find_sos_err,
port
huff_DIN(7
map
isr_latch,
isr_data_in,
qtable_req,
htable_req
downto
huff_RADR,
huff_WADR,
huffDCvalptr_DOUT,
huff_LDl,
DCvalptr_WEl,
next_req,
reset,
DecTheScan
sel
dc)
dec_scan
port
map
clock,
huffDCval
reset,
computeNumMCUs
huff2_reg256by8
decode_scan,
decode_scan_ack,
decode_scan_err,
port
map
val_RADR,
val_WADR,
computeNumMCUs ack,
valDCval_DOUT,
startscan,
val_LDl,
scancomplete,
DCval_WEl,
decode_scan_header,
decode_scan_header_ack,
reset,
decode
scan
header
sel
huf fACmincode
map
port
map
huff_DIN,
huff_RADR,
huff_WADR,
huffACmin_DOUT,
clock,
reset,
next_ack,
huf f_LDl
err,
ACmin_WEl,
isr_latch_ack,
reset,
next_req,
sel_ac,
isr_latch,
isr_data_in,
decode_scan_header,
sel
decode
scan
header
huf fACmaxcode
map
compute_MCUs
min) ;
map
huf f_regl6byl6
err);
port
port
huf f_regl6byl6
data,
computeMCU
dc)
err),
DectheScanHeader :
dec_scan_header
port
val_DIN,
huff_DIN,
huff_RADR,
huff_WADR,
clock,
huf fACmax_DOUT
reset,
huff_LDl,
ACmax_WEl,
computeNumMCUs
computeNumMCUsack,
reset,
x_data,
sel_ac,
y_data,
sel
max) ;
numMCUs_in,
latchMCUs)
huffACvalptr
huff_regl6by8
huf fDCmincode
port
map
huf f_regl6byl6
port
map
huff_DIN(7
downto
huff_RADR,
huff_WADR,
huffACvalptr_DOUT,
huff_DIN,
huff_RADR,
huff_WADR,
huffDCmin_DOUT,
huff_LDl,
DCmin_WEl,
huf f_LDl
ACvalptr_WEl,
reset,
sel
ac) ;
reset,
sel_dc,
sel
huffACval
min) ;
huff2_reg256by8
port
huf fDCmaxcode
huf f
port
egl
val_DIN,
val_RADR,
6byl 6
map
map
val_WADR,
huff_DIN,
huff_RADR,
huff_WADR,
huffDCmax_DOUT,
huff_LDl,
DCmax_WEl,
valACval_DOUT,
val_LDl,
ACval_WEl,
reset,
sel
A-13
ac) ;
0),
rreceive
CoeffLoader
load_coef f
port
eextend,
map
clock,
extend_ack,
reset,
Tdecode,
RecVal,
RetV,
LoadToDeqDINl,
startscan,
numMCUs_out,
load_coef f_complete,
LoadToDeqWADRl
loadtodeq_a_full,
loadtodeq_a_empty,
do_load,
do
CoeffUnLoad
load
LoadToDeqLDl,
LoadToDeqWEl )
map
ACload
port
clock,
map
reset,
startscan,
loadAC,
loadAC_ack,
huff_outSEL,
LoadToDeqDIN2,
LoadToDeqWADR2,
LoadToDeqLDl,
LoadToDeqWEl,
ddecode,
decode_ack,
Tdecode,
do
unload
ack) ;
dequant_coef f
map
clock,
reset,
idcttounload_a_full,
idcttounload_a_empty,
do_unloading,
port
do_loadAC
scancomplete,
idct_coef f_complete,
CoeffDeQuant
ack) ;
unload_coef f
port
receive_ack,
clock,
acrreceive
reset,
acreceive_ack,
startscan,
aceextend,
load_coef f_complete,
acextend_ack,
dequant_coef f_complete,
recSSSS,
loadtodeq_a_full,
loadtodeq_a_empty,
deqtoidct_a_full,
deqtoidct_a_empty,
do_dequant,
do_dequant_unload_ack,
RecV,
Eval,
do_dequant_ack)
mempreset) ;
CoeffDECODE
decode
port
map
clock,
reset,
CoefflDCT
ddecode,
decode_ack,
Tdecode,
idct_coef f
port
clock,
map
nextbit_req,
reset,
nextbit_ack,
startscan,
dequant_coef f_complete,
nextbit_data,
nextbit_err,
idct_coef f_complete,
huff_RADR,
deqtoidct_a_full,
deqtoidct_a_empty,
idcttounload_a_full,
idcttounload_a_empty,
do_IDCT,
do_IDCT_unload_ack,
val_RADR,
do
IDCT
done
huffval_DOUT,
huffvalptr_DOUT,
huffmin_DOUT,
huf fmax
DOUT ) ;
CoeffDCRECEIVE
ack);
receive
DoLoad
port
map
do_load_coef f
port
DCload
map
clock,
reset,
rreceive,
clock,
reset,
receive_ack,
do_load,
do_load_ack,
loadDC,
loadDC_ack,
loadAC,
Tdecode,
RecVal,
loadAC
nextbit
nextbit_req,
nextbit_ack,
nextbit_data,
ack) ;
err) ;
CoeffACRECEIVE
do_loadDC
port
map
receive
clock,
port
reset,
map
clock,
loadDC,
loadDC_ack,
reset,
ddecode
acreceive_ack,
acrreceive,
decode_ack.
recSSSS,
A-14
LoadToDeqWEl,
RecV,
mempreset) ;
nextbit_req,
nextbit_ack,
DeqToIDCTMem
nextbit_data,
nextbit
mem64byl6
err);
port
CoeffDCEXTEND
DeqToIDCT_DINl,
DeqToIDCT_RADRl,
map
DeqToIDCT_WADRl,
extend
port
map
clock,
DeqToIDCT_DOUTl,
reset,
DeqToIDCT_LDl,
DeqToIDCT_WEl,
eextend,
reset
extend_ack,
RecVal,
Tdecode,
RetV)
huf f_acdcsel
map
LoadToDeqDINl,
LoadToDeqDIN2,
huff_outSEL,
extend
port
map
LoadtoDeqDINSelect
port
CoeffACEXTEND
LoadToDeqDIN) ;
clock,
reset,
aceextend,
LoadtoDeqSelect
acextend_ack,
port
recSSSS,
Eval)
huf f_acdcsel6
RecV,
map
LoadToDeqWADRl,
LoadToDeqWADR2,
huff_outSEL,
LoadToDeqWADR) ;
GetNextBit
ThelDCT
nextbit
port
map
idct
clock,
port
reset,
map (
clock,
nextbit_req,
reset,
nextbit_ack,
do_idct,
do_idct_unload_ack,
do_idct_done_ack,
nextbit_data,
nextbit_err,
data,
DeqToIDCT_RADRl
next_req,
DeqToIDCT_DOUTl,
next_ack,
IDCT_ToUnload_DINl,
err) ;
IDCT_ToUnload_WADRl
IDCT_ToUnload_LDl,
huffJVALsel
IDCT
ToUnload WEI);
huf f_acdcsel
port
map
IDCTToUnloadMem
valDCval_DOUT,
mem64by8
valACval_DOUT,
port
huff_outSEL,
huffval
huff_VALPTRsel
map
DOUT);
map
IDCT_ToUnload_RADRl
IDCT_ToUnload_WADRl
IDCT_ToUnload_DOUTl,
IDCT_ToUnload_LDl,
huf f_acdcsel
port
IDCT_ToUnload_DINl,
IDCT_ToUnload_WEl
huffDCvalptr_DOUT,
huffACvalptr_DOUT,
huff_outSEL,
huffvalptr_DOUT) ;
reset) ;
DoUnload
do_unload
huff_MINsel
port
map
port
map
clock,
reset,
huf f_acdcsell6
do_unloading,
do_unload_ack,
IDCT_ToUnload_RADRl,
IDCT_ToUnload_DOUTl,
huffDCmin_DOUT,
huffACminJDOUT,
huff_outSEL,
huff min DOUT) ;
result_data_valid,
huff_MAXsel
result_data,
result
huf f_acdcsell6
port
map
data
ack) ;
huffDCmax_DOUT,
end
huffACmax_DOUT,
huff_outSEL,
huff max DOUT);
decoder
arch;
COMPONENT;
display
display module,
DESCRIPTION :
for test bench
(entity)
LoadToDeqMem
mem64by8
port
map
LoadToDeqDIN,
Name
LoadToDeqRADRl,
LoadToDeqWADR,
LoadToDeqDOUTl
display_entity
Purpose
output
LoadToDeqLDl,
A-15
display
connection.
module,
used
to
simulate
Receives
data
image
uncompressed
if
as
(d_byte(2)
input.
d_int
Author
Douglas A.
Created
12-Mar-1994
Revised
Carpenter
end
if
if;
(d_byte(3)
d_int
end
library and
library ieee;
use
if
clauses
ieee. std_logic_1164 all;

ieee. std_logic_1164_extensions.
if
use
d_int
if
use
my_packages;
if
my_packages.package_l.all;
display
port
is
result_data
in
in
downto
result_data_ack
complete
end
then
+
'1')
32;
then
d_int
:=
if;
(d_byte(7)
'1')
then
d_int
:=
64;
128;
if;
end
(result_data_valid
16;
if;
d_int
entity
'1')
(d_byte(6)
end
8;
then
d_int
:=
d_int
library
'1')
(d_byte(5)
all;
std.textio. all;
then
d_int
:=
4;
if;
end
use
'1')
if;
(d_byte(4)
end
use
then
d_int
:=
d_int
'1')
d_int
:=
std_ulogic;
(linel, d_int ) ;
(linel, d_string)
write
0);
write
out
std_ulogic;
in
std_ulogic);
display;
if
(j
1;
:=
then
=17)
writeline(OUT_FILE, linel) ;
COMPONENT:
display
display module (architecture)
DESCRIPTION:
0;
:=
if;
end
Name
display_arch
wait
'
Purpose
display
Author
:
Revised
'
module
Douglas A.
Created
result
"
display_arch
TEXT
display
of
is
end
is
end
out
/home/ stul/dac4 927 / jpg/vhdl
data
'0'
<=
ack
after
if;
end
OUT_FILE:
(result_data_valid
until
PROP_DELAY;
DAC
loop forever;
end
file
after
Carpenter
12-Mar-1994
architecture
'1'
<=
result_data_ack
PROP_DELAY;
process;
display_arch;
.ppm";
COMPONENT:
begin
DESCRIPTION:
Interrupt Status Register
(entity)
process
variable
linel
variable
d_string
variable
line;
string (1
1 ) ;
to
good
d_byte
variable
std_ulogic_vector
(7
downto
variable
d_int
variable
0)
isr_entity
Purpose
Interrupt
Status
Register
(ISR)
module
integer;
integer;
Author
Douglas A.
Created
30-Mar-1994
begin
Carpenter
Revised
<=
result_data_ack
0;
j
d_string
'0';
library and
library ieee;
--
:=
forever
(complete
if
:=
'
"
( (result_data_valid
until
'
1')
/=
'1')
0)
end
:=
reset
:=
if;
(d_byte(l)
d_int
end
downto
0);
downto
0);
:=
d_int
if
isr
result_data;
:=
'1')
d_int
output
to
all
latch the
then
+
incoming
.all;
'1')
d_int
then
+
clock
A-16
in
std_logic_vector (7
incoming
the
signal
);
if;
ISR data
ISR data
clock
2;
std_ulogic;
outgoing
isr_latch
out
std_logic_vector (7
in
std_ulogic;
out
std_ulogic;
data
isr_latch_ack
1;
in
zeroes
isr_data
acknowledge
=
all;
is
reset
isr_data_in
:=
my_packages;
port(
0;
0;
(d_byte(0)
d_int
.all;
my_packages.package_l
if;
d byte
end
std_logic_1164
entity isr
(OUT_FILE, linel )
else
if
ieee. std_logic_1164_extensions
then
then
writeline
ieee.
use
use
(complete
(j
clauses
use
library
1'));
if
use
";
loop
wait
or
Name
boolean-
data
incoming
:
in
latch
std_ulogic
isr;
end
data
(7
std_ulogic_vector
COMPONENT:
next_ack
isr
Interrupt Status Register (architecture)
DESCRIPTION:
ISR_arch
Purpose
ISR module
Author
Douglas A.
Created
30-Mar-1994
isr
of
std_ulogic
COMPONENT:
NextByte
DESCRIPTION;
(architecture)
Carpenter
DAC
nextbyte_arch
Purpose
is
signal
DO
std_ulogic;
signal
idata
std_logic_vector
downto
std_ulogic;
out
nextbyte;
Name
isr_arch
out
>;
Revised
architecture
err
end
Name
out
0);
downto
(7
0) ;
module
nextbyte
Carpenter
A.
Author
Douglas
Created
30-Mar-1994
DAC
Revised
begin
if
(reset
'
idata
elsif
clock
' 0'
<=
DO
(reset,
process
'
<=
then
std_ulogic;
a2
std_ulogic;
"00000000";
signal
a3
std_ulogic;
signal
a4
std_ulogic;
signal
aS
std_uloglc;
signal
a6
std_ulogic;
signal
idat
std_ulogic_vector
end
(clock
and
'1')
and
<=
then
if
ISR_Process;
output
isr_latch_ack
isr
values;
<=
DO;
idata;
<=
arch;
NextByte-;?::
COMPONENT:
Obtain nextbyte of compressed data from memory
DESCRIPTION:
<=
downto
0),
downto
0),
clock)
aO
<=
'0
al
<=
'0
a2
<=
'0
a3
<=
'0
a4
<=
'0
a5
<=
a6
<=
idata
<=
(clock1
( :ci
Purpose
nextbyte
'
0'
) )
0 ' )
1"
(clock
and
event)
=
and
then
'1'
'
and
(D(0)
( (D(1)
'1 ') );
'
'1'
<=
al
0 ' ) and ( D ( 0 )
( (D(2)
'1') );
( inc_data_ack
'1'
a2 <=
( ( D(l)
'0') and (D(0)
(inc data ack
'0') and (read_err
'0')
<=
a3
(( D(2)
'1') and (next_req
'
<=
1 ' ) and ( D ( 0 ) = ' 0 '
a4
D(1 )
'));
(next_req
'
'
0 ) and ( D ( 0 )
a5 <=
D(1 )
0 '
') );
[next_req
'
'
0 ' ) and ( D ( 1 )
a6 <=
D(2 )
1 '
nd
(inc data ack
'0'));
(D(0)
'I')
<=
aO
nextbyte_entity
then
"00000000";
ock'
last_va lue
(read_err
Name
'
'00 0";
elsif
(entity)
'
(reset
D
end
begin
process
isr_data
(reset,
process
next_process
if;
Assign
begin
isr_data_in;
if;
end
std_ulogic;
al
'0')) then
DO <= isr_latch;
if (isr_latch
'1')
end
aO
signal
idata
signal
signal
event)
is
nextbyte
std_ulogic_vector
(clock'
'last_value
signal
clock)
of
n extbyte_arch
architecture
ISR_Process
begin
and
and
module
Author
Douglas A.
Created
30-Mar-1994
Carpenter
Revised
and
'1') );
and
library and
library ieee;
clauses
use
ieee.
std_logic_1164
use
ieee.
std
use
all;
logic_1164_extensions. all;
my_packages;
my_packages
.package_l
nextbyte
port
and
and
1')
inputs
external
:
in
std_ulogic;
reset
in
std_ulogic;
inc_data_ack
in
std_ulogic;
cmprssed_data
in
(7
in
inputs
<=
=
<=
(a6
or
=
'1'
or
(inc_data_ack
(a5
=
or
(a3
or
(al
'1'
) )
1')
;
or
(a3
or
(a2
'1'));
(al
or
'1'));
'1') then
=
cmprssed_data;
if;
if;
process
assign
std_ulogic;
external
next_byte_req
'1'
next_process;
std_ulogic;
internal
next_req
end
end
end
in
( (aO
'1')
( (aO
'
1')
idata
0);
downto
((aO
<=
(a3
if
clock
err
or
<=
(a4
D(0)
read
or
is
std_ulogic_vector
D(2)
D(l)
all;
1')
entity
use
library
out
internal
next_ack
outputs
output
<=
'1'
values
when
((a4
'
1')
(a6
or
'1'))
else
std_ulogic;
'0';
outputs
err
A-17
<=
'1'
when
((aO
!)
or
(a3
'
1'))
else
0';
'1'))
((a2
when
'1')
(a5
or
else
data
end
1'
<=
next_byte_req
<=
'0';
idata;
nextbyte_arch;
COMPONENT:
controller
DESCRIPTION:
Controls the decoder module. Determines
submodule will
what
be working(entity)
Name
control
Purpose
ler_entity
Controller module
30-Mar-1994
Author
Created
use
clauses
ulogic
std
ulogic
signal
al6
std
ulogic
signal
al7
std
ulogic
signal
al8
std
ulogic
signal
al9
std
ulogic
signal
a20
std
ulogic
signal
a21
std
ulogic
signal
a22
std
ulogic
signal
a23
std
ulogic
signal
a24
std
ulogic
signal
a25
std
ulogic
signal
a26
std
ulogic
signal
a27
std
ulogic
signal
a28
std
ulogic
signal
a29
std
ulogic
signal
a30
std
ulogic
if
.all;
(reset
D
all ;
entity controller
a3
all;
a4
a5
is
a6
port
a7
inputs
external
a8
clock
in
std
ulogic
in
std
ulogic
in
std
ulogic
a9
start
decode
complete
ack
reset
in
external
out
std
ulogic
out
std
ulogic
out
internal
'0'
<=
0'
al2
<=
0'
al3
<=
0'
std
al4
<=
'0'
al5
<=
0'
al6
<=
0'
al7
<=
0'
al8
<=
'0'
al9
<=
'0'
a20
<=
0'
a21
<=
'0'
a22
<=
0'
a23
<=
'0'
a24
<=
'0'
ulogic
inputs
ack
in
err
std
in
internal
work_req
std_ulogic_vector (2 downto
<=
all
ulogic
complete
std
ulogic
ulogic
outputs
:
out
0));
controller;
alO
outputs
intr
end
std
decoding
req
COMPONENT:
Controller
a25
<=
'0'
DESCRIPTION:
(architecture)
a26
<=
O"
a27
<=
'0'
a28
<=
0'
<=
'0'
a30
<=
'0'
Name
a2
controller_arch
Purpose
Author
Created
Revised
Controller
module
Douglas A.
Carpenter
'0'
then
clock
(clock1
'last_value
event
cor
std_ulogic_vector
signal
al
std_ulogic;
signal
a2
std_ulogic;
signal
a3
std_ulogic;
signal
a4
std_ulogic;
signal
a5
signal
a6
std_ulogic;
signal
a7
std_ulogic;
signal
a8
std_ulogic;
signal
a9
std_ulogic;
signal
alO
std_ulogic;
signal
all
std_ulogic;
signal
al2
std_ulogic;
signal
al3
signal
clock)
) and (clock
'1') and
'0')) then
al <=
((D(3)='0') and (D(2)='0'l and (D(l)
'0') and (start_decode
'1') and (ack
'0'));
<=
a2
((D(3)='0') and (D(2)='0'l and (D(l)
and
(D(0)
'1') and (req_err
'0
'0') and (ack
'
'
a3 <=
1 ' ) and ( D ( 2 )
1 ' ) and ( D ( 1 )
( (D(3)
and
(D(0)
'1') and (complete_ack
'0'));
a4 <=
((D(3)='0') and (D(2)=,0") and (D(l)
'
'
'
and
D
0
0 ) and ( req_err
1 ) ) ;
( ( )
a5 <=
((D(3)='0'J and (D(2)='0*) and (D(l)
'
'
'
and
1 ) and ( req_err
1 ' ) ) ;
(D(0)
a6 <=
((D(3)='l') and (D(2)='l') and (D(l)
'
'
and
0 ' ) and ( req_err
1 ' ) ) ;
(D(0)
<=
a7
|(D(3)='l') and (D(2)='l') and (D(l)
and
(req_err
'0') and (ack
'0'));
a8 <=
((D(3)='l') and (D(2)='0') and (D(l)
and
(complete_ack
'1'));
a9 <=
((D(3)='0') and (D(2)='l') and (D(l)
'
'
'
'
and
0 ) and ( req_err
(D(0)
1 ) ) ;
elsif
30-Mar-1994
chitecture
(reset,
"0000";
<=
0';
<=
0";
<=
0';
<=
0';
<=
0';
<=
0';
<=
0';
<=
0';
<=
0';
a2
process
<=
al
my_packages;
begin
ieee std_logic_1164_extensions
library
use
std
al5
ContProcess
library and
library ieee;
use
al4
signal
begin
Revised
use
signal
(3
downto
0);
std_ulogic;
std_ulogic;
A-18
<=
alO
<=
all
D(0)
and
<=
D(0)
D(0)
D(0)
<=
and
D(0)
D(0)
and
req
and
D(0)
<=
and
D(0)
<=
req
and
D(0)
and
D(0)
and
D(0)
D(0)
and
<=
<=
or
or
D(l)
<=
al5='l')
or
'1'
(al7
or
(a22
(a24
or
(a27
'1')
(a29
or
'1')
'1'
or
'1'
or
Ial2='l')
(al9=
or
or
1 1'
(a27
or
( a3= 1')
(a21='l')
(a28='l')
((a7='l')
(al6='l')
or
or
or
or
or
or
or
'1'
(a29
controller
or
or
or
'1'
((a3='l'l or (a4='l')
(a9='l') or (al2='l'|
'1'
) ) else
or
or
((a4
'1')
or
'1')
or
(al2
(a5
'1'))
'1')
else
arch;
COMPONENT:
FindSOI
DESCRIPTION:
Module that
controls
finding the SOI
marker(entity)
Name
SOI_entity
Purpose
SOI
image
Assign
Douglas
Author
Created
the
start
of
Revised
A.
Carpenter
30-Mar-1994
library and
library ieee;
use
clauses
use
ieee.
std_logic_1164
use
ieee.
library
use
all;
.
all;
my_packages;
all;
(all='l')
(a22='l')
(a25='l')
(a29='l')
(al0='l')
(al7='l')
inputs
(a26
or
or
(al4=
1'
or
or
(a23=
1'
or
(a26
or
or
(a30=
or
(al3=
or
(al8=
'1'
or
'
<=
'1'
or
'1')
'0';
=
<='l'
work_req(l)
or
when
(a29
when
(a21='l')
or
std_ulogic;
or
in
0);
:
downto
0);
next_ack
in
std_ulogic;
err
in
std_ulogic;
isr_latch_ack
in
std_ulogic;
req_err
out
std_ulogic;
ack
out
std_ulogic;
next_req
isr_latch
out
std_ulogic;
out
std_ulogic;
isr_data_in
out
outputs
'1'
or
std_logic_vector (7
downto
0)
);
find
values
'1'
std_ulogic;
in
end
output
in
reset
data
) or
1') );
1'
) or
1'
) or
=
clock
work_req
1'
a27
is
port
) or (a8='l')
(a20='l'l or
'1'
or
a28
) or
ContProcess;
work_req(2)
(a26
finds
module,
marker.
process
((a7
=
'l'l
((a7='l')
(a24='l'l
'1'
or
else
or
or
soi;
(alO
COMPONENT:
findsoi
DESCRTPTION;
(architecture)
(al3='l') or
(a29='l')l
Name
else
find_soi_arch
'0';
<=
work_req(0)
or
or
when
(a9
'1') or
'0';
(a6=
or
) ) ;
D(0) <= ((al='l') or (a2='l'l or (a8='l I or
1'
(al4='l') or (al5='l') or (al8='l') or (a20=
) or
(a22=
'1') or (a26
'1') or (a27= '1')
'1'
'1'
(a28
) or (a30
) );
end if;
1*)
or
(a5='l')
or
a4='l')
a23
(al6='l')
or
when
(a6='l')
) )
a27='l')
or
'1'
a24='l')
'1')
'1')
'1'
<=
entity find_soi
or
end
'1')
'1'
else
<=
(a6
end
<=
al7='l')
'1'
or
L'
<=
) )
or
intr
or
<=
D(2)
(a28
(a26
or
(al4
'1
a25
(a29
(a2
(al5
'0';
<=
(;i9='l
(a5='l')
D(3)
or
'0';
'1'
complete
<=
'1')
(a28
a30
'1')
<=
D(0)
and
err
a29
(a30
<=
a28
a27
(a21
or
'1'
a26
<=
a25
'1')
err
and
a24
(a25
<=
a23
'1')
'1') or
a22
(a23
a21
<=
a20
and
(al6
(al8
(al3
or
((al
when
'1')
or
<=
al9
D(0)
(all
or
D(0)
al8
and
1')
'1'
<=
decoding
'0'
<=
al7
and
and
al6
and
(ack
<=
D(0)
D(0)
al5
and
'
<=
al4
and
and
<=
req_err
and
al3
and
D(3)
al2
and
'0'
'
1 ' ) and
(D(2)
D(l)
) ) ;
'0'
( D(3)='l') and (D(2)='l') and
D(l)
'1'
0 ) and (ack
) ) ;
'1'
( D(3)='0') and (D(2)='l') and
D(l)
'1'
1 ) and (req_err
) ) ;
'1'
( D ( 3 ) ' 0 ' ) and ( D ( 2 )
0 ' ) and
D(l)
'0') and (ack
'O'll;
'0'
( D(3)='l') and (D(2)='l') and
D(l)
' 0'
0 ) and (ack
) ) ;
( D ( 3 ) ' 0 ' ) and ( D ( 2 )
0' )
1 ) and (req_err
'1'));
'0') and (ack
'1'
( D ( 3 ) ' 0 ' ) and ( D ( 2 ) ' 0 ' ) and
D(l)
1 ) and ( ack
'O'll;
'1'
( D(3)='0')
and
D(l)
0 ) and (req_err
'I'D;
'0') and (ack
'1'
( D(3)='0') and (D(2)='0'l and
D(l)
'1'
1 ) and (ack
) ) ;
'
'0'
( D(3)
1 )
and
D(l)
0 I),
'0'
( D(3)='l') and (D(2)='l'
and
D(l)
rl ));
( D ( 3 ) ' 0 ) and ( D ( 2 ) ' 1 )
'0 ) and (req_err
'0'));
'0') and (ack
'
'
'
( D(3)
0 ' ) and ( D ( 2 )
1 ' ) and ( D ( 1 )
0'
'
'
'
'
0 ) and ( ack
1 ) ) ;
'1'
I D(3)='0') and (D(2)='l') and (D(l)
'1'
0 ) and (ack
) ) ;
'1'
( D(3)='0') and (D(2)='l') and (D(l)
'0'
'0 ) and (ack
) ) ;
'1'
( D(3)='l') and (D(2)='l') and (D(l)
'0'));
( D(3)='0') and (D(2)='l')
1 ) and (req_err
'0') and (ack
'0'));
'1'
(
(D(2)='l') and (D(l)
1 ) and (req_err
'0') and (ack
'1'));
'1'
( D(3)='l') and (D(2)='l') and (D(l)
' 1'
1 ) and (ack
) ) ;
'1'
( D(3)
'l') and (D(2)='l'l and (D(l)
' 0'
1 ) and (ack
) ) ;
'0'
( D(3)='0') and (D(2)='l') and (D(l)
D(0)
and
(a21
'1')
'0';
=
'1'
or
when
(a24
((al
=
'1'))
'1')
or
(a2
Purpose
else
find_soi
module,
find the
marker
A-19
Author
Douglas A.
Created
30-Mar-1994
Carpenter
SOI
Revised
find
architecture
soi_arch
of
find_soi
is
a28
<=
'0'
a29
<=
'0'
a30
<=
'0'
a31
<=
'0'
signal
signal
aO
std_ulogic;
a32
<=
'0'
signal
al
std_ulogic
a33
<=
'0'
signal
a2
std_ulogic
a34
<=
'0'
signal
a3
std_ulogic
a35
<=
'0'
signal
a4
std_ulogic
signal
a5
std_ulogic
signal
a6
std_ulogic
signal
a7
std_ulogic
signal
a8
std_ulogic
signal
a9
std_ulogic
signal
alO
std_ulogic
signal
all
std_ulogic
signal
al2
std_ulogic
signal
al3
std_ulogic
signal
al4
std_ulogic
signal
al5
std_ulogic
signal
al6
std_ulogic
signal
al7
std_ulogic
signal
al8
std_ulogic
signal
al9
std_ulogic
signal
a20
std_ulogic
signal
a21
std_ulogic
signal
a22
std_ulogic
signal
a23
std_ulogic
signal
a24
std_ulogic
signal
a25
std_ulogic
signal
a26
std_ulogic
signal
a27
std_ulogic
signal
a28
std_ulogic
signal
a29
std_ulogic
signal
a30
std_ulogic
signal
a31
std_ulogic
signal
a32
std_ulogic
signal
a33
std_ulogic
signal
a34
std_ulogic
signal
a35
std_ulogic
downto
0);
elsif
(clock'
(next_ack
<=
a2
(D(1)='0')
<=
(reset,
((D(3)
'0'l
D <
"
'0
<=
al
<=
0'
a2
<=
0';
a3
<=
0'
a4
c=
a5
<=
0';
0';
a6
i=
0'
a7
<=
0';
a8
<=
0';
a9
i=
(work_req(l)
(work_req(0)=*l'
<=
a4
0';
(err
and
((D(3)='0'l
all
<=
'0'
al2
<=
'0'
al3
<=
'0'
al4
<=
'0'
al5
<=
'0'
al6
<=
'0'
al7
<=
'0'
al8
<=
'0'
al9
<=
'0'
a20
<=
'0'
a21
<=
'0'
a22
<=
'0'
a23
<=
'0'
a24
<=
'0'
a25
<=
0'
a26
<=
0'
a27
<=
'0'
'0')
'
and
and
)=
(work_reg (2
and
'0') and
'1'));
(D(2)='0')
and
'0'J
and
(work_req
"001")
(next_ack
'0'));
'0') and (err
((D(3)='0') and (D(2)='0'l and
and
'0')
'1') and (data(6)
(D(0)
=
<=
a5
(D(l)='l')
and
(next_ack
<=
a6
(D(l)='l'l
'
0'
((D(3)='0') and
and
(D(0)
'1')
=
) ) ;
(D(2)='0'J and
and
(data(5)
=
'0'
'0'
'0'
and
(next_ack
<=
a7
(D(l)='l')
'
0'
((D(3) '0M and

and
(D(0)
'1')
=
) ) ;
(D(2)
and
'0'J
and
(data (4)
and
<=
'0'
((D(3)='0') and
and
(D(0)
'1')
=
) ) ;
(D(2)='0') and
and
(data(3)
=
and
clock)
'0'));
(D(2)='0'l and
1 )
0 ' ) and
(D(1)
(next_ack
'0') and (err
'0'));
(D(3)='0!
alO <=(
) and (D(2)='0') and
(D(l)='l') and (D(0)
'1') and (data(2)
'0')
then
<=
a9
'
'
((D(3)='0')
and
(D(0)
and
'
and
(next_ack
<=(
all
(D(1)
'0'
and
)='
and
<=
(D(1)='0')
alO
and
D000";
0';
aO
and
(data (7
) ) ;
(D(2)
and
(next_ack
(reset
'0'
) );
(D(2)='0'l
and
(D(1)='0')
begin
if
and
(D(0)='l')
(next_ack
a3
'0'
((D(3)='0'l
and
(D(l)='l')
process
pr
and
(data="llllllll"
(next_ack
and
and
a8
pro :ess
(clock
'0')) then
aO <=
((D(3)='0'l and (D(2)='l') and
)='
1 ' )
(D(l)='l') and (D(0)='0'1 and (data (2
(next_ack='0'
) ) ;
al <=
((D(3)='0') and (D(2)='0') and
(D(l)='l'l and (D(0)='1'1 and
begin
soi
and
event)
[clock'last_value
'
(0)
'
0'
and
'
) ) ;
(D(2)='0')
and
'1')
and
'
) and
(next_ack
'0') and (err
'0'));
(D(3)='0'
al2 <=(
) and (D(2)='0') and (D(l)
and
(D(0)
'1') and (data(l)
'0') and
'
(next_ack
0 ' ) ) ;
(D(3)='0'
al3 <=(
) and (D(2)='0') and (D(l)
and
(D(0)
'1') and (data(0)
'0') and
' 0'
(next_ack
) ) ;
(D(3)='0'
al4
<=(
) and (D(2)='l') and (D(l)
and
(D(0)
'0') and (data(7)
'1') and
(data (6) = '1') and (data (5)
'0')
(data(4)
'1') and (data (3)
'1') and
(data (2)
'0') and (data(0)
'0')
(next_ack
'0'));
(D(3)='0'
al5 <=(
) and (D(2)='l'j and (D(l)
and
0 ' ) and
(D(0)
'1'
(next_ack
) ) ;
=
(D(3)='0'
'1')
'1')
and
'
'
and
al6
'
'
<=(
'
1 ' ) and
(D(0)
(next_ack
=
al7
[D(0)
A-20
(D(2)='0')
and
and
'
<=(
1 ' )
(D(3)='0'
and
'1'
and
) )
(D(2)='0')
and
(D(l)
(next_ack
<=(
al8
0')
(err
and
(D(2)='0'l
and
'0'));
(D(l)
'1'
and
or
'1')
or
(a21
or
(a31
'0'));
(D(2)='0'l
and
<=(
(D(3)='0'
'0'
(D(0)
)
(data(0)
and
and
(D(l)
and
'1')
(next
and
ack
(D(0)
and
'0')
(data (4)
(a33
or
'0'
'1')
'0';
'1')
'0';
'1'
'1'
<=
ack
(a29
or
'1')
'1')
or
'1')
or
(a23
or
(al7
(a20
'1')
(a25
or
'1')
'1')
(a27
or
(a33
or
'1')
'1')
(a35
or
'I'D;
values
'1')
or
(al3
(a24
(a9
when
'1')
'1')
(a20
or
'1'
((aO
'1')
'1'
)
or
(a5
or
(a7
(alO
or
(all
'1')
or
(a4
or
(a28
(a30
'1'
next_req
(a2
'1')
'1') or
( (al4
'1')) else
when
(a32
( (a31
'1') or
'I'D else
(a34
(a6
'1')
(a22
(a25
'1'
'1'
) )
or
(a8
or
or
(a21
'1'
'1')
(a23
or
'1')
'1')
'1'
)
(al2
or
or
(al
or
'1')
'1'
'1')
'1'
or
or
or
or
'1'
when
(al9
=
(a32
or
or
or
<=
'1')
'1')
output
<=
req_err
'0') and
) ) ;
a23 <=( (D(3)='0' )
and
(D(2)='l') and (D(l)
'1') and (D(0)
'0') and (data(5)
'1') and
' 0'
(next_ack
) ) ;
(D(3)='0'
a24
<=(
) and (D(2)='l') and (D(l)
'1') and (D(0)
'0') and (data (6)
'0') and
'0'
(next_ack
) );
a25 <=( (D(3)='0' )
and
(D(2)='l') and (D(l)
'1') and (D(0)
'0') and (data (7)
'0') and
' 0'
(next_ack
) ) ;
a26 <=((D(3)='0')
and
(D(l)
'
'
1 ' ) and ( D ( 0 )
0 ' ) and
(next_ack
'0'));
'1') and (err
a27
<=( (D(3)='0' ) and (D(2)='0') and
[D(1)='0') and (D(0)='l') and (err
'1'));
(D(3)='l'
a28 <=(
) and (D(2)='l') and
(D(l)='l') and (D(0)='0'| and (work_req(l)
'1'));
(D(3)='l'
a2 9
<=(
) and (D(2)='1'J and
(D(l)='l!) and (D(0)='0') and (work_req(2)
'I'D;
(D(3)='l'
a30 <=(
) and (D(2)='l'( and
(D(l)='l') and (D(0)='0') and (work_req(0)
'I'D;
(D(3)='l'
a31 <=(
(D(l)='l') and (D(0)='1'1 and (work_req(l)
'I'D;
(D(3)='l'
a32 <=(
) and (D(2)='l'l and
(D(l)='l') and (D(0)='l') and (work_req(2)
'I'D;
(D(3)='l'
a33 <=(
(D(l)='l') and (D(0)='1'1 and (work_req(0)
'I'D;
(D(3)='l'
a34
) and (D(2)='0') and
<=(
(D(l)='l') and (D(0)='1'1 and (isr_latch_ack
'O'D;
(D(3)='0'
a35 <=(
) and (D(2)='0r) and
'1'));
(D(l)='l'l and (D(0)='0'| and (err
'1') or (al8
'1') or (al4
D(3) <= ((a3
or
'1')
'1') or (al9
'1') or (a27
(a28
'1') or (a30
'1') or (a29
'1')
'1') or (a33
'1') or (a32
'1') or (a31
and
or
(a22
soi_process;
process
assign
(next_ack
'1')
or
(al6
'1')
or
if;
end
<=( (D(3)='0' ) and (D(2)='l') and (D(l)

(D(0)
'0') and (data (3)
'0') and
'0'
(next_ack
) ) ;
<=( (D(3)='0'l and (D(2)='l') and (D(l)
=
a22
'1')
(a34
'1')
end
and
(al8
'1')
or
'0'));
a21
(a24
'1')
'0'));
(D(2)='l')
and
=
(al3
or
a20
'1')
(D(0)
'1') and
(isr_latch_ack
al9 <=( (D(3)='l'
) and
'1') and
(isr_latch_ack
and
(D(0)
'1'
(D(3)='l'
else
'0';
<=
isr_latch
(a27
or
'1')
'0';
[al8
'1')
'1'))
"00000001"
(a27
or
((a3
when
(a35
or
<=
isr_data_in
'1'
'1')
'1')
when
or
(al8
or
'1')
else
((a3
(a35
'1') or
'I'D else
=
"00000000";
find
end
soi
arch;
COMPONENT:
find
DESCRIPTION:
Find the SOF
sof
marker module
(entity)
Name
sof_entity
Purpose
SOF
Finds
module.
the
start
of
Frame
marker.
If
approriate
other
modules
are
markers
found before
SOF,
signalled.
Author
Douglas
Created
04-APR-1994
A.
Carpenter
Revised
library and
library ieee;
use
clauses
use
ieee.
std_logic_1164
use
ieee
=
.
all;
library
all ;
use
my_packages;
my_packages
.package_l
all;
or
(a34
D(2)
<=
or
(a28
'1')
((al4
=
or
(a33
D(l)
'1')
or
<=
(al5
'1'
or
(a28
'1')
or
(a33
'1'
or
<=
(a4
'1'
or
(alO
(a29
'1')
or
'1')
'1')
a31
or
entity
(a26
find_sof
port
or
inputs
(a32
or
is
in
std
ulogic
in
std
ulogic
in
clock
reset
'I'D;
'1')
'1')
or
'1')
or
'1')
or
((aO
'1')
or
(a5
'1')
or
or
(al2
(al4
work_req
'1')
(a26
or
data
std_ulogic_vector
(a7=
(7
downto
or
'1')
(a32
or
'1')
or
(a3
or
(a8
0);
next_ack
in
std_ulogic;
err
in
std_ulogic;
isr_latch_ack
in
std_ulogic;
qtable_ack
in
std_ulogic;
htable_ack
in
std_ulogic;
table
in
std_ulogic;
or
'1')
'1') or
0);
'1'));
'1')
=
or
or
=
'1')
(a2
or
=
'1')
(a31
=
'1')
(al9
or
(a34
'1')
or
(a29
'1')
(a9
or
(al6
'1')
'1')
) );
'1')
or
((al
'1'
(al5
or
or
(a34
(a6
(a35
or
(a30
D(0)
(al7
'1')
)
'1')
'1')
(a30
'1'
'1'
A-21
err
req_err
out
std
ulogic
ack
out
std
ulogic
next_req
isr_latch
out
std
ulogic
std
ulogic
isr_data_in
out
(D(l)
'
'
0 )
) and ( D ( 2 )
'0') and (next_ack
' 0'
(err
and
) );
<=
'1')
'ID and (D(2)
((D(3)
'1')
'0') and (htable_ack
'
( 9 ) <= ( ( D ( 3 )
'ID and (D(0)
outputs
'
and
'0')
std_logic_vector (7
out
downto
and
qtable_req
std
ulogic
htable_req
out
std
ulogic
(table_err
'0'));
'0')
(D(2)
(data(2)
'0'
(next_ack
) ) ;
and
<=
'0')
'ID and (D(2)
((D(3)
a(12)
'0') and [data (5)
'ID and (D(0)
'0'
(next_ack
) ) ;
and
<=
'0')
'ID and (D(2)
((D(3)
a(13)
'0') and (data (6)
'ID and (D(0)
'0'
(next_ack
) ) ;
and
<=
'0')
'ID and (D(2)
a (14)
((D(3)
'0') and (data(7)
'ID and (D(0)
'
'
0 ) ) ;
and
( next_ack
<=
'0')
'1') and (D(2)
((D(3)
a(15)
'0') and (data(0)
'1') and (D(0)
'0'
(next_ack
) ) ;
and
<=
'0')
'ID and (D(2)
((D(3)
a(16)
0)
(D(l)
<=
((D(3)
and
(D(0)
(11)
'1')
'ID
'0')
and
(D(l)
findsof
DESCRIPTION:
(architecture)
(D(l)
Purpose
find_SOF
Author
Douglas A.
Created
04-APR-1994
module
(D(l)
(D(l)
f ind_sof_arch
of
'ID
is
find_sof
signal
std_ulogic_vector
signal
std_ulogic_vector
0);
(60 downto 0);
downto
(3
(D(l)
(reset,
'0'
and
then
"0000";
<=
'1')
(D(l)
'I'D;
(D(l)
'0')
((D(3)
(D(0)
(D(1)
"11111111")
(D(l)
(next_ack
( 1 ) <= ( ( D ( 3 )
'1') and (D(0)
'
'
and
and
'
((D(3)
and
(D(0)
'
) and
'0') and
((D(3)
and
(D(0)
'1')
and
'
(data
'
and
<=
a(23)
(D(l)
'ID
and
(next_ack
=
'0')
0'
a
'
(data
and
(D(l)
(D(l)
'0')
'0')
and
(D(2)
'ID
'
'
and
((D(3)
(D(0)
'0')
'1')
and
'0'));
(D(2)
'0')
and
and
and
'0')
'ID
and
and
=
'0'));
'0') and
(D(2)
'0')
(data(0)
=
'0'
) )
'0') and
(D(2)
'0')
(data(l)
=
'O'D;
(D(2)
and
(data
and
'0')
(3)
and
'0')
<=
(next_ack
((D(3)
and
(D(0)
(25)
'1')
'0')
'1')
'0'
and
(D(l)
'0'
)) ;
'
0 ' )
(D(2)
and
(work_req
'0')
'0')
'1')
and
) ) ;
'0') and
(D(2)
and
'0')
(data(4)
'0'
(next_ack
and
) ) ;
<=
'0') and
'0') and (D(2)
((D(3)
a(26)
'0')
'1') and (data (6)
'ID and (D(0)
'0'
(next_ack
and
) ) ;
<=
'0') and
'0') and (D(2)
a (27)
((D(3)
'0')
'ID and (data(7)
'1') and (D(0)
'0'
(next_ack
and
) ) ;
<=
'0') and
'0') and (D(2)
((D(3)
a(28)
'0')
'1') and (data (2)
'ID and (D(0)
'0'
(next_ack
and
) ) ;
<=
'0') and
'0') and (D(2)
((D(3)
a(29)
'0')
'1') and (data(5)
'ID and (D(0)
'0'
(next_ack
and
) ) ;
<=
'1') and
a (30)
'0') and (D(2)
((D(3)
and
'ID
'0')
'ID
(next_ack
and
(next_ack
and
and
<=
(24)
'ID
and
and
(D(l)
(5)
'0'
<=
(D(3)
( next_ack
'
0 ' ) and
=
'
1 ' ) )
(D(2)
(work
and
;
'
'
and
(D[l)
req
'
(next_ack
0'
and
(err
(D(l)
a
=
(6)
'0'
<=
0'
( (D(3)
and
<=
'0')
(D(2)
and
)
and
a(7)
(work
'0'
req
and
(D(l)
'I'D;
'I'D;
'ID
'ID and (D(2)
'0') and (table_err
(err
((D(3)
and
(D(0)
and
(D(0)
(next_ack
a(8)
=
<=
'1')
(htable_ack
((D(3)
(D(0)
and
and
'0')
'0')
(err
'0'
'O'D;
and
and
) )
(next_ack
'0')
'0') and (D(2)
((D(3)
'1')
'1') and (next_ack
(err
and
'O'D;
<=
'1')
((D(3)
'1') and (D(2)
a(32)
'1') and (D(0)
<=
a(31)
and
=
and
'0')
and
(D(l)
) );
(D(l)
'0')
'
'0'));
'1') and (D(2)

=
'0') and (data
(next_ack
(D(0)
and
(D(l)
"010")
( 4 ) <= (
'0') and
and
'0'
'0')
'0')
'1'));
(D(2)
(D(l)
"010")
(next_ack
((D(3)
and
(D(0)
and
) )
(D(2)
a
and
'1')
(D(l)
"11000000")
'0'
and
)
(D(l)
"11000100")
<=
and
(next_ack
((D(3)
(D(0)
and
((D(3)
and
"11011011")
<=
(isr_latch_ack
<=
a(22)
'0'
) );
(D(2)
(isr_latch_ack
<=
a(21)
and
and
'1') and
( (clock 'event) and (clock
'0')) then
( clock 'last_value
<=
'0') and
'0') and (D(2)
((D(3)
a(0)
'1') and (data
'1') and (D(0)
(D(l)
=
and
'0'
and
(next_ack
((D(3)
(D(0)
000000000000";
(D(l)
"010")
'1')
and
<=
a(20)
elsif
'ID
'0')
clock)
"0000000000000000000000000000000000000000000000000
a(3)
(next_ack
((D(3)
a(19)
=
(data(l)
and
begin
(reset
'0')
(D(l)
process
sof_process
'
and
)) ;
'0') and
(D(2)
'l'l
and
(data(3)
'ID and (D(0)
'0'
(next_ack
) ) ;
and
'0') and
'ID and (D(2)
(18) <= ((D(3)
'ID
'0') and (data (4)
'1') and (D(0)
'1')
(D(0)
and
<=
a(17)
begin
a(2)
and
and
'0']
Carpenter
Revised
and
(D(l)
'0'|
find_SOF_arch
Name
<=
and
(D(l)
<=
'1')
COMPONENT:
'1')
if
find sof;
architecture
and
and
);
end
(D(0)
a
out
a(10)
and
(D(l)
'O'D;
(D(l)
'ID
<=
a(33)
A-22
'0'
((D(3)
'0')
and
(D(2)
'1')
and
-
and
and
=
<=
a(34
(D(l)
'0
( (D(3)
'0
<=
a(36
=
(D(l)
'1
'
(D(2)
and
'0')
'
'
'
and
(next_ack
and
(D(2)
and
'
(data (7)
( (D(3)
and
(D(0)
'
'
1)
I I;
1)
1)
and
'
(next
and
(D(3)
'
'0')
(D(2)
and
'1')
'
'
ack
(D(2)
and
C=
'0'
'1')
<=
(D(l)
((D(3)
'0')
(D(2)
and
'1')
and
<=
35)
'1
(data(l)
'1')
(next_ack
and
a(39
((D(3)
'0')
(D(2)
and
'1')
40)
'1
49)
and
(data(2)
'0')
<=
a(40
( (D(3)
'
'
(D(2)
and
'
'
60)
(data (3)
'1')
(next_ack
and
8)
<=
a(41
((D(3)
'0')
(D(2)
and
'1')
(data (4 )
'1')
(next
and
(D(l)
'I'D;
'1
and
(D(l)
'I'D;
(D(l)
'I'll;
'1
(D(2)
and
'0')
(next_ack
and
'
(qtable_ack
( (D(3)
and
(D(0)
'
'
)
'0')
(D(2)
'0')
'0'));
(D(2)
=
'
3)
or
31)
or
38)
'
'
43)
'1
'0
<=
( (D(3)
(D(0)
and
'0'
and
(2)
'
(table
and
'
52)
and
5)
<=
a(46
=
'0
( (D(3)
(D(0)
a(47
(D(l)
(D(l)
'I'D;
'1
a(48
'1
(err
<=
( (D(3)
(D(0)
<=
( (D(3)
) and (D(0)
)
and
and
'
'
and
'
'
'
'
( next_ack
and
'
'
13)
'
18)
and
24)
and
(D(0)
and
a(50
(D(l)
'1
(51
(D(l)
'I'D;
'1
(qtable_ack
( (D(3)
(D(0)
<=
( (D(3)
) and (D(0)
<=
'
and
'
'
)
'0')
1 ' )
'1')
and
and
and
and
(D(2)
'0')
'1'));
(D(2)
=
'
'
'1
(53
(D(l)
'I'D;
'1
(D(l)
'I'D;
(D(l)
( (D(3)
and
(D(0)
( (D(3)
and
(D(O)
'
'
)
'1')
and
and
a(54
'1
a(55
'0
<=
( (D(3)
(D(0)
and
<=
'
'
'
)
'1')
'
)
'1')
and
and
and
'
51)
'
'
0 )
(D(2)
(work_req(2)
(work
(D(2)
56)
'1')
'1')
'
'
'
'
(qtable_ack
and
1 )
(D(2)
(work_req(0)
'
'
'1'
or
'1'
'1'
or
end
or
or
) or
'1')
'1
or
'1'
'1
or
or
'1'
or
or
a(57)
or
or
or
'1'
'1
or
or
or
or
1'
'1
or
'1'
(a(48)
'1
or
I'D;
or
'1
or
(a(15)
a (17)
'1
or
(a(21)
or
a(12)
'1'
or
a(23)
or
or
'1
'1
'1
'1
or
'1')
or
or
'1'
or
or
or
1')
or
or
'1'
or
'1'
or
(a(53)
a(55)
or
(a (48)
a(50)
or
'1
(a (32)
a(43)
or
(a(26)
a(28)
*1
'1
or
or
'1'
'1'
'1'
'1'
)
')
(a(54)
'
(a(3)
'1'
a(52)
or
or
or
or
'1'
'1'
or
(a(58)
'1')
or
);
a(60
and
if;
process
sof_process
and
assign
'1')
ack
and
or
and
or
'1'
<=
next_req
'I'D;
A-23
or
or
'1'
(a(56)
(a(52)
'1')
'1'
)
output
<=
req_err
req(l)
or
(D(0)
'1')
or
'1'
a(46)
a(54
or
and
and
'1')
l'l
'1'
a(31)
a(49
0 ) and
'1'));
0 ' ) and
(D(2)
(work_req(0)
(D(2)
or
or
a(25)
a(36
45)
or
--
<=
'1')
'1'
(a(40)
a(51)
'1'
'
a(20)
a(27
end
<=
a(52
or
(err
or
1'
a(14)
or
'1')
or
(a(34)
a(42)
or
a(53)
=
or
or
'1'
a(22
'
(a(49)
a(37)
'1'
a(44)
or
'1')
'1
'1'
a(16
29)
'
0 ' ) and
( (D(3)
'1') and (table_err
<=
a(49
'1')
or
a(19)
or
a(39)
a(ll
or
=
'1'
1)
(a (6)
or
'0'
'1'
'1'
(33)
( (a
'1'
or
or
and
) );
'
0 ) and ( D ( 2 )
1
'0'));
'
0 ' ) and ( D ( 2 )
0
'1') and (next_ack
=
'1
or
=
'1
);
(57)
0)
'1') or (a(l
1') or (a(9)
(a(8)
or
D(0)
err
'1'
a(41
'1'
or
a(55)
or
and
ack
or
=
'1
') or (a(7)
'1') or (a(20)
a(47)
or
'1
or
or
a(43)
a(35
(htable
and
'1
I
)
'
2)
(a(10)
<
'1'
'1
'1
(a(54)
1') or (a(57)
'1
or
(a(59)
or
'1'
or
D(l)
and
and
'1'
'1
a(54
'
or
a(56)
a(49
a(45
(D(l)
'I'D;
'
<=
a(44
and
'1')
'0')
0 ) and
( (D(3)
'1') and (table_err
(D(0)
(D(l)
'1'
or
a(50)
=
(a(3)
(a(7)
or
1')
(D(2)
'1'));
and
err
'1'
a(10
<=
a(43
and
((D(3)
and
(D(0)
'1
(a(34)
'1') or
or
'1
(a(39)
'1') or (a(42)
or
'1
(a(45)
'1') or (a(51)
'1'
((a
56)
<=
a(42
I'D;
0 ' ) and
(D(l)
and
or
a(41)
(53
or
ack
'O'D;
(err
and
a(30
44)
and
and
I;
<-
'1'
and
'0
or
a(37)
or
'1
D(2)
'0'));
=
'1'
a(58
'0
and
(D(l)
or
and
)
'ID
'1
'1'
a(33
55)
and
and
'0'
a(10
'1
(next_ack
and
'1'
'1')
'1'
a(52
and
(D(l)
( (a(2)
(a(6)
or
'0
'0'));
'0'
a(44
<=
'
1 ' )
(D(2)
(work_req(l)
=
or
'0'));
=
and
a(38
and
(D(l)
'1')
or
'0
)
( (D(3)
'1') and (table
'0'));
a(38
(D(0)
<=
(next_ack
and
and
( (D(3)
(D(0)
( (D(3)
<=
4)
(data(O)
'!')
and
D(3)
and
'0'
(D(0)
and
(D(0)
<=
'0'
(D(2)
'1')
(work_req(2)
=
and
a(60)
and
(57)
a(59)
and
(qtable_ack
and
<=
a(58)
'0
and
(data (6)
( (D(3)
a(37
'
'0'));
[D(l)
'0'));
I
and
'
(56)
'0')
1)
) I;
<=
a(35
(next_ack
and
'0'));
(D(l)
=
'1')
)
and
(data (5)
'0'));
when
<=
'
((a (50)
'1')
'1')
(a(9)
values
when
or
((a(3)
(a(53)
or
'
when
'1')
or
'1') or
'1'))
(a(57)
'1') or
'1'))
((a(0)
(a(ll)
(a (55)
else
'0';
(a(51)
'1')
'0';
=
else
'1') or (a(5)
'1') or (a(12)
(a(15)
(a(18)
(a(24)
(a(29)
'1')
'1')
or
'1')
or
isr_latch
'ID
1'
or
(a(22)
(a(25)
(a(27)
(a(32)
(a(46)
'1'
<=
(a(45)
or
'l')
'1')
or
'1')
'1')
'1')
'1')
'1'
) )
or
or
((a (6)
(a(14)
(a(17)
or
'1'
)
'1')
or
end
when
'1')
(a(28)
or
(a(36)
else
'0';
(a(50)
or
(a(23)
(a(26)
or
'1')
'1')
'1')
'1')
'1')
'1')
(a(60)
frheader
(architecture)
or
or
fr header
Name
Purpose
'1')
<=
"00000010"
or
(a(45)
((a(6)
'1')
or
(a(50)
'1')
'1') or (a(60)
when
'1')
(a(58)
=
Created
Revised
else
qtable_req <=
'1')) else '0';
'1'))
find
end
sof
<=
'1'
"00000000";
((a(l)
when
'1'
when
((a(2)
'1')
'1')
or
or
(a(43)
(a(7)
Purpose
decode
Author
Douglas A.
Created
14-APR-1994
frame
header
module.
Carpenter
Revised
library
library ieee;
and
use
clauses
use
ieee.
use
ieee.std_logic_1164_extensions.
use
std_logic_1164
.all;
all;
my_packages;
my_packages
.package_l.
all;
entity fr_header is
port
(
inputs
clock
reset
work
std_
ulogic
vector
(2
req
downto
0);
downto
0);
data
std_
ulogic
vector
(7
std
ulogic
signal
aO
std
ulogic;
signal
al
std
ulogic;
signal
a2
std
ulogic;
signal
a3
std
ulogic;
signal
a4
std
ulogic;
signal
a5
std
ulogic;
signal
a6
std
ulogic;
signal
a7
std
ulogic;
signal
a8
std
ulogic;
signal
a9
signal
alO
std
ulogic;
std
ulogic;
signal
all
std
ulogic;
signal
al2
std
ulogic;
signal
al3
std
ulogic;
signal
al4
std
ulogic;
signal
al5
std
ulogic;
signal
al6
std
ulogic;
signal
al7
std
ulogic;
signal
al8
std
ulogic;
signal
al9
std
ulogic;
signal
a20
std
ulogic;
signal
a21
std
ulogic;
signal
a22
std
ulogic;
signal
a23
std
ulogic;
signal
a24
std
ulogic;
signal
a25
std
ulogic;
signal
a26
std
ulogic;
signal
a27
std
ulogic;
signal
a28
std
ulogic;
signal
a29
std
ulogic;
signal
a30
std
ulogic;
signal
a31
std
ulogic;
signal
a32
std
ulogic;
signal
a33
std
ulogic;
signal
a34
std
ulogic;
signal
a35
std
ulogic;
signal
a36
std
ulogic;
signal
a37
std
ulogic;
in
std
ulogic
signal
a38
in
std
ulogic
signal
a39
in
std
ulogic;
std
ulogic;
signal
a40
std
ulogic;
signal
a41
std
ulogic;
signal
a42
std
ulogic;
signal
a43
std
ulogic;
ulogic
signal
a44
std
ulogic;
in
in
std
in
std
ulogic
signal
a45
std
ulogic;
in
std
ulogic
signal
a46
std
ulogic;
signal
a47
std
ulogic;
out
std
ulogic
signal
a48
std
ulogic;
ack
out
std
ulogic
signal
a49
std
ulogic;
next
out
std
ulogic
signal
a50
std
ulogic;
out
std
ulogic
signal
a51
std
ulogic;
signal
a52
std
ulogic;
next
ack
err
isr
latch
req
err
ack
outputs
req
isr latch
isr data in
std_ logic vector (7 downto
std_
of
frjiea<fcr
DESCRIPTION:
Decodestheframeheaderdatafromthe
compressed data stream. Found after the SOF marker
(entity)
fr_header_entity
arch
arch;
Name
fr header
signal
COMPONENT:
library
04-APR-1994
or
'0';
else
module
Carpenter
or
'I'D
htable_req
header
Douglas A.
architect ure
(a(21)
arch
'0';
else
isr_data_in
frame
Author
'1'))
COMPONENT:
DESCRIPTION:
or
(21)
(a(58)
or
)
or
or
(a
or
fr header;
or
or
'1')
(a(13)
(a(16)
out
0)
signal
a53
x_latch
out
std
ulogic
signal
a54
y latch
xy data
out
std
ulogic
signal
a55
signal
(15
downto
out
())
A-24
std
ulogic;
std
ulogic;
std
ulogic;
a56
std
ulogic;
signal
a57
std
ulogic;
signal
a58
std
ulogic;
fr
header
vector
is
(5 downto
signal
a59
std
ulogic;
a5
<=
'
0';
signal
a60
std
ulogic;
a6
<=
'
0'
signal
a61
std
ulogic;
a7
<=
'
0'
signal
a62
std_ulogic;
<=
'
0';
signal
a63
std
ulogic;
a9
<=
'
0';
signal
a64
std
ulogic;
alO
<=
'0'
signal
a65
std
ulogic;
all
<=
0'
signal
a66
std
ulogic;
al2
<=
'0'
signal
a67
std
ulogic;
al3
<=
'0'
signal
a68
std_ulogic;
al4
<=
'0'
signal
a69
std_ulogic;
al5
<=
'0'
signal
a70
std
ulogic;
al6
<=
'0'
signal
a71
std_ulogic;
al7
<=
'0'
signal
a72
std_ulogic;
al8
<=
'0'
signal
a73
std_ulogic;
al9
<=
'0'
signal
a7
std_ulogic;
a20
<=
'0'
signal
a75
std
ulogic;
a21
<=
'0'
signal
a76
std
ulogic;
a22
<=
'0'
signal
a77
std
ulogic;
a23
<=
'0'
signal
a78
std
ulogic;
a24
<=
'0'
signal
a79
std
ulogic;
a25
<=
'0'
signal
a80
std
ulogic;
a26
<=
0'
signal
a81
std_ulogic;
a27
<=
'0'
signal
a82
std
ulogic;
a28
<=
'0'
signal
a83
std
ulogic;
a2
<=
'0'
signal
a84
std
ulogic;
a30
<=
0'
signal
a85
std
ulogic;
a31
<=
0'
signal
a86
std
ulogic;
32
<=
0'
signal
a87
std
ulogic;
a33
<=
0'
signal
a88
std
ulogic;
a34
<=
0'
signal
a89
std
ulogic;
a35
<=
0'
signal
a90
std_ulogic;
a36
<=
0'
signal
a91
std
ulogic;
a37
<=
0'
signal
a92
std
ulogic;
a38
<=
0'
signal
a93
std
ulogic;
a39
<=
0'
signal
a94
std
ulogic;
a4
<=
0'
signal
a95
std
ulogic;
a41
<=
0'
signal
a96
std
ulogic;
a42
<=
0'
signal
a97
std
ulogic;
a4
<=
0'
signal
a98
std
ulogic;
a44
<=
0'
signal
a99
std
ulogic;
a4
<=
0'
signal
alOO
std
ulogic
a4
<=
0'
signal
alOl
std
ulogic
a4
<=
0'
signal
al02
std
ulogic
a4
<=
0'
signal
al03
std
ulogic
a4
<=
0'
signal
al04
std
ulogic
a50
<=
0'
signal
al05
std
ulogic
a51
<=
0"
signal
al06
std
ulogic
a52
<=
0'
signal
al07
std
ulogic
a53
<=
0'
signal
al08
std
ulogic
a54
<=
0'
signal
al09
std
ulogic
a55
<=
0'
signal
alio
std
ulogic
a56
<=
0'
signal
alll
std
ulogic
a57
<=
0'
signal
all2
std
ulogic
a58
<=
0'
signal
all3
std
ulogic
a59
<=
0'
signal
all4
std
ulogic
a60
<=
0'
signal
all5
std
ulogic
a61
<=
0'
signal
all6
std
ulogic
a62
<=
0'
signal
all7
std
ulogic
a63
<=
0'
signal
all8
std
ulogic
a64
<=
0'
signal
all9
std
ulogic
a65
<=
0'
a66
<=
0'
a67
<=
0'
a68
<=
0'
a69
<=
0'
<=
0'
a71
<=
0'
signal
downto
xy da ta
std
a8
0) ;
begin
a7
sof
process
r rocess
(reset
begin
if
'
0')
D <
"0000C 0";
aO <=
'0';
=
then
al
<=
'
'
a2
<=
'
'
a3
<=
'
'
a4
<=
'
'
0'
<=
a73
<=
'
<=
'
0'
a75
<=
'
0'
a7
(reset
a7
0'
a7
<=
'
0'
a77
<=
'
0'
a7
<=
'
0'
a7
<=
'
0'
A-25
;
;
a80
<=
a81
<=
a82
<=
a83
<=
a84
<=
a85
<=
a86
<=
a87
<=
a88
<=
<=
a90
<=
0'
a91
<=
0'
a92
<=
a93
<=
0';
0';
a94
<=
0'
95
<=
0'
96
<=
0';
a97
<=
98
<=
a99
<=
0';
0';
0';
'0';
'0';
'0';
'0';
a8
0';
0';
0';
0';
0';
0';
0';
0';
0';
0';
'
0
( (D(5)
and
(D(2)
=
'0')
'0'
(D(3
(D(3
and
(work_req
'0'
(err
) ) ;
<=
'0')
((D(5)
'
0 ) and ( D ( 2 )
=
'
al02
<=
al03
<=
al04
<=
'0'
al05
<=
'0'
al06
<=
'0';
al07
<=
al08
<=
'0';
'0';
al09
<=
'0'
allO
<=
'0'
alll
<=
'0';
all2
<=
all3
<=
all4
<=
all5
<=
all6
<=
all7
<=
all8
<=
'0';
'0';
'0';
'0';
'0';
'0',
'0',
all9
<=
<=
'1'
al
<=
'0'
'
'
and
a2
<=
'1'
and
;
and
(D(2
(D(3
and
(D(3
'
<=
'
((D(5)
(D(2)
'1'
(D(2
'0'
<=
"0000000000000000";
(D(2)
'1'
and
(clock
'1') and
'0')) then
'0') and (D(4)
((D(5)
'0') and
and
(D(2)
'1') and (D(l)
'0')
'1'
(D(0)
) and (data
'event)
(D(3
(D(3
and
and
'0'
(D(4)
'0') and (D(l)
'0'
) and (data
=
(D(2)
(D(0)
and
(D(2
and
a6
<=
'0'
(D(4)
'0') and
'
1 ' ) and
(D(1)
'0'
(next_ack
)
'1') and (D(4)

'1') and
'1') and (next_ack
'1'
0')
'0')
=
'
and
'
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and
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'1')
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'1')
and
'0') and (D(4)

'1') and
'1') and
(next_ack
'0') and (err
'0'));
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a22 <=
(
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a23 <=
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1 ) and ( D ( 1 )
1 ) and ( D ( 2 )
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a24
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a27
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1 ) and ( D ( 1 )
1 ) and
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'0'
err
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A-26
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err
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a21
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and
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a81
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a83
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a87
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i_xy_data(7
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'0'
'1'
'0'
a94
(D(2)
(D(3)
(D(2)
(err
(D(2)
'1') )
(D(2)
(D(3)
91
(D(0)
a
and
ID )
(D(2)
(D(2)
'I'D
(D(2)
(D(2)
((D(5)
<
and
and
(
and
'1'
and
'0'
a88
(D(3)
and
'0'
'0'
(D(4)
(D(2)
and
(D(2)
(D(l)
and
'0'
a86
(D(l)
and
(D(0)
(D(3)
and
and
(D(l)
(D(0)
and
and
and
'0'
'
and
(D(4 )
and
and
'1'
a85
(D(3)
a84
(D(3)
and
'O'D
(D(3)
'I'D;
(data(l)
'1') and
'1') and (D(4)
((D(5)
'
'
0 ' ) and
0 ' ) and ( D ( 1 )
'1'
(data (3)
) ) ;
<=
al04
'1') and (D(4)
'1') and
((D(5)
'0') and
'0') and (D(l)
'1'
(data (4)
) );
al05 <=
'1') and
((D(5)
'1') and (D(4)
'O'l and
'0'
'I'D;
) and (err
(D(0)
al06 <=
'1') and
'1') and (D(4)
((D(5)
'1'
and
and
(D(l)
'1'
I;
(data(2)
<=
al07
1') and
'1') and (D(4)
(D(5)
'1'
and
'1') and (D(l)
'1 D;
(data(5)
1 ' ) and ( D ( 4 )
al08 <=
'1') and
( (D(5)
'
'
and
1 '
1 ' ) and ( D ( 1 )
'1 D;
(data(6)
'1'
al09 <=
) and (D(4)
'1') and
( (D(5)
'
'
'
and
1 ) and ( D ( 1 )
1 '
'1 ) );
(data(7)
'1'
allO <=
'1') and
( (D(5)
) and (D(4)
'1'
and
'1') and (D(l)
'0 ) );
(data(O)
1
'
alll <=
1 ) and
((D(5)
'1') and (D(4
'
'
1 ) and ( D ( 1 )
and
) );
(data(l)
'
all2 <=
1 ' ) and ( D ( 4 )
1 ' ) and
( (D(5)
'
'
'
1 ) and
1 ) and ( D ( 1 )
'1'
(data (3)
all3 <=
((D(5)
'ID and
'0') and (D(4)
'
0 ' ) ) ;
'1'
<=
all4
( (D(5)
) and
'0') and
(D(l)
'1') and
'1'
(work_req(2)
) ) ;
'1'
all5 <=
( (D(5)
) and
'0') and
(D(l)
'1') and
'1 ' ) ) ;
(work_req(0)
'1'
all6 <=
( (D(5)
) and
'
'
0 ' ) and
1 ' ) and
(D(1)
(work_req(l)
'I'D;
'1'
<=
all7
( (D(5)
) and
'
0 ' ) and
(D(O)
'0') and ( isr_latch_ack
<=
al03
(D(3)
) and
'1') and
(D(2)
0'
'
and
'1'
'
'1'
((D(5)
(D(l)
(D(0)
((D(5)
and
(D(l)
(D(0)
(
and
(D(2)
(D(0)
( (D(5)
'1'
0
=
and
(err
!D(2)
'
and
'0'
0')
and
(D(3)
(D(4)
(D(l)
=
'1'
(a44
'1')
'1')
(a8
(a4
or
=
'1')
or
or
(a45
(a34
=
'1')
'1')
or
=
'1')
or
(a29
'1')
or
or
(a47
(a5
'1')
(a35
=
or
=
'1')
or
(a48
=
'1
'1')
and
or
(a51
or
(a58
or
(a66
'1')
'1')
or
or
(a52
(a49
=
'1')
'1')
or
or
(a53
(a50
=
'1')
or
(a54
=
'1
'1')
and
'1')
'1')
or
or
(a59
(a55
=
'1')
'1')
or
or
(a60
(a57
=
'1')
or
(a61
=
'1
'1')
and
or
A-28
'1')
'1')
or
or
(a67
(a63
=
'1';
'1')
or
or
(a68
(a64
=
'1'
(a69
1'
(a72
or
'1')
or
or
(a73
'1')
or
or
(a83
'1')
or
or
(a94
'1')
or
'1')
(a70
'1')
(a71
'1')
or
or
(a74
'1')
or
or
(a84
'1')
or
or
(a95
'1')
or
(a81
or
'1')
(a77
'1')
(a80
(a24
or
(a45
or
(a87
((a3
'1')
or
(al4
'1')
'1')
(a91
or
'1')
(a89
'1')
(a90
'1')
(a5
or
(alO
'1')
'1')
(al7
'1')
or
or
(a27
'1')
(a37
'1')
'1')
or
(a6
or
(al2
or
'1')
(al9
'1')
or
or
(a31
'1')
'1')
(a39
'1')
or
or
(a62
'1')
(a41
'1')
or
or
(a65
'1')
'1')
or
(a96
1'
or
or
(a88
1'
(a7
or
'1'
or
or
(a76
1'
<=
D(0)
'1')
(a99
or
'1')
(a97
(alOO
or
'1')
'1') or
=
(a98
or
(alOl
(a75
'1')
or
(a78
'1')
or
or
(a89
(a83
'1')
or
or
(a93
'1')
'1')
or
(al02
')
'1')
or
(al05
or
(alll
(all4
'1') or (al04
'1') or (al07
'1') or (al03
'1') or (al06
'1')
(all5
or
'1')
(all6
or
'I'D;
or
(al08
')
'1') or (alio
'1') or (all4
'1') or (al09
'1') or (all2
or
end
(all5
')
or
(all8
D(4)
'1'
or
<=
(al8
'1') or (all6
'1') or (all9
'1')
'1')
((a4
(a6
or
or
(a23
'1')
or
or
(a45
'1')
process
assign
'1')
next_req
(a3 = '1')
or
or
(a25
'1')
or
or
(a56
sof_process;
(all7
or
'1'));
'1')
if;
end
(all
=
or
1')
'1')
output
or
or
(a44
'1')
(a36
'1')
(a42
=
'1') or
'1'
) or
'1')
(al3
or
(all3
'1')
'1')
(a92
or
(all9
or
'1')
'1'));
or
'1')
or
(a95
(a28
'1')
'1')
(a36
or
or
<=
(a5
((aO
'1')
or
(al5
1'
or
(a31
or
(a56
'1')
(a6
(al6
or
or
(a32
'1')
'1')
'1')
(a2
or
or
=
or
or
(a33
'1')
(a9
'1')
(a4
(a43
(a44
'1')
or
or
(a65
'1')
or
(a27
ack
(a90
'1')
(a45
'1')
or
or
(a75
'1')
'1'
or
(a88
or
or
(a90
'1')
(a82
'1')
or
or
(a91
'1')
(a84
'1')
'1'
(a34='l')
) or
'1')
(all8
or
'1')
or
(all9
'1')
'1'
((a2
when
(a91
or
<=
(a3
((aO
'1')
or
(a9
'1
or
(a25
'1')
(a4
'1')
'1') or
(al5
(a32
'1')
'1')
or
(al
or
or
or
(a5
'1')
'1') or
=
(a2
'1')
(a20
or
(a36
<=
or
'1'
or
(a52
1'
'1'
or
(a45
or
(a65
'1')
or
or
(a91
'1')
'1')
'1')
'1')
or
(a59
or
(a79
'1')
or
or
(a93
'1')
or
(a67
'1')
'1')
'1')
or
(a90
'1')
(a86
'1')
(a72
(a88
=
'1'
) )
'1')
'1'
(a81
'1')
<=
or
(a5
or
(a20
'1')
or
(al3
=
'ID
((al
'1')
(a2
or
(a6
'1')
'1')
or
or
(a21
(al5
=
'1')
or
=
or
(alO
'1')
or
or
(a22
'1')
(a3
or
(a73
'1')
or
(a94
'1'
(a23
(al6
or
(a27
'1')
'1')
or
or
(a32
'1')
or
or
(a83
(a24
=
'1')
or
or
(a36
'1')
or
or
(a85
'ID
'1')
or
(a75
'1')
(a46
=
'1')
1'
or
(a95
'1')
'1')
or
or
(a90
(all4
'1')
'1') or
=
or
'1')
'1'
or
(all9
or
'1'
'1')
or
'1'
or
'1')
'1') or
(al09='l') or
(al07='l')
(all2
(all7
(alio
'l') or
'0';
(a29
'1')
or
or
'1')
'1'))
(a51
'1'
'1')
or
"00110011"
<=
(a34
(a58
'I'D;
A-29
'1'
'1')
or
(a47
'1'
(a49
'1'
(a52
or
'1')
(a50
(a53
(a29='l')
or
(a48
or
'1'
'1')
or
or
or
(a57
(a60
'1'
(a54
'1')
or
or
(a61
or
(a64
(a68
'1'
'1')
or
or
or
(a71
(a74
'1'
(a69
'1')
or
or
(a76
or
(a80
(a96
'1'
'1')
or
or
(a97
or
(a99
'1'
(al02='l')
or
(al03
or
(al05
or
(al08='l')
or
'1')
or
or
(alll
((a8
'1')
or
'1')
or
else
'1')
)
)
or
when
(a35
'1')
or
or
(a48
'1'
or
(a50
'1'
(a53
'1')
)
)
or
or
or
(a54
or
(a55
=
or
'1'
or
(all6
(al06
'1')
(a91
(all5
or
or
or
(a88
'1')
'1')
(a56
=
(a88
or
(a47
'1')
'1') or
(al01='l')
isr_data_in
(a40
1'
or
'1')
(a26
=
'1')
or
'1'
(al04
or
or
'1'
else
or
'1')
=
'1'))
or
(alOO
D(l)
(a78
or
or
'1'
'1')
(a98
(all8
(a44
or
or
'1'
(a63
(a66
'1'
(a77
=
or
or
or
=
(a44
or
or
or
or
(a84
'1'
(a43
or
else
or
'1')
(a70
'1')
'1'
'1')
(al2
or
(a21
or
((a8='l')
when
(a35='l')
or
(a38
'1')
(a24
(a42
'1')
'1'))
(a55
(a58
D(2)
(a9
or
'1')
(a49
(a51
'1'
'1')
or
(a95
<=
'1') or
'0';
isr_latch
or
'1')
or
(a78
(a6
'0';
or
'1
'1')
or
or
'1')
=
'1')
'1')
'1')
'1') or
(a46
D(3)
(al
or
(a5=
or
(al4
or
(a22
=
'1')
'1')
or
(a62
'1')
or
or
'1')
(a7
(a28
((aO
when
(a4
or
1'
values
'1'
<=
'1')
or
or
(a59
'1'
'1')
or
or
(a57
(a60
'1'
'1')
or
or
(a61
(a63
(a66
=
'1')
'1')
(a67
or
or
(a73
or
(a94
'1'
'1')
(a68
'1')
'1') or
or
Purpose
(a69
'1')
'1')
(a71
or
(a74
or
'1'
'1')
or
(a76
or
'1'
'1')
(a80
or
(a96
or
'ID
'ID or
frame
Created
Revised
module
Carpenter
A.
Douglas
04-APR-1994
(a98
'1')
(al01='l')
or
(a99
or
(al02
or
(a97
'ID
'1')
or
or
(al03
(al04
(al06='l')
'1') or
(al07='l')
or
(alio
'1') or (all7
"00000000";
'1'
<=
x_latch
xy_data
<=
req_err
<=
'1')
'1'))
(a87
(a56
when
'1')
when
'1'
<=
y_latch
'1') or (al05
or
(al08='l') or
(alll
or
'ID
'1')
'1')
else
else
std
ulogic
signal
aO
std
ulogic;
signal
al
std
ulogic;
signal
a2
std
ulogic;
of
arch
a3
std
ulogic;
signal
a4
std
ulogic;
signal
a5
std
ulogic;
signal
a6
std
ulogic;
signal
a7
std
ulogic;
signal
a8
std
ulogic;
signal
a9
std
ulogic;
signal
alO
std
ulogic;
signal
all
std
ulogic;
signal
al2
std
ulogic;
signal
al3
std
ulogic;
signal
al4
std
ulogic;
sof_process
or
'0';
'0';
dec_frame
vector
signal
else
frame
or
(al09
=c
signal
architecture
or
or
(al00='l')
'1'
) or
(all2
Decode
or
(a77
(a81
(a64
or
Author
'1')
'1'
or
or
(a70
(a72
'1'
'1')
is
downto
'1')
and
'1')
'1'));
and
(2
i_xy_data;
begin
'1')
(all5
or
'1'
when
'1')
or
((a83
(all6
'1')
'1'))
or
(all4
else
'0';
process
(reset,
clock)
begin
fr
end
header
(reset
if
arch;
COMPONENT:
deejftame
Module confols the decoding ofa frame, (entity)
DESCRIPTION;
dec_f rame_entity
Name
Decode
Purpose
Author
<=
'0'
al
<=
'
a2
<=
a3
<=
'0';
'0';
a4
<=
'0'
a5
<=
'0'
a6
<=
'0'
a7
<=
'0'
a8
<=
'0'
a9
<=
'0';
Carpenter
04-APR-1994
Created
Revised
library and
library ieee;
use
ieee.
std_logic_1164
use
ieee.
library
use
all;
.all;
clock
my_packages;
my_packages
all;
(D(0)
'0'
'0'
al2
<=
'0'
al3
<=
'0'
al4
<=
'0'
is
frame
port
(D(0)
<=
clock
in
std
ulogic
reset
in
std
ulogic
<=
ulogic
<=
vector
req
(2 downto
find
sos
decode
find
sos
decode
ack
std
ulogic
in
std
ulogic
in
std
ulogic
in
std
(work_req
err
(D(0)
ulogic
ack
find
sos
decode
scan
(
"100") and
( f ind_sos_ack
'1')
(D(l)
)
'1'));
'0'
(D(l)
)
'
dec
0 ')
and
'0'));
(
"100")
(D(l)
=
(D(1)
(find_sos_ack
<=
DESCRIPTION;
(arebitectere)
out
std
ulogic;
out
std
ulogic;
out
std
ulogic;
'
'0')
0 ' ) ) ;
(D(l)
=
Olit
std
ulogic
(D(0)
'
<=
((D(2)
'0')
and
(D(0)
(D(0)
dec
frame
and
'
0 ')
and
and
'1')
and
0 ') ) ;
(D(l)
'1') and
'0') and (decode_scan_ack
'1') and
(decode_scan_err
'0'));
<=
a7
(
(D(l)
'0'.) and
'1') and (f ind_sos_err
'I'D;
'1'
<=
a8
( (D(2)
) and
'0') and (work_req(0)
'1'));
'1'
a9 <=
( (D(2)
) and
'0') and (work_req(l)
'1'));
alO <=
( (D(2)
'1') and
'1'));
(decode_scan_err
a6
(D(0)
Name
'0'
'1'));
(
and
and
deejframe
and
frame;
COMPONENT:
and
end
'0'
outputs
req
<=
( f ind_sos_err
'
((D(2)
0') and
decode_scan_ack
'0') and
a5
err
(D(l)
and
(find_sos_ack
and
(f ind_sos_err
a4
err
scan
<=
a3
in
(clock
then
(f ind_sos_err
0);
ack
scan
(work_req
and
(decode_scan_ack
and
'1')
in
work
std
)
'0'))
'0')
event
=
((D(2)
'1')
a2
inputs
(clock'
'last_value
al
entity dec
'
<=
then
all
aO
.package_l
'
<=
elsif
alO
clauses
use
aO
Frame.
Douglas A.
'0')
"000";
<=
(D(0)
arch
A-30
<=
all
(D(0)
'
( (D(2)
and
<=
al3
<=
al4
((D(2)
<=
D(2)
'ID
(a8
or
((a3
'1')
or
(all
=
'1')
'1')
or
(al4
D(l)
<=
(a5
or
'1')
or
(a8
'ID
(all
or
) );
'1')
((aO
(al2
or
(a9
'1')
'1')
or
(a3
'1')
'1'
<=
ack
'ID
or
req_err
(all
=
(alO
'1')
'1'))
'1'
<=
else
'1'
<=
'0';
decode_scan
(aE
'1')
'0';
((a3
'1') or
'1') or (al3
=
or
'ID
(a7
'1')
end
dec
frame
or
(a9
'1')
((a2
'1'
when
Finds the EOI
(al4
or
'1')
or
(a4
'1'))
(a5
'1')
else
'0';
marker
in
the compressed data
(entity)
eoi_entity
Purpose
image
eoi
finds
module,
the
start
of
marker.
Author
Douglas A.
Created
14-APR-1994
Carpenter
Revised
library and
library ieee;
use
clauses
use
ieee.
std_logic_1164
use
ieee.
library
use
(architecture)
eoi
f ind_eoi_arch
find_eoi
module
Douglas A.
Created
Revised
Carpenter
30-Mar-1994
eoi
arch
of
signal
ulogic
signal
aO
ulogic;
signal
al
ulogic;
signal
a2
ulogic;
signal
a3
ulogic;
signal
a4
ulogic;
signal
a5
ulogic;
signal
a6
ulogic;
signal
a'/
ulogic;
or
findeoi
Name
find
DESCRIPTION:
find
eoi
all;
.all;
signal
a8
ulogic;
signal
a9
ulogic;
signal
alO
ulogic;
signal
all
ulogic;
signal
al2
signal
al3
signal
al4
signal
al5
signal
al6
signal
al7
signal
al8
signal
al9
std
vector
(3
ulogic;
ulogic;
std
ulogic;
std
ulogic;
ulogic;
ulogic;
std
ulogic;
ulogic;
signal
a20
std
ulogic;
signal
a21
std
ulogic;
signal
a22
signal
a23
signal
a24
signal
a25
std
ulogic;
signal
a26
std
ulogic;
signal
a27
std
ulogic;
signal
a28
std
ulogic;
signal
a29
std
ulogic;
signal
a30
signal
a31
std
ulogic;
signal
a32
std
ulogic;
signal
a33
std
ulogic;
signal
a34
std
ulogic;
signal
a35
std
ulogic;
ulogic;
std
ulogic;
ulogic;
ulogic;
my_packages;
my_packages
entity find_eoi
port
begin
.package_l.all;
is
eoi
process
if
inputs
(reset
<=
'
'0')
0000";
=
clock
in
std_ulogic;
reset
in
std_ulogic;
aO
<=
'0'
al
<=
'0'
a2
<=
'0'
a3
<=
'0',
a4
<=
'0'
in
data
process
(reset,
begin
work_req
downto
next_ack
in
std_ulogic;
a5
<=
'0'
err
in
std_ulogic;
a6
<=
'0'
in
std_ulogic;
a7
<=
'0'
a8
<=
'0'
isr_latch_ack
is
"std"
arch;
COMPONENT:
DESCRIPTION:
COMPONENT:
chitecture
'0';
when
out
0)
eoi;
else
<=
downto
'I'D
find_sos
find
(7
else
when
(al2
or
end
vector
values
((a6
when
logic
Author
sof_process;
output
ulogic;
assign
std
Purpose
'1')
process
std
Name
end
ulogic;
out
'1') );
D(0) <= ((aO
'1') or (al
'ID or (a2
'1') or (a3
'1') or (a4
'1') or (a7
'1') or
(all
'1') or (al2
'1') or (al3
'ID or (al4
'1') ) ;
end if;
std
or
out
(alO
or
(al3
or
or
(al4
ulogic;
next
(al3
or
or
(a7
or
'1')
'1')
'1')
'1')
or
ulogic;
std
and
(a7
or
(alO
or
(al
or
'1')
(al2
or
'ID
'1')
'1')
'1')
(a6
'1')),
(D(l)
(a6
or
=
'1')
'1'
(a9
std
out
isr data in
=
and
'1')
err
req
isr latch
and
'0')
'1'));
=
'1')
(work_req(2)
err
1 ') )
and
'1')
out
ack
reg
'
(work_req(l)
and
(decode_scan
and
'1')
((D(2)
'1')
'1')
(work_req ( 0 )
and
'1')
(D(0)
( (D(2)
<=
al2
(D(0)
'
outputs
A-31
then
clock)
downto
0)
'0';
a9
alO
<=
all
<=
al2
<=
al3
<=
'0'
al4
<=
'0'
al5
<=
'0'
al6
<=
'0'
al7
<=
'0'
al8
<=
'0'
al9
<=
0'
a20
<=
'0'
a21
<=
'0'
<=
'0'
a23
<=
'0'
a24
<=
'0'
a25
<=
'0'
a26
<=
'0'
a27
<=
0'
a28
<=
'0'
a29
<=
'0'
a30
<=
'0'
a31
<=
'0'
a32
<=
0'
a33
<=
'0'
a34
<=
'0'
a35
<=
'0'
a22
Isif
( (
(cloc k'last
<=
aO
1 1'
(D(l)
all
'0',
'0',
'0',
(D(l)
<=
'0')
(D(l)
f 1'
<=
'1')
(D(l)
<=
'1')
(D(l)
(D(l)
'
<=
'1')
(data(4)
'1')
clock'
event)
and
'0'
'1')
and
ack
( (D(3)
'OD
and
(D(0)
=
and
'1'
(D(2)
and
'0'
(data
and
and
and
ack
((D(3)
'0')
'O'D;
and
(D(2)
and
(next_ack
'0') ) ;
'0') and (D(2)
'1')
((D(3)
and
(D(0)
'0') and (data (3)
=
'
0 ')
(work_req
<=
a21
and
(D(i;
'1')
and
=
'0')
and
(err
'I'D
( (D(3)
'0') and
) and (D(0)
'ID
t 1'
'
and
'0')
<=
a22
(D(i;
'1')
0'
(next_ack
) ) ;
'1')
((D(3)
'OD and (D(2)
and
(D(0)
'0') and (data (4)
=
(D(2)
'0')
and
(data(7)
and
=
'0')
and
<=
ack
((D(3)
'0')
OD
'0') );
and
(D(2)
(work_req
and
'0'
(next_ack
) ) ;
((D(3)
'0') and (D(2)
'1')
and
(D(0)
'0') and (data(5)
=
'0')
"110")
<=
a23
and
(D(l)
'1')
and
=
'1')
and
and
(next ack
'0')
((D(3)
'0') and
ID
ID and (D(0)
=
<=
a5
_
(err
'0') ) ;
'
0 ') and
(D(2)
and
(data(6)
'0')
'
0 ') ) ;
( next_ack
((D(3)
'0') and (D(2)
'1')
and
(D(0)
'0') and (data(6)
=
and
<=
a24
(D(l]
'1')
and
=
'0')
and
and
(next
'
( next_ack
'0'));
ack
'0') and
((D(3)
'ID
ID and (D(0)
<=
a6
(D(2)
and
'
'
)
(data (5)
=
'0')
<=
a25
and
(D(l)
'ID
'
0 ') ) ;
((D(3)
'0') and (D(2)
'1')
and
(D(0)
'0') and (data (7)
=
and
=
'0')
and
and
(next
<=
a7
_
1 1'
ack
[next_ack
'O'D;
'0') and
[ (D(3)
'1')
) and (D(0)
=
'
'
0 )
(D(2)
and
(data(4)
=
(D(1)
'0')
<=
a26
and
'1')
( (D(3)
and
(D(0)
=
(next
<=
a8
_
ID
ack
'0'));
'0') and
((D(3)
and
'ID
(D(0)
=
<=
a27
'0')
(D(2)
(data(3)
=
and
and
'0')
(D(l)
'I'D;
(D(l)
'1')
<=
a28
and
(next
<=
a9
=
'
ID
ack
'0')
(D(0)
((D(3)
and
'O'D;
and
'0'
(D(2)
and
'
(next
'
and
ack
'0')
<=
a29
'0'
(D(l
'1')
'0') )
'0'
)
'
(next_ack
and
and
')
'1')
and
and
(err
'0'));
((D(3)
'1') and (D(2)
'1') and
'
and
0 ' ) and (work_req ( 0 )
(D(0)
=
((D(3)
'0') and (D(2)
'0') and
(D(0)
'1') and (err
'1'));
((D(3)
'1') and (D(2)
'1') and
and
(D(0)
=
and
'ID
and
'O'D
'
'0'
0' )
) and ( D ( 2 )
l(D(3)
and
'ID and (data(2)
(D(0)
(err
alO
(D(l)
and
(next
(D(l)
(next_ack
) ) ;
'ID
((D(3)
'0') and (D(2)
and
(D(0)
'OD and (data (7)
OD
<=
a4
(D(l)
'0')
'0'
and
(D(l)
and
(D(l)
(next_ack
'0') ) ;
'0')
((D(3)
'0') and (D(2)
and
(D(0)
'1') and (data(O)
'0')
(data(6)
'1') and (data(5)
'1') and (data(3)
'1') and
'1')
'0') and (data(O)
(data(2)
and
(next_ack
'0'));
<=
al5
'1') and
((D(3)
'0') and (D(2)
(D(l)
'1') and (D(0)
'0') and (next_ack
'I'D;
'0'
al6 <=
) and
(D(2)
(
'
1 ') and ( next_ack
'1') and ( D ( 0 )
(D(1)
I'D;
<=
al7
'0') and
'0') and (D(2)
((D(3)
'1') and
(D(0)
'ID and (next_ack
(err
'O'D;
<=
al8
'0') and
((D(3)
'1') and (D(2)
'ID and (isr_latch_ack
'0') and (D(0)
(D(l)
'O'D;
al9 <=
'0') and
'1') and (D(2)
((D(3)
'1'));
(D(0)
'1') and (isr_latch_ack
<=
a20
'1') and
((D(3)
'0') and (D(2)
'0')
'0') and (data(O)
(D(l)
'1') and (D(0)
and
and
a3
'OD
and
(next
(D(l)
al4
<=
a2
and
and
"11111111 ")
(D(l)
(err
'O'D;
'0')
'0') and (D(2)
((D(3)
and
*1D and (data(l)
(D(0)
=
al3
and
(clock
'1')
) ) then
'
1 ')
( (D(3)
'0') and ( D ( 2 ) =
) and (D(0)
'0') and (data (2)
'OD
and
value
<=
al
_
(D(l)
and
al2
(next
(D(l)
'0')
'OD and (D(2)
((D(3)
'ID and (next_ack
(D(0)
and
and
and
"110"
<=
ID
(D(l
and
<=
a30
'ID
<=
a31
ack
'ID
'0')
and
(n ext
((D(3)
'1') and (D(2)
'1') and
(D(0)
and
(D(l
'O'D,
'ID
A-32
'
'
((D(3)
'1') and (D(2)
'1') and
'
1 ' ) and (work_req ( 0 )
(D(0)
=
and
<=
a32
(D(l)
'I'D;
Name
((D(3)
'1') and (D(2)
'1') and
and
(D(0)
=
'1')
<=
Purpose
((D(3)
'1') and (D(2)
'0') and
(D(0)
=
'1')
and
an
or
(a34
D(2)
<=
or
(a27
(a33
or
( (al4
'1')
=
(al5
or
(a35
or
'1
(al5
or
(a29
or
'1'
<=
D(l)
)
')
(a30
'1')
(a31
or
'I'D;
'1')
(a26
or
use
mgc_portable.qsim_logic.all;
use
mgc_portable. gsim_relations.
use
ieee.
std_logic_1164
use
ieee.
use
'1
( (al
'1')
'1
D;
) or
or
'1')
al6
'1')
(al4
or
(al7
or
(a29
or
'1')
'1
or
(a26
or
'1')
a30
'1'
components
use
my
components
.huff
use
my_
my_
components
use
my
components
use
my_
components
use
my
components
use
(a27
'1'
use
use
use
(a32
'1
( (aO
'1'
)
'1
or
(a33
or
(a2
(a34
or
use
'I'D;
use
<=
D(0)
(a4
or
(all
or
'1')
(
'1')
or
(a7=
(a8
or
or
'1'
al2
'1')
'1')
'1') or
(a3
or
(a6
or
'1'
or
(alO
(al3
use
or
use
use
'1')
or
(al6
(al9
or
'1'
'1
or
(al7
or
'1')
a20
'1')
(al8
or
(a21
or
'1'
use
or
'ID
(a31
or
(a22
'1
(a24
'1
'1')
)
)
or
or
(a23
or
(a25
'1')
a32
'1')
'1')
or
(a28
or
(a33
or
'1')
components
components
end
process
(a33
components
components
components
components
'1')
'1')
'0';
((a31
(a34
'1'))
((al4
when
(a30
'1'
<=
'1')
(a32
or
(a27
((aO
when
(a7
or
'1')
(a5
(al
or
'1')
(alO
'1')
or
'1')
or
(all
(a8
'1')
'1')
(al2
or
(a9
or
(al3
'1')
'1')
or
(a22
'ID or (a20
'1') or (a23
'1') or
'1') or (a24
'1'
) )
<=
isr_latch
=
'1')
'0';
'1')
find
,huff_
load_size
.all;
load_code
.all;
reg256by8
.huff_
reg256byl
.huff
'
or
'
((a2
when
(a35
or
'1'))
gen. all;
is
ulogic,
in
std
ulogic,
htable_ack
out
std
ulogic
next_req
out
std
ulogic
next_ack
in
std
ulogic
err
in
std
ulogic
out
std
ulogic
DCmax_WEl
out
std
ulogic
out
std
ulogic
DCval_WEl
out
std
ulogic
ACmin_WEl
out
std
ulogic
ACmax_WEl
out
std
ulogic
ACvalptr_WEl
out
std
ulogic
ACval_WEl
out
std
ulogic
huff_DIN
out
(al8
or
std
ulogic
std
ulogic
'1')
else
(a28
'1')
when
or
((a2
(a35
eoi
'ID or
"I'D else
=
DESeSIPTION:
(entity)
0);
(3
downto
out
0)
huff_LDl
out
val_DINl
out
std_ulogic_vector
(7
downto
(7
downto
val_LDl
);
end
definehtable
(15 downto
0)
val_RWADR
arch;
COMPONENT:
in
downto
DCmin_WEl
std_ulogic_vector
"00000111"
(7
huff_WADR
'ID
.all;
6. all;
htable_req
"00000000";
end
all;
ulogic,
std_ulogic_vector
<=
isr_data_in
(al8
all;
std
else
'0';
(a28
vals_load er
out
std_ulogic_vector
or
(a25
or
huf f_ bits_load er
DCvalptr_WEl
11;
table_err
'1')
len_loade r.all;
.huff_
data
or
(a6
or
a 11;
ulogic.
'1')
std
'1')
or
(a21
acdcsel
.huff
std
or
or
lencntr
.huff_
.all;
all;
in
std_ulogic_vector
'1')
'1')
in
else
'1') or
'1')) else
(a4
or
'1')
vals_addr
clock
values
when
or
or
next_req
or
(a3
'1')
'ID
.huff_
'1'
<=
=
'1'
.all;
bits. all;
entity define_htable
'I'D;
bits_addr
components .huff] acdc_reg. all;
eoi_process;
output
<=
'0'
ack
(a35
or
.huff
reset
assign
(a29
load. all;
.huff_
components .huff_ vals
if;
req_err
or
'1
read_in. a 11;
components
components
controlle r.all;
.huff
components
port
(a34
all;
or
end
all;
my_compon ents;
components
use
'1')
or
(a31
or
all;
all;
.package_l.
my_
my_
my_
my_
my_
my_
my_
my_
my_
my_
my_
my_
use
(a9
my_packages;
my_packages
library
or
'1')
loading
(a32
or
or
(a34
(al9
the
controls
Carpenter
18-APR-1994
use
'1'
A.
Douglas
Created
library
or
or
that
library and use clauses

library mgc_portable, ieee;
'1'
Module
table
'1')
huffman
Author
=
((D(3)
'0') and (D(2)
'0') and
(D(l)
'1') and (D(0)
'I'D;
'0') and (err
D(3) <- ((a2
'1') or (al4= '1') or (al8
'1'
'1'
a27
) or (al9
or
'1') or
)
'1'
(a28
'1 ) or (a29
) or (a30
'1'
or
(a31
a32
'ID or
'1')
'1') or (a33
'1')
htable
Revised
<=
a35
'1')
define
of
a34
(D(l)
'0'));
and
<=
a33
(D(l)
'I'D;
((D(3)
'1') and (D(2)
'1') and
(D(0)
'1')
define
COMPONENT:
A-33
htable;
<fefine
htable
out
0)
;
out
DESGRffTIOJN;
set
(architecture)
define htable
Name
arch
Purpose
of
define
all
huff man table
submodules
that
control
module.
the
out
std
ulogic;
out
std
ulogic;
hlength
in
std
ulogic
18-APR-1994
Carpenter
end
Revised
of
def ine_htable
is
huf f_controller
component
port
clock
in
std
ulogic;
reset
in
std
ulogic;
out
std
ulogic;
table
err
htable
req
in
std
ulogic;
htable
ack
out
std
ulogic;
out
std
ulogic;
hreset
std
ulogic) ;
huff_bits_l Dader
(
clock
in
std
ulogic;
hreset
in
std
ulogic;
hbits_req
in
std
ulogic;
hbits
out
std
ulogic;
err
out
std
ulogic;
next_req
out
std
ulogic;
ack
in
std
ulogic;
err
in
std
ulogic;
data
in
std
ulogic_vector
out
std
ulogic;
out
std
ulogic;
in
std
ulogic;
out
std
ulogic_vector
ack
next
std
ulogic;
bits
out
std
ulogic;
bits_inc
in
std
ulogic;
ack
in
std
ulogic;
in
std
ulogic) ;
huff
reset
bits
inc
bits
DIN1
LD1
out
std
ulogic;
bits_WEl
out
std
ulogic;
hlength
in
std
ulogic_vector
out
std
ulogic;
in
std
ulogic) ;
bits
read_ ir
clock
in
std
ulogic;
dec
hreset
in
std
ulogic;
dec
in
std
ulogic;
in
req
hread
in
ack
end
ack
out
std
ulogic;
out
std
ulogic;
in
std
ulogic;
hbits_ack
in
std
ulogic;
clock
in
std
ulogic;
hvals
in
std
ulogic;
hreset
in
std
ulogic;
err
in
std
ulogic;
hvals
req
in
std
ulogic;
req
out
std
ulogic;
hvals
ack
out
std
ulogic;
req
out
std
ulogic;
hlbv
err
out
std
ulogic;
req
out
std
ulogic) ;
next
req
out
std
ulogic;
next
ack
in
std
ulogic;
err
in
std
ulogic;
data
in
std
ulogic
out
std
ulogic;
in
std
ulogic;
reset
out
std
ulogic;
out
std
ulogic;
in
std
ulogic;
out
std
ulogic;
in
std
ulogic;
out
std
ulogic
hlbv
hlen
ack
hbits
hvals
port
huff_load
port
downto
in
std
ulogic;
Ln
std
ulogic;
std
ulogic;
dec
( 5Ut
std
ulogic;
dec
(3Ut
std
ulogic;
std
ulogic;
bits
inc
hcode_ack
std
ulogic;
bits
inc
hgen
ack
Ln
std
ulogic;
vals
inc
hscg
err
Ln
std
ulogic;
vals
inc
DUt
std
ulogic;
vals
DIN1
3Ut
std
ulogic;
DUt
std
ulogic) ;
hload_req
hload
ack
herr
hsiz
ack
hsiz
req
hcode_req
hgen_req
ulogic
vb
downto
component
huff_len_ Lo ader
std_ulogic;
hreset
in
std
hlen
req
in
std_ulogic;
hlen
ack
out
std
hlbv
err
out
std_ulogic;
next
req
out
std_ulogic;
next
ack
in
std_ulogic;
in
std_ulogic;
err
data
ack
in
std
ulogic_vector
LD1
ulogic;
std
ulogic;
bits
addr
in
std
ulogic
vector
data
in
std
ulogic
vector(7
DIN1
out
std
ulogic
vector
(7
RWADR
out
std
ulogic
vector
(7
vector
(0
downto
0);
downto
0);
val
LD1
out
std
ulogic;
WEI
out
std
ulogic;
ACval_WEl
out
std
ulogic;
in
std
ulogic
val
DCval
ACDC
downtc
A-34
(3
std
val
0) ;
(7
out
0);
(7
vector
out
downto
ulogic;
ack
0);
ulogic;
ack
0);
vals_WEl
bits
in
downto
0);
downto
(
clock
(15
vector
vals
component;
(7
in
hlength
std
vector
0);
clock
hreset
port
huff_vals_l oader
component
component;
component
(15
component;
:
ack
(7
0);
downto
hread
ack
0);
downto
(7
0);
downto
out
hlen
downto
out
re q
herr
end
req
in ac k
component
end
en
hlbv
component;
port
ulogic
in
herr
end
ulogic;
std
hload
hload
(0
std
out
hread
hread
vector
in
component;
port
def ine_htable_arch
(15
0);
component
architecture
vector
acdc
Douglas A.
vector (is
data
ack
acdc
tables
Created
ulogic
set
dec
downto
Author
std
dec
loading
huffman
out
0);
downto
Connects
data
0);
downto
OD;
data
out
end
huff
component
set_data
downto
in
std_ulogic_vector
0) ;
dec
in
std_ulogic;
set
in
std_ulogic;
clock
in
std_ulogic;
hlength
ou
out
std_ulogic_vector
in
std
ack
out
std
ulogic
hscg
err
out
std
ulogic
(15
bits
addr
out
std
ulogic
bits
inc
out
std
ulogic
bits
inc
in
std
ulogic
std
bits
data
ack
ou
out
hsize
(15
std
std_ulogic);
huf f_acdc_reg
std
ulogic
out
std
ulogic
hsize
out
addr
vector (7
downto
vector(7
downto
downto
downto
downto
end
( 0 downto
out
std
ulogic
clock
in
CLK
in
std
ulogic;
hreset
in
EN
in
std
ulogic;
hcode
req
in
in
std
ulogic);
hcode
ack
out
std
ulogic;
out
std
ulogic;
huff
load
hscg
huff_bits
DIN1
err
end
RADR1
in
std_ulogic_vector
(3
WADR1
in
std_ulogic_vector
(3
out
std_ulogic_vector
LD1
in
std_ulogic;
WEI
in
std_ulogic);
(7
0)
std_ulogic_vector
(15
std_ulogic_vector
component;
end
huf f_bits_addr
0)
out
std_ulogic;
out
std_ulogic;
out
out
(0 downto
0)
component;
huff_gen
component
port
hreset
in
std_ulogic;
clock
in
inc
in
std_ulogic;
hreset
in
clock
in
std_ulogic;
hbits_addr
out
std_ulogic_vector
0) ;
inc_ack
out
(3
std_ulogic);
component;
huf f_vals_addr
in
out
ulogic
hscg_err
out
ulogic
DCmin_WEl
out
ulogic
DCmax_WEl
out
DCvalptr_WEl
out
std
ulogic
std]
ulogic
std
ulogic
in
std_ulogic;
huff_DIN
out
clock
in
std_ulogic;
hvals_addr
out
std_ulogic_vector
out
std_ulogic) ;
std_ulogic_vector
std_ulogic_vector
DIN1
0)
downto
0)
downto
0)
(3 downto
huff_LDl
in
std_ulogic_vector
(7
in
out
bits_inc
out
std_ulogic_vector
in
std_ulogic_vector
in
:
(3 downto
(7
std_ulogic_vector
(7
out
std_ulogic_vector
(7
std_ulogic_vector
downto
LD1
in
std_ulogic;
in
std_ulogic) ;
std_ulogic_vector
std_ulogic_vector
end
( 0 downto
component;
huf f_load_size
component
component
clock
in
std_ulogic;
hreset
in
std_ulogic;
port(
A-35
0);
0);
out
0);
in
0)
out
( 0 downto 0);
acdc_data_out
component;
(15 downto
hcode_SEL
WEI
in
in
downto
hcode_DOUTl
DOUT1
0);
bits_addr
:
0);
0)
bits_reset
bits_inc_ack
huf f_reg256by8
ulogic
out
out
hcode_ADRl
WADR1
port
bits_data
RADR1
downto
(15 downto
huff_WADR
0)
ulogic
out
inc
ulogic
std
out
out
port
ulogic
ACmax_WEl
ACvalptr_WEl
huff_vals
std
ACmin_WEl
std_ulogic;
component;
ulogic
ulogic
hgen_ack
in
(7
std
hgen_req
hreset
0) ;
ulogic;
0)
downto
hsize_SEL
ulogic;
td
0)
downto
hcode_DINl
ulogic;
td
out
hcode_WEl
DOUT1
td
in
downto
hcode_LDl
0)
component
end
inc_ack
downto
out
hcode_ADRl
0)
port
end
downto
hsize_DOUTl
std_ulogic_vector
component
downto
std_ulogic_vector
vector (7
ulogic
in
0)
port
downto
std
code
port
component;
component
0));
std_ulogic_vector
hsize ADR1
downto
;
out
in
0)
:
component;
0);
port
hsize WEI
component
component
0]
out
ulogic
end
0);
end
in
out
downto
hsize data
std
port
ack
ulogic
LD1
ulogic
component;
component
reset
vector (7
ulogic
0) ;
dec
end
req
hsiz
lencntr
port
downto
hsiz
component;
in
0))
ulogic
std
ulogic
ulogic
DIN1
in
downto
bits_addr
std_ulogic_vector
(3
bits_data_out
std_ulogic_vector
(7
signal
vals_inc
std_ulogic;
signal
vals_DINl
std_ulogic_vector
signal
0)
downto
RADR1
in
downto
signal
0)
downto
WADR1
in
downto
0)
0) ;
(7
DOUT1
out
signal
vals_LDl
std_ulogic;
LD1
in
std_ulogic;
signal
vals_WEl
std_ulogic;
WEI
in
std_ulogic) ;
signal
vals_DOUTl
std_ulogic_vector
(7
vals_ADRl
std_ulogic_vector
(7
h_next_req
std_ulogic_wired_or
signal
vals_inc_ack
std_ulogic;
signal
hsiz_ack
std_ulogic;
signal
hcode_ack
std_ulogic;
signal
hgen_ack
std_ulogic;
signal
hscg_err
std_ulogic_wired_or
downto
downto
0)
end
0) ;
downto
component;
0) ;
0) ;
signal
huf f_reg256byl6
component
port(
DIN1
downto
0) ;
signal
:
in
std_ulogic_vector
RADR1
in
downto
WADR1
in
downto
(15
downto
std_logic;
0)
0)
0)
DOUT1
out
std_ulogic_vector
(15 downto
0)
std_ulogic;
end
LD1
in
std_ulogic;
WEI
in
std_ulogic);
signal
hsize_LDl
signal
hsize_WEl
std_ulogic;
signal
hsize_DINl
std_ulogic_vector
(7
hsize_ADR
std_ulogic_vector
(7
hsize_ADRl
std_ulogic_vector
(7
hsize_ADR2
std_ulogic_vector
(7
hsize
std_ulogic_vector
(7
signal
IN0
std_ulogic_vector
(7
downto
0)
INI
std_ulogic_vector
(7
downto
downto
SEL
std_ulogic_vector
(0 downto
downto
DOUT
std_ulogic_vector
(7
downto
downto
0)
std_ulogic;
0)
0)
signal
0)1;
0)
signal
downto
component;
std_ulogic;
0) ;
signal
end
std_ulogic;
std_ulogic;
huff_acdcsel
component
port
signal
hsiz_req
hcode_req
hgen_req
signal
component;
0)
signal
DOUT1
signal
hreset
std_ulogic;
signal
hread_in_reg
hload_req
std_ulogic;
std_ulogic;
signal
hcode_LDl
std_ulogic;
signal
hread_in_ack
std_ulogic;
signal
hcode_WEl
std_ulogic;
signal
hload_ack
std_ulogic;
signal
hcode_DINl
std_ulogic_vector
(15
signal
herr
std_ulogic_wired_or
downto
hcode_ADR
std_ulogic_vector
(7
downto
hcode_ADRl
std_ulogic_vector
(7
hcode_ADR2
std_ulogic_vector
(7
hcode
std_ulogic_vector
(15
hsize_SEL
std_ulogic_vector
(0
hcode_SEL
std_ulogic_vector
(0
signal
downto
std_ulogic;
hlen_ack
std_ulogic;
signal
hbits_ack
std_ulogic;
signal
hvals_ack
std_ulogic;
signal
hlbv_err
std_ulogic_wired_or
std_ulogic;
signal
signal
set_data
std_ulogic_vector
downto
(15
signal
downto
signal
set
std_ulogic;
signal
hlength
std_ulogic_vector
signal
dec_ack
std_ulogic;
signal
acdc_data
std_ulogic_vector
signal
acdc_en
std_ulogic;
signal
acdc_data_out
std_ulogic_vector
downto
downto
0) ;
begin
(15
0) ;
hcontr
(0
0) ;
port
signal
map
(
clock,
(0
reset,
table_err,
0) ;
signal
huf f_controller
bits_reset
htable_req,
htable_ack,
hreset,
hread_in_req,
hload_req,
std_ulogic_wired_or
std_ulogic;
bits_inc
std_ulogi c_wi r ed_or
std_ulogic;
signal
bits_inc_ack
std_ulogic;
signal
bits_DINl
std_ulogic_vector
signal
bits_LDl
std_ulogic;
signal
bits_WEl
std_ulogic;
downto
0) ;
signal
std_ulogic_wired_or
std_ulogic;
downto
DOUT1
0)
std_ulogic;
downto
dec
0)
signal
downto
std_ulogic;
0) ;
signal
0)
signal
downto
hlen_req
hbits_reg
hvals_req
0)
signal
downto
std_ulogic;
signal
0) ;
signal
signal
signal
0)
(7
hread_in_ack,
0) ;
hload_ack,
herr) ;
A-36
hreadin
hvals_load
huf f_read_in
port
map
port
map
clock,
hreset,
hreset,
hvals_req,
hvals_ack,
hlbv_err,
h_next_req,
hvals_req)
next_ack,
err,
data,
hlength,
dec,
dec_ack,
bits_reset,
bits_inc,
bits_inc_ack,
huf f_load
port
map
vals_inc,
clock,
vals_inc_ack,
hreset,
hload_req,
hload_ack,
herr,
hsiz_ack,
hcode_ack,
hgen_ack,
hscg_err,
vals_DINl,
vals_LDl,
vals_WEl,
bits_addr,
bits_data_out,
val_DINl,
val_RWADR,
val_LDl,
DCval_WEl,
ACval_WEl,
hsiz_req,
hcode_req,
hgen_req) ;
acdc_data_out
hlenreg
hlen_load
huf f_lencntr
huf f_len_loader
port
clock,
hread_in_req,
hread_in_ack,
herr,
hlen_ack,
hbits_ack,
hvals_ack,
hlbv_err,
hlen_req,
hbits_req,
hload
huf f_vals_loader
map
map (
port
set_data,
clock,
dec,
hreset,
hlen_req,
hlen_ack,
hlbv_err,
h_next_req,
set,
clock,
hlength,
dec_ack)
hacdc_reg :
huf f_acdc_reg
next_ack,
err,
data,
port
map
set_data,
acdc_data,
dec,
acdc_data_out,
set,
clock,
hlength,
dec_ack,
hreset)
acdc_en,
;
acdc_data,
hbits
acdc_en) ;
huffjoits
hbits_load
port
bits_DINl,
bits_addr,
bits_addr,
bits_data_out,
bits_LDl,
map
huf f_bits_loader
port
map
clock,
hreset,
hbits_req,
hbits_ack,
hlbv_err,
h_next_req,
bits
hbitsaddr
WEI)
huf f_bits_addr
port
next_ack,
map
bits_reset,
bits_inc,
err,
data,
bits_reset,
bits_inc,
bits_inc_ack,
bits_DINl,
bits_LDl,
bits_WEl,
hlength,
dec,
clock,
bits_addr,
bits_inc_ack)
hvals
huf f_vals
port
map
vals_DINl
dec ack) ;
vals_ADRl,
vals
A-37
ADR1,
huff_reg256by8
vals_DOUTl,
port
vals_LDl,
(
hsize_DINl,
hsize_ADR,
map
vals_WEl) ;
hvals addr
hsize_ADR,
hsize_DOUTl,
hsize_LDl,
huf f_vals_addr
port
map
hsize_WEl)
bits_reset,
vals_inc,
huffcodereg
clock,
port
vals_inc_ack) ;
(
hcode_DINl,
hcode_ADR,
hcode_ADR,
hcode_DOUTl,
hcode_LDl,
hcode WEI ) ;
map
hloadsize :
huf f_load_size
port
map
huff_reg256byl6
vals_ADRl,
clock,
hreset,
hsiz_req,
hsiz_ack,
hscg_err,
bits_reset,
bits_inc,
bits_inc_ack,
hsize_adr_sel
port
map
hsize_ADRl,
hsize_ADR2,
bits_data_out,
hsize_LDl,
hsize_WEl,
hsize_ADRl,
hsize_DINl)
huf f_acdcsel
hsize_SEL
hsize_ADR)
hcode_adr_sel
huf f_acdcsel
hloadcode
port
huf f_load_code
port
map
clock,
hcode_ADRl
next_req
define
end
<=
h_next_req;
htable
arch;
COMPONENT:
huffcontroller
DESCRIPTION:
(entity)
hcode_LDl,
hcode_WEl,
hcode_DINl,
hsize_SEL) ;
huf f_cont roll er_entity
Name
Purpose
huf fgen
huf f_gen
port
hcode_ADR2,
hcode_SEL,
hcode_ADR) ;
hreset,
hcode_req,
hcode_ack,
hscg_err,
hsize_ADR2,
hsize_DOUTl
map (
hcode_ADRl
Author
Douglas A.
Created
02-MAY-1994
map
Carpenter
Revised
clock,
hreset,
hgen_req,
hgen_ack,
hscg_err,

DCmin_WEl,
DCmax_WEl,
DCvalptr_WEl,
ACmin_WEl,
ACmax_WEl,
ACvalptr_WEl,
huff_DIN,
huff_WADR,
huff_LDl,
bits_reset,
bits_inc,
bits_inc_ack,
bits_addr,
bits_data_out,
hcode_ADR2
mgc_portable.qsim_logic.all;
use
mgc_portable.qsim_relations
use
use
ieee.
library
is
signals
clock
in
std
ulogic;
reset
in
std
ulogic;
out
std
ulogic;
table
err
htable
req
in
std
ulogic;
htable
ack
out
std
ulogic;
internal
hreset
hread in req
hload req
A-38
-all;
(
external
acdc_data_out) ;
ions
my_packages;
port
.all;
all;
std_logic_1164_ext ens
entity huf f_controller
hcode_DOUTl,
hcode_SEL,
huffsizereg
use
S-ignals
:
out
std
ulogic
out
std
ulogic
out
std_ulogic
hread
in
hload
ack
ack
herr
in
std
ulogic
in
std
ulogic
in
std
ulogic
(D(l)
'0'
)
);
end
<=
a3
(D(l)
'I'D;
<=
a4
huff controller;
COMPONENT:
DESCRIPTION:
'1') and
((D(3)
and
(D(0)
'1')
'0'
(D(3)
arch
(D(l)
'ID);
Carpenter
(D(l)
'0'));
(D(l)
huff controller
<=
Author
Douglas A.
Created
02-MAY-1994
huff_
of
iss
signal
signal
aO
std_ulogic;
signal
al
signal
a2
signal
a3
signal
a4
signal
a5
downto
0)
(D(l)
'I'D;
(D(0)
std_ulogic;
(D(0)
std_ulogic;
std_ulogic;
(D(l)
std_ulogic;
a6
signal
a7
std_ulogic;
:
(D(l)
std_ulogic;
a8
std_ulogic;
signal
a9
std_ulogic;
signal
alO
std_ulogic;
signal
all
signal
al2
std_ulogic;
signal
al3
std_ulogic;
(D(0)
1 ') and
in ack
'0'));
(htable_req
'
(hread_in_ack
1 ') ) ;
((D(3)
'0') and (D(2)
'0') and
and
'0') and (herr
'I'D;
(D(0)
((D(3)
'0') and (D(2)
'0') and
and
'1'));
(D(0)
'
'
0 ' ) and ( D ( 2 )
0 ' ) and
( (D(3)
and
'1')
(htable_req
'1'
and
(herr
) ) ;
'
'
D
3
0 ') and ( D ( 2 )
1 ') and
( ( ( )
=
and
<
<=
'1'
<
'0'
'
(hread
and
<=
al4
signal
(D(2)
(
and
'1'
(hread_in_ack
<
al3
signal
and
'0'
'0'
and
'1'));
'1'
al2
:
'1')
'
'0'
0 ') and ( D ( 2 )
and
( (D(3)
and
'I'D;
(D(0)
|(D(3)
'1') and (D(2)
'1') and
and
(D(0)
'1') and (htable_req
<=
all
:
(herr
<=
alO
std_ulogic;
ack
and
'0'
a9
and
in
'
0 ') and
( (D(3)
and
(D(0)
'0')
<=
'1'
a8
Revised
'1'
a7
Purpose
and
'0')
(hread
'0') )
(D(2)
'0') and
((D(3)
and
'1')
(D(0)
'
0 ' ) and
( (D(3)
and
'0')
(D(0)
'1'
a6
huf f_controller
(herr
and
(D(l)
(D(2)
and
'1')
(htable_req
and
<=
a5
(architecture)
architecture
'0
'1'
huffcontroller
Name
(D(2)
and
<
al5
std_ulogic;
signal
al4
std_ulogic;
signal
al5
std_ulogic;
signal
al6
std_ulogic;
signal
al7
std_ulogic;
(D(0)
al6
<=
al7
<=
or
'ID
or
( (D(3)
(
<=
D(3)
'ID
'1'
(a9
'I'D;
(D(2)
((a2
'1')
or
((a3
'1')
or
'1')
(a3
or
(al2
'1')
'1')
'i':
(a5
or
(al4
or
'1')),
begin
hcontr
process
process
(reset,
if
(reset
D
'
aO
<=
'
'
al
<=
'
'
a2
<=
'
'
a3
<=
'
'
<=
'
'
'
'
a6
<=
'
'
a7
<=
'0';
a8
<=
'
a9
<=
'
'1')
'
'
all
<=
'
'
al2
<=
'0';
al3
<=
'
'
end
'
'
'
'
al6
<=
'0';
al7
<=
'
or
(al4
'1')
((al
'1')
or
(a4
or
(a7
'1')
(a9
'1')
'1'));
=
'1')
'1')
(al2
or
(a5
or
(a8
or
'1'
'1')
(a9
(a3
or
'1')
(al4
'1'
'1')
or
or
( a7
'1')
or
(al2
(al5
(a9
output
values
;
;
<=
table_err
or
(al2
'1')
'1') and
value
'0')) then
'
'
<=
1 ' ) and
0 ' ) and ( D ( 2 )
( (D(3)
1 ' ) and (D(0)
'1') and (hload_ack
'1'
or
((a5
when
(al4
'1'))
'1')
else
or
'1')
'0';
htable_ack
'1'))
<=
((D(3 )
(herr
'
0 ')
and
0D
hreset
'
((D(3 )
(all
'O'D;
'
'1'
((a2
when
(a3
or
and
(hread_in_ack
'
(D(0)
0 ')
=
'0';
and
!')
(D(2)
and
<=
'1')
'1'
or
when
(hload
else
else
'1')
or
(al4
(al6
or
(alO
'1')
'1') or
1')
or
(al7
'0';
hread_in_req
'1'))
and
ack
((a4
(al3 ='1')
or
'1'))
'0'));
*
'
0 ) and
(D(2)
(htable_req
and
and
<=
else
<=
'
or
hcontr_process;
process
assign
<=
and
(D(l)
'O'D;
'1')
if;
end
<=
a2
al5
'
<=
(a8
or
'0'
(D(l)
'ID
((aO
'1')
'ID
al4
'
or
'
al
(a7
=
'I'D;
(al3
D(0)
<=
(a6
or
alC
'
(al5
(a6
'1') or
'1') or (al4
'1') ) ;
=
or
(al2
or
or
<=
'
<=
D(l)
'ID
a4
'1')
or
(clock'last
(D(l)
)
then
a5
aO
(a9
"0000'
<=
elsif
0')
<=
D(2)
clock)
begin
<=
'1'
when
((a4
or
(al3
'0*;
hload_req
else
A-39
'0';
<=
'1'
when
((aO
'
or
(a7
'I'D
begin
huff
end
controller
arch;
hread_process
COMPONENT:
DESCRIPTION:
huff_read_in_entity
Purpose
Author
Douglas A.
Created
02-MAY-1994

mgc_portable.qsim_logic. all;
use
mgc_portable
ieee.
use
ieee
use
library
qsim_relations
std_logic_1164
all ;
all;
std_logic_1164_ext ens ions
all ;
my_packages;
entity huff_read_in
<=
'0';
<=
'0';
a2
<=
a3
<=
a4
<=
a5
<=
a6
<=
a7
<=
a8
<=
a9
<=
'0';
'0';
'0';
'0';
'0';
'0';
'0';
'0';
alO
<=
'0'
all
<=
'0'
al2
<=
'0'
al3
<=
'0'
al4
<=
'0'
al5
<=
'0'
external
signals
clock
in
std
ulogic
'0'
(clock'
'0'
si gnals
in req
in ack
in
std
in
std
ulogic
out
std
ulogic
out
std
ulogic
(D(l)
'ID
ulogic
ack
in
std
hbits
ack
in
std
ulogic
hvals
ack
in
std
ulogic
hlbv
err
(D(2)
hvals
(D(l)
std
ulogic
out
std
ulogic
out
std
huff
(D(l)
'0'
)
ulogic
'OD
and
huffreadin
DESCRIPTION:
(architecture)
Purpose
(D(l)
'I'D;
in
arch
(D(l)
'I'D;
(D(0)
Create d
Revised
chitecture
signal
signal
signal
A.
Carpenter
02-MAY-1994
h iff
read
in
std
ulogic
aO
std
ulogic;
al
std
ulogic;
signal
a2
std
ulogic;
signal
a3
std
ulogic;
signal
a4
std
ulogic;
signal
a5
std
ulogic;
signal
a6
std
ulogic;
signal
a7
std
ulogic;
signal
a8
std
ulogic;
signal
a9
std
ulogic;
signal
alO
std
ulogic;
signal
all
std
ulogic;
ulogic;
signal
al2
std
signal
al3
std
ulogic;
signal
al4
std
ulogic;
signal
al5
std
ulogic;
of
vector
huff
(3
read
downto
err
'0')
and
(hbits_ack
and
(D(l)
'O'D;
(D(1)
'O'D;
(D(l)
'O'D;
(D(l)
'I'D;
(D(l)
'I'D;
(D(l)
'I'D;
(D(l)
'I'D;
'1')
(hlbv_err
'
'
0 ) )
(D(2)
and
=
and
(D(0)
'0')
(hlbv_err
=
;
=
'0')
(hlen_ack
and
'0'
'0'));
and
'
'
and
ack
(hbits_ack
(hvals
'O'D;
'1')
I'D;
and
(D(0)
'0')
and
<=
'ID
and
(hlen
<=
all
'
<=
'0')
al2
<=
'1')
al3
<=
'1')
al4
<=
'0')
al5
<=
'0D
and
(D(0)
'0'
and
(D(0)
'1')
and
'1')
and
(
and
'
and
ack
' r>''
and
'
and
(hlen
(D(2)
(D(0)
'
'
(hbits_ack
(D(2)
(
and
(hvals
(D(2)
'I'D;
(D(2)
ack
<=
'1')
'
and
(D(2 )
<=
'0')
alO
A-40
<=
a9
arch
'0')
( hlbv_err
(D(0)
!D(3)
'1')
a8
Douglas
Author
and
(hread_in_req
a6
read
(hlbv
and
(D(2)
<=
a7
huff
<=
'0')
a5
COMPONENT:
Name
(D(0)
and
in;
read
1 D ) ;
'0') and
(D(2)
and
(hread_in_req
(D(2)
and
ulogic
out
and
'
'0')
ack
<=
a4
req
(hlen
<=
'ID
and
hlen req
hbits req
'0')
and
std
( hlbv_err
(hread_in_req
and
'0')
);
end
a3
in
and
'0'));
(D(l)
ulogic
'1')
then
'0')
a2
hlen
(clock
and
and
=
herr
)
'0'))
<=
al
hreset
hread
clock
then
event
=
value
and
internal
<=
aO
(D(l)
'ID
al
(clock'last
is
hread
(hreset,
"0000";
aO
elsif
port
<=
Carpenter
Revised
use
(hreset
if
(entity)
Name
process
begin
huffread in
'
0 ')
ack
'1'
(hvals_ack
and
=
and
=
((D(3)
'0') and (D(2)
'1') and
(D(0)
'1') and (hread_in_req
=
and
(
and
(D(2)
(D(0)
'0')
and
(D(0)
'0')
and
(D(0)
'1')
and
(
and
(D(2)
(
and
'0')
(hlbv_err
=
'1')
(hlbv_err
(D(2)
'0'
(hlbv_err
and
=
and
=
and
=
<=
D(3)
'1')
(al4
or
(a6
or
'1')
or
'1')
'1')
(a6
or
(al4
or
<=
D(l)
((aO
(a7
or
(al3
or
(a5
'1')
'1'));
(a4
'1')
'1') or (a9
'1')
'1') or
'1'));
'1') or (al5
'1') or (a2
'1') or (a5
or
(a8
'1')
'1') or (alO
=
or(al2
='1')
(all
(al2
or
='1')
hsiz_req
hcode_req
hgen_req
out
std_ulogic;
out
std_ulogic;
out
std_ulogic
std_ulogic;
'1') or
(al3
'1') or (al4
'I'D;
'1') or (al5
D(0) <= ((aO
'1') or (al
'1') or (a3
'1') or (a5
'1') or (a7
'1')
'1') or (a8
or
(all ='1') or (al2
'1') or
(al3
'1') or (al4
'I'D;
'1') or (al5
or
in
);
huff load;
end
hscg_err
=
or
'1')
'1')
(all
(a5
or
(al5
or
((aO
or
(al3
'1')
'1')
<=
D(2)
'1')
((aO
COMPONENT:
huffload
DESCRIPTION:
(architecture)
huff
Name
load
arch
end
end
Purpose
if;
Douglas
Created
02-MAY-1994
huff
architecture
assign
output
hread_in_ack
'I'D
herr
(al3
'1'
'1')
'1'
((all
when
'1')
or
(al2
when
((aO
(al4
or
(a5
'1')
or
or
(al5
'1')
or
'1')
hlen_req
when
((al
'1') or
'1')) else
(a3
else
'1'
<=
((a2
when
'1')
or
(alO
load is
(3
downto
signal
std_ulogic_vector
(3
downto
signal
i_outs
0);
0);
std_ulogic_vector
( 4 downto
(hreset,
process
clock)
begin
'1'))
if
(hreset
'0') then
"0000";
i_outs <= "00000";
(clock'
elsif
'1') and
(
event) and (clock
'0')) then
( clock 'last_value
if (D
"0000") then
if (hload_req
'0') then
Q <= "0000";
i_outs <= "00000";
elsif
( (hload_req
'1') and (hsiz_ack
'
'0')) then
1') and (hscg_err
Q <= "0000";
i_outs <= "00000";
elsif
( (hload_req
'1') and (hscg_err
I')) then
Q <= "1111";
i_outs <= "01000";
elsif
( (hload_req
'1') and (hsiz_ack
'0') and (hscg_err
'0')) then
Q <= "0001";
i_outs <= "00100";
end if;
elsif
(D
"0001") then
if ((hsiz_ack
'0') and (hscg_err
'0')
Q
hbits_req
'I'D
huff
std_ulogic_vector
begin
*0';
else
of
hload_process
'
arch
0);
'0';
<=
load
signal
=
'0';
else
<=
values
<=
A.
Revised
hread_process;
process
Carpenter
Author
<=
'0';
end
else
huff
'1'
<=
hvals_req
'1'))
((a4
when
'1'
or
(a9
'0';
read
in
arch;
COMPONENT:
huflDoad
DESCRIPTION:
(entity)
huf f_load_entity
Name
Purpose
Author
Douglas A.
Created
02-MAY-1994
Carpenter
Revised

use
mgc_portable.qsim_logic.
use
use
ieee.
std_logic_1164
use
ieee.
library
"0001";
<=
"00100";
elsif
(hscg_err
'1') then
<=
"1111";
Q
i_outs <= "01000";
elsif
( (hsiz_ack
'1') and
i_outs
.all;
all;
.all;
'
port
<=
all;
my_packages;
entity huff_load
then
0'
) )
(hscg_err
then
is
<=
"0011";
<=
"00000";
if;
i_outs
(
external
end
signals
in
clock
std
elsif
ulogic;
if
internal
in
std
ulogic;
req
in
std
ulogic;
hload
ack
out
std
ulogic
out
std
ulogic
herr
hsiz
hcode
hgen
ack
ack
ack
in
std
ulogic;
in
std
ulogic;
in
std
ulogic;
"0011") then
'1') then
=
<=
"0011";
i_outs <= "00000";
elsif
(hsiz_ack
'0')
Q <= "0010";
<=
i_outs
"00010";
end if;
elsif
(D
"0010") then
if ((hcode_ack
'0')
signals
hload
hreset
(D
(hsiz_ack
then
'
A-41
'
) )
then
and
(hscg_err
<=
"0010";
i_outs
<=
<=
"00010";
(hscg_err
elsif
'
end
1')
"1111";
<=
"01000";
i_outs
( (hcode_ack
elsif
'0'))
load arch;
huff
then
huf f_bits_addr
COMPONENT:
'1')
and
(hscg_err
()
DESCRIPTION:
then
<=
"0110";
Q
i_outs <= "00000";
end if;
(D
elsif
if
"0110")
(hcode_ack
1') then
"0110";
i_outs <= "00000";
elsif
(hcode_ack
'0') then
Q
<=
<=
huf f_bits_addr_entity
Name
then
'
Huffman
bits
Author
Douglas
A.
Created
06-MAY-1994
Purpose
array
addresser
module
counter
Carpenter
"0100";
<=
"00001";
Revised
i_outs
if;
end
(D
"0100") then
( (hgen_ack
'0') and
elsif
library and
library ieee;
if
(hscg_err
'0'))
clauses
use
ieee.
std_logic_1164
use
ieee.
then
all;
.all;
<=
"0100";
i_outs <= "00001";
elsif
(hscg_err
'1') then
Q <= "1111";
<=
i_outs
"01000";
elsif
( (hgen_ack
'1') and
library
use
(hscg_err
my_packages;
my_packages
all;
.package_l
entity huf f_bits_addr is
inputs
port
then
'O'D
use
hreset
in
in
<=
"0101";
i_outs <= "00000";
end if;
elsif
(D
"0101") then
'
if (hgen_ack
1') then
<=
Q
"0101";
i_outs <= "00000";
elsif
(hgen_ack
'0') then
Q <= "0111";
i_outs <= "10000";
end if;
elsif
(D
"0111") then
if (hload_req
'1') then
<=
"0111";
Q
i_outs <= "10000";
elsif
'0') then
(hload_req
Q <= "0000";
i_outs <= "00000";
end if;
elsif
(D
"1111") then
if (hload_req
'1') then
<=
"0111";
Q
i_outs <= "01000";
elsif
'0') then
(hload_req
Q <= "0000";
i_outs <= "00000";
end if;
Q
std_ulogic;
inc
std_ulogic;
clock
in
std_ulogic;
outputs
hbits_addr
out
std_ulogic_vector
(3
downto
inc_ack
0);
out
std_ulogic) ;
end
huff bits
addr;
COMPONENT:
huffbitsaddr
DESCRIPTION:
(architecture)
--
Name
huf f_bits_addr_arch
Purpose
huf f_bits_addr_
Author
Douglas A.
Created
06-MAY-1994
module
Carpenter
DAC
Revised
architecture
of
huf f_bits_addr
signal
b_addr
std_ulogic_vector
l_ack
std_ulogic;
(3
downto
0);
else
huf f_bits_addr_arch
is
<=
signal
"0000";
<=
"00000";
begin
i_outs
if;
if;
end
end
hl_Process
process
(hreset, inc)
begin
end
process
if
(hreset
b_addr
assign
<=
values
<=
'1')
and
<=
i_outs ( 4 ) ;
i_outs(3);
h2_Process
hsiz_req
<=
<=
(hreset
i_ack
i_outs(l);
elsif
<=
process
(hreset,
clock)
begin
i_outs(2);
if
hcode_req
hgen_req
<=
Q;
hload_ack
herr
output
'
1') then
"0000";
elsif
((inc'event) and (inc
(inc'last_value
'0')) then
b_addr <= b_addr + "0001";
end if;
end process hl_Process;
hload_process;
A-42
'
'
then
( (clock 'event)
(clock'last
i_outs ( 0 ) ;
<=
' 1'
value
'0'))
and
(clock
then
'1')
and
if
(inc
'1 ')
i_ack
then
<=
'1';
<=
'0'
REGISTER_FILE_write_Process
else
variable
i_ack
end
if;
if;
assign
write
h2_Process;
output
<=
hbits_addr
values
<=
load
b_addr;
addr
15;
to_Integer
:=
LD1
end
end
(entity)
library IEEE;
use
IEEE. std_logic_1164
use
IEEE. std_logic_1164_extensions. all;
.all;
LL_to_VHDL
to
be
'1'
Tue
at
May
'
'
WADR1,0);
then
DIN1;
REGISTER_FILE_write_Process;
process
rtl;
COMPONENT:
huffvalsaddr
DESCRIPTION:
(entity)
09:08:37
)
<=
(waddr)
if;
WEI;
and
ram
huffbits
by
LD1
and
integer
to
address
:=
(load
arch;
end
COMPONENT:
DESCRIPTION:
(need both WEI
mode?
convert
waddr
if
Written
0 to
range
std_ulogic;
high)
i_ack;
huff bits
end
begin
process
inc_ack
load
integer
waddr
variable
end
end
(DIN1, WEI, LD1,WADR1)
process
huf f_vals_addr_entity
Name
1994
Parameterized Generator
Specification
to
VHDL
counter
LogicLib
Passed
generator
Parameters
tinst
Douglas A.
Created
06-MAY-1994
Carpenter
library and
library ieee;
use
clauses
use
ieee.
16
use
ieee.std_logic_1164_extensions
library
is
all;
.all;
my_packages;
my_packages.package_l. all;
entity huf f_vals_addr

port
inputs
(
(
DIN1
std_ulogic_vector
in
(7
downto
0);
RADR1
std_ulogic_vector
in
(3 downto
WADR1
std_ulogic_vector
(3
0);
downto
out
downto
(7
in
std_ulogic;
inc
in
std_ulogic;
clock
in
std_ulogic;
outputs
in
0);
end
LD1
in
std_ulogic;
WEI
in
std_ulogic
);
huffbits
DESCRIPTION;
(architecture)
out
std_ulogic
0) ;
inc_ack
out
std_ulogic);
huff
vals
addr;
COMPONENT:
huffvalsaddr
DESCRIPTION:
(architecture)
Description
huff_bits Architecture
rtl
architecture
is
huff_bits
of
ramword
is
std_ulogic_vector
(7
downto
vector (7
hvals_addr
huff bits;
COMPONENT:
is
hreset
0);
downto
DOUT1
std_ulogic_vector
subtype
Entity Description
entity huff_bits
port
std_logic_1164
use
huff_bits
addresser
Revised
are:
read_ports
end
array
are:
huff_bits
name
parameters
vals
module
Author
REGISTER_FILE
called:
Huffman
Purpose
Code
Name
huf f_vals_addr_arch
Purpose
huf f_vals_addr_
Author
Douglas A.
Created
06-MAY-1994
module
Carpenter
DAC
Revised
0) ;
rammemory is
type
(15 downto
array
0)
of
architecture
signal
ram
signal
rammemory;
of
huf f_vals_addr
v_addr
std_ulogic_vector
i_ack
std_ulogic;
(7
downto
0);
begin
signal
REGISTER_FILE_read_Process:
variable
raddrl
process
integer
begin
(ram, RADR1)
range
number
to
15;
begin
hl_Process
Process
convert
raddrl
DOUT1
end
huf f_vals_addr_arch
is
ramword;
:=
<=
process
the
port
read
address
integer
to
to_Integer
'
'
&
process
(hreset, inc)
begin
if
(hreset
'1') then
"00000000";
elsif
((inc 'event) and (inc
'1')
(inc'last_value
'0')) then
<=
v
v_addr
addr + "00000001";
RADR1,0);
v_addr
rami raddrl);
<=
REGISTER_FILE_read_Process;
A-43
and
if;
end
end
if
process
(hreset,
'
RADR1,0);
ram(raddrl);
process
clock)
REGISTER_FILE_write_Process :
(hreset
i_ack <=
'1')
'
'
then
( (clock 'event)
|clock'last_value
'0'))
'1'
<=
'
'
<=
'
'
i_ack
(clock
and
'1')
and
( DIN1 , WEI , LD1 , WADR1 )
variable
waddr
variable
load
integer
range
to
255;
std_ulogic;
begin
then
(inc
process
elsif
if
<=
D0UT1
end
h2_Process
begin
to_Integer
:=
raddrl
hl_Process;
process
then
(need both
mode?
write
WEI
and
LD1
to be
high)
else
i_ack
convert
if;
if;
end
end
end
waddr
load
h2_Process;
process
if
to_Integer
:=
LD1
(load
'
'
&
WADR1,0);
WEI;
and
then
'1')
integer
to
address
:=
(waddr) <= DIN1;

end if;
end process REGISTER_FILE_write_Process;
ram
assign
inc_ack
output
<=
values
i_ack;
hvals_addr
<=
v_addr;
end
huff_vals_addr_arch;
end
COMPONENT:
DESCRIPTION:
rtl;
COMPONENT:
hufflencntr
DESCRIPTION:
(entity)
huffvals
(entity)
library IEEE;
use
IEEE.
use
IEEE.std_logic_1164
Name
huf f_lencntr_entity
std_logic_1164. all;
Written
by
extensions. all;
LL_to_VHDL
Tue
at
May
09:08:37
Purpose
huffman data
Author
Douglas A.
Created
05-MAY-1994
length
counter
module
Carpenter
Revised
1994
Parameterized Generator Specification to VHDL
library and
library ieee;
Code
LogicLib
Passed
generator
Parameters
tinst
parameters
256
use
ieee.
std_logic_1164
use
ieee
use
std.textio. all;
are:
library
use
port
in
RADR1
Description
downto
is
WADR1
DOUT1:
(7
downto
0);
0);
in std_ulogic_vector (7 downto 0);
out std_ulogic_vector (7 downto
0);
std_ulogic_vector
in
in
LD1,WE1:
all ;
my_packages;
.
all;
data
in
std_ulogic_vector
0) ;
dec
in
std_ulogic;
set
in
std_ulogic;
in
std_ulogic;
clock
downto
(15
outputs
hlength
downto
std_ulogic
);
end
entity huff_lencntr is
port
inputs
(
DIN1
all;
set
Entity
entity huff_vals
REGISTER_FILE
are:
read_ports
huff_vals
clauses
huff_bits
name
called:
use
end
0) ;
dec
huff
ack
out
std_ulogic_vector
out
std_ulogic) ;
(15
lencntr;
huff vals;
COMPONENT:
huffvals
DESCWTJON;:
(architecture)
Description
huff_vals Architecture
architecture
subtype
rtl
huff_vals
of
ramword
is
COMPONENT:
buff_lencntr
DESCRIPTION:
(architecture)
Name
--
std_ulogic_vector
(7
downto
Purpose
0);
Author
type
rammemory is
array
(255 downto
0)
huffman data
Douglas A.
arch
length
counter
module
Carpenter
DAC
rammemory;
begin
architecture
signal
variable
lencntr
05-MAY-1994
Revised
ram
huff
Created
of
ramword;
signal
is
raddrl
integer
process
range
(ram,RADRl)
0 to
signal
begin
Process
the
address
read
port
to
number
integer
A-44
of
huff
std_ulogic_vector
d_ack
std_ulogic;
0);
255;
begin
convert
huf f_lencntr_arch
d_len
lencntr
is
(15 downto
Hl_Process
process
(set, dec,
huff_acdcsel Architecture
set_data)
begin
if
architecture
(set
'ID
d_len
<=
(dec
and
'1')
huf f_acdcsel_Process
and
(dec'last_value
'0')) then
d_len <= d_len
"0000000000000001";
end if;
process
variable
iaddress
variable
state
process
(set,
'1')
d_ack
<=
then
clock
'0';
if
(de
'1')
d_ack
when
( (clock 'event)
'last_value
'0'))
<=
'
'
<=
'
'
range
0
(7
to
1;
downto
(clock
and
'1')
and
when
then
end
'
SEL,0);
:=
IN0;
=>
:=
others
:=
state
'
=>
state
then
is
state
elsif
to_Integer
:=
when
(set
(IN0, INI, SEL)
integer
std_ulogic_vector
iaddress
case
clock)
begin
if
process
:
begin
iaddress
0);
Hl_Process;
H2_Process
is
begin
set_data;
=
end
Description
huff_acdcsel
of
then
((dec'event)
elsif
rtl
INI;
=>
INI;
case;
else
d_ack
Assign
if;
if;
end
end
end
H2_Process;
process
assign
output
dec_ack
<=
hlength
<=
<=
DOUT
end
end
outputs
state;
huf f_acdcsel_Process;
process
rtl;
values
d_ack;
d_len;
COMPONENT:
huff
DESCRIPTION:
(entity)
acdc
reg
library IEEE;
huf f_lencntr_arch;
end
COMPONENT:
huff
DESCRIPTION:
(entity)
use
IEEE.
std_logic_1164
use
IEEE.
port
use
IEEE. std_logic_1164_extens ions. all;
.all;
in
std_ulogic_vector
out
std_ulogic_vector
in
std_ulogic;
EN
in
std_ulogic;
in
std_ulogic
CLK
by
LL_to_VHDL
at
Tue
May
10:07:38
1994
huf f_acdc_reg;
end
Code
generator
Parameters
tinst
name
type
SIMPLE
huffacdcreg
(architecture)
acdcreg Architecture Description

rtl of huf f_acdc_reg is
architecture
begin
LAT_Process:
process (D, CLK, EN, R)

begin
'0') then
Q <= "0";
elsif
(R
'1') and (EN
'1') and (CLK
numin
SW
COMPONENT:
DESCRIPTION:
huf f_acdecsel
are:
MULTIPLEXER
are:
parameters
=
called:
if
bus_mask
comp_out
(R
'1')
huff_acdcsel
Description
Entity
end
is
end
then
<=
entity huff_acdcsel
NO
end
port
( 0 downto 0);
( 0 downto 0);
);
Passed
all;
acdcreg Entity Description

entity huf f_acdc_reg is
use
LogicLib
acdcsel
library IEEE;
Written
.all;
D;
if;
process
LAT_Process;
rtl;
(
IN0
in
std_ulogic_vector
(7
downto
INI
in
std_ulogic_vector
(7
downto
SEL
in
std_ulogic_vector
(0
downto
0);
COMPONENT:
huff len loader
DESCRIPTION:
(entity)
0);
Name
0);
DOUT
out
Purpose
0)
);
end
huf f_len_loader_entity
downto
huff acdcsel;
Author
Douglas A.
Created
07-MAY-1994
Revised
COMPONENT:
huffacdcsel
DESCRIPTION;
(architecture)
library and
library ieee;
A-45
use
clauses
Carpenter
use
ieee.
use
std_logic_1164
and
.all;
(err
'1'
entity huf f_len_loader is
and
clock
in
internal
signals
in
std_ulogic;
in
std_ulogic;
elsif
hlen_ack
out
std_ulogic;
hlbv_err
out
std_ulogic;
out
std_ulogic;
in
std_ulogic;
std_ulogic;
err
in
data
in
downto
set_data
std_ulogic_vector
std_ulogic;
acdc_data
( 0 downto
<=
<=
(next_ack ='1'))
and
"00000000";
"00011")
<=
((D
(next_ack ='0'))
and
"00100000";
downto
"00010")
<=
8)
and
data;
(next_ack
'1'))
(next_ack
'0'))
(next_ack
'0')
"00010";
<=
"00000000";
i_outs
((D
elsif
hufflenloader
DESCRIPTION:
(architecture)
"00010")
and
<=
"00110";
<=
"00000001";
i_outs
((D
"00110")
) ) then
"00110";
elsif
and
(err
<=
<=
i_outs
len
loader
arch
Purpose
Carpenter
A.
Douglas
07-MAY-1994
((D
((D
"00000001";
elsif
and
Revised
(err
(err
'1'))
then
<=
Created
and
"00110") and
"11111";
i_outs <= "01000000";
elsif
Author
'0'
--
"00011")
then
COMPONENT:
--
'1')
"00010";
<=
Q
std_ulogic
out
huff
then
);
loader;
Name
(next_ack
and
"00011";
((D
elsif
signals
out
"00001")
i_length(15
std_ulogic;
0);
acdc_en
<=
in
then
'1'))
then
i_outs
reg
then
in
acdc
(err
and
"00011";
<=
"00000000";
((D
elsif
0);
:
"00001")
) )
i_outs
out
huff
<=
set
dec_ack
'0')
"00000001";
((D
'0'
out
std_ulogic;
std_ulogic_vector
(err
0);
downto
then
out
(15
(next_ack
<=
elsif
hlength
and
i_outs
dec
std_ulogic_vector
i(D
elsif
and
signals
( 15 downto
'1')
"11111";
i_outs <= "01000000";
0);
huff_lencntr
"00001")
<=
i_outs
'0') ) then
Q <= "00001";
hlen_req
next_ack
(hlen_req
'0')) then
hreset
next_req
len
(err
"00000001";
<=
((D
elsif
std_ulogic;
i_outs
and
huff
<=
Q
signals
external
end
(next_ack
port
'ID
"01000000";
"00000") and
'0') and (err
"00001";
((D
elsif
(hlen_req
and
then
<=
i_outs
my_packages;
"00000")
) )
"11111";
<=
library
((D
elsif
all;
'0'
<=
"00110")
and
(next_ack
'1')
(next_ack
'1'))
(next_ack
'0'))
then
) )
"00100";
<=
"00000000";
i_outs
huf f_len_loader_arch
architecture
std_ulogic_vector
std_ulogic_vector
( 4 downto
(4
<=
downto
"00100";
<=
"00000000";
((D
elsif
i_length
std_ulogic_vector
signal
i_acdc
std_ulogic;
signal
i_outs
std_ulogic_vector
(15
downto
and
<=
"00101";
<=
"00100000";
i_outs
downto 0)
"00101"))
"00111";
downto
((D
elsif
0);
<=
i_outs
:
process
(hreset,
clock)
begin
(hreset
if
<=
<=
i_outs
'0')
i_length
then
( (clock 'event)
'last_value
'0'))
((D
"00000")
(clock
'1')
(hlen_req
then
else
'0'))
then
<=
"01101";
<=
i_outs
"00010000";
<=
"00000";
i_outs <= "00000000";
"0000000000000000")
and
then
and
<=
"11111";
i_outs <= "01000000";
and
if
"00001000";
(hlength
if
"00000000";
elsif
clock
<=
data;
then
"0000000000000000";
"00000";
<=
"00111") then
Q <= "01111";
i_outs <= "00001000";
elsif
(D
"01111") then
(D
elsif
hload_process
<=
i_length(7
(7
begin
elsif
and
"00100")
then
0);
and
i_outs
0);
signal
"00100")
then
0);
signal
((D
elsif
is
huf f_len_loader
signal
of
((D
(next_ack
"00000")
'ID
"00000";
<=
outs
<=
and
end
elsif
(hlen_req
and
(err
'0'))
'1')
if;
((D
"01101")
and
then
then
"00000000";
A-46
<=
outs
"01101";
<=
"00010000";
(dec_ack
'0'))
((D
elsif
"01101")
and
(dec_ack
(hlength
if
'I'D
then
<=
"01100";
<=
"00000000";
((D
"01100") and
=
then
"0000000000000000")
"11111";
i_outs <= "01000000";
i_outs
elsif
<=
else
(dec_ack
'I'D
<=
then
"11011";
<=
"10000000";
i_outs
Q <= "01100";
i_outs <= "00000000";
((D
elsif
"01100")
and
(dec_ack
<=
Q
(hlength
<=
((D
"OHIO")
and
"11011";
<=
"10000000";
((D
"11011") and
(hlen_req
'0'))
"00000";
<=
"00000000";
((D = "11111") and
(hlen_req
'1'))
"11111";
<=
"01000000";
((D
"11111") and
(hlen_req
'0'))
i_outs
"OHIO";
i_outs <= "00010000";
end if;
elsif
'I'D
elsif
<=
then
else
(hlen_req
"11011")
i_outs
then
"0000000000000000")
Q <= "11111";
i_outs <= "01000000";
=
and
((D
then
'0'))
then
if
if;
end
elsif
elsif
then
(dec_ack
'0'))
<=
then
i_outs
<=
"OHIO";
<=
"00010000";
((D
"OHIO") and
elsif
elsif
i_outs
then
(dec_ack
<=
'1'))
then
"00000";
<=
"00000000";
i_outs
<=
"01010";
<=
"00000000";
((D
"01010") and
elsif
end
(dec_ack
'1'))
then
end
Q <= "01010";
i_outs <= "00000000";
((D
elsif
"01010")
if;
if;
end
i_outs
assign
and
(dec_ack
hload_process;
process
<=
output
values
'0'))
then
hlen_ack
<=
i_outs ( 7
hlbv_err
<=
i_outs ( 6 ) ;
Q;
then
if
(hlength
"0000000000000000")
"11111";
<=
i_outs
"01000000";
=
<=
else
<=
"01011";
<=
"00000001";
dec
<=
i_outs ( 4 ) ;
set
<=
i_outs(3);
i_outs
if;
end
((D
elsif
and
(err
"01011")
and
'0')
'0'
) ) then
"01011";
i_outs <= "00000001";
elsif
((D
"01011") and
Q <= "11111";
i_outs <= "01000000";
elsif
((D
"01011") and
[err
'0') ) then
Q <= "01001";
i_outs <= "00000000";
elsif
((D
"01001") and
=
<=
acdc_en
i_outs(l);
<=
and
(next_ack
(err
'1'))
(next_ack
'1')
next_req
<=
i_outs ( 0 ) ;
set_data
<=
ilength;
then
<=
acdc_data(0)
i_acdc;
end
(next_ack
'1'))
loader
(next_ack
'0'))
(entity)
(data (3
downto 0)
"0000")
"01000";
i_outs <= "00000100";
i_acdc <= data (4);
huf f_bits_loader_entity
Name
then
then
arch;
huffbitsloader
<=
"01001";
i_outs <= "00000000";
elsif
((D
"01001") and
if
len
COMPONENT:
DESCRIPTION:
then
huff
Purpose
--
<=
Author
Douglas
Created
07-MAY-1994
A.
Carpenter
Revised
else
<=
"11111";
<=
"01000000";
library and
library ieee;
i_outs
end
if;
(D
"01000") then
"11000";
i_outs <= "00000010";
elsif
(D
"11000") then
Q <= "11001";
i_outs <= "00010010";
elsif
((D
"11001") and
elsif
use
ieee
use
ieee
use
clauses
std_logic_1164
all;
<=
library
port
(dec_ack
'1'))
is
[
external
then
clock
<=
elsif
signals
in
std_ulogic;
"11001";
i_outs
((D
<=
=
"00010000";
"11001")
and
(dec
internal
ack
'0'))
hreset
then
A-47
all ;
my_packages;
entity huf f_bits_loader

=
signals
.
in
std_ulogic;
hbits
req
hbits ack
hlbv err
in
std
ulogic;
elsif
out
std
ulogic;
out
std
ulogic;
next
req
out
std
ulogic;
next
ack
in
std
ulogic;
in
std
ulogic;
err
data
std_ulogic
vector
downto
out
std
ulogic;
bits
inc
out
std
ulogic;
bits
inc
in
std
ulogic;
vector (7
ack
std
ulogic;
bits WEI
out
std
ulogic;
dec
)
out
std
ulogic;
in
std
ulogic
i_outs
arch
Carpenter
<=
"0000011000";
<=
data;
if;
(D
(D
"0101") then
'0') then
Q <= "0101";
i_outs <= "0010000000";
(dec_ack
elsif
'ID then
Q <= "0111";
of
is
std_ulogic_vector
downto
(3
i_outs
std_ulogic_vector
( 3 downto
i_outs
std_ulogic_vector
(9
i_counter
std_ulogic_vector
( 3 downto
<=
"0000000000";
if;
"0111") then
'1') then
Q <= "0111";
i_outs <= "0000000000";
(dec_ack
elsif
'0') then
if (hlength
"0000000000000000")
Q <= "1010";
i_outs <= "0100000000";
elsif
0);
(D
(dec_ack
if
downto
0);
signal
then
(dec_ack
end
signal
"0110")
(D
elsif
0);
signal
<=
if
huf f_bits_loader_arch
signal
then
'0')
"0110";
"0100") then
"0101";
i_outs <= "0010000000";
Revised
architecture
"0000000000";
i_outs
elsif
Purpose
huf f_bits_loader
<=
<=
07-MAY-1994
0);
i_data
signal
std_ulogic_vector
( 7 downto
0);
begin
else
hload
process
process
(hreset,
Q
clock)
(hreset
if
<=
i_outs
<=
i_counter
<=
i_data
<=
"1111";
<=
"0000100010";
i_counter
'0'
<=
i_outs
begin
) then
"0000";
"0000000000";
end
end
elsif
"1111";
"00000000";
(clock 'event)
and
(clock
'1')
<=
i_counter
"0001";
if;
if;
(D
"1111")
(bits_inc_ack
if
elsif
(
'0')) then
( clock 'last_value
if (D
"0000") then
if (hbits_req
'0') then
Q <= "0000";
then
=
'0')
then
<=
"1111";
i_outs <= "0000100000";
and
(bits_inc_ack
elsif
'1')
then
<=
"1101";
i_outs
<=
i_counter
'1')
and
(err
<=
<=
'0'))
"0000";
i_outs
elsif
<=
i_outs
end
"0000000000";
elsif
"1111";
( (hbits_req
elsif
'ID
if
and
(next_
ack
<=
'1')
and
(err
<=
<=
(dec_ack
and
(err
'ID
else
Q
and
(next_
ack
<=
"0011";
i_outs
<=
"0000000001";
i_outs
end
'1')
"1101") then
'1') then
"0000000000";
'0') then
if (i_counter
"1111") then
Q <= "1100";
<=
i_outs
"1000000000";
"1010";
<=
"0100000000";
=
"0000000000";
"1101";
i_outs
"0000000000";
( (hbits_req
'0'
) ) then
"0001";
<=
elsif
i_outs
elsif
(D
(dec_ack
then
( (hbits_req
<=
if;
then
'0'
'0')]
"0100";
i_outs <= "0000001100";
Douglas A.
"0000000000";
i_data
elsif
Created
<=
(next_ack
<=
end
(entity)
Author
(err
and
<=
huff bits loader
loader
'ID
"0010") then
'ID then
"0010";
(D
huff bits
"0100000000";
(next_ack
if
loader;
Name
<=
"0010";
elsif
COMPONENT:
DESCRIPTION:
then
'ID
if;
elsif
huff_bits
end
<=
end
in
ack
<=
then
"0000000001";
=
((next_ack
i_outs
0);
dec
'0'))
"1010";
i_outs
Q
out
(15 downto
<=
elsif
hlength
<=
(err
then
LD1
vector
(err
out
downto
i_outs
reset
bits
std_ulogic
if
elsif
bits
then
"0001")
(D
"0011") then
'0') and
( (next_ack
Q <= "0011";
elsif
0)
bits_DINl
std_ulogic
"0011";
i_outs <= "0001000001";
in
(7
(D
<=
if;
if;
end
end
"0001000000";
elsif
if;
if
A-48
(D
"1100")
(hbits_req
then
'1')
then
then
<=
"1100";
<=
"1000000000";
elsif
'0') then
(hbits_req
<=
"0000";
Q
<=
i_outs
"0000000000";
i_counter <= "1111";
end if;
elsif
(D
"1110") then
Q <= "0000";
i_outs <= "0000000000";
elsif
(D
"1010") then
if (hbits_req
'1') then
<=
Q
"1010";
i_outs <= "0100000000";
elsif
'0') then
(hbits_req
Q <= "0000";
i_outs <= "0000000000";
i_counter <= "1111";
end if;
elsif
(D
"1011") then
Q <= "0000";
i_outs <= "0000000000";
elsif
(data
"1001") then
Q <= "0000";
i_outs <= "0000000000";
elsif
(D
"1000") then
Q <= "0000";
i_outs <= "0000000000";
end if;
end if;
end process hload_process;
Q
port
i_outs
signals
external
in
clock
internal
signals
in
std
ulogic;
hvals
req
in
std
ulogic;
hvals
ack
out
std
ulogic
std
ulogic
hreset
std_
hlbv
err
out
next
req
out
next
ack
in
std
ulogic;
err
in
std
ulogic;
data
in
vector
ulogic
downto
(7
std_
vector
ulogic
in
(15 downto
0)
out
bits
inc
bits
inc
vals
inc
vals
inc
vector
std_
output
<=
hbits_ack
<=
LD1
out
std
ulogic
out
std
ulogic
bits
addr
in
vector
std
ulogic
vector
std_
ulogic
vector
downto
(3
0);
in
data
(7
downto
0);
(7
out
downto
0);
(7
out
downto
0);
LD1
out
std
ulogic
DCval WEI
out
std
ulogic
ACval_WEl
out
std
ulogic
val
i_outs(9);
ACDC_data_out
hlbv_err
dec
<=
<=
i_outs ( 8 ) ;
i_outs(7);
bits_reset
<=
i_outs(6);
bits_inc
<=
i_outs(5);
bits_LDl
<=
i_outs(3);
bits_WEl
<=
i_outs(2);
next_req
<=
i_outs ( 0 ) ;
2nd
huff bits
loader
std
ulogic
end
huff
vector
huffvalsloader
DESCRIPTION:
(architecture)
huff
Name
(entity)
Douglas A.
Created
07-MAY-1994
signal
0)
Douglas A.
Created
07-MAY-1994
Carpenter
signal
std_ulogic_vector
(13
i_valaddr
0) ;
begin
clauses
hload_process
all;
.
variable
all;
process
(hreset,
bits_data_counter
downto
begin
my_packages;
if
entity huf f_vals_loader
(4
i_vals_data
library
std_ulogic_vector
i_outs
signal
0) ;
downto
std_logic_1164
(4
0);
Revised
ieee.std
std_ulogic_vector
signal
downto
Author
0) ;
downto
Purpose
of
is
signal
huf f_vals_loader_entity
ieee.
Carpenter
huf f_vals_loader_arch
huf f_vals_loader
downto
use
arch
Revised
DESCRIPTION:
use
loader
vals
Author
architecture
use
loader;
vals
arch;
huffvalsloader
library and
library ieee;
in
Purpose
COMPONENT:
Name
( 0 downto 0)
COMPONENT:
--
ulogic
ulogic;
WEI
ulogic
i_data;
std
std
0);
val_RWADR
bits_DINl
ulogic
ulogic;
vals
std
Q;
std
ulogic
out
downto
bits
values
std
in
val_DINl
assign
std
ulogic;
vals
vector
ulogic
(7
out
out
out
ack
vals_DINl
ulogic
std
std
in
ack
ulogic
std
in
ack
reset
vb
<=
dec
dec
ulogic
std
0);
hlength
std_ulogic;
is
(hreset
A-49
<=
'0')
"00000";
=
then
0);
clock)
downto
<=
i_outs
"00000000";
"00000000";
<=
'
'event) and (clock

1') and
( clock 'last_value
*0')) then
if (D
"00000") then
if (hvals_reg
'0') then
Q <= "00000";
i_outs <= "00000000000000";
bits_data_counter := "00000000";
i_valaddr <= "00000000";
elsif
( (hvals_req
'1') and (next_ack
'1'
'0'
) and (err
) ) then
Q <= "00000";
i_outs <= "00000000000000";
elsif
( (hvals_req
'1') and (err
'1'))
(
elsif
(D
elsif
if
(clock
(D
"01101")
'ID
<=
<=
i_outs
=
end
ivaladdr
<=
<=
'
1')
end
then
"00100")
if
(bits_inc_ack
(D
'0')
'1')
"11111";
<=
i_outs
elsif
<=
"00011";
<=
"0000OOO00000OO";
if;
end
then
(D
elsif
"01001")
if (hlength
then
"0000000000000000")
Q <= "01000";
i_outs <= "00100000000000";
=
else
(err
i_outs
if;
elsif
then
<=
((next_ack
'0'))
then
end
"11111";
<=
"00010000000000";
if
<=
if;
(D
"01000") then
'1') then
Q <= "01000";
i_outs <= "00100000000000";
elsif
'0') then
(hvals_req
Q <= "00000";
i_outs <= "00000000000000";
end if;
elsif
(D
"11111") then
if (hvals_req
'1') then
Q <= "11111";
i_outs <= "00010000000000";
elsif
'0') then
(hvals_req
Q <= "00000";
i outs <= "00000000000000";
elsif
then
"00010000000000";
((next_ack=
'1') and (err
<=
i_outs
'0'))
(hvals_req
then
<=
"00111";
i_outs
end
elsif
if
<=
"00000000000000";
if;
(D
<=
"00111") then
'ID then
"00111";
(next_ack
i_outs
<=
"00000000000000";
(next_ack
'0') then
"01111";
i outs <= "00001000010000";
elsif
then
else
'ID
"00101") then
'0') and (err
Q <= "00101";
i_outs <= "00000000000001";
elsif
'ID
"01011";
i_outs <= "00000000000000";
then
<=
elsif
"00100";
i_outs <= "00000000000000";
"00000001";
(D
"01010") then
'1') then
( vals_inc_ack
Q <= "01010";
i_outs <= "00000000000000";
elsif
(vals_inc_ack
'0') then
Q <= "00010";
i_outs <= "00000000000000";
end if;
(D
elsif
"01011") then
if (bits_addr
"0000") then
Q <= "01001";
i_outs <= "00000000000000";
if;
(D
then
(vals_inc_ack
if
"00000000000000";
(bits_inc_ack
if
i_valaddr
if;
end
then
'0')
<=
"OHIO")
"01010";
i_outs <= "00000000000000";
"00100";
i_outs
end
<=
then
(bits_inc_ack
bits_data_counter
'0') then
"OHIO";
i_outs <= "00000000100000";
elsif
"00110";
<=
"00000010000000";
<=
:=
<=
if;
=
then
"01100")
(vals_inc_ack
if
<=
elsif
elsif
(D
elsif
i_outs
bits_data_counter
"00101";
i_outs <= "00000000000001";
(D
<=
elsif
"00110")
"10000000001000";
"00000001";
else
<=
"OHIO";
i_outs <= "00000001100000";
(D
then
"01000000001000";
if;
if;
elsif
(bits_inc_ack
"0")
<=
end
if
then
'0')
else
end
(acdc_data_out
if
elsif
then
"01100";
i_outs
then
(dec_ack
elsif
i_outs
'0'
"01101";
i_outs <= "00000000001000";
then
'1')
<=
then
"11111";
<=
"00010000000000";
elsif
( (hvals_req
'1') and (next_ack
and
(err
'0') ) then
Q <= "00001";
i_outs <= "00000100000000";
end if;
elsif
(D
"00001") then
Q <= "00011";
i_outs <= "00000100000000";
elsif
(D
"00011") then
Q <= "00010";
i_outs <= "00000000000010";
bits_data_counter := bits_data;
elsif
(D
"00010") then
if (bits_data_counter
"00000000") then
Q <= "00110";
i_outs <= "00000010000000";
"00000000001000";
<=
(dec_ack
"00001000000000";
if;
elsif
if
<=
"01101";
i_outs
end
<=
then
(dec_ack
elsif
<=
i_outs
then
"01111")
'0')
"01111";
(dec_ack
data;
if;
end
<=
i_vals_data
i_valaddr
"00000000";
:=
<=
i_vals_data
"00000000000000";
bits_data_counter
<=
A-50
then
if;
end
else
<=
std
ulogic;
std
ulogic;
"00000";
if;
if;
end
end
std
end
assign
<=
bits
inc
output
inc
data
(7
<=
dec
<=
<=
i_outs(ll);
i_outs(10);
i_outs(9);
<=
vb_reset
i_outs(8);
bits_inc
<=
i_outs(7);
vals_inc
<=
i_outs(5)
<=
vals_DINl
std
ulogic
vector
std
ulogic
vector
end
huff
lo ad
i_outs(3),
vals_WEl
<=
i_outs(2),
next_req
<=
i_outs(0),
val_DINl
<=
(7
<=
val_LDl
i_valaddr;
i_outs(3);
i_outs(12);
ACval_WEl
<=
i_outs(13);
loader
out
downto
0)
size;
huffloadsize
(architecture)
huff
load
size
A.
Author
Douglas
Created
16-MAY-1994
Carpenter
huff loadsize
(entity)
signal
std_ulogic_vector
(3 downto
signal
std_ulogic_vector
(3
signal
signal
signal
signal
signal
( 6 downto
std_ulogic_vector
(7
downto
std_ulogic_vector
(7
downto
std_ulogic_vector
(4
downto
downto
data
hload_process
if
process
(hreset,
(hreset
'0'
<=
Purpose
Author
Douglas A.
Created
16-MAY-1994
Carpenter
Revised
clauses
use
use
ieee.std_logic_1164_extensions. all;
all;
my_packages;
entity huf f_load_size
is
(
external
clock
signals
in
std_ulogic;
i_outs
internal
hreset
in
std_ulogic;
hsiz_req
in
std_ulogic;
hsiz
out
ack
hscg_err
<=
"0000000";
"0010") then
if (i
"10001") then
Q <= "1010";
i_outs <= "0001010";
i_data <= "00000000";
elsif
signals
(D
std_ulogic;
std
clock)
) then
"0000000";
Q <= "0000";
i <= "00001";
j <= "00000001";
k <= "00000000";
elsif
( clock 'last_value
'0')) then
if (D
"0000") then
if (hsiz_req
'0') then
Q <= "0000";
i <= "00001";
j <= "00000001";
k <= "00000000";
i_outs <= "0000000";
elsif
'1') then
(hsiz_req
Q <= "0001";
i_outs <= "0000001";
end if;
elsif
(D
"0001") then
Q <= "0011";
i_outs <= "0000001";
elsif
(D
"0011") then
Q <= "0010";
huf f_load_size_entity
port
downto
std_ulogic_vector
outs
library
huff_load_siz
begin
DESCRIPTION:
use
of
egm
arch;
COMPONENT:
library and
library ieee;
arch
huf f_load_size_arch
i_outs
Name
data
Purpose
i_vals_data;
vals
0);
is
<=
huff
out
addr
Revised
DCval_WEl
end
(7
ulogic
0);
downto
DESCRIPTION
architecture
<=
downto
std
in
out
COMPONENT;
i_vals_data;
<=
in
ack
out
ulogic;
Name
vals_LDl
val_RWADR
out
hsize_WEl
std
hsize
hlbv_err
out
out
ulogic;
hsize
hvals_ack
reset
hsize_LDl
std
values
Q;
bits
bits
vector
ulogic
hload_process;
process
addr
"00000000000000"
<=
i_outs
bits
else
out
ulogic;
A-51
<=
"0110";
1 ')
and
0)
0)
0)
0)
0)
0)
0)
<=
i_outs
(D
elsif
if
"0000000";
>
(j
<=
"0110") then
bits_data_out)
<=
i_outs(6),
hscg_err
<=
i_outs(5),
bits_inc
<=
i_outs(4),
then
"1101";
i_outs
<=
"0000000";
else
hsize_LDl
<=
i_outs(3);
hsize_WEl
<=
i_outs(2);
<=
"0100";
i_outs <= "0001010";
i_data <= "000" & i;
end if;
elsif
(D
"0100") then
Q <= "0101";
<=
i_outs
"0001100";
elsif
(D
"0101") then
Q <= "0111";
i_outs <= "0001100";
Q
hsiz_ack
if;
end
<=
bits_addr_reset
i_outs(0)
load
huff
end
size
elsif
(D
"0111")
arch;
COMPONENT;
huffloadcode
DESCRIPTION:
(entity)
then
<=
"1111";
i_outs <= "0000000";
<=
j
j + "00000001";
elsif(D
"1111") then
Q <= "0110";
i_outs <= "0000000";
k <= k + "00000001";
elsif
(D
"1101") then
Q <= "1100";
i_outs <= "0010000";
j <= "00000001";
i <= i + "00001";
elsif
(D
"1100") then
if (bits_inc_ack
'0') then
Q <= "1100";
i_outs <= "0010000";
elsif
(bits_inc_ack
'1') then
Q <= "1110";
i_outs <= "0000000";
end if;
elsif
(D
"1110") then
if (bits_inc_ack
'1') then
Q <= "1110";
i_outs <= "0000000";
(bits_inc_ack
elsif
'0') then
Q <= "0010";
i_outs <= "0000000";
huff
Name
load
code
entity
Purpose
Carpenter
A.
Author
Douglas
Created
16-MAY-1994
Revised
library and
library ieee;
use
clauses
use
ieee.
use
std_logic_1164
all;
.
all;
library
my_packages;
is
entity huf f_load_code
port
signals
external
in
clock
internal
std_ulogic;
signals
in
std
ulogic;
hcode
req
in
std
ulogic;
hcode
ack
out
std
ulogic;
out
std
ulogic;
hreset
hscg
end
hsize_ADRl
std_ulogic_vector
if;
(D
(7
out
downto
hsize_DOUTl
"1010") then
"1011";
Q
i_outs <= "0001100";
elsif
(D
"1011") then
Q <= "1001";
<=
i_outs
"0001100";
elsif
(D
"1001") then
Q <= "1000";
i_outs <= "1000000";
elsif
(D
"1000") then
if (hsiz_req
'1') then
Q <= "1000";
i_outs <= "1000000";
elsif
'0') then
(hsiz_req
Q <= "0000";
i_outs <= "0000000";
end if;
end if;
end if;
end process
hload_process;
elsif
err
0);
in
std_ulogic_vector
downto
(7
0);
<=
hcode_ADRl
out
std_ulogic_vector
downto
(7
hcode_LDl
0);
.
out
std_ulogic;
hcode_WEl
out
std_ulogic;
hcode_DINl
out
std_ulogic_vector
(15
downto
hsize_SEL
0);
out
std_ulogic_vector
( 0 downto
0)
);
end
huff
load
code;
COMPONENT:
huffloadcode
DESCRIPTION:
(architecture)
huff
Name
Purpose
output
Douglas A.
Created
values
code
arch
Author
assign
load
Carpenter
16-MAY-1994
Revised
D
<=
Q;
architecture
hsize_addr
<=
k;
data
<=
i data;
hsize
huff_load_code_arch
of
huff
load
code
is
A-52
signal
downto
signal
std_ulogic_vector
(3
downto
signal
i_outs
std_ulogic_vector
0)
0)
( 3 downto 0)
signal
SI
std_ulogic_vector
(7
downto
signal
downto
signal
CODE
std_ulogic_vector
0),
0),
(15 downto
if
i_data
std_ulogic_vector
(15 downto
i_sel
std_ulogic_vector
( 0 downto 0),
0);
signal
begin
"00000001";
"0111") then
hsize_DOUTl) then
Q <= "0001";
i_outs <= "0000";
i_sel <= "1";
(D
(SI
else
<=
Q
hloadc_process
begin
if
SI
if;
elsif
0);
signal
<=
SI
end
(hreset
process
(hreset,
(D
"0000")
(hcode_req
if
and
(D
then
=
<=
then
"0000";
"1";
then
"1010")
then
'1')
(hcode_req
'0')
then
<=
"0000";
i_outs <= "0000";
i_sel <= "0";
end if;
Q
else
<=
"0000";
<=
"0000";
i_outs
<=
i_sel
if;
end
assign
<=
hloadc_process;
process
end
"0";
if;
end
output
values
Q;
i_outs ( 3 ) ;
<=
hcode_ack
then
<=
hscg_err
"0010";
i_outs
"0";
&
<=
elsif
CODE;
"0011")
0)
"1010";
i_outs <= "1000";
i_sel <= "1";
i_data
(hcode_req
Q
elsif
<=
(D
elsif
'1')
downto
"00000001";
"1111")
<=
i_sel
"0111";
i_outs
'0') then
"0000";
i_outs <= "0000";
i_sel <= "0";
SI <= "00000000";
k <= "00000000";
CODE <= "0000000000000000";
i_data <= "0000000000000000";
elsif
'1') then
(hcode_req
Q <= "0001";
i_outs <= "0000";
i_sel <= "1";
SI <= hsize_DOUTl;
end if;
elsif
(D
"0001") then
Q <= "0011";
i_outs <= "0010";
i_sel <= "1";
<=
(D
<=
SI
if;
end
elsif
<=
<=
SI
"1";
CODE (14
<=
CODE
if
<=
i_sel
'0'
) then
i_outs <= "0000";
Q <= "0000";
SI <= "00000000";
k <= "00000000";
CODE <= "0000000000000000";
i_data <= "0000000000000000";
i_sel <= "0";
elsif
( clock 'last_value
'0')) then
if
"1111";
<=
"0000";
i_outs
clock)
i_outs(2);
<=
"0011";
i_sel <= "1";
(D
elsif
"0010") then
Q <= "0110";
i_outs <= "0000";
i_sel <= "1";
elsif
(D
"0110") then
Q <= "0100";
i_outs <= "0000";
i_sel <= "1";
CODE <= CODE + "0000000000000001";
k <= k + "00000001";
elsif
(D
"0100") then
if (SI
hsize_DOUTl) then
Q <= "0001";
i_outs <= "0000";
i_sel <= "1";
hcode_LDl
<=
i_outs ( 1 ) ;
hcode_WEl
<=
i_outs(0);
hcode_DINl
<=
i_data;
hcode_ADRl
<=
k;
<=
hsize_ADRl
<=
hsize_SEL
k;
i_sel;
huff
end
load
code
arch;
COMPONENT:
huffreg256by8
DESCRIPTION:
(entity)
else
<=
"0101";
<=
i_outs
<=
i_sel
use
use
IEEE.
.all;
std
extensions
if;
end
(D
elsif
if
library IEEE;
"0000";
"1";
(hsize_DOUTl
"00000000")
"1010";
i_outs <= "1000";
i_sel <= "1";
Q
all;
then
"0101")
=
then
Written
<=
by
LL_to_VHDL
at
Tue
May
09:08:37
1994
Parameterized
Generator
Specification
to
Code
else
<=
"0111";
<=
"0000";
i_sel <= "1";
i_outs
CODE
<=
CODE (14
downto
LogicLib
Passed
0)
&
"0";
A-53
generator
Parameters
called:
are:
REGISTER_FILE
VHDL
tinst
W
256
huf f_reg256by8
name
parameters
are:
256
read_ports
read_ports
huff_reg256byl6
huf f_reg256by8 Entity Description

entity huf f_reg256by8 is
port(
DIN1:
is
port(
DIN1
0);
0);
in std_ulogic_vector (7 downto 0)
0),
in
in
downto
0);
0);
downto 0);
(7 downto 0),
WADR1:
in std_ulogic_vector (7
in std_ulogic_vector (7
DOUT1:
out
LD1,WE1:
std_ulogic_vector
in
WADR1.
downto
std_ulogic_vector
in
RADR1.
RADR1:
Description
Entity
entity huf f_reg256byl6
D0UT1:
(15 downto
std_ulogic_vector
in
LD1,WE1:
(7
downto
std_ulogic
);
std_ulogic
end
huff
reg256byl6;
);
huff_reg256by8;
end
COMPONENT:
huffj-eg256by8
DESCRIPTION:
(architecture)
COMPONENT;
huff
DESCRIPTION:
(architecture)
huff_reg256by8 Architecture
subtype
rtl
is
ramword
Description
huf f_reg256by8
of
Description
huf f_reg256byl6 Architecture

rtl
architecture
architecture
reg256byl6
is
is
ramword
subtype
huf f_reg256byl6
of
is
std_ulogic_vector
(15 downto
0);
(7
std_ulogic_vector
downto
rammemory is
type
0) ;
downto
(255
array
0)
of
ramword;
type
rammemory is
(255 downto
array
0)
ram
signal
of
rammemory;
begin
ramword;
signal
ram
rammemory;
begin
REGISTER_FILE_read_Process
variable
raddrl
process
integer
( ram, RADR1 )
to 255;
begin
Process
the
convert
address
end
port
<=
number
' 0'
end
waddr
load
variable
integer
:
-
port
number
ram
integer
to
'
'
RADR1,0);
(raddrl );
range
to
waddr
variable
load
integer
:
:
range
to
255;
std_ulogic;
begin
255;
write
mode?
(need both WEI
and
LD1
high)
write
(need both WEI
mode?
LD1
and
to
be
high)
convert
waddr
convert
address
waddr
:=
to_Integer
load
:=
LD1
if
(load
(waddr)
if;
end
'
load
integer
to
'
if
WADR1,0);
:=
LD1
and
integer
to
to_Integer (
'
0'
&
WADR1,0);
WEI;
'1') then
(waddr) <= DIN1;
if;
=
ram
then
)
<=
address
:=
(load
WEI;
and
*1'
ram
end
read
to_Integer
:=
<=
variable
std_ulogic;
begin
end
variable
address
process
process
process
( ram, RADR1 )
to 255;
range
ram(raddrl);
process
the
convert
D0UT1
RADR1,0);
Process
raddrl
integer
to
to_Integer (
:=
raddrl
DOUT1
read
process
begin
range
integer
raddrl
variable
end
DIN1;
end
end
process
rtl;
process
rtl;
COMPONENT:
huff_reg256byl6
DESCRIPTION:
(entity)
COMPONENT:
huff
DESCRIPTION:
(entity)
gen
huf f_gen_entity
Name
library IEEE;
Purpose
use
IEEE.
use
IEEE.std_logic_1164_extensions
std_logic_1164
.all;
.all;
Author
Douglas A.
Created
16-MAY-1994
Carpenter
Revised
Written
by
LL_to_VHDL
at
Tue
May
09:08:37
library and
library ieee;
1994
Generator
Parameterized
Specification
to VHDL
Code
LogicLib
Passed
tinst
generator
Parameters
name
parameters
called:
ieee.
use
ieee.std_logic 1164
std
my_packages;
are:
entity huff_gen
huf f_reg256byl6
are:
port
A-54
clauses
use
library
REGISTER_FILE
use
is
all;
extensions. all;
to
be
external
i_data
signals
clock
in
<=
Q
internal
std
ulogic
hreset
in
hgen_req
in
hgen_ack
out
hscg_err
out
ulogic;
DCmin_WEl
out
ulogic;
elsif
DCmax_WEl
out
ulogic;
DCvalptr_WEl
out
out
ACmax_WEl
out
ACvalptr_WEl
out
huff_DIN
out
vector
(15
downto
std
ulogic
std_
vector
(3
downto
end
ulogic;
elsif
std
ulogic;
"00001") then
"00011";
i_outs <= "001010000000000";
ulogic;
std
ulogic;
(D
"00010") then
"00000000") then
Q <= "11111";
i_outs <= "000010000000001";
(D
elsif
ulogic;
if
(bits_data
i_outs
bits_inc
out
std_ulogic;
bits_inc_ack
bits_addr
in
std_ulogic;
vector
(7
std_
ulogic
vector
std_
ulogic
vector
std
ulogic
vector
end
huff_gen;
(0
(D
<=
0
:
(D
elsif
0)
<=
then
"00100")
"00101";
=
i_outs
<=
"000010000000001";
i_data
<=
hcode_DOUTl;
(D
<=
then
"00101")
"00111";
(acdc_data_out
<=
"0") then
"000011000000001";
=
else
<=
i_outs
(D
elsif
Purpose
A.
Douglas
Created
16-MAY-1994
then
"00111")
"01111";
=
<=
"000010000000000";
"00000001";
elsif
(D
"01111") then
Q <= "01101";
i_outs <= "000010000000000";
elsif
(D
"01101") then
Q <= "01100";
i_outs <= "000010000000001";
i_data <= hcode_DOUTl;
elsif
(D
"01100") then
Q <= "OHIO";
if
( acdc_data_out
"0") then
i_outs <= "000010100000001";
<=
bits_data
Revised
huf f_gen_arch
<=
i_outs
Carpenter
Author
"000010000100001";
if;
end
of
huff_gen
is
std_ulogic_vector
( 4 downto 0),
( 4 downto 0),
( 14 downto
std_ulogic_vector
(3 downto
0),
std_ulogic_vector
(7
0),
signal
std_ulogic_vector
signal
std_ulogic_vector
signal
outs
"000010000001001";
0)
huf f_gen_arch
Name
<=
if;
end
i_outs
(architecture)
"00100";
i_outs
if
DESCRIPTION:
then
"00110")
"0") then
"00100";
i_outs <= "000010010000001";
Q
huff_gen
j;
<=
elsif
COMPONENT:
else
downto
"00000000"
(acdc_data_out
0)
acdc_data_out
(0
if
0)
downto
<=
if;
elsif
hcode_SEL
"1111111111111111";
"00110";
<=
"000010000000001";
i_data
in
(15 downto
<=
end
0),
downto
else
downto
<=
i_data
out
std_ulogic;
ulogic
then
"00011")
<=
std_ulogic;
hcode_DOUTl
0);
signal
signal
data
signal
std
ulogic_vector
downto
(15 downto
0);
else
begin
i_outs
hloadg_process
process
(hreset,
clock)
<=
<=
<=
<=
"000000000000000";
"00000";
"0000";
"00000000";
<=
i_data
elsif
then
'0')
'last_value
event)
"000010000010001";
"0000000000000000";
(clock'
(D
elsif
(hreset
i_outs
clock
<=
"00000001";
"OHIO") then
Q <= "01010";
i_outs <= "000110000000000";
i <= i + "0001";
elsif
(D
"01010") then
if (bits_inc_ack
'0') then
Q <= "01010";
i_outs <= "000110000000000";
begin
if
<=
if;
end
out
downto
architecture
(D
<=
"11110";
i_outs <= "001010000000000";
i_data <= "0000000000000000";
ulogic;
std_
std_
if;
out
ulogic
ulogic
"00001";
<=
"001010000000000";
huff_LDl
bits_reset
hcode_ADRl
std
ulogic;
0)
bits_data
std_
std_
std_
huff_WADR
"0000000000000000";
i_outs
signals
ACmin_WEl
<=
else
std_ulogic;
and
(clock
'1')
and
'0')) then
if (D
"00000") then
if (hgen_req
'0') then
i_outs <= "000000000000000";
Q <= "00000";
=
else
<=
<=
<=
"01011";
<=
"000010000000000";
i_outs
end
elsif
"0000";
"00000000";
if
(D
"01011")
(bits_inc_ack
A-55
if;
<=
"01011";
then
=
'1')
then
i_outs
<=
"000010000000000";
huff_LDl
<=
i_outs(0);
else
<=
"01001";
<=
"000010000000000";
<=
hcode_ADRl
i_outs
if;
end
if
(i
"01001") then
"0000") then
"01000";
i;
<=
<=
huff_WADR
(D
elsif
i_outs
<=
huff_DIN
"100000000000000";
end
huff
<=
i_data;
gen_arch;
else
<=
"00010";
i_outs
(D
elsif
if
<=
COMPONENT:
DESCRIPTION:
"000010000000000";
if;
end
"01000") then
'1') then
"01000";
qtable
(entity)
(hgen_req
Q <=
i_outs
<=
<=
Purpose
"000000000000000";
"00000";
i_outs
<=
def ine_qtable_entity
Name
else
define
Author
Douglas A.
Created
18-APR-1994
Carpenter
Revised
"000000000000000";
if;
end
(D
elsif
"11111")
"OHIO";
=
library and
library ieee;
then
<=
if
(acdc_data_out
"0") then
i_outs <= "000010100000001";
=
use
clauses
use
ieee.
std_logic_1164
use
ieee.
all;
ions
.all;
else
i_outs
<=
<=
(D
elsif
<=
if
"11110")
<=
i_outs
<=
"0")
then
"000011111000001";
"000010000111101";
if;
(D
"11000") then
Q <= "00010";
i_outs <= "000010000000000";
i <= i + "0001";
elsif
"00000";
i_outs <= "000000000000000";
end if;
end if;
end process hloadg_process;
output
is
in
std
ulogic
reset
in
std
ulogic
table_err
out
std
ulogic
qtable_req
in
std
ulogic
qtable_ack
out
std
ulogic
qreset
out
std
ulogic
inc
out
std
ulogic
qtable_addr
in
std
ulogic
0);
in
data
in
downto
0);
next_req
out
std
ulogic
next_ack
in
std
ulogic
err
in
std
ulogic
qdata_in
out
values
downto
inc_ack
<=
assign
all;
clock
else
port
else
end
.package_l
entity define_qtable
"000010000000001";
"11100") then
"11000";
(acdc_data_out
i_outs
my_packages;
my_packages
then
"11100";
i_outs
library
"000010000010001";
use
(D
elsif
<=
if;
end
downto
0);
qload
out
std
ulogic
qload_ack
in
std
ulogic
);
D
<=
end
Q;
hgen_ack
hscg_err
<=
<=
bits_reset
bits_inc
i_outs(14);
define_qtable;
COMPONENT:
definejjtabfe
DESCRIPTION
(architecture)
i_outs(13);
<=
<=
hcode_SEL(0)
i_outs(12);
i_outs(ll);
<=
i_outs(10);
--
Name
def ine_qtable_arch
Purpose
define
Author
Douglas A.
Created
18-APR-1994
quant
table
module
Carpenter
Revised
DCmin_WEl
<=
i_outs ( 9 ) ;
DCmax_WEl
<=
i_outs ( 8 ) ;
architecture
DCvalptr_WEl
<=
define_qtable_arch
of
def ine_qtable
is
i_outs(7);
signal
std_ulogic_vector
( 4 downto 0);
signal
std_ulogic
(59 downto
i_data
vector
0);
ACmin_WEl
<=
i_outs(5);
signal
begin
ACmax_WEl
<=
i_outs ( 4 ) ;
sof_process
process
(reset,
begin
ACvalptr_WEl
<=
i_outs(3);
if
(reset
i
A-56
data
<=
'0'
) then
"00000000";
clock)
downto
0);
<=
<=
"00000";
<=
"0000000000000000000000000000000000000000000000000
00000000000";
elsif
'1') and
( clock 'last_value
*0')) then
<=
'
a ( 0 )
(
1 ') and
(D(3)
'
'
'
1 ') and ( D ( 1 )
[D(2 )
1 ') and
0 ') and ( D ( 0 )
(data
"00000000") ) ;
<=
'
a ( 1 )
0 ' ) and
(
(D(3)
'
'
0 ') and ( D ( 1 )
[D(2)
1 ) and ( D ( 0 )
0 ') and
(data
"00000000") ) ;
'
0 ' ) and
a(2)<=(
(D(3)
'
'
1 ') and ( D ( 1 )
(D(2)
1 ') and
0 ' ) and ( D ( 0 )
(data
"01000011") ) ;
<=
a (3)
((D(4)
'0') and (D(3)
'1') and
(D(2)
'1') and (D(l)
'0') and
'0') and (D(0)
=
<=
<=
<=
a(4)
'
0
a(5)
<=
( (D(4 )
'
<=
'
( (D(4 )
and
(D(1)
D(2)
err
<=
D(2)
D(2)
(7) <= (
'0') and
(8) <= (
'1') and
(D(2)
'
(D(2)
<=
1 ')
'0
(10)
'ID
and
(D(l)
'0
'
'
(D(l)
'1
'0'
( (D(4 )
and
(D(1)
'0')
'
<=
and
)
=
)
=
)
=
)
=
)
=
)
=
(next_ack
a
(D(2)
<=
(16)
'0'
(D(2)
(17)
'
1 ')
<=
and
(D(1)
<=
(21)
'ID
<=
(1)
( (D(4)
and
(D(1 )
((D(4)
and
(D(0)
D(2)
'
'
'1
'0
'0'
'0
'1
'0
'0
'1
(qload_ack
(D(0)
'0
'0
'0
(D(2)
<=
and
'1'
'0
<=
and
and
) and
D;
and
'1
'0
I);
'0'
) )
0 ')
and
(D(3)
(D(0)
'1')
'ID
and
'ID
'1')
and
'
and
and
0 ')
and
and
'I'D;
'0') and
=-
'1'
'
) )
0 ')
and
(D(3)
(D(0)
'
)
'1')
=
=
and
and
'O'D;
'
( (D(4)
'
(D(3)
(D(0)
'
and
'1')
')
and
'I'D;
and
(D(0)
'
'
=
=
'
and
'
1 ')
and
'
1 ') ) ;
'0') and (D(0)

(D(l)
(data(6)
'1') and (data(0)
<=
(
and
(D(l)
'0') and (D(0)
(data (6)
'0') and (data(l)
'
<=
0 ' ) and ( D ( 3 )
( (D(4 )
'
and
0 ' ) and ( D ( 0 )
(D(1)
(err
'I'D;
<=
( (D(4 )
'1') and
'
and
0 ' ) and
(D(0)
'
(inc_ack
0 ') ) ;
<=
(
(D(3)
'
and
1 ' ) and ( D ( 0 )
(D(1)
(data(2)
-ID);
<=
(
(D(3)
and
(D(l)
'1') and (D(0)
(data (3)
'1') );
<=
(
(D(3)
'
and
1 ' ) and ( D ( 0 )
(D(1)
(data (4)
'1') );
<=
(
(D(3)
'
and
1 ') and ( D ( 0 )
(D(1)
(data(5)
'1'));
<=
(
(D(3)
and
(D(l)
'1') and (D(0)
'1'
(data(7)
) );
<=
(
(D(3)
and
(D(l)
'1') and (D(0)
(data(0)
'I'));
<=
(
(D(3)
'
and
1 ' ) and ( D ( 0 )
(D(1)
(data(l)
'1'));
=
and
= =
'0'));
'
= =
'
'
) and
'I'D;
1 ' ) and
'
0 ') and
and
(D(0)
'1
and
(D(3)
(D(0)
'1'
'1
'
'
'
'
and
and
and
'
and
'
(D(2)
and
and
and
'
0 ')
'
0 ')
and
and
(D(0)
(D(3)
'1
'
'1'
(D(2)
and
and
'
(D(3)
(D(0)
(D(3)
'1'
'0
(D(2)
and
I
and
'
'
'
and
and
0 ')
'
0 ')
and
and
'
'1'
(D(2)
and
) and
D;
and
)) ;
(D(3)
(D(l)
)
);
and
'
and
and
'0') );
and
(D(2)
and
(inc_ack
and
and
'
and
(D(2)
=
'
and
and
'1'
and
(D(2)
=
(D(l)
and
and
'1'
) );
(D(3)
(D(1)
(data(l)
<=
( (D(4)
(D(2)
and
and
and
(D(2)
=
and
'1'
(next_ack
and
'1'
and
and
'1'
<=
and
'
'
'
and
and
a(47
(D(3)
(D(1)
ID(2)
and
'1'
'1')
'1'
'1'
(D(2)
=
((D(4)
and
and
and
'1'
'1'));
and
(D(3)
(D(3)
'0') and (D(0)
'I'D;
(data(0)
'
<=
0 ') and ( D ( 3 )
( (D(4)
'
0 ')
and
(D(1)
'1') and (err
(qtable_req
<=
(D(3)
(
(D(2)
and
|D(2)
and
'0
'1')
(next_ack
and
'0'
(qload_ack
<=
a(22)
(D(2)
and
)
);
'0'
'1'
(qload_ack
a
( (D(4)
(qtable_req
(
and
(D(1)
and
'0')
'
1 )
(D(3)
and
<=
) );
'0'
'0
'0'
(20)
'
1 ')
'1
'1
and
and
'
and
(D(3)
(next_ack
D(2)
and
((D(4)
'1') and (D(l)
<=
a(19)
((D(4)
0 ') and ( D ( 1 )
a
)
);
and
<=
a(18)
(D(2)
'
(next_ack
(D(2)
'0
and
and
(qload_ack
a
'
0 ')
'0')
(D(3)
and
(D(0)
'I'D;
and
(D(3)
and
(D(0)
'I'D;
and
(D(3)
and
(D(0)
'I'D;
and
(D(3)
and
(D(0)
'I'D;
and
(D(3)
and
(D(0)
'I'D;
'
'
(qtable_addr(5)
<=
'1')
( (D(4)
'
and
(D(2)
(D(3)
and
(D(0)
'I'D;
and
'0'
(err
)
'OD
(D(2)
<=
'0'
(D(2)
(err
(D(2)
(D(3)
) and (D(0)
and
( err
(D(3)
)
(D(2)
'
(D(3)
and
(D(0)
and
'0'
( (D(4)
and
'0
(D(l)
(qtable_addr(l)
'0'
a(ll) <= ((D(4)
'
0
'1') and ( D ( 1 )
(qtable_addr(2)
'0'
<=
a (12)
( (D(4)
'
1 ' ) and ( D ( 1 )
0
(qtable_addr(3)
'0'
<=
a(13)
((D(4)
'0
'1') and ( D ( 1 )
(qtable_addr(4)
'0'
<=
a(14)
((D(4)
'0
'1') and (D(l)
(qtable_addr (5)
'0'
<=
a (15)
( (D(4)
'1
'1') and (D(l)
=
( (D(4 )
(D(2)
<=
(qtable_addr(0)
a
"000000"));
'
0' )
and
(D(3)
0' )
'1') and (next_ack
'0')
(next_ack
a(9)
(next_ack
a
'
and
and
'
(next_ack
a
'
0 ) ) ;
( (D(4 )
and
(D(l)
=
'0')
'0')
a(6)
and
'
'1'
'1'));
(qtable_addr(4)
and
(qtable_req
'
"000000"));
) and ( D ( 3 )
(qtable_addr
'
'1')
'ID );
and
(D(3)
(D(2)
(qtable_addr
<=
and
and
((D(4)
(qtable_addr(3)
'1'
and
(D(3)
and
(D(2)
'1')
(qtable_addr(2)
((D(4)
(D(2)
'
and
and
1'
'1') );
(qtable_addr(l)
'
(D(3)
and
(D(2)
1 ')
and
(D(2)
'
(qtable_addr(0)
(D(2)
( (D(4 )
(D(2)
'1'
(D(2)
and
and
'0
A-57
0 ')
'
0' )
and
and
<=
a(48
(D(2)
'0
(D(1)
(data(6)
<=
(
and
'0
(D(2)
(D(2)
'1
(51
(D(2)
'1
(52
(D(2)
'0
(53
'1
<=
a(50
<=
( (D(4 )
'
(D(l)
(D(1)
'1'
'1
'1
a(58
'1
'1'
) )
a(59
'1
'
and
(a(10)
and
'1') or
'1') or (a(9)
((a(l)
'1')
'ID or (a(12)
(a(ll)
or
'1')
'1') or (a(14)
(a(13)
'ID
'1') or (a(32)
'ID or (a(21)
or
'1')
(a(35)
'1') or (a(36)
'1')
'1') or (a(41)
'ID or (a(40)
or
'1')
(a(42)
'1') or (a(43)
'1')
'1') or (a(46)
'ID or (a(45)
or
'1')
(a(47)
'1') or (a(48)
'1') or (a(59)
'1') or (a(52)
D(2) <=
'ID
=
or
(a(20)
'
'
and
or
'
'
and
or
(a(39)
(D(3)
(D(0)
'
'
'
(a(50)
'I'D;
and
or
and
'
0 ')
and
'1')
(a(15)
and
'ID or (a(8)
'1') or
(<a(2)
'1')
(a(20)
'1') or (a(21)
or
'ID
'ID or (a(31)
(a(30)
'1')
'1') or (a(34)
'1') or (a(33)
or
'1')
(a(37)
'1') or (a(38)
'1')
'1') or (a(49)
'1') or (a(40)
or
'1')
(a(52)
'1') or (a(53)
'1') or (a(56)= '1')
'1') or (a(55)
or
'1')
'1') or (a(58)
(a(57)
'I'D;
D(l) <=
'1')
=
or
;
or
and
(a(44)
(
'
'
)
'I'D;
and
(D(0)
'
1 ')
(a(32)
and
or
(a(39)
'0')
) );
and
(D(0)
'1')
and
or
(a(54)
'1'
'
'
0 )
'I'D;
or
and
(D(0)
'
'
(a(59)
'0')
'1'
) ) ;
and
(D(0)
'1'
and
(a(16)
'1') or
((a(5)
'1') or (a(7)
'1')
'1') or (a(18)
(a(17)
or
'1')
(a(19)
'1') or (a(30)
'1')
'1') or (a (33)
'ID or (a (32)
or
'1')
'1') or (a(38)
(a(37)
'1')
'1') or (a(42)
'1') or (a(41)
'1'
or
'1')
) or (a(44)
(a(43)
'1')
'ID or (a(47)
'1') or (a(46)
or
'1')
(a(48)
'1') or (a(52)
'1')
'1') or (a(55)
'1') or (a(54)
or
'1')
(a(56)
'1') or (a(57)
'
'
1 )) ;
'1') or (a (59)
D(0) <=
'1')
=
or
and
or
(a (31)
'0')
'1'));
'1')
(D(0)
'
(D(2)
));
(D(2)
'
'
) ) ;
(D(3)
(D(l)
(D(1)
(data (2)
<=
(
) and (D(l)
(data (3)
<=
(
) and ( D ( 1 )
(data (4)
<=
(
) and (D(l)
(data(5)
<=
(
) and (D(l)
(data(7)
<=
( (D(4)
) and
a(56
(57
) and
"O'D;
'
and
<=
'1
(D(2)
'
and
<=
'1
<=
a(55
1D(2)
'
(D(3)
and
a(54
=
(D(3)
(D(0)
(err
(D(2)
and
I);
(err
(D(2)
'
or
(D(l)
and
)
'1') );
a(49
'
and
(D(0)
'1'
and
or
(a(39)
or
and
(a(45)
(qtable_req
'1'
) );
or
(a(53)
if
'0')
( (D(3)
(D(0)
and
i_data
<=
'1') and (D(2)

'I'D then
data;
'0')
and
(D(l)
or
(a (58)
end
<=
process
assign
<=
((a(4)
'1') or (a(20)
'1') or
(a(31)
'1') or (a(32)
'1')
'1'
or
(a (34)
or
(a(36)
'1') or
'
'
'1') or (a(38)
) or (a(39)
'1')
'1'
or
or
(a(40)
(a(41)
'1') or
'
'1') or (a(43)
') or (a(44)
'1')
'1'
or
or
(a(45)
(a(46)
'1') or
'
'1') or (a(48)
') or (a (51)
'1')
'1'
or
(a (52)
or
(a(53)
'1') or
(a(56)=
'1') or (a(55)
'1') or
'1')
(a (57)
or
or
(a(58)
'1') or
'I'D;
D(4)
=
(a(37)
(a(42)
(a(47)
(a(54)
(a(59)
'1')
'1'
'1')
or
(a(34)
'ID
or
(a(41)
'ID
or
(a(45)
'1')
or
(a(52)
'ID
or
(a(56)=
'I'D
(a(37)
or
(a(38)
'1') or (a(42)
or
(a(43)
'1') or (a(46)
or
(a(47)
'1') or (a(53)
or
(a(54)
'1') or (a(57)
or
(a(58)
or
'1') or (a (32)
'1')
'1') or (a(39)
'1.')
'1') or (a(44)
'1')
'1') or (a(48)
'1')
'1') or (a(55)
'1')
'1') or (a(59)
((a (31)
when
'1')
values
i_data;
<=
table_err
or
output
<=
qdata_in
(a(29)
sof_process;
i_data;
if;
end
if;
end
else
i_data
else
'0';
'
'
1 )
D(3) <= ((a(3)
'1
(a(9)
'1') or (a(10)
or
(a I(12)
or
'1') or (a(15)
(a(14)
(a ((19)
or
or
'1') or (a(22)
(a(21)
(a (24)
or
or
'1') or (a(27)
(a(26)
or
(a (30)
I
or
'1') or (a(35)
(a(34)
or
(a (37)
or
(a(39)
'1') or (a(40)
or
(a (42)
or
(a(44)
'1') or (a(45)
or
(a (47)
or
(a(51)
'1') or (a(52)
or
(a I(54)
or
(a(56)
'1') or (a(57)
or
(a ((59)
=
or
'1
=
'1
'1
(a(6)
'1') or
or
(a(ll)
'1')
'1
) or (a 13)
1'
) or
a(16)
'1
) or (a 20)
ID or
a(23)
'1
) or (a 25)
ID or
a(28)
'1
) or (a 32)
ID or
a(36)
'1
) or (a 38)
a(41)
ID or
'1
) or (a 43)
1'
a(46)
) or
'1
) or (a 48)
a(53)
ID or
'1
) or (a 55)
a(58)
ID or
));
'1
=
'1
_
'1
_
'1
__
'1
_
'1
ID
)
ID
)
ID
)
ID
)
ID
)
ID
)
ID
)
ID
'0'
<=
(a(10)
((a(4)
when
'1')
((a(0)
'1') or
(a(ll)
'1')
or
(a(12)
'1')
'1')) else
when
'1')
or
(a(14)
or
(a(9)
'1')
'ID
(a(29)
or
'0';
else
qreset
or
'1'
<=
qtable_ack
'1'))
or
(a(13)
'l';
<=
inc
'1'
when
((a(20)
'1')
or
(a(40)
'1'))
else
'0';
next_req
'1')
'ID
<=
(a(3)
or
'
or
(a(24)
'1')
or
or
else
A-58
'
when
'1')
or
(a(7)
(a(25)
(a(27)
((a(l)
(a(5)
=
'1')
'1')
(a(2)
(a(6)
or
or
'1') or (a(8)
'1') or (a(26)
'1') or (a(28)
'1') or
'1')
'1'))
else
'1'
<=
qload
(a(22)
when
'1')
'0';
if;
end
COMPONENT:
DESCRIPTION:
end
output
values
<=
i_ack;
qtable_addr <= i_addr;
inc_ack
(entity)
end
Name
Q2_Process;
process
assign
qaddr
if;
end
define_qtable arch;
end
'0'
<=
i_ack
else
qaddr_entity
Purpose
quant
Author
Douglas A.
Created
19-APR-1994
table
addr
module
counter
qaddr_arch;
COMPONENT;
qmem
DESCRIPTION:
(entity)
Carpenter
Name
qmem_entity
Revised
Purpose
library
and
use
clauses
Douglas A.
Created
18-APR-1994
library ieee;
use
use
ieee. std_logic_1164_extensions. all;
use
std.textio. all;
library
use
Revised
.all;
library and
library ieee;
my_packages;
my_packages
.package_l
ieee.
std_logic_1164
use
ieee.
in
std
ulogic;
inc
in
std
ulogic;
clock
in
std
ulogic;
entity
qmem
.package_l
all;
is
port
o itputs
qtable
addr
out
std
ulogic
out
std
ulogic) ;
vector
clock
in
std_ulogic;
reset
in
std_ulogic;
(5
0) ;
inc
end
all;
inputs
qreset
downto
.all;
my_packages;
my_packages
use
clauses
use
library
port
use
all;
is
qaddr
entity
Carpenter
Author
qdata_in
ac <:
qaddr;
downto
0);
in
std
ulogic
out
std
ulogic
in
std
ulogic
out
std
ulogic
qload
qload
COMPONENT:
qaddr
DESCRIPTION:
(architecture)
qdata
std
ulogic
vector
(7
ack
out
out
downto
0)
qreq
Name
qreq
qaddr
arch
qaddr
module
ack
qtable_addr
Purpose
Author
Douglas
A.
Created
19-APR-1994
std_ulogic_vector
Carpenter
(5
downto
0),
qt abl e_r addr
DAC
std_ulogic_vector
Revised
( 5 downto
0)
tr
architecture
qaddr_arch
i_addr
signal
of
qaddr
end
is
std_ulogic_vector
0);
i_ack
signal
qmem;
( 5 downto
std_ulogic;
COMPONENT:
qmem
DESCRIPTION:
(architecture)
begin
Ql_Process
Name
(qreset, inc)
process
qmem_arch
begin
if
(qreset
then
'0')
<=
i_addr
((inc'event)
last_value
'0'))
elsif
line'
end
end
and
i_addr
(inc
'1')
and
Ql_Process;
process
(qreset,
clock)
begin
(qreset
<=
'0')
'
'
then

value
'0')) then
if (inc
1') then
<=
i ack
'1';
elsif
(clock'
last
21-APR-1994
architecture
Q2_Process
i_ack
Douglas A.
Created
Carpenter
"000001";
if;
process
if
Author
Revised
then
<=
i_addr
Purpose
"000000";
'1')
and
A-59
qmem_arch
of
qmem
is
signal
q0
std_ulogic_vector I 7
downto
0)
signal
qi
downto
signal
q2
downto
downto
0)
0)
0)
0)
0)
0)
0)
0)
0)
signal
q3
std_ulogic_vector
signal
q4
std_ulogic_vector
downto
signal
qs
std_ulogic_vector
downto
signal
q6
std_ulogic_vector
downto
signal
q7
std_ulogic_vector
signal
q8
std_ulogic_vector
downto
downto
signal
q9
std_ulogic_vector
downto
signal
qlO
downto
q7
<
To_StdUlogicVector
signal
qll
downto
q8
<
To_StdUlogicVector
signal
ql2
q9
<
signal
ql3
signal
ql4
signal
ql5
signal
ql6
signal
ql7
signal
ql8
signal
ql9
signal
q20
signal
q21
signal
q22
signal
q23
signal
q24
signal
q25
signal
q26
signal
q27
signal
q28
signal
q2
signal
q30
signal
q31
signal
q32
signal
q33
signal
q34
signal
q35
signal
q36
signal
q37
signal
q38
signal
q39
signal
q40
signal
q41
signal
q42
signal
q43
signal
q44
signal
q45
signal
q46
signal
q47
signal
q48
q49
q50
signal
q51
signal
q52
signal
q53
signal
q54
signal
q55
signal
q56
signal
q57
signal
q58
signal
q59
signal
q60
signal
q61
signal
q62
signal
q63
signal
std_ulogic_vector
(5 downto
0)
std_ulogic_vector
(2
downto
0)
To_StdUlogicVector
qll
<=
To_StdUlogicVector
9,8
ql2
<=
To_StdUlogicVector
8,8
ql3
<=
To_StdUlogicVector
10,1
ql4
<=
To_StdUlogicVector
ql5
<=
To_StdUlogicVector
12, i
20, i
ql6
To_StdUlogicVector
13,!
ql7
To_StdUlogicVector
ql8
To_StdUlogicVector
ql9
To_StdUlogicVector
12, i
H, (
11, i
To_StdUlogicVector
12,!
q21
<
To_StdUlogicVector
25,!
q22
<
To_StdUlogicVector
18,!
q23
To_StdUlogicVector
19,!
q24
To_StdUlogicVector
15,!
q25
To_StdUlogicVector
20,!
q26
To_StdUlogicVector
29,!
To_StdUlogicVector
26,!
q28
To_StdUlogicVector
31,!
q29
To_StdUlogicVector
30,!
q30
To_StdUlogicVector
29,!
q31
To_StdUlogicVector
26,!
q32
To_StdUlogicVector
28,!
q33
To_StdUlogicVector
28,!
q34
To_StdUlogicVector
32,!
q35
To_StdUlogicVector
36,!
q36
To_StdUlogicVector
46,!
q37
To_StdUlogicVector
39,!
q38
To_StdUlogicVector
32,!
q39
To_StdUlogicVector
34,!
q40
To_StdUlogicVector
44,!
q41
To_StdUlogicVector
35,!
q42
To_StdUlogicVector
28,!
q43
To_StdUlogicVector
28,!
q44
To_StdUlogicVector
40,!
q45
To_StdUlogicVector
55,!
<=
To_StdUlogicVector
41,!
q47
<
To_StdUlogicVector
44,!
q48
<;
To_StdUlogicVector
48,!
<
To_StdUlogicVector
49,!
To_StdUlogicVector
52,!
q4
q4
q50
To_StdUlogicVector
52,!
q52
<
To_StdUlogicVector
52,!
q53
<
To_StdUlogicVector
31,!
q51
q54
To_StdUlogicVector
39,!
q55
To_StdUlogicVector
57,!
q56
To_StdUlogicVector
61,!
q57
To_StdUlogicVector
56,!
q58
To_StdUlogicVector
50,!
q59
To_StdUlogicVector
60,!
q60
To_StdUlogicVector
46,!
q61
To_StdUlogicVector
51,
q62
To_StdUlogicVector
52,!
To_StdUlogicVector
50,
q63
data
out
std
ulogic_vector
(7
downto
(clock'
i
i
and
(clock
'1') and
'0')) then
'
<=
0 ' ) and
a(0)
((D(2)
'0') and ( D ( 1 )
'0') and (gload
'1') and (qreq
'0'));
'
a(l) <= ((D(2)
0 ) and
'0') and ( D ( 1 )
'0') and (qload
'0') and (qreq
'1'));
a(2) <= ((D(2)
'0') and (D(l)
'1') and
'1') and (qreq
'1'));
a(3) <= ((D(2)
'1') and
'0') and (qload
'I'D;
a(4) <= ((D(2)
'1') and (D(l)
'0') and
'0') );
<=
'
a(5)
((D(2)
0 ' ) and
'0') and ( D ( 1 )
'I'D;
elsif
signal
StdUlogicVector(7,8)
9,8
<=
q27
signal
To
(7,8)
(7,8)
qlO
q20
signal
signal
0) ;
0) ;
r(7
(7 downto 0)
std_ulogic_vector
std_ulogic_vector (7 downto 0) ;
0) ;
0),
0)
0) ,
downto 0)
std_ulogic_vector (7 downto 0) ,
0)
0)
std_ulogic_vector (7 downto 0),
0)
0)
downto 0)
0)
downto 0) ,
downto 0)
0)
downto 0)
downto 0)
downto 0) ,
downto 0)
downto 0)
std_ulogic_vector (7 downto 0),
downto 0)
downto 0)
downto 0)
downto 0)
0)
downto 0)
downto 0)
downto 0)
0)
downto 0)
downto 0)
downto 0)
downto 0)
downto 0)
0)
clock'
last_value
event)
0);
(D(0)
begin
Qmem
process
(reset,
(D(0)
clock)
begin
(reset
if
<=
<=
'0')
"000";
"000000";
=
(D(0)
then
qO
<=
To_StdUlogicVector (8
ql
<=
To_StdUlogicVector(6
q2
<=
q3
<=
q4
<=
q5
<=
q6
<=
(D(0)
(D(0)
(D(0)
if
=
A-60
'0')
((D(2)
and
(qload
'
and
'0')
(D(l)
and
'
(qreq
'
) and ( D ( 0 )
'I'D then
if
''
(qtable_raddr
out_data
elsif
<=
<=
<=
<=
then
data
out
"001111"
then
"010000"
then
"010001"
then
data
out
data
out
"010010"
then
(qtable
data
out
"010011"
then
"010100"
then
"010101"
then
data
out
(qtable
data
out
"010110"
then
"010111"
then
(qtable
"011000"
then
"011001"
then
"011010"
then
"011011"
then
(qtable
(qtable
<=
data
out
(qtable
elsif
=
<=
data
out
elsif
<=
data
out
elsif
<=
data
out
elsif
<=
(qtable
elsif
=
<=
data
out
elsif
<=
(qtable
elsif
=
<=
(qtable
elsif
=
<=
data
out
elsif
<=
(qtable
elsif
=
<=
(qtable
elsif
=
<=
(qtable
elsif
=
out
raddr
"100110"
then
"100111"
then
"101000"
then
"101001"
then
"101010"
then
"101011"
then
"101100"
then
"101101"
then
"101110"
then
"101111"
then
"110000"
then
"110001"
then
"110010"
then
"110011"
then
"110100"
then
"110101"
then
"110110"
then
"110111"
then
"111000"
then
"111001"
then
"111010"
then
"111011"
then
"111100"
then
"111101"
then
"111110"
then
"111111"
then
q38;
=
raddr
q39;
=
raddr
q40;
=
raddr
q41;
raddr
q4
2;
raddr
"q43;
=
raddr
q44;
raddr
q45;
raddr
q46;
raddr
q47;
raddr
q48;
raddr
q49;
raddr
q50;
raddr
q51;
=
raddr
q52;
raddr
q53;
raddr
q54;
raddr
q55;
raddr
q56;
raddr
q57;
raddr
q58;
raddr
q59;
raddr
q60;
raddr
q61;
raddr
q62;
raddr
data
<=
q63;
data
<=
q0;
else
=
out
if;
if;
end
=
"011100"
then
end
"011101"
if
then
'0')
=
"011110"
"011111"
then
"100000"
<=
"100001"
then
<=
elsif
q3
"100010"
then
elsif
q4
q34;
=
"100011"
then
elsif
q5
q35;
=
"100100"
then
elsif
q6
q36;
=
"100101"
then
elsif
A-61
(D(l)
and
and
"000001")
then
"000010")
then
"000011")
then
"000100")
then
"000101")
then
"000110")
then
"000111")
then
qdata_in;
qdata_in;
(qtable_addr
<=
qdata_in;
(qtable_addr
<=
qdata_in;
(qtable_addr
<=
qdata_in;
(qtable_addr
<=
'0') and (D(0)

'0')) then
"000000") then
(qreq
qdata_in;
(qtable_addr
elsif
q2
'0')
'1')
(qtable_addr
elsif
then
(qtable_addr
<=
ql
=
(qload
qO
q33;
(qtable_raddr
((D(2)
and
if
then
q32;
(qtable_raddr
out_data
elsif
<=
"001110"
<=
(qtable_
elsif
=
<=
(qtable
data
out
q31;
(qtable_raddr
out_data
elsif
<=
then
elsif
=
q30;
(qtable_raddr
out_data
elsif
<=
"001101"
(qtable
data
out
9;
(qtable_raddr
out_data
elsif
q2
(qtable_raddr
out_data
elsif
<=
then
elsif
=
<=
q37;
q28;
(qtable_raddr
out_data
elsif
<=
"001100"
data
out
q27;
(qtable_raddr
out_data
elsif
<=
then
q26;
(qtable_raddr
out_data
elsif
<=
"001011"
<=
(qtable
elsif
=
<=
(qtable
data
out
q25;
(qtable_raddr
out_data
elsif
<=
then
4;
(qtable_raddr
out_data
elsif
q2
(qtable_raddr
out_data
elsif
<=
"001010"
elsif
=
<=
(qtable
data
out
q23;
(qtable_raddr
out_data
elsif
<=
then
elsif
=
q22;
(qtable_raddr
out_data
elsif
<=
"001001"
(qtable
data
out
q21;
(qtable_raddr
out_data
elsif
<=
then
q20;
(qtable_raddr
out_data
elsif
<=
"001000"
elsif
=
<=
data
out
ql9;
(qtable_raddr
out_data
elsif
<=
then
ql8;
(qtable_raddr
out_data
elsif
<=
"000111"
<=
(qtable
elsif
=
<=
(qtable_
data
out
ql7;
(qtable_raddr
out_data
elsif
<=
then
ql6;
(qtable_raddr
out_data
elsif
<=
"000110"
elsif
=
<=
(qtable_
data
out
ql5;
(qtable_raddr
out_data
elsif
<=
then
elsif
=
ql4;
(qtable_raddr
out_data
elsif
<=
"000101"
data
out
ql3;
(qtable_raddr
out_data
elsif
<=
then
ql2;
(qtable_raddr
out_data
elsif
<=
"000100"
<=
(qtable
elsif
=
qll;
(qtable_raddr
out_data
elsif
<=
data
out
qlO;
(qtable_raddr
out_data
elsif
<=
then
q9;
(qtable_raddr
out_data
elsif
<=
"000011"
<=
(qtable_
elsif
=
<=
(qtable_
data
out
q8;
(qtable_raddr
out_data
elsif
<=
then
q7;
(qtable_raddr
out_data
elsif
<=
"000010"
data
elsif
=
<=
(qtable_
out
q6;
(qtable_raddr
out_data
elsif
<=
then
q5;
(qtable_raddr
out_data
elsif
<=
"000001"
q4 ;
(qtable_raddr
out_data
elsif
<=
q3;
(qtable_raddr
out_data
elsif
<=
data
out
elsif
q2;
(qtable_raddr
out_data
elsif
<=
then
ql;
(qtable_raddr
out_data
elsif
<=
000000")
qO;
(qtable_raddr
out_data
elsif
(qtable_raddr
out_data
elsif
<=
qdata
in;
(qtable_addr
q7
q8
<=
q9
elsif
qlO
elsif
qll
elsif
ql2
elsif
ql3
elsif
ql4
elsif
ql5
elsif
ql6
elsif
ql7
elsif
ql8
elsif
ql9
elsif
q20
elsif
q2i
elsif
q22
elsif
q23
elsif
q24
elsif
q25
elsif
q26
elsif
q27
elsif
q28
elsif
q2
elsif
q30
elsif
q31
elsif
q32
elsif
q33
elsif
q34
elsif
q35
elsif
q36
elsif
q37
elsif
q38
elsif
q39
elsif
q40
elsif
q41
elsif
q42
elsif
q43
elsif
q44
"OOIOOO")
then
"001001")
then
"001010")
then
"001011")
then
"001100")
then
"001101")
then
"001110")
then
"001111")
then
"010000")
then
"010001")
then
"010010")
then
"010011")
then
"010100")
then
"010101")
then
"010110")
then
"010111")
then
q45
q46
<=
<=
<=
"011101")
"011110")
(a(4)
(a(5)
then
then
"011111")
then
"100000")
then
end
end
"110111"
then
"111000"
then
"111001"
then
"111010"
then
"111011"
then
"111100"
then
"111101"
then
"111110"
then
"111111"
then
qdata_in;
=
qdata_in;
=
qdata_in;
=
qdata_in;
=
qdata_in;
=
qdata_in;
=
qdata_in;
=
qdata_in;
if;
if;
or
(a (3)
'ID
or
'ID or
'I'D;
'ID or
(a(3)
'ID
or
(a (2)
'1')
or
'ID
if;
Qmem;
process
outputs
"100001")
then
"100010")
then
"100011")
then
qreq_ack
<=
"100100")
then
qdata_out
<=
"100101")
then
end
"100110")
then
COMPONENT:
dequantize
DESCRIPTION:
(entity)
qload_ack
1')
"100111")
then
"101000")
then
"101001")
then
or
<=
(a(5)
'1'
'1'
((a(3)
'0';
when
) )
'1')
or
(a (4)
else
'
'
when
(2)
'1')
out_data;
qmem_arch;
"101010")
then
"101011")
then
Name
dequant ize_entity
Created
22-APR-1994
Revised

qdata_in;
(qtable_addr
<=
qdata_in;
(qtable_addr
<=
then
qdata_in;
(qtable_addr
<=
qdata_in;
D(2) <= ( (a(0)

'I'D;
D(l) <= ( (a(2)
'1') or (a (5)
D(0) <= ((a(l)
'I'D;
(a(4)
qdata_in;
[qtable_addr
<=
then
qdata_in;
(qtable_addr
<=
"011100")
then
"110110"
end
end
qdata_in;
(qtable_addr
<=
then
"110101"
qdata_in;
(qtable_addr
<=
then
"110100"
qdata_in;
(qtable_addr
<=
"011011")
then
qdata_in;
(qtable_addr
<=
<=
"110011"
qdata_in;
(qtable_addr
elsif
q63
(qtable_addr
<=
then
qdata_in;
(qtable_addr
<=
then
qdata_in;
(qtable_addr
<=
"011010")
qdata_in;
(qtable_addr
<=
q62
then
"110010"
qdata_in;
(qtable_addr
<=
elsif
qdata_in;
(qtable_addr
<=
then
qdata_in;
(qtable_addr
<=
"011001")
qdata_in;
(qtable_addr
<=
q61
qdata_in;
(qtable_addr
<=
then
"110001"
qdata_in;
(qtable_addr
<=
"011000")
(qtable_addr
<=
elsif
=
qdata_in;
(qtable_addr
<=
q60
then
in;
qdata
(qtable_addr
<=
elsif
qdata_in;
(qtable_addr
<=
q59
(qtable_addr
<=
"110000"
qdata_in;
(qtable_addr
<=
elsif
qdata_in;
(qtable_addr
<=
q58
qdata_in;
(qtable_addr
<=
q57
elsif
(qtable_addr
<=
then
qdata_in;
(qtable_addr
<=
elsif
qdata_in;
(qtable_addr
<=
q56
qdata_in;
(qtable_addr
<=
q55
elsif
(qtable_addr
<=
elsif
qdata_in;
(qtable_addr
<=
q54
"101111"
qdata_in;
(qtable_addr
<=
elsif
qdata_in;
(qtable_addr
<=
q53
qdata_in;
(qtable_addr
(qtable_addr
<=
elsif
=
qdata_in;
(qtable_addr
<=
q52
then
qdata_in;
(qtable_addr
<=
elsif
=
qdata_in;
(qtable_addr
<=
q51
(qtable_addr
<=
then
"101110"
qdata_in;
(qtable_addr
<=
elsif
qdata_in;
(qtable_addr
<=
q50
qdata_in;
(qtable_addr
elsif
qdata_in;
(qtable_addr
<=
q4
(qtable_addr
<=
elsif
=
qdata_in;
(qtable_addr
<=
q48
qdata_in;
(qtable_addr
<=
"101101"
qdata_in;
(qtable_addr
<=
elsif
qdata_in;
(qtable_addr
<=
q47
qdata_in;
(qtable_addr
<=
elsif
qdata_in;
(qtable_addr
<=
elsif
qdata_in;
(qtable_addr
elsif
(qtable_addr
elsif
qdata_in;
(qtable_addr
elsif
"101100")
then
qdata_in;
A-62
use
use
use
all;
all;
.
all;
else
'0'
ieee.std_logic_1164_extensions.all;
use
signal
q_data
std_ulogic_vector
signal
int data
integer
(7
downto
library
use
my_packages;
range
-32768
to
32768;
begin
entity dequantize
is
Dequant
port
process
(reset,
clock
if
in
std_ulogic;
'0') then
"0000";
unzigaddr <=
0;
<=
ziggedaddr
0;
(reset
Q
reset
in
do_dequant
in
out
do_dequant_ack
out
qdata_out
in
std_ulogic;
std_ulogic;
clock
<=
<=
<=
0;
0;
(clock'
) and (clock
'0')) then
if (D
"0000") then
unzigaddr <=
0;
ziggedaddr <=
0;
<=
i
0;
elsif
std_ulogic;
'last_value
event
std_ulogic;
downto
<=
0;
ZigZagRam(O) <=
To_StdUlogicVector(0,6) ;
ZigZagRam(l) <=
To_StdUlogicVector (1,6)
ZigZagRam! 2) <=
To_StdUlogicVector (5,6) ;
ZigZagRam! 3) <=
0);
qreq
out
qreq_ack
in
qtable_raddr
out
std_ulogic;
std_ulogic;
std_ulogic_vector
(5
downto
0);
To_StdUlogicVector(6,6)
LoadToDeqRADRl
downto
ZigZagRam! 4)
downto
ZigZagRam(S)
in
0);
<=
<=
"0"
;
"0"
;
"0"
DeqToIDCT_LDl
out
ZigZagRam(8) <=
ZigZagRam! 9) <=
DeqToIDCT_WEl
out
0);
ZigZagRam(7)
( 5 downto
0);
std_ulogic;
<=
"0"
"0"
ZigZagRam(lO) <=
To_StdUlogicVector (7,6);
std_ulogic
);
dequantize;
'0"
ZigZagRam(ll) <=
COMPONENT:
dequantize
DESCRIPTION:
(architecture)
ZigZagRam(12) <=
ZigZagRam(13) <=
) <=
(29,6) ;
ZigZagRam(15) <=
ZigZagRam(16) <=
ZigZagRam ( 17 ) <=
ZigZagRam! 18) <=
To_StdUlogicVector (12, 6)
ZigZagRam! 19) <=
To_StdUlogicVector (17,6),
ZigZagRam(20) <=
ZigZagRam(21) <=
ZigZagRam) 22) <=
ZigZagRam (23) <=
ZigZagRam! 24 ) <=
ZigZagRam (25) <=
To_StdUlogicVector(ll,6) ;
ZigZagRam(26) <=
ZigZagRam ( 14
dequantize_arch
Author
Douglas
Created
22-APR-1994
A.
Carpenter
Revised
dequantize_arch
dequantize
of
std_ulogic_vector
0"
"0"
"0"
"0"
To_StdUlogicVector
Purpose
signal
"0"
std_ulogic_vector
architecture
0"
out
(15 downto
DeqToIDCT_WADRl
--
'
out
DeqToIDCT_DINl
0"
"0"
ZigZagRam) 6) <=
std_ulogic_vector
Name
"0"
0);
LoadToDeqDOUTl
end
clock)
begin
is
( 3 downto
"0"
"0"
"0"
'0"
'0"
&
0);
signal
std_ulogic_vector
(3
downto
0);
subtype
0) ;
type
ramword
is
std_ulogic_vector
rammemory is
array
( 6 downto
(63 downto
0)
of
ramword;
signal
ZigZagRam
signal
i_outs
rammemory;
std_ulogic_vector
(3
downto
0);
signal
integer
range
signal
integer
range
signal
unzigaddr
integer
range
signal
ziggedaddr
integer
range
signal
i_data
std
0 to
7;
7;
0 to 63;
0 to 63;
0 to
ulogic_vector
(15 downto
0);
A-63
and
ZigZagRam(27)
<=
"0"
ZigZagRam (28)
<=
ZigZagRam(29)
<=
"0"
i_outs
ZigZagRam (31)
<=
ZigZagRam! 33) <=

ZigZagRam) 34) <=
ZigZagRam(35) <=
ZigZagRam! 36) <=
ZigZagRam! 37) <=
"0"
start
"0"
<=
ZigZagRam(57)
<=
<=
<=
"0"
ZigZagRam(60)
(57,6)
ZigZagRam(61 ) <=
ZigZagRam! 62) <=
To_StdUlogicVector (62, 6]
ZigZagRam(63) <=
(do_dequant
unzigaddr
"0"
Q
"0"
<=
"0"
"0"
<=
"0000";
"0001") then
<=
(i*8) + j;
top
of
"0011";
<=
i_outs
(D
elsif
"0"
for
waiting
loop
"0000";
"0011") then
<=
ziggedaddr
To_Integer( ZigZagRam (unzigaddr ) ) ;

Q <= "0010";
i_outs <= "0000";
elsif
(D
"0010") then
if (qreq_ack
'0') then
Q <= "0110";
i_outs <= "0010";
"0"
"0"
"0"
&
"0"
&
<=
Q
ready,
"0010";
(D
elsif
"0"
"0"
ack
signalled
<=
"0000";
else
<=
"0110";
<=
"0010";
wait
i_outs
if;
end
(D
elsif
if
"0"
qreq
"0000";
"0110") then
'1') then
"0100";
<=
not
i_outs
"0"
<=
(qreq_ack
if
qêq
if;
end
"0"
ready
wait
i_outs
"0"
qreq
else
"0100") then
'0') then
"0101";
(qreq_ack
<=
qreq done,
latch data
"0"
"0"
i_outs
<=
"0000";
q_data
<=
qdata_out;
else
<=
Q
"0"
(D
elsif
int_data
"0"
"0"
<=
"0"
"0000";
"0111") then
Q <= "1111";
i_outs <= "0100";
=
i_data
<=
(D
To_StdUlogicVector
"1111") then
Q <= "1101";
i_outs <= "1100";
elsif
(D
"1101") then
(int_data, 16)
do
write
if
"0"
<=
(D
elsif
"0"
then
To_Integer (q_data)
"0111";
i_outs
elsif
"0"
"0101")
<=
To_Integer (LoadToDeqDOUTl) ;
"0"
wait
if;
end
"0"
"0100";
<=
"0000";
i_outs
(j
"0"
"0"
=7)
<=
then
0;
i_outs
<=
"0000";
"1100";
<=
else
<=
"0"
<=
"0"
"0"
&
(D
"1100") then
7) then
i <= 0;
i_outs <= "0001";
Q <= "1000";
elsif
if
(i
dequant
1')
then
else
A-64
<=
if;
end
"0"
i;
"0000";
"0001";
i_outs
To_StdUlogi cVector
if
(D
elsif
<=
"0000";
if;
end
ZigZagRam(59)
<=
"0000";
i_outs
&
ZigZagRam(58)
do
signal
To_StdUlogi cVector (52, 6)
ZigZagRam(39) <=
ZigZagRam! 40) <=
ZigZagRam! 41) <=
ZigZagRam) 42) <=
ZigZagRam(43) <=
ZigZagRam! 44 ) <=
ZigZagRam (45) <=
ZigZagRam(46) <=
ZigZagRam) 47) <=
ZigZagRam! 48) <=
ZigZagRam! 49) <=
ZigZagRam! 50) <=
ZigZagRam (51) <=
ZigZagRam) 52) <=
ZigZagRam(53) <=
To_StdUlogi cVector (56,6)
ZigZagRam! 54 ) <=
ZigZagRam(55) <=
ZigZagRam (56) <=
<=
ZigZagRam! 38)
got
else
To_StdUloglcVector ( 53, 6 )
ZigZagRam (32) <=
"0001";
dequant
ZigZagRam (30) <=
<=
end
of
<=
1;
"0000";
"0001";
<=
(D
elsif
if
end
"1000")
(do_dequant
(15
);
if;
end
ulogic_vector
0)
downto
<=
std
out
out_data
i_outs
regl6;
then
'0')
Q <= "0000";
<=
i_outs
"0000";
=
then
COMPONENT:
reg 16
DESCRIPTION:
(architecture)
else
<=
"1000";
<=
"0001";
Name
regl6_arch
i_outs
if;
end
Purpose
else
"0000";
i_outs <= "0000";
end
end
Carpenter
A.
Douglas
Created
23-APR-1994
DAC
Revised
if;
if;
end
module
regl6
Author
<=
Dequant;
i_data
signal
of
regl6_arch
architecture
process
regl6
is
std_ulogic_vector
(15 downto
0);
assign
<=
qreq
output
values
begin
Q;
<=
process
reg process
begin
i_outs(l);
(reset
if
do_dequant_ack
<=
DeqToIDCT_WEl
<=
i_outs(0)
clock
'event) and (clock

'0')) then
if (in_latch
'ID then
i_data <= in_data;
'last_value
'ID
and
i_outs(2);
else
<=
i_data
i_outs ( 3 ) ;
i_data;
if;
if;
end
end
<=
LoadToDeqRADRl
"0000000000000000";
(clock
elsif
i_outs ( 0 ) ;
<=
DeqToIDCT_LDl
<=
clock)
then
'0')
<=
i_data
(reset,
end
process
reg_process;
To_StdUlogicVector ( ziggedaddr, 6 ) ;
output
assign
out_data
(ziggedaddr, 6)
i_data;
regl6_arch;
end
To_StdUlogi cVector
DeqToIDCT_DINl
<=
<=
DeqToIDCT_WADRl
end
values
<=
qtable_raddr
To_StdUlogicVector
(unzigaddr, 6)
<=
i_data;
COMPONENT:
reg32
DESCRIPTION:
(entity)
dequantize_arch;
Name
COMPONENT:
regW
DESCRIPTION:
(entity)
reg32_entity
A
Purpose
purpose
general
Author
Douglas A.
Created
26-MAY-1994
16
bit
register
Carpenter
Revised
Name
regl6_entity
Purpose
purpose
general
A.
Created
23-APR-1994
Revised
Author
library and
library ieee;
use
16 bit
ieee.
use
ieee.std_logic_1164_extens ions. all;
use
std_logic_1164
ieee.
entity
port
my_packages;
downto
port
regl6
is
reset
clock
0) ;
in_latch
std_ulogic;
in
std_ulogic;
reg32
in
.all;
all;
is
inputs
(
reset
in
std_ulogic;
clock
in
std_ulogic;
in_data
in
std_ulogic_vector
0) ;
in_latch
in
std_ulogic;
std_ulogic_vector
out_data
downto
(15
0)
);
end
all;
(31
outputs
in
in
my_packages;
inputs
in_data
downto
std_logic_1164
entity
clauses
use
use
all;
use
use
library
clauses
use
library
library and
library ieee;
register
Carpenter
Douglas
reg32;
std_ulogic;
outputs
COMPONENT;
A-65
reg32
out
std_ulogic_vector
( 31
DESCRIPTION:
htable
(architecture)
end
Name
reg32_arch
Purpose
reg32
Author
Douglas A.
Created
26-MAY-1994 DAC
module
find sos;
COMPONENT:
find_sos
DESCRIPTION:
(architecture)
Carpenter
Revised
find_sos_arch
Name
architecture
is
Purpose
Find
Author
Douglas A.
0);
Created
27-APR-1994
begin
Revised
reg32_arch
i_data
signal
reg_process
of
std
process
reg32
ulogic
(reset,
vector
downto
(31
architecture
(reset
i_data
then
'0')
<=
"00000000000000000000000000000000";
( clock 'last_value
'0')) then
if (in_latch
'1') then
i_data <= in_data;
elsif
'1')
and
else
i_data
<=
i_data;
if;
if;
end
end
end
process
assign
out_data
end
reg_process;
output
<=
start
of
values
l_data;
reg32_arch;
f ind_sos_arch
of
std_ulogic_vector
signal
aO
std_ulogic;
signal
al
std_ulogic;
signal
a2
std_ulogic;
signal
a3
std_ulogic;
signal
a4
std_ulogic;
signal
ab
std_ulogic;
signal
a6
std_ulogic;
signal
a'.
std_ulogic;
signal
a8
std_ulogic;
signal
a9
std_ulogic;
signal
alO
std_ulogic;
signal
all
std_ulogic
signal
al2
std_ulogic
signal
al3
std_ulogic
signal
al4
std_ulogic
signal
al5
std_ulogic
signal
al6
std_ulogic
findsos
signal
al7
std_ulogic
DESCRIPTION:
(entity)
signal
al8
std_ulogic
signal
al9
std_ulogic
signal
a20
std_ulogic
signal
a21
std_ulogic
signal
a22
std_ulogic
signal
a23
std_ulogic
signal
a24
std_ulogic
signal
a25
std_ulogic
signal
a26
std_ulogic
signal
a27
std_ulogic
signal
a28
std_ulogic
signal
a29
std_ulogic
signal
a30
std_ulogic
signal
a31
std_ulogic
signal
a32
std_ulogic
signal
a33
std_ulogic
signal
a34
std_ulogic
signal
a35
std_ulogic
signal
a36
std_ulogic
Find
Author
Douglas A.
Created
27-APR-1994
Start
of
Scan
Carpenter
Revised

use
mgc_portable.qsim_logic. all;
use
use
ieee.
std_logic_1164
use
ieee.
library
use
all;
all;
ions
.all;
my_packages;
my_packages
.package_l
entity find_sos
port
all;
is
(
inputs
clock
in
std
ulogic;
reset
in
std
ulogic;
find_sos_req
in
std
data
in
std_ulogic_vector
(7
signal
a37
std_ulogic
signal
a38
std_ulogic
signal
a39
std_ulogic
signal
a40
std_ulogic
signal
a41
std_ulogic
signal
a42
std_ulogic
signal
a43
std_ulogic
signal
a44
std_ulogic
signal
a45
std_ulogic
signal
a46
std_ulogic
signal
a47
std_ulogic
signal
a48
std_ulogic
signal
a49
std_ulogic
signal
a50
std_ulogic
signal
a51
std_ulogic
signal
a52
std_ulogic
signal
a53
std_ulogic
signal
a54
std_ulogic
signal
a55
std_ulogic
ulogic;
downto
next_ack
in
std
ulogic;
err
in
std
ulogic;
isr_latch_ack
in
std
ulogic;
qtable_ack
in
std
ulogic;
htable_ack
in
std
ulogic;
table_err
in
std
ulogic;
outputs
find_sos_ack
out
std
ulogic
find_sos_err
out
std
ulogic
next_req
isr_latch
out
std
ulogic
out
std
ulogic
isr_data_in
out
std_logic_vector
(7
downto
qtable_req
module
0)
out
std
ulogic
A-66
find_sos
signal
COMPONENT:
Purpose
scan
Carpenter
clock)
begin
if
std_ulogic
out
req
(3
is
downto
0)
begin
(next_ack
and
<=
a3
fsos_process
process
(reset,
begin
if
(reset
'0')
"0000";
<=
D
aO
<
al
<
a2
<=
a3
<=
a4
<=
a5
<=
a6
<=
a7
<=
a8
<=
a9
<=
(D(l)
'ID
al2
<=
al3
<=
al4
<=
al5
<=
al6
<=
al7
<=
al8
<=
al9
<=
a20
<=
a21
<=
a22
<=
a23
<=
a24
<=
a25
<=
a26
<=
a27
<=
a28
<=
<=
a30
<=
a31
<=
a32
<=
a33
<=
a34
<=
a35
<=
a36
a37
<=
a4
<
a41
<
a42
<
a43
<
a44
a45
a46
a47
a48
<
a51
<=
a52
<=
a53
<=
a54
<=
a55
<=
elsif
( (
<=
!D(1)
'1')
'11111111")
=
(D(l)
<=
'1'
(D(l)
"11011011")
'0'));
(D(2)
and
(next_ack
'0')
and
'0')
1 ')
and
=
and
(find_sos_req
and
(err
<=
'0'
((D(3)
and
<=
'1'
'1')
and
(htable_ack
(table_err
(D(2)
'1')
'0'));
'1')
and
'
0 ') and
( (D(3)
and
'ID
(D(0)
'0') and (next_ack
'0'
and
(err
));
((D(3)
'1') and (D(2)
'0') and
and
'0') and (data(l)
'0')
(D(0)
'0'
(next_ack
and
) ) ;
'ID and (D(2)
'0') and
((D(3)
and
'1')
(D(0)
'0') and (data(2)
'0'
(next_ack
and
) );
'0') and
((D(3)
'1') and (D(2)
and
'0')
(D(0)
'0') and (data (3)
=
<=
'1'
<=
'1'
alO
(D(l)
<
'1'
all
(D(l)
<
'1'
and
(next_ack
'0'));
'0')
((D(3)
'1') and (D(2)
(D(0)
'0') and (data(4)
and
(next_ack
'0'));
'
0' )
( (D(3)
'1') and ( D ( 2 )
and
(D(0)
'0') and (data(5)
and
(next_ack
'0'));
'
0 ' )
'1') and ( D ( 2 )
( (D(3)
and
(D(0)
'0') and (data(6)
and
(next_ack
'0'));
'
0 ' )
( (D(3)
'1') and ( D ( 2 )
and
'0') and (data (7)
(D(0)
and
(next_ack
'0'));
'
'
0 ') and ( D ( 2 )
1 ' )
( (D(3)
and
(D(0)
'0') and (next_ack
=
and
and
'0')
al2
(D(l)
<
'1'
and
'ID
al3
(D(l)
<
'1'
and
'0')
al4
(D(l)
<
'1'
and
'0')
al5
(D(l)
'I'D;
(D<1)
<
'1'
al6
<
'1'
al7
(D(l)
<
'1'
and
( (D(3)
(D(0)
=
'
1 ')
and
'0')
and
and
(next_ack
'
0 ' )
(D(2)
(data(0)
'0'));
(D(2)
'0')
and
and
'1')
and
((D(3)
'0') and
(D(0)
'0') and (next_ack
'0')
'0'
and
(err
) ) ;
((D(3)
'1') and (D(2)
'0') and
and
(D(0)
'1') and ( isr_latch_ack
=
and
al8
(D(l)
'O'D;
(D(l)
'O'D;
<
'0'
a20
(D(l)
<
'0'
al9
<=
'1'
((D(3)
'1') and (D(2)
'0') and
(D(0)
=
and
'
'
'
0' )
) and ( D ( 2 )
'1') and (data(0)
and
(next_ack
'0'));
'
'
0 ' ) and ( D ( 2 )
0 ')
( (D(3)
and
(D(0)
'1') and (data(l)
and
(next_ack
'0'));
'0'
( (D(3)
'0') and (D(2)
)
and
(D(0)
'1') and (data(3)
and
(next_ack
'0'));
'
'
0 ' ) and ( D ( 2 )
( (D(3)
0' )
and
(D(0)
'1') and (data (4)
and
(next_ack
'0'));
((D(3)
'0') and (D(2)
'0')
and
(D(0)
'1') and (data(6)
and
(next_ack
'0'));
((D(3)
'0') and (D(2)
'0')
( (D(3)
(D(0)
=
and
and
'0')
a21
(D(l)
<;
'1'
and
'0')
and
a22
(D(l)
(next_ack
=
'
'
and
'0'
) )
(D(2 )
and
'1'
and
=
'0')
a23
(D(l)
=
and
(D(3)
a9
(D(l)
'1')
'event) and (clock
'
0 ' ) ) then
'
'
0 ' )
0 ') and ( D ( 2 )
D(3 )
(data
and
nd
'ID
(D(0)
lue
<
'1'
and
=
'0')
;
=
'ID
(data
and
a24
(D(l)
<
'1'
and
=
'0')
and
'0')
'
(htable_ack
<=
(table_err
((D(3)
'0'
a8
(D(l)
!D(1)
'0')
11000100")
a2
and
and
ock
and
al
and
a50
aO
a7
a3
last_
<=
a6
(D(0)
0
(clock'
'0')
(data
'0'));
(D(2)
'1') and
( (D(3)
and
'0')
(D(0)
and
<
'0'
and
'0'));
<=
(next_ack
'
0 ) )
(D(2)
and
<=
a38
and
and
<=
a4
a5
all
a4
then
(D(l)
'0'
)
alO
a2
'1'
(D(l)
"11011010")
clock)
'
'1') and
'0')
(D(0)
[(D(3)
(next_ack
'
0
( (D(3)
and
(D(0)
=
'
and
'OD
'0'));
(D(2)
and
a25
=
'
(data
')
(D(l)
and
<
'1'
and
and
A-67
(D(0)
(next
'1')
ack
and
(data(7)
'0'));
and
=
'0')
a26
!D(1)
'I'D
<=
'0'
( (D(3)
'
'
(D(2)
and
and
'ID
a51
and
(next_ack
(D(l)
a27
=
<=
'1')
((D(3)
'0') and (D(2)
'0')
(D(0)
'1') and (data (2)
=
and
and
and
(next_ack
'0'));
0 ') and ( D ( 2 )
0 ' )
[ (D(3)
and
(D(0)
'1') and (data(5)
'
and
0 ') ) ;
( next_ack
'
'
0 ' ) and ( D ( 2 )
0' )
( iD(3)
and
(next_ack
'1')
'0'
and
(err
) ) ;
'
0 ' )
( (D(3)
'1') and ( D ( 2 )
and
(D(0)
'0') and (next_ack
a52
'0')
a28
(D(l)
<=
'1'
(D(l)
(D(l)
and
(D(0)
<=
'1')
'1')
(D(0)
<=
'
'
'1')
'ID
( (D(3)
and
(D(0)
1 ')
<=
(a6
or
(a37
'0')
and
'
'ID
(a42
1 ') and
(htable_ack =
(D(2)
and
a33
=
<=
'1'
( (D(3)
and
and
a34
(D(l)
<=
and
(table_err
'0')
and
<=
<=
'0'
(D(2)
'0')
or
(next_ack
[ (D(3)
'
'
(D(2)
and
(next_ack
=
'0')
'
'
or
[a50
(a55
'1'
and
(D(l)
'I'D
<=
'1')
'1')
(data (5)
a38
=
<=
'0'
'1'
'1')
<=
(a7
or
( (al
'1')
'
'
(data (6)
'0'));
(D(2)
'1')
(data (7)
(a46
and
'1')
<=
D(l)
and
'0')
(a6
'1')
or
(a30
'1')
or
(a37
'ID
or
(a42
'1')
or
(
'
(D(l)
<=
'0'
(D(2)
'1')
(data(O)
=
and
and
a39
and
(next_ack
((D(3)
'0')
a4
=
<=
'0')
(D(l)
<=
'0')
a42
=
<=
'0'
(D(l)
'I'D
<=
'0')
<=
D(0)
'ID
or
(al3
(a20
(a8
'1'
or
a44
(D(l)
ID
'1')
or
'1')
(a32
'1')
or
and
(D(2)
and
'
'
(a47
'1')
or
(D(l)
<=
'0'
'1'
or
'1'
(a41
'1'
(a51
or
'1'
or
'1')
or
'1')
or
'1')
a48
'1'
'1')
(a36
or
(a3
or
(al5
=
a39
or
(a52
)
'I'D;
or
(a50
a22
a28
a43
'1'
a49
'1'
a55
'1'
or
'1'
or
'1')
or
'1')
'1')
'1'
or
'1')
) );
or
'1')
(a51
or
or
(a45
or
or
'1')
(a31
or
or
'1')
'1'
) or
(a24
or
or
'1'
(a5
or
'1')
(al9
or
'1'
(al2
al6
or
'1')
a54
(alO
or
or
or
'1'
'1'
'1'
and
(find_sos_req
1 ') ) ;
and
( err
'0') and
( (D(3)
and
'1') and (next_ack
(D(O)
'0'
(err
and
) ) ;
'1')
'0') and (D(2)
((D(3)
and
'0'));
(D(0)
'0')
'0') and (D(2)
((D(3)
'
1 ' ) and ( next_ack
and
(D(0)
(a44
or
'1'
'1'
a3
'
'1'
'1')
a48
or
=
'1')
(a29
or
if;
end
a45
(a23
a33
'1'
(a29
or
'1'
'1'
a27
or
or
( (D(3)
or
(a6
or
'1')
a34
or
'1'
(al8
a21
or
(a25
(all
or
'0')
'1')
or
or
'1'
(a9
or
al4
'
or
'1')
a2
or
'
(a49
(a26
a2
'
'1'
'1')
ID
(a40
or
;
<=
or
a43
'1')
'1'
(a37
a51
or
=
'1')
a47
'0'));
and
(D(l)
(a35
'1'
or
or
or
'1')
or
'1')
a41
(al7
a38
and
=
(D(l)
or
'1'
(a7
or
or
(D(2)
'1') and
and
(data(l)
'1')
and
(next_ack
'0'));
'
'
0 ' ) and ( D ( 2 )
1 ') and
( (D(3)
and
(data (2)
'0')
and
(next_ack
'0'));
((D(3)
'0') and (D(2)
'1') and
and
(data (3)
'1')
and
(next_ack
'0'));
((D(3)
'0') and (D(2)
'1') and
and
(data (4)
'1')
(next_ack
and
'0'));
'
1 ') and
'1') and ( D ( 2 )
( (D(3)
and
'0') and (table_err
(D(0)
=
'1')
(a54
1')
'1'
'1')
aO
1')
a33
'0')
or
'1')
a4
'1')
(a52
or
(a33
or
and
(next_ack
'0'));
((D(3)
'1') and
'1') and (D(2)
and
(D(0)
((D(3)
(a49
or
or
(al9
or
(a48
or
'0')
'1')
or
(D(2)
and
'1'
'I'D;
D(2)
and
=
(D(l)
(a53
'1'
'1'
or
'1'
'1')
(a52
or
(a4
or
(a41
(a44
'1'
(a36
or
or
(a34
or
(a39
or
'1')
or
and
a37
(a48
a51
or
or
'1'
'1')
a43
'1'
'1')
(a40
1'
'1'
a3
or
(a30
(a35
a38
'0'));
and
((D(3)
'1')
'1')
or
'0'));
and
and
'
'0')
a36
(D(l)
'0')
a35
=
'
((D(3)
and
(D(l)
(qtable_ack
'1'));
'ID and
al
1')
or
(D(0)
and
or
<=
'0')
;
a32
(D(2)
and
or
and
'0'
'
'
1 ) and
) and ( D ( 2 )
'1') and (qtable_ack
=
1')
'1')
and
<=
D(3)
( (D(3)
and
(D(0)
and
'1')
'1'
(D(0)
) and
( (D(3)
'1') and (err
(D(0)
'0') and (D(2)
((D(3)
(table_err
and
'I'D;
<=
'0')
'1') and
(D(2)
( f ind_sos_req
(
and
<=
((D(3)
'O'D;
a55
;
a31
(D(l)
'0'
) )
<=
<=
'0')
a54
and
a30
(D(l)
) )
a53
'0')
(D(l)
'I'll;
a29
'0'
and
'I'D;
(D(l)
(D(l)
'ID)
'ID and
'ID and (D(2)
((D(3)
'1') and (qtable_ack
(D(0)
<=
'1')
process
end
fsos_process;
'0')
assign
output
values
a4
(D(l)
(D(l)
'I'D
<=
'1']
a47
<=
'1'
'1'
) )
<=
'1')
( (D(3)
and
and
a4
=
<=
'1'
'
0 ')
and
(qtable_ack
(table_err
(D(2)
'1')
'0'
) )
(D(2)
( (D(3)
'1') and
(D(0)
'1') and
=
and
'
else
find_sos_err
else
'
next_req
(a8
'1')
=
and
(f ind_sos_req
or
=
'1')
or
(al4
'1')
or
(a22
'1')
or
(a28
or
a50
=
<=
'1'
((D(3)
'0') and (D(2)
'
and
0 ' ) and ( err
(D(0)
=
<=
'1'
when
!(a3
when
((al9
'1')
or
(a4 9
'1')
(a52
or
'0';
<=
or
'
'1'
and
;
=
<=
'0';
and
=
'1'))
a4
(D(l)
find_sos_ack
and
(D(0)
(D(l)
'I'D
'0') and
'I'D;
or
A-68
'1'
or
when
(a9
(all
=
'1')
(a24
=
'1')
(al7
=
'1')
((aO
'1')
'1')
or
or
or
(a23
'1')
or
'1')
or
(a31
or
(alO
or
(al6
'1')
or
(al2
=
'1')
'1')
'1')
or
(al3
*1')
or
(a21
'1')
or
(a27
'1')
(a25
=
(a5
'1')
(a20
=
'1')
(a32 =!')
or
(a45
or
'I'D
else
'0';
isr_latch
'ID
<=
'1'
'1'
(a44
or
((al8
when
(a50
or
(a54
or
'1'
'1'
'1')
or
(a43
isr_data_in
'1') or
(a43
"01100110"
<=
(a44
or
or
or
(a55
'1'
) )
(a54
Created
27-APR-1994
( (al8
'1')
(a50
'1')
'ID
or
scan
module
Carpenter
(a55
scan
arch
of
dec
is
scan
signal
std_ulogic_vector
signal
std_ulogic_vector
signal
i_outs
std_ulogic_vector
(3 downto
0)
0)
(4 downto 0)
downto
(3
begin
or
dec
architecture
'1'
) )
"00000000";
else
Douglas A.
when
'1')
Decode
Revised
'0';
else
Purpose
Author
dscan_process
process
(reset,
clock)
begin
<=
qtable_req
'1')) else '0';
htable_req
'1'))
else
'1'
((a2
when
'1')
or
(a33
if
(reset
<=
'1'
((al
when
'1')
or
(a4
'0'
) then
"0000";
i_outs <= "00000";
(clock'
elsif
event )
and
(clock
(
[ clock 'last_value
'0')) then
if (D
"0000") then
'0';
<=
'1')
and
find
end
sos
if
arch;
(decode_scan ='1')
<=
COMPONENT:
DESCRIPTION:
scan
dec_scan
i_outs
compute
Purpose
Decode
Douglas A.
Created
27-APR-1994
MCU
num
<=
Carpenter
scan
std_logic_1164
use
ieee
std
library
use
ions
MCUs
.
for decode
<=
(D
"00000";
then
"0001")
<=
then
'1')
"0011";
got
compute
ack
all ;
i_outs
<=
"00000";
else
my_packages;
<=
port
wait
(computeNumMCUsack
all;
ens
entity dec_scan
out
if;
elsif
if
ieee.
send
"0000";
i_outs
clauses
use
"00010";
signal
signal
end
use
<=
else
Scan
Revised
library and
library ieee;
decode
recvd
signal,
(entity)
Author
then
"0001";
"0001";
<=
"00010";
(D
elsif
if
inputs
back to
std_ulogic;
<=
then
'0')
"0101";
i_outs
decode
then
dropped
ack
reset
std_ulogic;
"0011")
(computeNumMCUsack
clock
<=
"10000";
send
out
for
ack
header
scan
else
decode_scan
<=
std_ulogic;
"0011";
wait
to
drop
outputs
i_outs
out
<=
"00000";
if;
end
std_ulogic;
decode_scan_err
ack
if;
end
is
decode_scan_ack
for
waiting
i_outs
(D
"0101") then
( (decode_scan_header_ack
(decode_scan_header_err
'0')) then
Q <= "0111";
i_outs <= "00000";
elsif
(decode_scan_header_err
Q <= "1111";
i_outs <= "00100";
=
elsif
out
if
std_ulogic;
'1')
and
computeNumMCUs
out
computeNumMCUsack
in
std_ulogic;
std_ulogic;
'1')
<=
"0101";
<=
"10000";
i_outs
if;
end
std_ulogic;
(D
elsif
if
std_ulogic;
"0111")
then
(decode_scan_header_ack
'0')
then
<=
"0010";
i_outs <= "00001";
Q
out
else
std_ulogic;
<=
s cancompl et e
if;
end
)
dec
(D
elsif
scan;
if
decscan
DESCRIPTION;
(architecture)
complete
<=
then
=
'ID
"0110";
signal
i_outs
else
A-69
"0010")
(scancomplete
Q
COMPONENT:
"0111";
<=
"00000";
i_outs
std_ulogic
end
then
else
decode_scan_header
std_ulogic;
startscan
<=
"00000";
then
got
scan
<=
"0010";
for
wait
scan
use
my_packages
.package_l.all;
complete
i_outs
<=
entity dec_scan_header is
"00001";
if;
elsif
(Q
"0110") then
if (scancomplete
'0')
<=
Q
"0100";
end
port
inputs
then
back to
ack
clock
dropped
std_ulogic;
reset
i_outs
<=
"00000";
std_ulogic;
data
else
<=
"0110";
wait
for
ack
to
std_ulogic_vector
drop
i_outs
end
elsif
if
<=
"00000";
if;
(Q
"0100")
(decode_scan
0);
err
'0')
std_ulogic;
isr_latch_ack
then
"0000";
decode
std_ulogic;
scan
turned
off, back to start

i_outs <= "00000";
signal
outputs
std_ulogic;
<=
Q
return
to
"0100";
wait
for
i_outs
if;
(Q
elsif
isr_data_in
"01000";
std_logic_vector
"1111")
then
(decode_scan
Q<=
'0')
then
"0000";
decode
scan
off, back to start

i_outs <= "00000";
out
0);
decode
scan
header
decode
scan
header
ack
out
decode
scan
header
err
out
in
std_ulogic;
else
std_ulogic
<=
Q
to
"1111";
wait
for
signal
off
i_outs
end
<=
else
<=
dec
scan
)
header;
"00100";
if;
end
downto
std_ulogic;
turned
return
(7
error
condition
signal
out
std_ulogic;
<=
latch
isr
signal
off
end
if
out
next_req
else
to
downto
std_ulogic;
then
Q<=
to
(7
next_ack
"0000";
<=
"00000";
COMPONENT-
decjscanjheader
DESCRIPTION:
(architecture)
i_outs
end
end
end
if;
if;
assign
dscanjprocess;
process
<=
output
Douglas A.
Created
07-JUN-1994
startscan
<=
<=
<=
<=
i_outs(3);
i_outs(2);
i_outs ( 1 ) ;
<=
of
is
signal
signal
signal
i_outs
dscanh_process
std_ulogic_vector
(2
downto
std_ulogic_vector
(2
downto
std_ulogic_vector
0)
0)
(3 downto 0)
begin
downto
process
len_cntr
variable
i_outs(0);
decode_scan_header
scan
module
Carpenter
dec_scan_header_arch
architecture
computeNumMCUs
header
scan
values
dec_scan_header
decode_scan_err
dec
Decode
Revised
Q;
decode_scan_ack
end
Purpose
Author
(reset,
clock)
std_ulogic_vector
(3
0) ;
begin
i_outs(4);
if
(reset
'0'
) then
"000";
i_outs <= "0000";
len_cntr
"1000";
elsif
[ clock 'last_value
'0')) then
if (D
"000") then
Q
arch;
<=
:=
COMPONENT:
decscanheader
DESCRIPTION:
(entity)
'1')
and
if
dec
Name
scan
header
Created
07-JUN-1994
Carpenter
use
ieee. std
"000";
<=
"0000";
len_cntr := "1000";
end if;
i_outs
use
std_logic_1164
if
.
(D
elsif
clauses
"001")
cntr
<=
"101";
all;
(len
then
"0000")
header
all;
l_outs
library
then
<=
Revised
ieee.
'1')
"001";
i_outs <= "0000";
else
Douglas A.
use
<=
Purpose
Author
library and
library ieee;
(decode_scan_header
else
my_packages;
A-70
<=
"0010";
then
end
of
scan
<=
"Oil";
get
another
byte
dec
end
i_outs
<=
if;
end
(D
elsif
if
"Oil")
then
((next_ack=
'0') and
"010";
i_outs <= "1000";
elsif
(err
'1') then
Q <= "111";
i_outs <= "0001";
arch;
get
byte
huff2_reg256by8
(entity)
library IEEE;
err
COMPONENT:
DESCRIPTION:
then
(err='0'D
<=
header
scan
"0000";
on
use
IEEE.
std_logic_1164
use
IEEE.
std
.all;
logic
all;
read
else
<=
Q
next
byte
Written
"011";
wait
ready
i_outs <=
(D
elsif
if
"010")
<=
:=
(err
and
(err
'0'))
got
then
LogicLib
Passed
len_cntr
'ID then
generator
Parameters
tinst
"0001";
name
parameters
"111";
<=
"0001";
VHDL
"010";
<=
"1000";
REGISTER_FILE
called:
256
are:
huf f_reg256by8
are:
read_ports
else
<=
to
ack
i_outs
Specification
then
'1')
"110";
<=
i_outs
"0000";
len_cntir
09:08:37
May
Code
<=
elsif
Tue
at
"0000";
((next_ack
LL_to_VHDL
1994
if;
end
by
until
is
wait
i_outs
(D
elsif
if
huf f2_reg256by8
if;
end
"110")
(next_ack
WADR1
"110";
i_outs <= "0000";
end if;
(D
if
"101")
<=
in
downto
std_ulogic;
:
in
in
std_ulogic;
then
=
'
'
acdc
then
scan
std_ulogic
header
);
done
<=
reset
"000";
i_outs
LD1,WE1:
(decode_scan_header
Q
request
downto
0);
0);
0)
DOUT1:
<=
in
RADR1:
else
elsif
in
DIN1:
Q <= "001";
i_outs <= "0000";
is
port(
then
'0')
Entity Description
entity huff2_reg256by8
then
huff2_reg256by8;
end
"0000";
else
<=
Q
request
is
"101";
i_outs
till
if
<=
COMPONENT:
huff2_reg256by8
DESCRIPTION:
(architecture)
"0010";
if;
end
(D
elsif
huf f 2_reg256by8 Architecture

=
"111")
<=
'0')
"000";
then
scan
<=
"0000";
architecture
is
subtype
<=
"111";
wait
till
type
<=
"0001";
if;
end
vals
rtl
huf f2_reg256by8
of
ramword
is
is
std_ulogic_vector
(7
downto
rammemory is
array
(255 downto
0)
of
signal
ram
rammemory;
begin
<=
"000";
<=
"0000";
i_outs
if;
if;
end
process
assign
<=
huffman
of
ramword;
else
storage
0);
dropped
i_outs
end
the
done
i_outs
end
for
Used
header
else
request
Description
then
(decode_scan_header
Q
request
wait
dropped
variable
output
values
Process
the
convert
address
:=
raddrl
DOUT1
end
<=
<=
process
read
port
isr_latch
<=
<=
( ram, RADR1 )
to 255;
range
number
to_Integer (
ram
integer
to
'
'
RADR1,0);
(raddrl);
"00000000";
next_req
process
integer
begin
dscanh_process;
Q;
isr_data_in
raddrl
i_outs ( 3 ) ;
process
i_outs(2);
(DIN1,WE1,LD1,WADR1, reset, acdc)
variable
waddr
variable
load
:
:
integer
range
to
255;
std_ulogic;
begin
decode
scan
header
err
<=
<=
i_outs(l);
i
if
for
outs(0);
A-71
(reset
'0'
if
(acdc
DC
tables
) then
'0') then
is
ram(0
<=
To_StdUlogicVector(0,8);
ram
ram
ram(l
<=
To_StdUlogicVector(l,8);
4 9)
50)
(2
ram
ram
(3
(4
ram
(5
ram( 6
ram (7
ram( 8
ram!
9)
<=
<=
<=
52)
ram 53)
ram 54)
ram 55)
ram 56)
ram 57)
ram 58)
ram 59)
ram 60)
ran K61)
ram 62)
ram 63)
ram 64)
ram 65)
ram 66)
ram 67)
ram 68)
ram 69)
ram 70)
To_StdUlogicVector(2,l
To_StdUlogicVector(4,i
<=
<=
To_StdUlogicVector(6,i
<=
<=
<=
To_StdUlogicVector ( 9, 8
9
ram(
10)
<=
10
rami
11)
<=
ram
else
ram
0)
ram( 1)
ram! 2)
rami 3)
ram( 4)
ram! 5)
<=
To_StdUlogicVector (1,8
ram
<=
ram
<=
ram
<=
ram
<=
ram
<=
ram
ram(
<=
<=
To_StdUlogicVector (5, 8
ram
ram!
rami
<=
ram
rami
<=
To_StdUlogicVector 49
ram
<
To_StdUlogicVector
65
ram
ram
<
To_StdUlogicVector
6,8
ram
ram
<
To_StdUlogicVector
19
ram
ram
<
To_StdUlogicVector
81
ram
rami
<=
ram
<
ram
To_StdUlogi cVector
7,8
ram
ram
To_StdUlogicVector
34
ram
rami
To_StdUlogicVector
113
);
<
To_StdUlogicVector
20
rami
<
To_StdUlogi cVector
50
ram
To_StdUlogi cVector
129,
145,
161,
8,8]
35,
66,
177,
193,
21, E
82,
209,
240,
36, E
ram
<
To_StdUlogicVector
ram
ram
To_StdUlogi cVector
<
To_StdUlogicVector
To_StdUlogi cVector
ram
ram
<
To_StdUlogicVector
ram
<
To_StdUlogi cVector
To_StdUlogicVector
ram
ram
<'
To_StdUlogi cVector
ram
<
To_StdUlogicVector
ram(
<
To_StdUlogi cVector
ram
<
To_StdUlogicVector
ram
<
To_StdUlogicVector
ram
ram
ram
ram
);
ram
);
8);
8);
ram
ram
<
:=
<=
<-
<=
<=
<=
To_StdUlogicVector(68,8
<=
<=
82)
83)
84)
85)
86)
87)
88)
89)
90)
92)
93)
94)
95)
96)
97)
98)
99)
100)
ram
ram
ram
ram
ram
ram
rami
To_StdUlogi cVector
ram(
To_StdUlogi cVector
ram
ram(
To_StdUlogi cVector
4,8
ram
ram(
To_StdUlogicVector
0,8
ram(
To_StdUlogi cVector
ram(
To_StdUlogi cVector
ram
ram(
To_StdUlogicVector
ram
rami
To_StdUlogicVector
ram
rami
To_StdUlogi cVector
ram
rami
To_StdUlogi cVector
ram
rami
To_StdUlogicVector
ram
rami
To_StdUlogicVector
ram
rami
To_StdUlogicVector
ram
rami
To_StdUlogi cVector
ram!
To_StdUlogicVector
ram
<==
<=
To_StdUlogicVector(7 4,8
<=
<=
<=
<-=
<=
<=
<=
<=
<
<
<
<=
<
<=
<=
<=
:=
<'=
<=
<==
<
<=
<=
=
<=
<=
<=
To_StdUlogicVector
ram
A-72
To_StdUlogicVector(133,
<=
<
<=
<:=
To_StdUlogi cVector
< =To_StdUlogicVector
<=
<=
112)
113)
114)
115)
116)
117)
118)
119)
120)
<=
<=
<=
<=
<=
<=
<=
<=
<=
To_StdUlogicVector(14 9,
To_StdUlogicVector (154,
<=
<=
To_StdUlogicVector (166,
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
To_StdUlogicVector(170, 8),
To_StdUlogicVector( 17 9
<=
<=
<=
);
(137, 8
(138,8)
<=
102)
103)
104)
105)
106)
107)
108)
109)
110)
122)
123)
<
rar n(121)
ram
<=
rara(lll)
ram
<=
ran1(101)
36
ram!
ran 1(91)
ram
ram(
72)
73)
74)
75)
76)
77)
78)
79)
80)
<=
ran 1(81)
ram
ram
<=
ran 1(71)
11
ram!
<
=
ran i(51)
ram
ram
<-
ram(124
<=
ram(125
<=
read
ram(126
<=
To_StdUlogi cVector (198,8
ram(127
<=
ram(128
<=
ram(129
<=
ram(130
<=
ram(131
<=
ram(132
<=
ram(133
<=
ram(134
<=
ram(135
<=
ram( 136
<=
ram(137
<=
ram(138
<=
ram(139
ram(140
256
huf f_regl6byl6
port
DIN1
in
in
std_ulogic_vector
(3
downto
in
std_ulogic_vector
(3
downto
DOUT1
out
LD1
in
std_ulogic;
WEI
in
std_ulogic;
<=
reset
<=
acdc
ram(141
<:
ram(142
<-
ram(143
<-
ram(144
<=
COMPONENT:
huff_regl6byl6
DESCRIPTION:
(architecture)
<
<
To_StdUlogicVector(22 9,8
ram(147
<
ram(148
<
To_StdUlogicVector ( 231 , 8 )
<
<
ram(151
<
subtype
ram(152
<
ram(153
<
(154
<
<
<
ram(157
<
To_StdUlogicVector (24 6,8
ram(158
<
ram(159
<
ram(160
<
ram( 161
<
std_ulogic;
in
std_ulogic
rtl
ramword
rammemory is
type
signal
ram
LD1
raddrl
load
if
:=
LD1
(load
(waddr)
if;
ram
end
'
the
convert
address
<=
if
(reset
(entity)
(acdc
DC
tables
min
if
IEEE.
use
std
Written
.all;
by
LL_to_VHDL
at
Tue
May
09:08:37
1994
load
Specification
to
VHDL
Code
'0'
(minmax
Passed
generator
Parameters
tinst
name
parameters
called:
number
to
15;
integer
'
'
RADR1,0);
FILE
read
Process;
reset, acdc, minmax

integer range 0 to 15
std_ulogic;
REGISTER_FILE
then
0
then
is
0
ram(0)
<=
ram(2)
<=
ram(3)
<=
ram( 4
<=
ram(
<=
To_StdUlogi cVector (30,16) ;
<=
<=
<=
<=
ram(10)
<=
ram(ll)
<=
ram(12)
<=
ram(13)
<=
ram(14)
<=
ram(15;
<=
;
max
table
ram(0)
<=
<=
"1111111111111111";
2)
3)
<=
<=
ram(l
are:
then
<=
else
LogicLib
table
)
5)
ram( 6)
ram (7 )
ram( 8)
ram( 9)
library IEEE;
IEEE.
(ram,RADRl |
range
(raddrl);
waddr
'0'
if
ram(l
DESCRIPTION:
of
begin
DIN1;
rtl;
huff_regl6byl6
0)
(DIN1,WE1,LD1,WADR1,
variable
COMPONENT;
ram
REGISTER
variable
if;
process
port
to
then
read
to_Integer (
:=
<=
process
process
WADR1,0);
WEI;
and
'1'
'
process
integer
Process
DOUT1
to
integer
to
address
to_Integer
(15 downto
begin
end
:=
downto
(15
rammemory;
variable
high)
convert
array
raddrl
waddr
is
std_ulogic_vector
begin
if;
and
is
ramword;
To_StdUlogicVector(24 9,8)
(need both WEI
Description
huf f_regl6byl6
of
0);
mode?
std_ulogic;
in
huf f_regl6byl6 Architecture

architecture
ram(156
(15 downto
huf f_regl6byl6;
end
rami 145
ram(150
:
:
minmax
ram(146
ram(149
std_ulogic_vector
0),
0),
);
To_StdUlogi cVector (227, 8

wr Lte
use
(15 downto
else
end
std_ulogic_vector
0);
:
end
end
is
RADR1
ram(155
end
Entity Description
entity huf f_regl6byl6
WADR1
ram
ports
huf f_reg256byl6
are:
rami
ram(
A-73
is
ram(4)
<=
ram(5)
<=
ram(6)
<=
To_StdUlogicVector
To_StdUlogicVector
To_StdUlogicVector
To_StdUlogicVector
(14,16);
library IEEE;
(30,16);
use
IEEE.
( 62, 16 )
use
IEEE. std
(7 )
8)
<=
ram(
<=
To_StdUlogicVector(254,16),
ram(9)
<=
ram
logic_1164_extensions.all;
(126,16),
Written
(10)
<=
"1111111111111111";
1994
ram(ll)
<=
"1111111111111111";
Code
(12)
<=
"1111111111111111";
ram(13)
<=
"1111111111111111";
ram(14)
<=
"1111111111111111";
ram( 15)
<=
"1111111111111111";
ram
all;
std
LL_to_VHDL
by
Generator
Parameterized
Tue
at
May
09:08:37
Specification
to VHDL
1
ram
LogicLib
tinst
are:
parameters
16
are:
huf f_regl6by8
name
REGISTER_FILE
called:
generator
Parameters
Passed
read_ports
if;
end
else
if
(minmax
'
'
0 ) then
huff_regl6by8
ram(0)
ram ( 1 )
<=
2)
rami 3)
<=
ram(4)
<=
ram(5)
<=
ram
(6)
7)
rami 8)
ram ( 9 )
ram (10)
<=
rami
<=
reset
<=
acdc
<=
ram(
<=
port
<=
To_StdUlogicVector ( 502 , 16 )
<= To_StdUlogicVector
(1014,16)
ram(ll) <= To_StdUlogi cVector (2038, 16)
ram(12) <= To_StdUlogi cVector ( 4084, 16)
ram(13) <= To_StdUlogicVector (0,16);
<=
ram (14)
<= To_StdUlogicVector
ram (15)
(32704,16)
else
ram(0)
ram
(1)
2)
ram( 3)
<=
ram(
<=
WADR1
std_ulogic_vector
in
DOUT1:
std_ulogic_vector
in
LD1,WE1:
std_ulogic;
in
<=
ram(5)
<=
ram(6)
<=
ram(7)
<=
8)
ram ( 9 )
ram (10)
ram (11)
ram (12)
ram (13)
<=
<=
<=
<=
<=
<=
ram(14)
<=
ram(15)
<=
huff
std_ulogic
regl6by8;
COMPONENT:
huff_reglo"by8
DESCRIPTION:
(architecture)
huff_regl6by8 Architecture
holds
huffman
architecture
subtype
rtl
val
signal
ram
convert
waddr
:=
to_Integer
load
:=
LD1
if
raddrl
and
'
'
Process
the
convert
address
read
port
end
process
WADR1,0)
ram
'
'
number
RADR1,0);
(raddrl);
( DIN1 , WEI , LD1 , WADR1 , reset,

waddr
load
variable
WEI;
:
:
integer
acdc
range
)
0 to
15;
std_ulogic;
begin
if
(reset
if
(acdc
'0') then
'0') then
for DC tables
if;
process
( ram, RADR1 )
to 15;
range
process
to
'1') then
(waddr) <= DIN1;
if;
(load
of
integer
to
to_Integer (
:=
<=
variable
0)
process
integer
integer
to
downto
begin
ram
end
(15 downto
address
(7
rammemory;
variable
end
LD1
array
raddrl
and
is
std_ulogic_vector
begin
DOUT1
(need both WEI
is
rammemory is
type
if;
mode?
m
huf f_regl6by8
of
ramword
ptrs
ramword;
high)
end
Description
0);
if;
write
e
end
downto
std_ulogic;
in
else
be
downto
(3
);
end
-1
"1111111111111111";
To_StdUlogicVector (1, 16) ;
To_StdUlogicVector(123,16]
-1
"1111111111111111";
-1
"1111111111111111";
To_StdUlogicVector( 32704, 16)
<=
ram(4)
ram(
end
(7
0);
0);
out std_ulogic_vector (7
downto 0)
in
RADR1
max
<=
end
is
DIN1:
Description
Entity
entity huf f_regl6by8
ram(0)
<=
To_StdUlogicVector ( 0, 8)
ram(l)
<=
ram(2)
<=
ram(3)
<=
rtl;
COMPONENT:
huffregl6by8
DESCRIPTION:
(entity)
To_StdUlogicVector ( 0, 8 )
0
1
A-74
To_StdUlogicVector (1, 8) ;
is
ram(4)
<=
ram(5)
<=
To_StdUlogicVector (6, 8 )
(entity)
DESCRIPTION;
6)
<=
ram(7)
<=
ram(8)
<=
ram(9)
<=
ram(
Purpose
ComputeMCUs
Author
Douglas A.
Created
26-MAY-1994
Carpenter
Revised
library and
library ieee;
10
clauses
use
use
ieee.
std_logic_1164
use
ieee.
std
all;
logic_1164_extensions. all;
11
ram(10)
<=
ram(ll)
<=
(12)
<=
ram(13)
<=
To_StdUlogicVector (
ram(14)
<=
library
0
0
entity
ram
my_packages;
use
compute_MCUs
all;
is
port
inputs
0, 8 )
clock
std_ulogic;
reset
std_ulogic;
<=
ram(15)
computeNumMCUs
std_ulogic;
else
ac
ram(0)
<=
ram(l)
<=
2)
<=
0, 8
std
comput eNumMCUs ack
out
x_data
in
ulogic;
std_ulogic_vector
ram(
To_StdUlogicVector
(0, 8
(15 downto
0);
in
y_data
std_ulogic_vector
ram(3)
<=
To_StdUlogicVector
ram(4)
<=
std_ulogic_vector
ram(5)
<=
std_ulogic
ram(6)
<=
end
ram(7)
<=
To_StdUlogicVector
(11,
ram(8)
<=
To_StdUlogicVector
(15, 8)
ram(9)
<=
To_StdUlogicVector
(18, 8)
(15
downto
0);
(2, 8
out
numMCUs_in
(31
downto
0);
latchMCUs
out
);
9, 8
11
compute_MCUs;
COMPONENT:
ComputeMCUs
DESCRIPTION:
(architecture)
15
Purpose
compute
number
MCUs
of
decode
to
module
18
<=
ram(10)
To_StdUlogicVector
(23, 8)
23
ram(ll)
<=
To_StdUlogicVector
(28, 8)
ram(12)
<=
To_StdUlogicVector
(32, 8 )
Author
Douglas A.
Created
26-MAY-1994
Carpenter
Revised
<=
ram(13)
0, 8 )
0
ram(14)
<=
To_StdUlogicVector
( 0, 8)
15)
<=
To_StdUlogicVector
(36, 8 )
std_ulogic_vector
(2
downto
signal
std_ulogic_vector
(2
downto
signal
i_outs
std_ulogic_vector
(1
std_ulogic_vector
(31
dscan_process
else
(need both WEI
mode?
and
LD1
variable
to
downto
waddr
load
:=
(load
if
to
'
( 0
WEI;
to_Integer
LD1
=
and
'1'
(waddr)
if;
ram
end
address
<=
downto
integer
'
WADR1
(reset,
clock)
std_ulogic_vector
if
std_ulogic_vector
(15
0) ;
(reset
'OD then
"000";
i_outs <= "00";
:=
width
"0000000000000000";
Q
then
DIN1;
<=
height
:=
i_data
<=
"0000000000000000";
"00000000000000000000000000000000";
elsif
'1')
( clock 'last_value
'0')) then
if (D
"000") then
if (computeNumMCUs
'0') then
=
rtl;
COMPONENT;
(15
begin
0) ;
if;
process
process
height
variable
convert
width
0) ;
downto
high)
end
downto
if;
write
is
0);
0);
begin
end
end
i_data
signal
end
compute_MCUs
0);
36
be
of
signal
0);
0
ram(
compute_MCUs_arch
architecture
32
wrapirte_MCUs
A-75
and
<=
"000";
<=
"00";
i_outs
i_data
Written
<=
LL_to_VHDL
by
Tue
at
09:08:37
May
1994
"00000000000000000000000000000000";
Generator
Parameterized
else
to VHDL
Specification
Code
<=
"001";
<=
"00";
i_outs
if;
(Q
end
elsif
LogicLib
"001")
then
width;
tinst
Q <= "Oil";
i_outs <= "00";
:=
width
downto
![x_data(2)
'1')
(x_data(0)
'1')) then
=
or
3) 4 "000";
(x_data(l)
'1')
64
REGISTER_FILE
called:
are:
huf f_regl6by8
name
parameters
x_data(15
if
or
generator
Parameters
Passed
compute
are:
read_ports
:=
width
if;
(Q
end
elsif
"1000";
width
"011")
then
compute
port
<=
Q
"010";
i_outs <= "00";
height
:=
|(y_data(2)
(y_data(0)
'1'))
=
height
DIN1
downto
:=
'1')
or
then
"1000";
width
height
4width(15
"000"
i_outs
<=
"00";
i_data
<=
width
(Q
"100")
Q <= "101";
<=
i_outs
"01";
elsif
(Q
"101")
Q <= "111";
i_outs <= "10";
elsif
(Q
"111")
=
elsif
if
downto
height (15
3);
downto
3);
height;
subtype
end
std_ulogic
rtl
of
ramword
mem64by8
is
rammemory is
type
then
array
signal
'1')
then
ram
<=
variable
raddrl
Process
the
convert
address
raddrl
DOUT1
:=
<=
process
read
port
number
to
63;
'
'
0
4 RADR1,0);
(raddrl);
to_Integer (
ram
if;
variable
dscan_process;
waddr
load
variable
output
values
if
Q;
(mempreset
ram(l
<=
i_outs(l);
<=
integer
3)
)
rami 5)
rami 6)
ram ( 7 )
rami 8)
rami 9)
ram (10)
numMCUs_in
<=
i_data;
compute_MCUs_arch;
"00000000"
COMPONENT:
mem64by8
ram(ll)
<=
"00000000"
DESCRIPTION:
(entity)
ram(12)
<=
"00000000"
ram(13)
<=
"00000000"
ram(14)
<=
"00000000"
library IEEE;
ram(15)
<=
"00000000"
IEEE.
ram(16)
<=
"00000000"
ram(17)
<=
"00000000"
all;
A-76
range
std_ulogic;
'0') then
"00000000";
"00000000";
"00000000";
"00000000";
"00000000";
"00000000";
"00000000";
"00000000";
"00000000";
ram(
i_outs(0);
(DIN1, WEI, LD1,WADR1, mempreset)
rami 4
use
(ram, RADR1 )
range
integer
to
process
ram(2)
use
process
integer
begin
"00";
computeNumMCUsack
end
of
rammemory;
if;
latchMCUs
0)
then
end
assign
(63 downto
"000";
process
<=
downto
begin
begin
D
(7
ramword;
<=
<=
is
std_ulogic_vector
0);
else
end
in
(architecture)
"000";
i_outs <= "00";
end
if;
end
std_ulogic;
:
mem64by8
else
i_outs
0);
0);
std_ulogic;
DESCRIPTION:
<=
downto
mem64by8;
architecture
"111";
i_outs <= "10";
(5 downto
COMPONENT:
then
(computeNumMCUs
std_ulogic_vector
in
then
<=
in
0);
0);
);
end
(Q
"110")
"100";
elsif
then
"000"
:=
(5 downto
out
downto
(7
std_ulogic_vector
in
WEI
std_ulogic_vector
in
mempreset
:=
LD1
height +
if;
(Q
"010")
Q <= "110";
<=
i_outs
"00";
DOUT1
end
elsif
WADR1
3) 4 "000";
(y_data(l)
'1')
in
RADR1
y_data(15
if
is
mem64by8
entity
width;
or
Entity Description
mem64by8
=
to
63;
ram
18
<=
"00000000"
ram
19
<=
"00000000"
ram
20
<=
"00000000"
ram
21
<=
"00000000"
ram
22
<=
ram
23
<=
"00000000"
ram
24
<=
"00000000"
ram
25
<=
"00000000"
ram
26
<=
"00000000"
ram
27
<=
"00000000"
ram
28
<=
"00000000"
ram
29
<=
"00000000"
ram
30
<=
"00000000"
ram
31
<=
"00000000"
ram
32
<=
"00000000"
ram
33
<=
"00000000"
LogicLib
tinst
"00000000"
are:
16
64
Description
Entity
mem64byl6
is
mem64byl6
entity
read_ports
port
DIN1
in
DOUT1
LD1
in std_ulogic;
in
WADR1
std_ulogic_vector
std_ulogic_vector
ram
34
<=
ram
35
<=
"00000000"
ram
36
<=
"00000000"
ram
37
<=
"00000000"
ram
38
<=
"00000000"
ram
39
<=
"00000000"
ram
40
<=
"00000000"
ram
41
<=
"00000000"
COMPONENT:
mem64byl6
ram
42
<=
"00000000"
DESCRIPTION;
ram
43
<=
"00000000"
ram
44
<=
"00000000"
ram
45
<=
"00000000"
ram
46
<=
"00000000"
ram
47
<=
"00000000"
ram
48
<=
"00000000"
ram
49
<=
"00000000"
ram
50
<=
"00000000"
ram
51
<=
"00000000"
ram
52
<=
"00000000"
ram
53
<=
"00000000"
ram
54
<=
"00000000"
ram
55
<=
"00000000"
ram
56
<=
"00000000"
ram
57
<=
"00000000"
ram
58
<=
"00000000"
ram
59
<=
"00000000"
);
mem64byl6;
subtype
rtl
of
ramword
is
mem64byl6
is
std_ulogic_vector
(15
downto
0);
type
rammemory is
(63 downto
array
0)
of
ramword;
signal
ram
rammemory;
begin
variable
raddrl
process
integer
range
( ram, RADR1 )
0 to 63;
begin
Process
the
convert
address
:=
raddrl
D0UT1
end
60
<=
"00000000"
61
<=
"00000000"
ram
62
<=
"00000000"
ram
63
<=
"00000000"
<=
read
port
to_Integer (
ram
number
integer
to
'
0'
RADR1,0);
(raddrl);
process
( DIN1 , WEI , LD1 , WADR1 , mempres et )
process
mode?
(n
if
convert
waddr
:=
load
:=
if
(load
address
'1'
(waddr)
if;
ram
end
integer
to
to_Integer ( ' 0
LD1 and WEI;
=
'
WADR1,0);
then
<=
DIN1;
if;
process
variable
waddr
variable
load
rtl;
(mempreset
to
ram(3)
<=
rami 4
<=
rami
5)
6)
ram(7 )
ram( 8)
<=
ram!
<=
ram(9)
<=
<=
<=
<=
( 11
<=
ram(12
<=
DESCRIPTION:
(entity)
ram
(13
<=
ram(14
<=
ram(15
<=
use
IEEE. std_logic_1164. all;
ram(16
<=
use
IEEE.std_logic_1164
ram(17
<=
extensions. all;
at
Tue
May
09:08:37
1994
Code
<=
ram(19
<=
ram(20
<=
ram(21)
<=
(22)
<=
ram(23)
<=
(24)
<=
ram
ram(25
A-77
ram(18
ram
Specification to VHDL
<=
ram
library IEEE;
'0') then
ram(2)
mem64byl6
range
<=
COMPONENT:
LL_to_VHDL
integer
std_ulogic;
ram(l)
ram(10
by
begin
high)
Written
downto
in std_ulogic;
mempreset
in
std_ulogic
architecture
ram
end
(5
WEI
end
ram
end
(15 downto
0)
0);
0)
RADR1
"00000000"
writ e
end
REGISTER_FILE
called:
are:
huf f_regl6by8
name
parameters
else
be
generator
Parameters
Passed
<=
63;
ram(26
<=
ram(27
<=
ram(28
<=
ram(29
<=
ram( 30
<=
ram(31
<=
ram(32
<=
ram(33
<=
To_StdUlogicVector (0 16)
To_StdUlogi cVector (0 16)
To_StdUlogicVector ( 0,16);
ram(34
<=
ram(35
<=
ram(36
<=
(37
<=
ram(38
<=
ram(39
<=
ram(40
<=
(41
<=
ram(42
<=
ram(43
<=
ram( 4 4
<=
rami 4 5
<=
rami 4 6
<=
ram(47
<=
ram( 48
<=
ram( 49
<=
ram(50
<=
ram(51
<=
ram(52
<=
(53
<=
ram(54
<=
ram(55
<=
ram(56
<=
ram(57
<=
ram(58
<=
ram(59
<=
ram( 60
<=
ram( 61
<=
ram(62
<=
To_StdUlogi cVector (0
ram(63
<=
To_StdUlogi cVector (0
ram
ram
ram
reset
std_ulogic;
startscan
std_ulogic;
load
if
:=
:=
(load
to_Integer ( '
LD1 and WEI;
=
COMPONENT:
loadcoeff
DESCRIPTION:
(architecture)
Purpose
load
Author
Douglas A.
Created
27-MAY-1994
<=
std_ulogic_vector
signal
std_ulogic_vector
signal
i_comp
std_ulogic;
signal
i_afull
std_ulogic;
signal
std_ulogic;
load
FULL
don't
end
don't
'1';
begin
WADR1,0);
load_process
variable
DIN1;
if
(reset
'0')
"0000";
<=
Load
'
<=
Carpenter
(D
if
use
ieee.
'1')
and
<=
->
'0')
then
"0000";
i_afull
iload
all;
not_full
then
(startscan
all;
Send
"0000")
i_comp
.
0.
clauses
std_logic_1164
if
ieee.
0'
"00000000000000000000000000000000";
elsif
( clock 'last_value
'0')) then
Coefficients
use
'
27-MAY-1994
use
NOT_FULL;
'
<=
numMCU
Revised
library and
library ieee;
(31
then
<=
i_load
(entity)
clock)
std_ulogic_vector
begin
Douglas A.
Created
(reset,
0) ;
downto
load_coeff
Author
process
numMCU
i_afull
std_ulogic
fill
to
ok
i_comp
Purpose
std_ulogic
fill
DONEJJNLOADING
rtl;
COMPONENT:
DESCRIPTION:
std_ulogic
unload
UNLOADING
constant
to
is
0);
0);
unload
NOT_FULL
constant
( 3 downto
( 3 downto
std_ulogic
to
ok
'0';
LD1
load_coeff
of
constant
process
Carpenter
signal
'1';
if;
end
module
load_coef f_arch
architecture
if;
end
end
coeff
Revised
then
'1')
ram(waddr)
0'
ack
coeff;
constant
waddr
in
);
load
end
integer
to
a_empty_right
do load
'0'
address
out
std_ulogic
high)
convert
a_full_right
do_load
16)
16)
16)
16)
16)
16)
16)
16)
and
out
std_ulogic;
(need both WEI
std_ulogic;
mode?
0);
std_ulogic;
write
wri
downto
(31
std_ulogic;
else
in
numMCUsout
std_ulogic_vector
<=
<=
<=
'
'
NOT_FULL;
'0';
else
library
use
my_packages;
my_packages
.package_l
<=
"0001";
i_comp
all;
i_afull
entity load_coeff is
port
numMCU
end
<=
:=
'
'
NOT_FULL;
numMCUsout;
if;
inputs
1.
Check
if
loaded
clock
std
<=
ulogic;
elsif
A-78
(D
"0001")
then
all
MCU's
have been
if
(numMCU
<=
"1010";
'
<=
i_comp
i_afull
<=
'
startscan
NOT_FULL;
Q
"0011";
i_afull <= N0T_FULL;
do
next
MCU
Wait
"0011")
for done
end
a_empty_right
<=
"1111";
iload
'
<=
i_afull
<=
'
complete
seen
until
seen
NOT_FULL;
if;
<=
"0000";
i_afull
N0T_FULL;
'
<=
i_comp
else
<=
'
NOT_FULL;
if;
if;
end
<=
"0011";
done_unloading,
'
<=
i_afull
still
this
at
stay
i_load
<=
'
waiting
for
end
load_process;
process
end
step
N0T_FULL;
assign
values
output
if;
end
3.
(D
elsif.
if
Do
load
"1111")
then
(do_load_ack
<=
Q
therefore
<=
wait
else
done_unloading
got
'
then
DONE_UNLOADING)
NOT_FULL;
'
<=
i_afull
empty
'
until
seen
complete
i_comp
unloading
check if A
then
wait
Q <= "0000";
drops, acking
startscan
2.
(D
elsif
'
<=
then
complete
else
if;
end
if
<=
i_comp
i_afull
<=
'1')
Q <= "1010";
drops, acking
complete
then
"1010")
(startscan
if
then
else
buffer is
(D
elsif
"00000000000000000000000000000000")
'0')
Q;
then
"0010";
<=
ready to
load
<=
a_full_right
iload
'
<=
i_afull
<=
'
<=
i_comp;
load,
i_afull;
do_load
N0T_FULL;
<=
i_load;
else
<=
Q
to
load,
ack
"1111";
iload
<=
i_afull
<=
end
ready
'0';
NOT_FULL;
3.
(D
elsif
if
Do
load
"0010")
then
(do_load_ack
<=
Q
to wait
till
'1')
coeff
till
load
<=
has
COMPONENT:
dequantcoeff
(entity)
<=
<=
<=
wait
for
load to
'1';
NOT_FULL;
(D
elsif
<=
full
Send
'0')
is
port
load
:=
inputs
signal
that
reset
'0';
std_ulogic;
numMCU
<=
<=
i_afull
complete
ack
in
load_coeff_complete
in
out
std_ulogic;
0.
'0';
<=
N0T_FULL;
5.
Wait
std_ulogic;
a_full
if;
7.
(D
Go
to
<=
started
to
in
d_empty_left
out
a_full_right
out
a_empty_right
in
do_dequant
out
std_ulogic;
UNLOADING)
wait
left
std_ulogic;
Send
then
"0001";
i_afull
6.
unloading
#2
step
"0100")
for
(a_empty_right
Q
signals
load
"0110";
iload
if
startscan
std_ulogic;
dropped back to
->
is
std_ulogic;
numMCU
elsif
all;
clock
else
not_full
complete
full
iload
end
.package_l
entity dequant_coeff
then
"0100";
<=
FULL;
<=
.all;
my_packages;
my_packages
"00000000000000000000000000000001";
not
clauses
->
i_afull
data buffer
use
use
library
then
"0110")
(do_load_ack
27-MAY-1994
use
use
4.
Carpenter
Created
library and
library ieee;
NOT_FULL;
if;
end
Coefficients
Douglas A.
Revised
finish
i_afull
DeQuantize
drops
ack
"0010";
iload
Purpose
Author
acked,
'0';
<=
i_afull
load
else
has
arch;
DESCRIPTION:
then
"0110";
iload
if
load
if;
end
go
wait
until
then
next
std_ulogic;
unit
unload
<=
std_ulogic;
NOT_FULL;
else
Q
has
started
<=
"0100";
until
next
std_ulogic;
unit
do_dequant_unload
unloaded
i_afull
end
wait
<=
std_ulogic;
FULL;
if;
A-79
ack
in
do
dequant
i_aempty_left
ack
std_ulogic
signal
buffer
signal
that
dequantcoeff;
is
data
<=
UNLOADING;
<=
NOT_FULL;
empty
i_afull_right
);
end
not
<=
i_outs
loaded
not
at
output
"0";
else
COMPONENT:
dequant_coeff
DESCRIPTION:
(architecture)
dequant
Author
Douglas A.
Created
27-MAY-1994
--
buffers
in/out
<=
i_outs
Purpose
coeff
if;
end
(D
elsif
Revised
"0";
if;
end
module
Carpenter
dequant_coef f_arch
of
signal
dequant_coef f
buffer
unload/load
<=
not
signal
std_ulogic_vector
signal
(3 downto
signal
std_ulogic_vector
(3
<=
signal
i_aempty_left
std_ulogic;
signal
i_afull_right
std_ulogic;
signal
i_outs
std_ulogic;
std_ulogic_vector
FULL
constant
ok
'1';
ok
not
not
i_outs
<=
"0";
<=
signal
buffer
signal
that
std_ulogic
not
begin
i_outs
<=
"0";
clock)
begin
(reset
<=
'0'
the
then
'
(D
i_aempty_left
i_afull_right
<=
<=
outs
DONEJJNLOADING;
dequant
NOT_FULL;
<=
is
'
<=
'
(D
<=
for
;
<=
DONEJJNLOADING;
<=
N0T_FULL;
<=
<=
got
<=
i_aempty_left
<=
UNLOADING;
i_afull_right
<=
NOT_FULL;
<=
"1010";
Q
'
1
i_comp <=
if
<=
"1001";
<=
if;
(D
<=
<=
'1')
"1101")
<=
<=
done
<=
end
DONEJJNLOADING;
( (a_full left
ready to
Q
load,
<=
FULL)
DONEJJNLOADING) )
<=
"1";
(D
"1100") then
'0') and
( (do_dequant_ack
(do_dequant_unload_ack
'0')) then
Q <= "0010";
i_outs <= "0";
buffer
and
then
else
data
"0011";
out
and
then
"1101";
if
'1')
"1100";
<=
"0";
if
'1'))
if;
elsif
NOT_FULL;
"0";
else
(a_empty_right
then
else
then
complete,
i_afull_right
i_outs
(do_dequant_ack
i_outs
aempty_left
"1";
i_outs
then
scan
'
"1";
<=
empty
<=
"1100";
i_outs
end
A-80
then
DONEJJNLOADING;
elsif
DONEJJNLOADING;
(load_coeff_complete
if
'1')
NOT_FULL;
end
start
process
"0";
"0001")
then
"1001")
<=
Q
=
till
<=
i_outs
dequantization
aempty_left
(D
wait
i_afull_right
"0";
"0001";
start
"0";
i_aempty_left
if;
end
out
"1101";
i_outs
i_afull_right
elsif
send
else
i_aempty_left
i_outs
and
then
if;
waiting
<=
signal
signal,
i
'0')
do
"1111";
else
scan
'0'))
if
<=
then
"1111")
ready
elsif
and
output
signal
end
'1')
i_outs
at
"1001";
<=
"1";
i_outs
<=
i_comp
NOT_FULL;
(do_dequant_ack
Q
<=
scan
<=
if;
dequant
"0";
elsif
(clock'
last_value
'0')) then
if (D
"0000") then
if (startscan
'0') then
Q <= "0000";
start
UNLOADING;
else
"0000";
'
<=
0
i_comp
i_outs
output
<=
loaded
not
if
at
empty
is
if
(reset,
NOT_FULL;
"1011";
data
end
process
<=
i_afull_right
std_ulogic
fill
UNLOADING;
loaded
is
elsif
dequant_process
<=
empty
i_aempty_left
fill
to
then
NOT_FULL)
"1111";
data
DONE_UNLOADING
constant
output
else
unload
don't
i_afull_right
std_ulogic
UNLOADING
constant
that
unload
don't
'0';
signal
std_ulogic
to
NOT_FULL
constant
buffer
(0
0) ;
'1';
left
i_aempty_left
signal
at
then
"1011")
<=
i_comp
NOT_FULL;
loaded
not
"0";
(a_full
if
signal
downto
(D
elsif
downto
0);
'0'
<=
i_outs
0);
is
data
that
UNLOADING;
empty
i_afull_right
is
then
"0011")
"1011";
<=
i_aempty_left
architecture
wait
"0001";
<=
Q
for
if;
<=
"0";
do
(D
"0010")
"0110";
elsif
<=
<=
DONEJJNLOADING;
<=
FULL;
buffer
signal
empty
i_afull_right
signal
that
data
i_outs
(D
elsif
<=
Q
to
is
loaded
at
output
"0";
"0110")
then
(a_empty_right= DONEJJNLOADING)
if
signals
<=
data
"0110";
wait
<=
i_comp;
a_empty_left
<=
i_aempty_left;
a_full_right
<=
i_afull_right;
do_dequant
for
end
DONEJJNLOADING;
i_afull_right
<=
FULL;
is
at
output
not
i_outs
<=
Q
to wait
loaded
<=
i_outs ( 0 ) ;
<=
dequant_coef f_arch;
(entity)
then
signals
is
right
acked,
Coefficients
Purpose
IDCT
Author
Douglas A.
Created
27-MAY-1994
Carpenter
Revised
empty.
i_aempty_left
buffer empty
<=
i_afull_right
<=
that
idct_coeff
DESCRIPTION:
signal
UNLOADING)
"0100";
until
COMPONENT;
"0";
(a_empty_right=
elsif
signal
<=
change
i_aempty_left
signal
Q;
then
buffer empty
signal
<=
i_aempty_left
go
done
loading
unloading/
that
then
data
is
loaded
i_outs
<=
"0";
DONEJJNLOADING;
library and
library ieee;
NOT_FULL;
at
use
ieee.
std
use
ieee.
std
output
use
clauses
all;
ens
ions. all;
else
<=
library
"0110";
i_aempty_left
<=
buffer empty
i_afull_right
data is not loaded
<=
FULL;
at
output
use
DONEJJNLOADING;
my_packages;
my_packages
.package_l
all;
signal
that
entity idct_coeff
signal
is
port
inputs
--
i_outs
"0";
clock
if;
end
(D
elsif
if
<=
<=
buffer
signal
that
DONEJJNLOADING)
reset
then
std_ulogic;
"0001";
i_aempty_left
signal
std_ulogic;
then
"0100")
a_empty_right
<=
DONEJJNLOADING;
empty
i_afull_right
<=
data
is
loaded
i_outs
<=
"0";
NOT_FULL;
at
<=
empty
i_afull_right
data
is
not
i_outs
<=
"0";
that
<=
DONEJJNLOADING;
if
(D
<=
NOT_FULL;
loaded
<=
at
"1010")
<=
'
i_afull_right
<=
for
DONEJJNLOADING;
NOT_FULL;
do
<=
<=
DONEJJNLOADING;
NOT_FULL;
idct_coeff
(architecture)
"0";
'
<=
DONEJJNLOADING;
i_afull_right
<=
NOT_FULL;
end
assign
Douglas A.
Created
27-MAY-1994
coeff
module
Carpenter
idct_coef f_arch
of
idct
coeff
is
downto
downto
signal
i_comp
std_ulogic;
signal
i_aempty_left
std_ulogic;
signal
i_afull_right
std_ulogic;
signal
0);
if;
if;
process
idct
architecture
"0";
end
end
Purpose
Author
Revised
i_aempty_left
<=
coeff;
DESCRIPTION;
<=
i_outs
idct
COMPONENT:
if;
"0000";
'
0
i_comp <=
ack
else
done
IDCT
);
i_afull_right
end
in
std_ulogic
end
i_aempty_left
<=
a_empty_right
std_ulogic;
<=
i_outs
out
std_ulogic;
ack
else
'
u_full_right
do_IDCT
then
"0";
"0000";
'
0
i_comp <=
out
do_IDCT_unload_ack
<=
i_outs
a_empty_left
std_ulogic;
i_aempty_left
<=
in
output
wait
'
left
std_ulogic;
then
"1010";
i_comp
out
std_ulogic;
(startscan ='1')
std_ulogic;
if;
end
elsif
in
a_full
"0100";
buffer
signal
std_ulogic;
i_aempty_left
signal
in
std_ulogic;
output
else
startscan
std_ulogic;
signal
0);
dequant_process;
output
values
A-81
i_outs
signal
downto
std_ulogic_vector
(0
(D
elsif
0) ;
<=
Q
FULL
constant
'
1';
to
ok
'0';
don't
'1';
to
ok
<=
<=
fill
<=
7.
std_ulogic
fill
(D
elsif
if
(reset
unload
'
'
<=
DONEJJNLOADING;
NOT_FULL;
<=
'last_value
->
if
(D
if
<=
<=
'1')
done_unload
'
and
then
DONEJJNLOADING;
NOT_FULL;
<=
(D
Send
end
for
Wait
and
->full
elsif
'1')
then
<=
DONEJJNLOADING;
<=
"1101";
<=
"1";
if;
(D
load
then
"1110")
<=
'
then
complete,
done
;
<=
i_afull_right
<=
<=
'1')
scan
'
"1000";
<=
( (do_IDCT_done_ack
'1') and
(do_IDCT_unload_ack
'1')) then
data was
Q <= "1010";
then
i_aempty_left
i_aempty_left
<=
DONEJJNLOADING;
i_afull_right
<=
NOT_FULL;
i_outs
DONEJJNLOADING;
NOT_FULL;
<=
IDCT
"0";
else
"0";
<=
data
"1110";
was
not
IDCT
else
3.
Got
->
full
and
<-
done_unloading
( (a_full_left
FULL) and
DONEJJNLOADING) ) then
<=
data ready to
"0011";
Q
signal
that
<=
is
not
<=
i_outs
if
UNLOADING;
<=
NOT_FULL;
loaded
at
output
"0";
<=
"0001";
for
wait
in/out
"0";
if;
if;
end
(D
Send <-unloading
<=
"1010";
and
i_afull_right
<=
end
<=
i_aempty_left
<=
then
elsif
unload/load
UNLOADING;
unloading/
<=
not empty
i_afull_right <= NOT_FULL;
data
i_outs
is
<=
not
loaded
at
"0";
signal
output
signal
to
do
that
5.
Wait
for
->not
full
(D
Send
full
"0010")
"0110";
<=
->
then
done
loading
<=
DONEJJNLOADING;
<=
FULL;
buffer
empty
i_afull_right
data
is
elsif
A-82
done
if;
loaded
i_outs
IDCT
not
DONEJJNLOADING;
NOT_FULL;
"0";
i_aempty_left
buffer
data
<=
11.
"0011")
"1011";
=
i_aempty_left
<-
(D
then
=
i_outs
full->
Send
"1010")
( (do_IDCT_done_ack
'0') and
'0')) then
data done
Q <= "0010";
i_aempty_left <= DONEJJNLOADING;
i_afull_right <= FULL;
i_outs <= "0";
Q
<=
"1";
else
buffers
i_outs
DONEJJNLOADING;
NOT_FULL;
if;
11.
else
<=
(do_IDCT_unload_ack
empty
i_afull_right
data
<=
elsif
empty
i_aempty_left
buffer
<=
i_afull_right
end
buffer
signal
i_aempty_left
i_outs
(a_empty_right=
that
<=
i_outs
"0";
"0001")
i_outs
then
(do_IDCT_unload_ack
done_unloading
DONEJJNLOADING;
(dequant_coef f_complete
elsif
done
"1101")
if
i_comp
not_full
"0";
10.
(D
end
<=
if;
Q
<=
done_unload<-
signal
NOT_FULL;
if;
2.
signal
UNLOADING;
<=
i_aempty_left
B.
"0001";
i_outs
if
not
"1110";
i_outs <= "1";
"0";
i_aempty_left
was
else
<=
elsif
data
"1111";
<=
Q
<=
"1";
i_afull_right
elsif
else
out
<=
i_outs
and
<=
end
ready to
UNLOADING;
NOT_FULL;
i_aempty_left
if
'
i_afull_right
<=
<=
unload
'0')
i_aempty_left
i_outs
load,
<=
"0000";
i_comp
if
<=
i_afull_right
then
(startscan
data
i_aempty_left
end
"0000")
and
unloaded";
then
<-
Send
(clock
and
1.
not_full
'0')
else
ready to
( (clock 'event)
'0'))
elsif
clock
then
'0'))
"1101";
i_outs
i_aempty_left
i_afull_right
i_outs <= "0";
then
(do_IDCT_done_ack
<=
clock)
then
<=
i_comp
(reset,
"0";
unload";
'0')
"0000";
<=
process
"0";
"1111")
(do_IDCT_unload_ack
:
->
if;
end
if
idct_process
begin
Got
"1011";
i_outs
std_ulogic
DONEJJNLOADING
constant
'0';
begin
6.
else
std_ulogic
unload
don't
then
NOT_FULL)
"1111";
i_outs
unload
UNLOADING
constant
left
not_full
std_ulogic
NOT_FULL
constant
then
"1011")
(a_full
if
(D
<=
=
at
output
"0";
"0110")
then
signal
(a_empty_right=
if
<=
Q
signals
signal
to
wait
then
for
end
i_aempty_left
buffer empty
i_afull_right
<=
FULL;
is
at
output
not
i_outs
elsif
<=
Q
to wait
loaded
<=
DONEJJNLOADING;
arch;
l_outs
idct
(entity)
Name
UNLOADING)
"0100";
until
COMPONENT:
signal
then
signals
is
right
<=
deguantize_entity
22-APR-1994
Created
acked,
Revised
empty.
<=
DONEJJNLOADING;
buffer empty
i_afull_right <= NOT_FULL;
that data is loaded at output
signal
coeff
DESCRIPTION:
"0";
a_empty_right=
i_aempty_left
signal
idct
change
<=
that data
go
DONEJJNLOADING)
"0110";
library and
library ieee;
"0";
clauses
use
use
ieee.
std
use
ieee.
use
std. math. all;
all;
.all;
else
Q <= "0110";
i_aempty_left
buffer empty
i_afull_right
signal
that
data
is
not
i_outs
(D
elsif
<=
FULL;
at
output
library
use
entity idct
"0";
"0100")
DONEJJNLOADING)
"0001";
go
to
i_afull_right
<=
N0T_FULL;
data
is
loaded
i_outs
<=
"0";
at
MCU
<=
buffer empty
i_afull_right
signal
that
data
is
not
i_outs
<=
"0";
<=
DONEJJNLOADING;
do_idct
in
do_idct_unload_ack
out
do
out
<=
NOT_FULL;
loaded
at
(D
DeqToIDCT_RADRl
std_ulogic_vector
output
std_ulogic_vector
=
"1000")
'
<=
'
for
<=
i_afull_rlght
i_outs <= "0";
<=
std_ulogic_vector
'
'
out
0);
(5 downto
out
0);
IDCT_ToUnload_LDl
out
IDCT_ToUnload_WEl
out
);
;
<=
DONEJJNLOADING;
i_afull_right
<=
NOT_FULL;
<=
downto
std_ulogic
i_aempty_left
i_outs
(7
std_ulogic;
"0000";
<=
0);
IDCT_ToUnload_WADRl
std_ulogic_vector
DONEJJNLOADING;
NOT_FULL;
else
i_comp
(15 downto
ack
i_aempty_left
<=
0);
IDCT_ToUnload_DINl
then
wait
(5 downto
then
"1000";
i_comp
ack
DeqToIDCTJDOUTl
(startscan ='1')
<=
idct done
std_ulogic;
if;
elsif
end
in
std_ulogic;
output
"0100";
signal
reset
std_ulogic;
i_aempty_left
in
std_ulogic;
else
end
clock
std_ulogic;
then
next
DONEJJNLOADING;
then
=
.packagel.all;
is
port
i_aempty_left
buffer empty
if
my_packages;
my_packages
signal
<=
that
signal
<=
(a_empty_right
Q
signal
<=
DONEJJNLOADING;
if;
end
if
loaded
<=
end
"0";
if;
idct;
COMPONENT:
idct
DESCRIPTION:
(architecture)
else
<=
"0000";
i_comp
<=
'
'
Name
i_aempty_left
<=
i_afull_right
<=
i_outs
<=
DONEJJNLOADING;
NOT_FULL;
end
if;
if;
Author
Douglas
Created
16-MAY-1994
A.
Carpenter
Revised
idct_process;
process
architecture
assign
arch
Purpose
"0";
end
end
idct
output
values
behav
arch
of
idct
is
i_outs
downto
signal
i_data
downto
signal
load_addr
downto
signal
0);
);
D
<=
Q;
<=
i_comp;
0);
u_empty_left
<=
i_aempty_left;
a_full_right
<=
i_afull_right;
constant
IDCT
do
IDCT
<=
i_delay
begin
outs(0);
A-83
process
time
:=
15 ns;
subtype
32768
to
type
of
is
ramword
integer
Xloop
(63 downto
rammemory
is
array
iramword
is
integer
0)
range
0 to
of
irammemory
is
0)
variable
ram
rammemory;
variable
sss
rammemory;
variable
tmp
32768;
integer
real
tworoot
range
Cu
-32768.0
0.0
range
real
to
to
real
range
-32768.0
wait
real
range
-32768.0
wait
real
range
-32768.0
32768.0;
1.0;
32768.0;
ftmp
Cu
real
0.0
range
to
i_delay;
REAL(ram( (y*8)+u) ) *Cu*a;
sum
1;
i_delay;
for
for
wait
i_delay;
:=
sum;
for
wait
i_delay;
:=
INTEGER! ftmp)
i_delay;
sss((y*8)+x)
Cv
real
x,y,u,v, NUMBER
ss
irammemory;
0.0
range
to
integer
range
end
variable
begin
load
<=
"0000";
"000000";
loop Yloop;
end
<=
addr
wait
for
wait
until
Ins;
(reset
((reset
'0')
or
(do_idcf event) ) ;
i_delay;
for
Yloop
"waiting
until
reset
complete
in
'ID;
"reset
report
complete
severity NOTE;
elsif
( (do_idct
'1')
'0')) then
=
in
IDCT"
cos(
and
(do_idct
Cv
IDCT"
for
for
for
wait
NUMBER
:=
<=
end
<
64)
loop
)
wait
ftmp
level
tmp;
+
1;
1.0
Yloop
:=
sqrt(2.0);
i_delay;
(y
:=
i_delay;
(sum/4.0)
for
128.0;
also
i_delay;
for
then
i_delay;
:=
wait
<
8)
:=
for
INTEGER (
i_delay;
:=
y
y + l;
wait
for i_delay;
end loop Yloop;
i_delay;
while
for
ss((y*8)+x)
for
i_delay;
if;
end
wait
0;
:=
wait
:=
for
:=
ns;
wait
for
REAL (sss ( (v*8 )+x) ) *Cv*b;
:=
i_delay;
i_outs <= "0001";
tworoot
i_delay;
1;
(ftmp < 0.0) then

0.0;
ftmp
elsif
(ftmp > 255.0)
255.0;
ftmp
for
wait
for
if
"000001";
loop LoadLoop;
wait
i_delay;
sum
shift
wait
load_addr
NUMBER +
loop Vloop;
end
i_delay;
:=
for 1
wait
(NUMBER
i_delay;
load_addr
:=
ns;
ram(NUMBER)
wait
wait
To_Integer (DeqToIDCTJDOUTl
:=
wait
for
wait
while
1.0;
:=
:=
sum
Ins;
LoadLoop
tmp
loop
0 ) *REAL (v) *pi ) /16. 0 )

0) then
tworoot;
+1
:=
wait
i_delay;
:=
0;
for
8)
if;
end
for
NUMBER
(v <
i_delay;
else
severity NOTE;
load_addr <= "000000";
wait
(v
Cv
"doing
report
wait
FALSE
assert
for
( ( (2.0*REAL(y) )
last_value
loop
if
'
8)
i_delay;
while
wait
FALSE
assert
<
(y
0.0;
for
Vloop
=
loop
0;
:=
wait
severity NOTE;
wait until
(reset
8)
<
i_delay;
while
:=
sum
IDCT"
(x
while
0;
:=
wait
FALSE
report
for
Xloop
'0'
0;
:=
wait
) then
i_outs <= "0000";
<=
load_addr
"000000";
assert
for
y +1;
for i_delay;
wait
i_outs
if
:=
wait
64;
1;
i_delay;
loop Xloop;
:=
variable
for
wait
10.0;
tworoot;
:=
loop Uloop;
end
variable
then
for i_delay;
:=
10.0;
to
loop
0) *REAL (u) *pi ) /16. 0 )
:=
:=
sum
variable
0)
for
wait
32768.0;
variable
8)
<
if;
sum
variable
+1
Cu
end
variable
to
(u
range
(u
i_delay;
if
10.0;
to
( ( (2.0*REAL(x) )
32768.0;
variable
for
else
ftmp
variable
cosl
i_delay;
while
wait
iramword;
32768 to
to
downto
(63
array
loop
0;
for
Uloop
type
8)
0.0;
:=
wait
255;
(x <
while
:=
subtype
sum
ramword;
i_delay;
for
wait
range
32768;
loop
end
0;
A-84
+1;
for i_delay;
loop Xloop;
ftmp )
IDCT
unload
load_addr
<=
data to
for y in 0 to 7
for x in 0 to
i_data
load_addr
for
<=
+x
8 ) ;
end
for
"000001";
end
unload
unload
coeff;
unloadcoeff
(architecture)
(do_idct
in
ack
DESCRIPTION:
=
'0');
Purpose
unload
coeff
Author
Douglas A.
Created
27-MAY-1994
module
Carpenter
Revised
"0000";
architecture
unload
coeff
of
arch
unload
coeff
is
std_ulogic_vector
(3
downto
std_ulogic_vector
(3 downto
i_comp
i_aempty
std_ulogic;
i_outs
std_ulogic
0);
"0000";
signal
if;
0);
signal
IDCT;
process
signal
assign
out
);
15ns;
<=
do_unload
std_ulogic
signal
i_outs
out
do
load_addr
else
end
a_empt y_l e f t
COMPONENT:
for 15ns;
for
in
ns;
wait
wait
a_full_left
"0011";
until
<=
in
std_ulogic;
i_delay;
wait
i_outs
std_ulogic;
end
15
<=
out
std_ulogic;
loop;
loop;
i_outs
scancomplete
std_ulogic;
end
wait
in
std_ulogic;
<=
y*
startscan
std_ulogic;
loop
7 loop
To_StdUlogicVector ( ss ( (
8 )
wait for i_delay;
i_outs <= "0101";
wait for i_delay;
i_outs <= "1101";
wait for i_delay;
i_outs <= "0001";
wait for i_delay;
wait
buffer
next
"000000";
signal
outputs
std_ulogic;
vector
(0 downto
0);
do_idct_unload_ack
<=
outs(0);
FULL
constant
do_idct_done_ack
<=
ok
i_outs(l);
to
NOT_FULL
constant
IDCT_ToUnload_LDl
<=
IDCT_ToUnload_WEl
<=
don't
i_outs(2);
don't
i_outs(3);
DeqToIDCT_RADRl
load_addr;
IDCT_ToUnload_WADRl
IDCT_TOUnload_DINl
end
<=
<=
UNLOADING
DONEJJNLOADING
unload_process
(reset
process
'OD
"0000";
<=
UnLoad Coefficients
Author
Douglas
Created
27-MAY-1994
A.
clock
<=
"0";
( (clock 'event)
Carpenter
(D
if
use
ieee.
std_logic_1164
ieee.
<=
all;
<=
'1'
std
ulogic
'0'
clock)
is
inputs
if
in
Q
complete
std_ulogic;
:
'1')
<-
done_unloading
'0')
'
'
then
<=
DONEJJNLOADING;
"0";
in
<=
(D
for
"0001")
->
full
then
(idct_coeff_complete
<=
"1010";
'1')
signal
i_comp
A-85
DONEJJNLOADING;
"0";
wait
=
i_a empty
std_ulogic;
<=
if;
2.
elsif
(clock
then
"0001";
i_outs
all;
reset
<=
i_aempty
.package_l
clock
else
end
port
"0000";
i_outs
all;
my_packages;
unload_coeff
ulogic
then
(startscan
entity
Send
i_comp
i_aempty
use
my_packages
std
(reset,
and
'0'))
"0000")
<=
clauses
1.
if
use
'0'
'
'last_value
Revised
library
i_outs
Purpose
use
0 ;
i_comp <=
i_aempty <= DONEJJNLOADING;
elsif
library and
library ieee;
ulogic
then
'
(entity)
std
begin
behav arch;
DESCRIPTION:
'1'
fill
to
if
unloadcoeff
begin
load_addr;
i_data;
COMPONENT:
fill
constant
ok
ulogic
unload
constant
<=
std
unload
<=
<=
'
DONEJJNLOADING;
1
'
then
recvd
and
else
(a_full
<=
left
FULL)
then
"0011";
3.
got
->
output
assign
i_aempty
<=
D
<=
"0001";
2.
wait
<=
if;
if;
4
(D
elsif
Send unloading
<=
i_comp;
a_empty_left
<=
i_aempty;
Wait
(D
for
unload
end
not_full
"1110")
(a_full_left
Q <= "1111";
then
NOT_FULL)
6.
"1110";
if
(D
5.
wait
do
(entity)
"1111")
Purpose
Do
Douglas A.
<=
Created
27-MAY-1994
library and
library ieee;
'0')
then
"1101";
send
Load
Coefficients
Carpenter
Revised
then
(do_unload_ack
unload
Author
for
unload
arch;
got
if;
7
elsif
coeff
COMPONENT:
not_full
end
i_outs(0);
DESCRIPTION:
else
<=
unload
then
not_full
<=
5.
if
scancomplete
do_unload
"0011") then
Q <= "1110";
<=
i_aempty
UNLOADING;
elsif
Q;
DONEJJNLOADING;
end
end
<=
for
full
i_aempty
values
UNLOADING;
else
unload_process;
process
end
full
->
if;
end
if
do
use
clauses
use
ieee.
use
std_logic_1164
all;
.all;
unload
i_outs
<=
library
"1";
use
else
<=
"1111";
<=
"0";
entity do_unload
i_outs
7
if
"1101")
(do
unload
clock
then
ack
'1')
std_ulogic;
then
"1100"
<=
inputs
unload
(D
elsif
do
reset
unload
ack
std_ulogic;
recvd
i_outs
<=
do_unload
"0";
<=
do
"1101";
<=
"1";
if
(D
std_ulogic_vector
unload
"1100")
<=
'0')
do
unload
ack
<=
"0";
<=
(D
<=
<=
Send
=
end
done_unload
"0010")
for
(D
elsif
if
done
<=
full
=
signal
"1010")
to
'1')
drop
in
wait
for
Purpose
do
Author
Douglas A.
Created
22-JUN-1994
'
<=
<=
unload
module
Carpenter
Revised
ack
'
architecture
"0000";
i_comp
do_unload
arch
of
do
unload
is
downto
downto
i_outs
downto
i_data
downto
i_radr
downto
0);
'
signal
0);
DONEJJNLOADING;
if;
signal
0);
else
<=
"0000";
'
signal
'
0 ;
i_comp <=
end
(architecture)
signal
i_a empty
dounload
--
else
end
0);
unload;
DESCRIPTION:
then
"1010";
'
do
COMPONENT:
then
i_comp <= 1 ;
<=
out
downto
DONEJJNLOADING;
(startscan
<=
result_data
then
"0001";
i_aempty
wait
out
std_ulogic
"0";
unloading
to
in
0);
);
8.
elsif
downto
result_data_ack
"1100";
if;
end
out
0);
result_data_valid
else
i_outs
downto
std_ulogic;
i_outs
(5
then
"0010";
dropped back to
out
IDCT_ToUnload_DOUTl
then
(do_unload_ack
ack
I DCT_ToUnl o ad_RADRl
if;
elsif
unload
std_ulogic;
i_outs
end
in
std_ulogic;
else
go
is
port
if;
end
my_packages;
my_packages.package_l. all;
0);
signal
if;
0);
A-86
begin
if;
end
unload_process
process
(reset,
unload_process;
process
end
clock)
begin
if
(reset
'0'
) then
Q <= "0000";
<=
i_outs
"00";
i_radr <= "000000";
=
( (clock 'event)
'last_value
'0'))
elsif
clock
(D
if
"0000")
(do_unload
<=
Q;
<=
result_data
(clock
and
'ID
i_data;
and
then
if
outputs
assign
<=
result_data_valid
i_outs(l);
then
'1') then
"0001";
i_outs <= "00";
i_radr <= "000000";
IDCT_ToUnload_RADRl
i_radr ( 5
<=
downto
0)
<=
<=
do_unload_ack
else
end
do
unload
(0)
i_outs
arch;
<=
"0000";
i_outs <= "00";
i_radr <= "000000";
end if;
elsif
(D
"0001") then
Q <= "0011";
i_outs <= "00";
elsif
(D
"0011") then
Q <= "0010";
i_outs <= "00";
i_data <= IDCT_ToUnload_DOUTl;
elsif
(D
"0010") then
if (result_data_ack
'0') then
<=
Q
"0110";
COMPONENT:
do loadcoeff
DESCRIPTION:
(entity)
Purpose
Do
Author
Douglas A.
Created
27-MAY-1994
--
Load
Coefficients
Revised
library and
library ieee;
use
ieee.
use
ieee.std
use
clauses
std_logic_1164
i_outs
<=
"10";
library
else
<=
elsif
(D
use
"0010";
i_outs <= "00";
end if;
if
"0110")
ens
load
inputs
reset
else
"0110";
<=
"10";
(D
if
"0100")
<=
load
do
load
ack
ack
'0')
loadAC
then
"0101";
<=
"00";
end
i_outs
do
load
ack
in
std
in
std
ulogic.
in
std
ulogic,
out
ulogic,
std
ulogic,
out
std
ulogic,
in
std
ulogic.
out
std
ulogic.
in
std
ulogic
loadAC
then
(result_data_ack
do
loadDC
if;
elsif
loadDC
i_outs
end
all;
clock
"0100";
i_outs <= "00";
<=
is
coeff
then
<=
.all;
port
'1')
ions
my_packages;
entity do
all;
then
(result_data_ack
Carpenter
coeff;
else
COMPONENT:
Q <= "0100";
i_outs <= "00";
k>
load
coeff
(ardHteeture>;::
if;
end
(D
elsif
i_radr
<=
"0101")
i_radr
then
Purpose
do
Author
Douglas A.
Created
27-MAY-1994
"000001";
<=
i_outs
Revised
"0111";
<=
"00";
elsif
(D
"0111") then
if (i_radr
"000000")
Q <= "1000";
i_outs <= "01";
Q
;;
DESCRIPTION:
load
coeff
module
Ca rpenter
then
else
Q<=
arch
of
do
load
coeff
is
std_ulogic_vector
(2
downto
signal
downto
signal
i_outs
std_ulogic_vector
0);
0);
(2 downto 0),
<=
"00";
begin
if;
(D
elsif
then
"1000")
(do_unload
'0')
doload_process
then
<=
if
<=
process
(reset,
clock)
'0') then
"000";
i_outs <= "000";
elsif
'1') and
( clock 'last_vaiue
'0')) then
if (D
"000") then
if (do_load
'0') then
Q <= "000";
wait for do load
i_outs <= "000";
"1000";
<=
"01";
<=
i_outs
end
(reset
else
begin
"0000";
i_outs <= "00";
if;
else
<=
"0000";
i_outs <= "00";
end if;
Q
load
signal
"0001";
i_outs
end
if
do
architecture
else
A-87
<=
Q
load DC
"001";
do
got
load,
Revised
i_outs
"010";
library
(D
elsif
if
<=
if;
end
"001")
(loadDC_ack
<=
"001";
i_outs
<=
'0')
then
library
wait
for
load
DC
"010";
else
<=
elsif
(D
"011";
got load DC ack,
to wait for loadDCack to turn off
<=
i_outs
"000";
end if;
if
"011")
(loadDC_ack
use
use
ieee.
std_logic_1164
use
ieee.
library
use
then
loadDC
entity do
load
"010";
i_outs <= "001";
load AC
DC
if
inputs
load
DC
ack
coeff
"010")
(loadAC_ack
<=
then
'0')
"010";
in
ulogic
loadDC
in
ulogic
loadDC_ack
out
ulogic
decode
out
wait
for
load AC
i_outs
<=
"001";
Tdecode
Q
to wait
"110";
loadACack to turn
i_outs <= "000";
(D
elsif
"110")
(loadDC_ack
<=
vector (7
std
ulogic
vector (7
std
ulogic
vector
'1')
std
ulogic
vector
"110";
<=
"000";
std_ulogic
vector
ack
"100";
i_outs <= "100";
to
load AC
ack
end
if;
(D
"100") then
if (do_load
'1') then
<=
do load
Q
"100";
elsif
<=
still
do
<=
<=
"100";
<=
out
std
ulogic
LoadWEl
out
std_
ulogic
Purpose
do_loadDC
Author
Douglas
Created
02-JUN-1994
"000";
"000";
if;
if;
process
do
architecture
<=
Carpenter
loadDC
arch
of
do
loadDC
signal
signal
signal
i_outs
signal
PRED
integer
signal
TMP
integer
i_data
is
downto
(3
downto
0)
0)
std_ulogic_vector
range
-1024
range
1024
to
-1024
to
1024;
doload_process;
signal
downto
0);
begin
Q;
do_load_ack
loadDC
<=
loadAC
<=
load
<=
doloadDC_process
i_outs(2);
downto
variable
downto
(reset
'0'
) then
"0000";
i_outs <= "000000";
PRED <= 0;
elsif
( clock 'last_value
'0')) then
if (D
"0000") then
Q
<=
Douglas A.
clock)
if
doloadDC
( reset,
begin
arch;
(entity)
process
IDIFF
0);
i_outs(0);
DESCRIPTION:
variable
0);
i_outs(l);
COMPONENT:
Author
module
A.
Revised
"000";
i_outs
do
0);
loadDC;
else
end
out
(architecture)
on.
if;
end
0);
downto
do loadDC
"000";
i_outs
<=
(5
COMPONENT:
off
end
out
downto
DESCRIPTION:
else
end
0);
i_outs
end
downto
in
(7
LoadLDl
ulogic
end
end
till
ulogic
in
<=
wait
0);
LoadWADRl
load AC
ulogic
out
in
(7"
else
go
downto
LoadDINl
on
done,
0);
RetV
then
std
in
downto
DIFF
then
=
i_outs
still
ulogic
ack,
off
if;
end
if
load AC
got
for
std
ulogic
ulogic
in
ack
ulogic
ulogic
std
out
ack
extend
extend
std
in
ack
receive
else
go
in
reset
receive
then
ack
<=
all;
clock
decode
(D
elsif
is
ack
if;
end
.all;
port
<=
to
all;
my_packages;
else
go
all;
on
done,
all;
then
'1')
"011";
i_outs <= "000";
ieee;
mgc_portable,
use
<=
Q
still
clauses
use
and
then
=
ack
go
27-MAY-1994
Created
send
coeff
Carpenter
A-88
'1')
and
(loadDC
if
to
next
'1')
"0001";
<=
step
i_outs
got
do
load,
<=
"000000";
off,
"0000";
load
for do
wait
(D
<=
(decode_ack
<=
Q
decode
is
"0001")
not
'1')
in
ensure
in use,
end
if;
if
(decode_ack
<=
<=
<=
"001000";
for
wait
<=
"0010";
it
to
drop
i_outs
(D
elsif
to
decode
(D
to
=
<=
turn
see
"0010";
<=
else
"000000";
send
off,
out
decode
"0110";
receive
ack
in
else
value
<=
(D
<=
then
"0110")
=
end
then
'0')
"0110";
end
for
wait
<=
for
loadDC_ack
"0100";
it to
drop
i_outs
(D
to
receive
turn
decode
off
'1')
then
wait
extend
for
turned
"0101";
extend
out
<=
(D
<=
signal
"0101")
=
'0')
then
"0100";
i_outs
for
wait
<=
for
<=
i_outs(5);
LoadLDl
<=
i_outs
'ID
"0111";
<=
(4)
i_data;
to
turn
do
loadDC arch;
COMPONENT:
doJoadAC
DESCRIPTION:
(entity)
then
got
ack
<=
extend
"000010";
extend
i_outs
"000000";
LoadWEl
end
wait
(extend_ack
<=
Q
to
<=
then
ack
elsif
i_outs(l);
ack
LoadDINl
=
i_outs(2);
"000010";
(extend_ack
if
receive
if;
end
<=
LoadWADRl
off, send
i_outs
elsif
<=
"000000";
else
<=
i_outs(3);
receive
off
<=
then
"0100")
<=
i_outs(0);
"000000";
"0100";
i_outs
<=
ack,
receive
=
<=
Q
to
back
(receive_ack
if
ack
<=
got
if;
end
elsif
Q;
"000100";
else
<=
doloadDC_process;
process
<=
i_outs
wait
"000000";
receive
ack
<=
if;
if;
end
(receive_ack
"0000";
i_outs
"000100";
if;
elsif
if
<=
from decode
i_outs
extend
ack,
Author
Douglas A.
Created
02-JUN-1994
off
"000000";
Carpenter
Revised
else
Q
wait
for
<=
"0100";
extend
i_outs
end
wait
if;
end
lock
"1010";
<=
"000001";
i_outs
turned
signal
Tdecode;
:=
end
<=
Q
<=
then
"0000";
i_outs <= "000000";
else
'0')
<=
for decode
wait
"000001";
(loadDC
elsif
off
i_outs
<=
i_outs
then
'1')
wait
ack
my
then
"0010")
ack,
off
"000000";
(decode_ack
Q
ack
<=
to
if;
end
if
got
back
unknown
input,
library and
library ieee;
ack
<=
8 ) ;
<=
"110000";
"1110") then
Q <= "1010";
i_outs <= "000001";
elsif
(D
"1010") then
if (loadDC
'1') then
Q <= "1010";
else
(TMP,
then
"1110";
elsif
ack
i_outs
To_StdUlogicVector
"1100")
i_outs
for decode
wait
TMP;
<=
(D
<=
then
'0')
"1100";
<=
"010000";
elsif
then
"0011";
(RetV)
then
"1101")
i_outs
not
PRED
"0011")
To_Integer
PRED +
=
i_data
(D
elsif
decode
decode
req
then
"1111")
(D
<=
"0011";
<=
"001000";
i_outs
DIFF;
:=
<=
TMP
"000000";
elsif
<=
wait
"1101";
i_outs <= "000000";
else
"000000";
<=
that
use
<=
(D
elsif
then
"0001";
i_outs
turned
if;
end
then
<=
"0111";
<=
"000000";
IDIFF
=
ack
extend
i_outs
"000000";
if;
end
elsif
if
<=
then
else
Q
i_outs
'0')
"1111";
i_outs
<=
done
signal
DC
go
<=
then
"0111")
(extend_ack
if
go
else
(D
elsif
then
"000010";
use
if;
A-89
ieee.
use
clauses
std_logic_1164
all;
for
loadDC
ieee. std_logic_1164_extensions
use
<=
all;
load
for do
wait
"00000";
AC
library
use
<=
all;
Q
63 to
inputs
in
std
ulogic
i_data
in
std
ulogic
i_outs
loadAC
in
std
ulogic
(D
loadAC_ack
out
std
ulogic
huff_outSEL
out
downto
(5 downto
turn
(D
std
ulogic
elsif
(D
std
ulogic
<=
"00100";
decode
out
std
ulogic
all
to
zero
decode_ack
in
std
ulogic
Tdecode
in
setting
ulogic
receive_ack
in
std
ulogic
extend
out
std
ulogic
extend_ack
in
std
ulogic
AC
load
0)
downto
0)
downto
0)
<=
decode
to
<=
<=
Carpenter
arch
of
do
loadAC
(4
(D
then
decode
<=
<=
RS
std
ulogic
vector
signal
std
ulogic
vector
signal
std
ulogic
vector
signal
std
ulogic
vector
signal
std
ulogic
vector
signal
SSSS
std
ulogic
vector
0)
(4 downto 0)
(7 downto 0)
(5 downto 0)
(7 downto 0)
(7 downto 0)
signal
RS
std
ulogic
vector
(7
downto
signal
std
ulogic
vector
(5
downto
(reset,
'0')
"00000";
i_outs
<=
"10000000";
<=
i_data
<=
"000001";
"00000000";
( (clock 'event)
'0'))
'last_value
(D
<=
"10000010";
"01111")
"01101";
<=
SSSS
clock)
if
<=
"10000010";
"0000"
<=
"00"
<=
(D
then
RS(7
RS(3
downto
downto
0);
4);
"01101") then
"00000000") then
Q <= "01100";
i_outs <= "10000010";
=
(SSSS
else
and
<=
"OHIO";
i_outs
=
'1')
and
if
<=
"00001";
i_outs <= "10000010";
start
turn
(D
on
AC
"10000010";
"01100") then
"001111") then
k <= k + "010000";
i_outs <= "10000010";
Q <= "00100";
elsif
then
<=
if;
end
(clock
"00000") then
'ID then
(loadAC
then
"00111";
<=
"10000010";
i_outs
then
<=
then
'0')
if;
end
elsif
begin
i_outs
elsif
process
"10010010";
Tdecode;
<=
R
:
for
else
begin
process
done
"01111";
i_outs
is
data
wait
"00111")
downto
outs
<=
(decode_ack
if
signal
(R
else
sel
then
'1')
if;
"00101";
i_outs
module
elsif
"00101")
<=
end
loadAC
for
"10000010";
(decode_ack
02-JUN-1994
(D
wait
decode
Douglas A.
do
is
"10010010";
"00100";
(D
elsif
std_ulogic
Revised
if
decode
else
loadAC
do
Created
if
then
"00111";
i_outs <= "10000010";
elsif
'0')
if;
(architecture)
clock
<=
ready
i_outs <=
if
do loadAC
of
be
end
out
DESCRIPTION:
"00101";
i_outs
COMPONENT:
(reset
top
else
mempreset
if
then
ready
);
do loadAC;
doloadAC
"10000010";
(decode_ack
if
Eval
with
loop
out
downto
<=
then
done
"000001";
(D
"00100")
elsif
0)
std
preset
<=
out
"00110")
i_outs
RecV
architecture
out
to
<=
out
recSSSS
Author
"00000000";
LoadWEl
to
off
receive
Purpose
<=
"00010") then
"00110";
i_outs <= "10000010";
0)
downto
<=
LoadLDl
mem
preset
elsif
out
0)
LoadWADR2
std_ulogic_vector
preset
zeroes
LoadDIN2
downto
then
"00000110";
"00011") then
Q <= "00010";
i_outs <= "00001110";
elsif
0)
zero
reset
--
"00001")
"00011";
<=
clock
end
(D
elsif
"10000000";
"000001";
if;
end
entity do_loadAC is
port
<=
i_outs
my_packages;
<=
"000001";
i_data <= "00000000";
<=
"11111";
<=
"10000001";
i_outs
end
else
elsif
A-90
if;
(D
"OHIO")
then
go
to
end
<=
k +
<=
"01010";
i_outs
R;
<=
else
<=
"10000010";
rec
if;
end
(D
elsif
if
"01010")
(receive_ack
then
else
recieve
'0')
do
then
"11111";
<=
"10000001";
i_outs
to
go
<=
receive
"00000";
<=
"10000000";
i_outs
<=
"01011";
<=
"10100010";
end
else
end
<=
"01010";
i_outs <= "10000010";
doloadAC_process;
process
wait
<=
Q;
if;
end
(D
elsif
if
if;
if;
end
i_outs
"01011")
(receive_ack
<=
<=
loadAC_ack
then
'1')
i_outs(0);
then
"01001";
<=
"10000010";
<=
huff_outSEL(0)
ack
got
i_outs(l);
i_outs
else
<=
"01011";
i_outs <= "10100010";
end if;
elsif
(D
"01001") then
if (receive_ack
'0')
Q <= "01000";
i_outs <= "10000010";
<=
i_outs(2);
loadWEl
<=
i_outs(3);
idata;
then
go
to
loadWADR2
extend
<=
decode
else
<=
"01001";
i_outs <= "10000010";
end if;
elsif
(D
"01000") then
if (extend_ack
'0') then
Q <= "11000";
i_outs <= "11000010";
Q
<=
loadDIN2
loadLDl
wait
<=
k;
i_outs ( 4 ) ;
wait
<=
receive
<=
extend
i_outs(5);
i_outs ( 6) ;
extend
else
extend
mempreset
<=
<=
recSSSS
ready
"01000";
for
wait
end
do
SSSS;
i_outs ( 7 ) ;
<=
loadAC
arch;
be
to
ready
i_outs <=
(D
elsif
if
"10000010";
if;
end
"11000")
(extend_ack
decode
DESCRIPTION;
(entity)
then
'1')
then
<=
"11001";
i_outs <= "10000010";
COMPONENT:
done
extend
Author
Douglas
Created
02-JUN-1994
A.
Carpenter
Revised
else
<=
"11000";
for
wait
library and
library ieee;
extend
i_outs
(D
"11001")
(extend_ack
<=
Q
complete,
"11000010";
if;
end
elsif
if
<=
then
'0')
use
clauses
use
ieee.
std_logic_1164
use
ieee.
all;
.
all;
then
"11011";
library
extend
use
latch data
i_outs
<=
"10000110";
i_data
<=
Eval;
set
LD1
my_packages;
entity decode
on
port
all;
is
(
inputs
else
<=
"11001";
i_outs <= "10000010";
Q
end
if;
then
"11011")
"11010";
<=
i_outs
"10001110";
elsif
(D
"11010") then
if (k
"111111") then
Q <= "11111";
i_outs <= "10000001";
elsif
(D
<=
clock
in
std
ulogic
reset
in
std
ulogic
decode
in
std
ulogic
decode_ack
out
std
ulogic
value
out
wait
write
data
std_ulogic_vector
(7
downto
0);
nextbit_req
out
std
ulogic
nextbit_ack
in
std
ulogic
nextbit_data
in
std
ulogic
nextbit_err
in
std
ulogic
huff_RADR
out
done
else
<=
<=
std_ulogic_vector
k +
"000001";
"00100";
i_outs
end
<=
"10000010";
(D
0);
downto
out
0);
=
downto 0);
huffvalptr_DOUT
then
then
return
to
huffmin_DOUT
start
downto
huffval_DOUT
if;
"11111")
'0'
if (loadAC
)
Q <= "00000";
elsif
(3
val_RADR
outs
<=
"10000000";
A-91
downto
0]
if
huffmax_DOUT
(15 downto 0)
'0'
std_ulogic_vector
) )
);
<=
decode;
end
(nextbit_ack
wait
elsif
decode
(architecture)
Douglas A'.
Created
02-JUN-1994
module
<=
bit,
"00";
(nextbit_err
<=
Carpenter
'ID
then
at
err
next
bit
decode
(D
of
decode
is
std_ulogic_vector
(3 downto
std_ulogic_vector
(3 downto
i_outs
std_ulogic_vector
(1
downto
std_ulogic_vector
(3 downto
<=
CODE
std_ulogic_vector
(15
i_data
std_ulogic_vector
(7
downto
elsif
std_ulogic_vector
(15 downto
DIFF
std_ulogic_vector
(15
"1111111111111111"]
"001";
(CODE
>
huf fmax_DOUT )
then
<=
"0100";
i_outs <= "00";
<=
i + "001";
i
downto
else
0);
<=
"1111";
i_outs
begin
(D
elsif
decode_process
process
(reset,
clock)
if
begin
'0'
'
0'
) then
"0000";
i_outs <= "00";
i <= "0001";
CODE <= "0000000000000000";
(clock'
elsif
and
(clock
event)
'ID and
(
(clock'
last_value
'0')) then
if (D
"0000") then
if (decode
'1') then
<=
decode was
"0001";
Q
=
) )
<=
"00";
if;
end
(reset
"0100";
<=
"00";
<=
downto
huffMIN
then
"0110")
i_outs
0);
signal
<=
downto
0);
signal
wait
then
0);
signal
(huffmax_DOUT
if
0);
signal
"0010";
<=
"00";
(D
elsif
0);
nextbit
if;
end
then
i_outs
0);
signal
'0')
else
0);
signal
then
"0010")
CODE(0) <= nextbit_data;

got
Q <= "0110";
i_outs <= "00";
0);
signal
(nextbit_ack
if
arch
wait
if;
end
elsif
architecture
"0011";
<=
"10";
i_outs
Revised
then
"0100")
(nextbit_ack
'0')
and
(nextbit_err
then
<=
<=
next
else
decode
if
got
drops
"1000";
i_outs <= "01";
Purpose
signal
(nextbit_err
and
<=
Author
signal
'1')
"0010";
signal
until
i_outs
COMPONENT:
DESCRIPTION:
then
"0101";
<=
"10";
get
next
bit
i_outs
elsif
(nextbit_err
'1')
then
<=
"1000";
<=
outs
"01";
Q
i
to
need
error,
here
signal
some
how
else
<=
nextbit
is
signaled
<=
<=
"00";
"0001";
<=
CODE
<=
"0000";
wait
i_outs
i_outs
<=
"00";
elsif
"0001";
CODE <= "0000000000000000";
(D
elsif
"0001")
then
=
'0')
and
elsif
"0011";
<=
"10";
get
next
<=
outs
<=
here
some
how
'1')
if
then
end
then
err
"01";
error,
need
"0101";
<=
"10";
(D
"0111")
(nextbit_ack
CODE
"1001";
at
<=
then
=
CODE (14
'0')
then
downto
0)
nextbit_data;
to
<=
"0110";
<=
"00";
got
"0111";
<=
"00";
wait
i_outs
"0001";
wait
until
<=
"00";
end
"0011")
if;
(D
"1111")
"1101";
i outs <= "00";
elsif
=
<=
i_outs
if;
(D
next
wait
else
<=
ready
i_outs
elsif
'1')
if;
bit
elsif
(nextbit_err
is
i_outs
else
nextbit
bit,
"00";
(nextbit_err
<=
(nextbit_err
end
<=
next
else
=
(nextbit_ack
i_outs
signal
<=
"1000";
i_outs <= "01";
then
(nextbit_err
got
<=
if;
end
and
drops
<=
if
'1')
"0111";
signal
until
signal
'0'))
<=
for decode
wait
then
else
then
if
'O'D
until
"00";
(D
"0101")
( (nextbit_ack
elsif
"0000000000000000";
<=
wait
if;
end
i_outs
"0100";
ready
i_outs
then
A-92
<=
then
nextbit
bit
(D
elsif
<=
"1101")
huffMIN
<=
then
huffmin_DOUT(15 downto 0);
huffvalptr_DOUT;
Q <= "1100";
i_outs <= "00";
(D
elsif
DIFF
<=
(CODE
then
(D
<=
<=
DIFF (7
then
downto
std_ulogic_vector
0);
downto
0);
end
nextbit_ack
in
std
ulogic
receive;
COMPONENT:
receive
DESCRIPTION:
(architecture)
Douglas A.
Author
Created
then
Carpenter
02-JUN-1994
Revised
then
out
nextbit_err
if;
"1000")
'0')
Q
"0000";
<=
i_outs
"00";
nextbit_req
);
"1011";
<=
"01";
out
(7
nextbit_data
i_outs
(decode
0);
std_ulogic;
else
if
downto
std_ulogic;
(D
in
(7
std_ulogic;
end
out
Vout
"1110")
elsif
receive_ack
std_ulogic_vector
<=
in
SSSS
huffMIN);
"1010";
i_outs <= "00";
elsif
(D
"1010") then
i_data <= huf fval_DOUT;
Q <= "1011";
i_outs <= "01";
elsif
(D
"1011") then
if (decode
'0') then
<=
Q
"0000";
i_outs <= "00";
Q
receive
std_ulogic;
Q <= "1110";
i_outs <= "00";
elsif
in
std_ulogic;
"1100")
reset
std_ulogic;
<=
library and
library ieee;
else
Q <= "1000";
i_outs <= "01";
if;
end
"0000";
i_outs <= "00";
end
if;
end if;
end process decode_process;
D
<=
<=
huff_RADR
val_RADR
value
<=
all;
.all;
my_packages;
receive
arch
all;
of
is
receive
signal
std_ulogic_vector
(2
downto
signal
std_ulogic_vector
(2
downto
signal
outs
std_ulogic_vector
signal
std_ulogic_vector
signal
std_ulogic_vector
receive_process
i_outs ( 1 ) ;
0)
0)
(1 downto 0)
(7 downto 0)
(7 downto 0)
process
(reset,
clock)
(reset
if
'0') then
"000";
i_outs <= "00";
i := "00000000";
v <= "00000000";
(clock'
elsif
(
event) and (clock
'1') and
(clock'
last_value
'0')) then
if (D
"000") then
if (receive
'1') then
wait for do
Q <= "001";
Q
i_data;
<=
end
decode
arch;
COMPONENT:
DESCRIPTION:
receive
(entity)
receive
Author
Douglas A.
Created
Revised
Carpenter
<=
i_outs
02-JUN-1994
"00";
else
<=
"000";
<=
"00";
"00000000";
"00000000";
i_outs
library
use
and
clauses
library ieee;
use
ieee.
use
std_logic_1164
use
:=
<=
if;
end
.all;
(D
"001") then
SSSS) then
"111";
Q
i_outs <= "01";
elsif
if
library
my_packages;
.
all;
i_v
is
receive
port
(
clock
i=
done
v;
else
<=
"011";
<=
"00";
i_outs
inputs
std
(i
<=
entity
downto
begin
i;
variable
<=
<=
std_logic_1164
begin
i_outs(0);
<=
nextbit_reg
architecture
Q;
decode_ack
ieee.
use
use
<=
clauses
use
library
else
use
in
end
elsif
ulogic;
A-93
if;
(D
"011")
then
get
more
0),
if
'0'))
( (nextbit_ack
'0')
and
(nextbit_err
then
<=
"010";
i_outs <= "10";
elsif
(nextbit_err
Q <= "111";
i_outs <= "01";
get
'1')
next
library and
library ieee;
bit
then
use
ieee.
std
use
ieee.
std_logic_1164_extensions. all;
library
use
<=
"Oil";
till
wait
next
(D
all;
is
extend
'00"
port
if;
end
elsif
if
my_packages;
entity
<=
all;
bit
ready
i_outs
clauses
err
else
use
input 5
=
"010")
then
( (nextbit_ack
'1')
and
(nextbit_err
then
clock
in
std
ulogic;
reset
in
std
ulogic;
in
std
ulogic;
extend
Q <= "110";
i_outs <= "00";
(nextbit_err
Q <= "111";
i_outs <= "01";
elsif
got
next
bit
extend
'1')
then
(7
std_ulogic_vector
downto
err
till
wait
next
bit
(7
in
downto
0);
(7
std_ulogic_vector
ack
ulogic
0);
std_ulogic_vector
"010";
std
in
RetV
<=
out
else
ack
out
downto
0)
);
i_outs
"10";
end
extend;
if;
end
(D
elsif
if
<=
"110")
(nextbit_ack
<=
then
=
'0')
"100";
then
got
next
bit
COMPONENT:
extend
DESCRIPTION:
(architecture)
ack
off
i_outs
i := i
Author
<=
"00";
"00000001";
v <= v(6 downto
0) 4 nextbit_data;
elsif
(nextbit_err
'1') then
err
Q <= "111";
i_outs <= "01";
Douglas A.
Created
Carpenter
02-JUN-1994
Revised
library and
library ieee;
--
else
<=
"110";
wait
till
next
bit
use
ieee.
use
ieee.std
use
clauses
std_logic_1164
all;
.all;
ack
i_outs
<=
library
'00";
use
if;
end
(D
"100") then
Q <= "001";
i_outs <= "00";
elsif
(D
"111") then
if (receive
'0') then
Q <= "000";
<=
i_outs
"00";
elsif
package_l
all;
go
to
architecture
check
else
<=
my_packages;
my_packages
"111";
i_outs <= "01";
end if;
extend
arch
of
is
extend
signal
std
ulogic
vector
(2
downto
signal
std
ulogic
vector(2
downto
0)
0)
signal
std
ulogic
vector
(0
downto
0)
signal
i V
std
ulogic
vector (7
downto
0)
signal
Vtl
integer
range
-1024
signal
Vtemp
integer
range
-1024
signal
Vt
signal
Vt2
outs
to
1024;
to 1024;
std
ulogic
vector (7
downto
std
ulogic
vector (7
downto
0)
0)
begin
else
<=
extend_process
"000";
<=
"00";
end
<=
if
process
i_outs(0);
nextbit_req
<=
i_outs(l);
end
<=
(reset,
clock
if
(D
if
"000")
(extend
'0'))
:=
(clock
wait
"00000010";
"001";
<=
"0";
i_outs
(entity)
end
if
Author
Created
Douglas A.
:
if;
(D
"001") then
"00000001") then
Vt <= "00000001";
elsif
(T
"0000010") then
Vt <= "00000010";
elsif
Carpenter
02-JUN-1994
(T
Revised
A-94
'1')
and
then
else
<=
then
'0')
"000";
i_outs <= "0";
arch;
DESCRIPTION:
0);
then
<=
two
extend
downto
'0'
'last_value
COMPONENT:
clock)
<=
i_v;
receive
process
) then
"000";
i_outs <= "0";
two := "00000010";
elsif
( (clock 'event) and
Q;
<=
(reset
receive_process;
receive_ack
Vout
begin
if;
if;
end
end
two
variable
i_outs
for do
extend
(T
"0000011")
"00000100";
elsif
(T
"0000100")
Vt <= "00001000";
elsif
(T
"0000101")
Vt <= "00010000";
elsif
(T
"0000110")
Vt <= "00100000";
elsif
(T
"0000111")
Vt <= "01000000";
elsif
then
then
DESCRIPTION;
(entity)
<=
Vt
Created
then
then
then
Carpenter
Douglas A.
Author
02-JUN-1994
Revised
library and
library ieee;
if;
Q <= "Oil";
i_outs <= "0";
clauses
use
use
ieee.
use
std
all;
end
(D
library
use
"Oil") then
if (V < Vt) then
if (T
"00000000") then
Vt2 <= "11111111";
elsif
(T
"00000001") then
elsif
my_packages;
my_packages
package_l
all;
is
nextbit
entity
port
inputs
Vt2
<=
(T
in
std_ulogic;
reset
in
std_ulogic;
nextbit_req
in
std_ulogic;
nextbit_ack
out
std_ulogic;
nextbit_data
out
std_ulogic;
nextbit_err
out
std_ulogic;
"11111110";
"00000010")
Vt2
"11111100";
elsif
(T
"00000011")
Vt2 <= "11111000";
elsif
(T
"00000100")
elsif
clock
then
then
<=
Vt2
<="11110000";
(T
"00000101")
Vt2 <= "11100000";
elsif
(T
"00000110")
Vt2 <= "11000000";
elsif
(T
"00000111")
Vt2 <= "10000000";
elsif
then
then
<=
in
data
std_ulogic_vector
(7
downto
0)
next_req
out
next
in
std_ulogic;
in
std
ack
then
if;
end
then
end
"010";
<=
"0";
std_ulogic;
ulogic
nextbit;
i_outs
COMPONENT:
DESCRIPTION:
else
i_V
<=
V;
Purpose
Created
02-JUN-1994
signal
downto
To_StdUlogicVector
downto
Vtl;
signal
downto
else
downto
<=
(3
std_ulogic_vector
(3
i_outs
std_ulogic_vector
(2
i_data
std_ulogic;
std_ulogic_vector
(3
nextjoyte
std_ulogic_vector
next_byte2
std_ulogic_vector
(7
next_counter
0)
signal
is
nextbit
std_ulogic_vector
signal
of
0) ;
signal
,
"111") then
if (extend
'0') then
Q <= "000";
i_outs <= "0";
(D
nextbit_arch
0) ;
downto
(Vtemp, 8)
Carpenter
0) ;
signal
module
Douglas A.
architecture
<=
nextbit
Author
Revised
1;
elsif
(architecture)
<=
"111";
i_outs <= "1";
end if;
elsif (D
"010") then
Vtl <= To_Integer (Vt2)
i_outs <= "0";
Q <= "110";
elsif
(D
"110") then
Q <= "100";
i_outs <= "0";
Vtemp <= To_Integer(V)
elsif
(D
"100") then
Q <= "111";
i_outs <= "1";
i_V
nextbit
downto
0)
signal
0)
begin
"111";
<=
"1";
i_outs
if;
end
nextbit_process
<=
if
if;
if;
process
(reset
end
end
process
(reset,
clock)
'0') then
"0000";
i_outs <= "000";
next_counter <= "0000";
(clock'
elsif
event )
and
(clock
(
'1') and
( clock 'last_value
'0')) then
if (D
"0000") then
if (nextbit_req
'1') then
got nextbit
Q <= "0001";
"000";
<=
"0";
i_outs
end
begin
else
<=
extend_process;
<=
Q;
extend_ack
<=
i_outs(0);
request
RetV
end
<=
i_outs
i_V;
extend
COMPONENT;
<=
"000";
else
arch;
<=
outs
"0000";
wait
nextbit
A-95
<=
"000";
no
request,
if;
end
if
"0001")
then
(next_counter
Q <= "0011";
"0000")
if
then
another
get
no
with
i_outs
there
is
no
<=
"000";
current
make
byte,
byte
next
<=
"1010";
go
to
send
back
<=
have data
(D
i_outs
"000";
(err
ready for
not
dropped,
<=
ok
to
ready for
(err
elsif
<=
'0'))
got
drops
ack
zero,
<=
<=
err
"100";
(D
for
wait
"010";
<=
next_counter
next_ack
"0110";
for
then
then
"11111111")
to
go
if
return
<=
nextbyte
bit.
elsif
<=
then
"1011")
=
'0')
(err
'0')
then
ready to
"1100")
then
=
'0')
<=
<=
"1100";
<=
"100";
if;
<=
"0000";
<=
"000";
if;
if;
end
end
get
end
process
then
not
ready
nextbit_process;
<=
Q;
for
there
is
an
<=
"100";
nextbit_ack
"0101";
<=
"000";
<=
error
<=
i_outs(0);
else
<=
i_outs
next
byte
req,
then
"1011";
<=
"001";
(D
i_outs
byte,
"010";
'1')
"1100";
downto
"1011";
<=
"001";
i_outs
so.
(err
(6
next_counter
else
<=
<=
(nextbit_req
end
"000";
do
nextjoyte
i_outs
was
i_outs
<=
else
"0101") then
if (next_ack
'0') and
Q <= "0111";
byte,
then
"1000")
"0000";
i_outs <= "000";
if;
(D
if;
to
<=
get
"000";
"1010";
i_outs
(7)
<=
elsif
else
<=
nextjoyte
else
byte
<=
then
"1010")
i_outs
"0101";
i_outs
to
"100";
"0000";
i_outs <= "000";
"000";
(nextjoyte
<=
<=
(D
Q
wait
"0100")
equal
"000";
(nextbit_req
end
=
<=
<=
if
if;
(D
(D
Q
<=
then
was
<=
elsif
data;
<=
"1000";
drop
i_outs
"00000000")
i_outs
else
<=
<=
next_counter
"000";
<=
then
"1101")
nextjoyte
latch data.
nextjoyte
end
(D
elsif
i_outs
"000";
"1000";
i_outs <= "000";
to
<=
"1100";
i_data
ok
for
if;
end
"0110") then
if (next_ack
'0') then
Q <= "0100";
next
<=
with
if;
elsif
wait
"1010";
i_outs
"0010";
i_outs
end
elsif
"000";
<=
data;
else
go
<=
ok
next_ack
next
<=
elsif
<=
FF,
(D
next_ack,
else
not
next_ack
"1111";
i_outs
(next_byte2
if
then
then
'1')
"1100";
i_outs
another
"010";
if;
elsif
(err
nextbyte
for
drop
i_outs
err, go to wait till

i_outs <= "000";
to
next_ack
end
if
wait
latch data.
<=
Q
not
(D
"0010") then
( (next_ack
'1') and
Q <= "0110";
elsif
end
<=
next_byte2
elsif
"100";
i_outs
if;
<=
(next_ack
if
wait.
req,
to
with
else
end
next_ack
err
"1111") then
'0') then
"1101";
(D
elsif
"0011";
i_outs <= "000";
dropped,
then
if;
end
get
<=
no
drops
"0111";
i_outs
then
'OD
ready to
else
with
then
next_ack
if
<=
"0011") then
if (next_ack
'0') and
Q <= "0010";
byte, do so.
i_outs <= "010";
elsif
(err
'1') then
Q <= "1100";
byte, there is an error
i_outs <= "100";
byte
'0'))
next_ack,
else
next
got
"000";
'1')
"1100";
<=
ack
(err
nextbyte
bit
next
till
wait
<=
(err
elsif
request/err
still
to
go
i_outs
if;
end
elsif
next
i_outs
next
err,
sure
else
in
(D
"0111") then
'1') and
( (next_ack
Q <= "1111";
elsif
byte
that
if;
end
(D
elsif
next_req
not
ready
i_outs ( 1 )
<=
(2);
for
nextbit_err
wait.
A-96
outs
then
0) 4 '0';
"0001";
end
nextbit
DESCRIPTION;
<=
nextbit_data
library IEEE;
arch;
COMPONENT;
DESCRIPTION:
use
IEEE.
use
std_logic_1164
by LL_to_VHDL
at
Tue
May
LogicLib
10:07:38
generator
Parameters
tinst
10:07:38
are:
type
SIMPLE
called:
Specification
to VHDL
type
SIMPLE
MULTIPLEXER
numin
SW
MULTIPLEXER
huf f_acdecsel
name
are:
huf f_acdecsel
name
bus_mask
comp_out
0
NO
16
numin
SW
May
are:
parameters
are:
parameters
Tue
called:
generator
Parameters
tinst
at
Generator
Parameterized
Code
LogicLib
LL_to_VHDL
by
Code
all;
Passed
Passed
all;
1994
IEEE. std_logic_1164. all;

IEEE.std_logic 1164 extensions
Written
1994
(entity)
Written
use
.all;
huff_acdcsell6
library IEEE;
use
(entity)
i_data;
huff_acdcsel
bus_mask
comp_out
is
port
NO
Description
Entity
entity huf f_acdcsel6

IN0
in
std_ulogic_vector
(5
downto
INI
in
std_ulogic_vector
(5
downto
SEL
in
std_ulogic_vector
(0 downto
0)
huff_acdcsel Entity Description
entity huf f_acdcsell6 is
port
0)
IN0
0)
0)
0)
in
std_ulogic_vector
DOUT
(15 downto
out
std_ulogic_vector
(5
downto
0)
INI
in
std_ulogic_vector
(15 downto
);
end
SEL
in
DOUT
out
std_ulogic_vector
huff
acdcsel6;
( 0 downto
0);
std_ulogic_vector
(15
downto
COMPONENT:
huff_acdcsel6
DESCRIPTION:
(architecture)
0)
);
end
huff
huf f_acdcsel6 Architecture
acdcsell6;
architecture
COMPONENT;
huf_acdcsell6
DESCRIPTION;
(architecture)
rtl
Description
huf f_acdcsel6
huf f_acdcsel6_Process
Description
huf f_acdcsell6
of
of
is
begin
huff_acdcsel Architecture
architecture
rtl
is
variable
iaddress
variable
state
process
integer
(IN0, INI, SEL)

range
std_ulogic_vector
to
0);
begin
begin
iaddress
huf f_acdcsell6_Process
variable
iaddress
variable
state
process
integer
(IN0, INI, SEL)

range
std_ulogic_vector
to
1;
when
(15 downto
when
begin
to_Integer
:=
iaddress
case
when
0
1
SEL,0);
when
IN0;
:=
INI;
others
:=
end
=>
INI;
end
<=
process
outputs
state;
huf f_acdcsell6_Process;
rtl ;
iSOJSIPOSENJl:
huff
aedcsel6
A-97
<=
process
rtl;
IN0;
:=
others
:=
INI;
=>
INI;
case;
Assign
DOUT
:=
=>
state
end
:=
case;
Assign
DOUT
=>
state
end
0'
is
state
when
'
=>
state
when
=>
state
iaddress
end
' 0'
is
state
0);
end
to_Integer (
:=
iaddress
case
outputs
state;
huf f_acdcsel6_Process;
1;
(5 downto
SEL,0);
Appendix B State Tables

[Corrtroller
Espresso Results
Sfeate Table
-_
cu
u
CD
-o
o
o
CD
a,'
CD
I
as
QO to
cr
CD
D3 D2 D1 DO
CD
*-
a.
u
CD
-a
o
CO
C3>
CD
a.
as
er
CD
__
CD
_-
Q3 Q2 Q1
and
o
o
Comment
reset state, wait
have start decode,
0 have start, ack is off, goto FindSOI
0 SOI,
wait
0 SOI,
ack
err on
wait
ack went to
0 SOF,
0 SOF, ack
err on
wait
ack went
for start
for ack
1,
wait
1, no
err, goto wait ack
0,
to
goto err state
Fr Header
goto
Fr Header,
wait
Fr Header,
ack
err on
wait
ack went
dec frame,
0 decjrame, ack
err on
wait
ack went
0 FindEOI, wait for ack
0 FindEOI, no err, ack
err on
wait
ack
complete, wait
complete, got c_ack
comp, wait for c_ack
comp, got c
err state, wait
err
0 Unused
B-l
SOF request,
for ack
1.
for ack
goto wait ack
FrHeader, goto
err state
0, goto decjrame
to
for ack
wait
1,
decjrame,
for ack
to
for ack
goto wart ack
goto err state
0, goto FindEOI
FindEOI,
1, goto
ack
goto err state
0, goto
complete
for complete_ack
ack
1, goto
for c
ack
-
c_ack
0, goto
state, got c ack
Unused
for ack
-
for ack
0, goto SOF
goto err state
off
no err, go to wait ack
SOI req,
for ack
for ack to turn
wait
reset state
1, goto 1001
Controller Espresso Input
# 2-bit by 2-bit binary

.i
.0
10
.type
fr
1111111111
.phase
0000
0000
000000
0000
1-1-
0000
000000
1-0-
0001
001100
0001
001100
000100
0000
0001
-00-
0001
-01-
0011
0001
-1
1000
000011
1-
0011
000100
0-
0010
010100
0011
0011
0010
0010
0010
-00-
-01-
0010
010100
0110
000100
1000
000011
0110
1-
0110
000100
0110
0-
0100
011100
0100
011100
0101
000100
0100
0100
0100
0101
0101
0111
0111
0111
-1
-00-
-01-
1000
000011
1-
0101
000100
0-
0111
100100
0111
100100
-1
-00-
-01-
-1
1111
000100
1000
000011
1111
1-
1111
000100
1111
0-
1110
110100
1110
1100
110100
000100
1000
000011
1110
1110
1110
1100
1100
-00-
-01-
-1
10-
1100
000100
1101
000010
1101
1101
000010
1101
1001
000000
000000
1001
1001
1001
0000
000000
1000
1000
000000
1000
1001
000000
1010
0000
000000
1011
0000
000000
end
B-2
Son tiolier
%sp;res:so
# jpeg dscoder
.i
.0
10
Results
controller
#. phase :Llllllllll
.p
30
00001-0-
0001001100
#A0
0001-00-
0001001100
0100000010
1000000011
#A1
#A2
#A3
#A4
1101
0010-1
0001-1
1110-1
11100-
100
0100-1
1000000011
1000000011
0010110000
1001000000
1000000011
#A5
#A6
#A7
#A8
01010-
0010100000
#A9
11001-
0100000100
0111-1
1000000011
00100-
0010010100
11000-
0101000010
#A10
#A11
#A12
#A13
00-1-01-
0011000100
00110-
0010010100
0-10-01-
0110000100
1-
0011000100
0011
1-00
1000000000
1101
1001000000
01-0-00-
0100011100
01001-
0101000100
01101-
0110000100
01100-
0100011100
1110
1100000100
01-1-00-
0111100100
-111-01-
11111-
1111000100
1111000100
11110-
1110110100
0101
0101000100
#A14
#A15
#A16
#A17
#A18
#A19
#A20
#A21
#A22
#A23
#A24
#A25
#A26
#A27
#A28
#A29
B-3
NextByte State;
;$ab_e<
-_
o
re
re
I
er
CD
*-*
re
er
CD
t
QO
CD
J
-
o
o
sr
>
CJ
CD
c=
"E
Q2 Ql
__
J
CD
-1
er
CD
D2 D1
DO
-_
CD
1_
CD
CD
Comment
0 Wait for
next request
1 Got
request, send out to memory a request
wait
err on
got
wait
0 inc
wait
next
err state, wait
err state,
0 Not Used
0 Not Used
0 Not Used
NextByte Espresso
next
for inc
ack
memory req
inc
ack
for inc
no err
ack
for
next
req
.o
returned
for
Input
.phase
fr
111111
000
000
000
000
001
001
001
-00
001
001
001
001
111
010
001
-10
011
000
011
000
010
100
011
011
-1-
-0-
010
010
100
010
000
000
111
111
010
111
000
000
to
next
ack
end
B-4
0, go to 000
next
nextreq
type
0, send
req to return to 0
# 2-b Lt by 2-bit bina

.i
to return to 0
ack returned to
req to
returned
return
to 0
to 0
Neggfyt-e Espresso Results

# NextByte Module
.i
.o
#. phase 111111
P
111010
011000
-011
0-1-1-
#A0
#A1
#A2
#A3
001001
-01-00
111010
010100
-101
011-0.
#A4
#A5
#A6
001001
010100
-001
FindSOI
.i
.o
Espresso
Input
18
16
type
.phase
0000
0000
fr
1111111111111111
0
-1-
0000
0000
001
0000
001
0000
001
10-
0001
00000000
00000000
0000
0000
00000000
0000
0000
00000000
1001
0001
00000001
0001
0010
00000000
00-
0001
0010
00000000
1001
0001
00000001
0011
0000
00000000
-1-
10-
0001
0000
0000
00-
-1-
0001
0000
0000
0011
11111111
0011
0000
00000000
0011
11111111
0010
0010
00000000
0011
0011
0000
00000000
0011
0001
0010
00000000
0011
o-
0011
0000
00000000
0011
o-
0001
0010
00000000
0011
0011
0000
00000000
0011
0001
0010
00000000
0011
0011
0000
00000000
0011
0001
0010
00000000
00000000
0011
0011
0000
0011
0001
0010
00000000
0000
00000000
0011
0011
0011
0001
0010
00000000
0011
0000
00000000
0001
0010
00000000
0011
-0
0011
-0
0011
0011
0000
00000000
0011
0001
0010
00000000
00-
0010
0010
00000000
1001
0001
00000001
10-
0110
0000
00000000
0010
0010
-1-
0010
0110
11011000
0110
0000
00000000
0110
11011000
1110
0100
00000000
B-5
0110
0110
0000
0110
0001
0010
00000000
0110
1-
0110
0000
00000000
0110
1-
0110
0000
00000000
0110
0001
0010
00000000
00000000
0110
00000000
0001
0010
0110
0110
0000
00000000
0110
0001
0010
00000000
0110
0110
0000
00000000
0110
0001
0010
00000000
0110
0110
0000
00000000
0110
0001
0010
00000000
0110
0000
00000000
0001
0010
00000000
0110
-0
0110
-0
0110
0110
0000
00000000
0110
0001
0010
00000000
1110
000
0000
0000
00000000
1110
1110
0100
00000000
1110
0100
00000000
1110
0100
00000000
1110
1110
-1-
1001
1001
0001
00000001
1001
1011
0000
00000000
1011
1011
0000
00000000
1011
1111
1000
00000000
1111
000
0000
0000
00000000
1111
1111
1000
00000000
1111
1000
00000000
1111
1000
00000000
0100
0000
0000
00000000
0101
0000
0000
00000000
0111
0000
0000
00000000
1111
1111
-1-
1000
0000
0000
00000000
1010
0000
0000
00000000
1100
0000
0000
00000000
1101
0000
0000
00000000
end
Esprfes so
FindSOI
.i
.o
18
16
#. phase
.p
Results
1111111111111111
36
10
0110
0001001000000000
0011
111111110
0010001000000000
0011
0001001000000000
000-001
1-
1001000100000001
000-001
00-
0001001000000000
0001001000000000
0001001000000000
0001001000000000
0011
0011
0011
0011
0010
0
0
0
0
0001001000000000
00-
0010001000000000
B-6
0011
0001
0001001000000000
00-
0001001000000000
0011
0-0
0001001000000000
0011
00
0001001000000000
0110
110110-00
1110010000000000
0110
0110000000000000
-Oil
0011000000000000
00-1
10-
0011000000000000
1001
1001000100000001
10-1
1011000000000000
0110
0110
10
0001001000000000
0001001000000000
0001001000000000
0001001000000000
0001001000000000
0001001000000000
0110
0110
0110
0110
0-10
10-
0110000000000000
0001
1-
1001000100000001
1110-1
1110010000000000
11101
1110010000000000
11101
1110010000000000
1111-1
1111100000000000
11111
1111
1111100000000000
1111100000000000
1011
1111100000000000
0010
1-
1001000100000001
FindSOF Espresso
.i
.o
Input
21
11
type
fr
11111111111
.phase
0000
0000
1
-0-
0000
0000
010
0000
010
0000
010
00
00
0000
00
0000
00
1001
0001
00
00-
0001
0010
00
00-
0001
0010
00
1001
0001
00
10-
0011
0000
00
-1-
0001
0000
0000
-1-
0001
0000
0000
1000
10-
0001
0000
0011
11111111
0011
0000
00
0011
11111111
0010
0010
00
0011
0011
0000
00
0011
0001
0010
00
0011
0-
0011
0000
00
0011
0-
0001
0010
00
0011
0011
0000
00
0011
0001
0010
00
0011
0011
0000
00
0011
0001
0010
00
0011
0011
0000
00
0011
0001
0010
00
0011
0011
0000
00
0011
0001
0010
00
B-7
0011
-0
0011
0000
00
0011
-0
0001
0010
00
0011
0011
0000
00
0011
0001
0010
00
0010
oo
0010
0010
00
0010
-i
1001
1001
00
0010
io
0110
0000
00
0110
11011011
0110
0000
00
0110
11011011
0111
0000
10
0110
0110
0000
00
0110
0100
0000
00
0110
0-
0110
0000
00
0110
0-
0100
0000
00
0110
0110
0000
00
0110
0100
0000
00
00
0110
0110
0000
ono
0100
0000
00
0110
0000
00
00
ono
0110
0100
0000
0110
0110
0000
00
0110
0100
0000
00
0110
-0
0110
0000
00
0110
-0
0100
0000
00
0110
0110
0000
00
0110
0100
0000
00
0100
11000100
0100
0000
00
0100
11000100
1100
0000
01
0100
0100
0000
00
0100
1010
0000
00
0100
1-
0100
0000
00
0100
1-
1010
0000
00
00
0100
0100
0000
0100
1010
0000
00
0100
0000
00
0100
0100
1010
0000
00
0100
0100
0000
00
0100
1010
0000
00
00
0100
0100
0000
0100
1010
0000
00
0100
-0
0100
0000
00
0100
-0
1010
0000
00
0100
0100
0000
00
0100
1010
0000
00
0111
0-0
0111
0000
10
0111
1-0
1111
0000
00
0111
1001
0001
00
1111
1111
0000
00
1111
0001
0010
00
1100
00
1100
0000
01
1100
10
1110
0000
00
1100
1001
0001
00
1110
1-
1110
0000
00
1110
0-
0001
0010
00
B-8
1010
11000000
1-
1010
0000
00
1010
11000000
0-
1011
0100
00
1010
i-
1010
0000
00
1010
0-
0001
0010
00
1010
1-
l-
1010
0000
00
1010
1-
0-
0001
0010
00
1010
l-
1010
0000
00
1010
0-
0001
0010
00
1010
1-
1010
0000
00
1010
0-
0001
0010
00
1010
1-
1010
0000
00
1010
0-
0001
0010
00
1010
1-
1010
0000
00
1010
0-
0001
0010
00
1-
1010
0000
00
0-
0001
0010
00
1010
-0
1010
-0
1010
1-
1010
0000
00
1010
0-
0001
0010
00
1011
000
0000
0000
00
1011
--1
1011
0100
00
1011
0100
00
1011
0100
00
1011
1011
-1-
1001
0-
1001
0001
00
1001
1-
1000
0000
00
1000
1-
1000
0000
00
1000
0-
1101
0000
00
1101
000
0000
0000
00
1101
--1
1101
1000
00
1101
1000
00
1101
1000
00
1101
1101
.
-1-
end
FindSOF Espresso Results

21
.i
11
.o
#.
11111111111
phase
.p
61
0011
111111110
00100010000
0110
110110110
00110000010
010
110001000
11000000001
1010
110 000000
10110100000
-000010
10000000000
000-010
00
000-010
0-10
10
0010
00
1
1010
1
1010
0
1010
0
11000000001
01100000000
00100010000
10
11-0
1010
10010001100
00
1100
1010
00010010000
11100000000
00010010000
00010010000
00010010000
00010010000
10
00010010000
B-9
1010
00010010000
1-0
1010
1010
0110
00010010000
00010010000
00100000000
1000
01010000000
1001
00010001100
oon
00
0011
00010010000
00010010000
0-0
0011
00010010000
00010010000
00010010000
00010010000
00
00010010000
00010010000
010
01000000000
00-1
10
-0
0011
0011
0011
0011
0011
00110000000
0-
1110
010
010
010
00010010000
10100000000
10100000000
10100000000
0
1111
00010010000
010
10
10100000000
010
1-0
10100000000
010
00
10100000000
10100000000
10100000000
010
010
1010
10100000000
01-1
0-0
01110000010
1110
1-
11100000000
1100
10010001100
0-01
00
00010010000
0110
01000000000
0011
00110000000
01-1
1-0
0010
11110000000
10011001100
10111
10110100000
10111
10110100000
1011-1
10110100000
1
1111
-101
11011000000
11011000000
-1011
11011000000
-101-1
0-01
10010001100
10000000000
100
1
01-1
.
11110000000
10010001100
Fr__Header
.i
.o
Espresso
Input
20
15
.type
.phase
fr
111111111111111
# o
000000
000000
0
-0-
000000
000000
Oil
10
B-10
000000
000000000
000000
000000000
000000
000000000
000000
000000000
000000
Oil
-1
100000
001100000
000000
Oil
00
000001
100000000
000001
00
000001
100000000
000001
-1
100000
001100000
000001
10
000011
000000000
000011
1-
000011
000000000
000011
0-
000010
000000000
#1
#3
#2
000010
000110
100000000
100000
001100000
000010
100000
001100000
000010
100000
001100000
000010
100000
001100000
000010
100000
001100000
000010
100000
001100000
000010
100000
001100000
100000
001100000
00000000
000010
000010
#6
000110
00
000110
100000000
000110
-1
100000
001100000
000110
10
000100
000000000
000100
000100
000000000
000100
000101
000000000
000111
100000000
100000
001100000
100000
001100000
000101
100000
001100000
000101
100000
001100000
000101
100000
001100000
000101
100000
001100000
#4
#5
000101
00001011
000101
0-
000101
000101
1
000101
100000
001100000
100000
001100000
#7
000111
00
000111
100000000
000111
-1
100000
001100000
000111
10
001111
000000000
001111
1-
001111
000000000
001111
0-
001101
000000000
#15
#13
001100
100000000
001101
100000
001100000
001101
100000
001100000
001101
100000
001100000
001101
100000
001100000
001101
100000
001100000
001101
100000
001100000
001101
00001000
B-ll
001101
100000
001100000
001101
100000
001100000
#12
001100
00
001100
100000000
001100
-1
100000
001100000
001100
10
001110
000000000
001110
1-
001110
000000000
001110
0-
001010
000000001
001010
001011
000000000
#11
001011
001001
100000000
#14
#10
#9
001001
00
001001
100000000
001001
-1
100000
001100000
001001
10
001000
000000000
001000
001000
000000000
001000
011000
000000010
010000
000000000
010001
000001000
010011
000001000
010010
100000000
#8
#24
011000
#16
010000
#17
010001
#19
010011
#18
010010
00
010010
100000000
010010
-1
100000
001100000
010010
10
010110
000000000
010110
010110
100000000
010110
010100
000000001
010101
000000000
010111
100000000
#22
#20
010100
#21
010101
#23
010111
00
010111
100000000
010111
-1
100000
001100000
010111
10
011111
000000000
#31
B-12
011111
011111
1-
0-
011111
000000000
011101
000000010
011100
000000000
011110
000000100
011010
000000100
011011
100000000
011011
100000000
100000
001100000
000000000
#29
011101
#28
011100
#30
011110
#26
011010
#27
011011
011011
011011
#25
011001
011001
00
-1
10
011001
10-
#57
111001
111001
111001
111001
111001
111001
00000001
011001
000000000
111001
000000000
111011
100000000
001100000
001100000
001100000
001100000
001100000
001100000
001100000
001100000
100000
100000
100000
100000
100000
100000
100000
100000
111001
111001
111001
#59
111011
00
111011
-1
111011
10
111011
100000
111010
100000000
001100000
000000000
111010
111110
000000000
000000000
111100
100000000
001100000
001100000
001100000
001100000
001100000
001100000
001100000
001100000
#58
111010
111010
10-
#62
111110
00000001
111110
100000
111110
100000
111110
111110
100000
100000
100000
100000
111110
111110
111110
100000
111110
100000
#60
111100
00
111100
-1
111100
10
111100
100000
111101
B-13
100000000
001100000
000000000
#61
111101
1-
mioi
0o-
111101
000000000
min
ooooooooo
lomi
101111
ioooooooo
iooooo
oonooooo
100000
iooooo
001100000
100000
iooooo
001100000
100000
iooooo
001100000
iooooo
IOOOOO
oonooooo
iooooo
100000
oonooooo
-l
iooooo
IOOOOO
oonooooo
100000
IOOOOO
001100000
101111
IOOOOOOOO
100000
IOOOOO
001100000
101101
ooooooooo
101101
OOOOOOOOO
101100
ooooooooo
101110
010000000
100000
IOOOOO
001100000
100000
IOOOOO
001100000
100000
IOOOOO
001100000
100000
IOOOOO
001100000
100000
IOOOOO
001100000
IOOOOO
100000
001100000
-1
100000
IOOOOO
001100000
100000
IOOOOO
001100000
000000
ooooooooo
101110
010000000
101110
010000000
101110
010000000
100000
IOOOOO
001100000
100001
ooooooooo
100001
ooooooooo
100011
000010000
000000
ooooooooo
100011
000010000
100011
000010000
100011
000010000
_-..-
#63
min
oooioooi
00010001
mm
111111
1-
111111
111111
mm
min
min
111111
#47
101111
00
101111
-1
101111
10
#45
101101
1-
101101
0-
#44
101100
00000000
101100
101100
1-
101100
1
101100
1
101100
1
101100
101100
101100
#46
101110
ooo
101110
101110
101110
-1-
#32
iooooo
100000
#33
100001
100001
--
#35
100011
ooo
100011
100011
100011
-i-
--
end
Fr Header Espresso Results
B-14
.i
.o
20
15
#. phase
.p
111111111111111
120
001101
00001000-
001100100000000
-00010
00000000-
000110100000000
101-00
00000000-
101110010000000
0101
00001011-
000111100000000
11-110
00000001-
111100100000000
11-111
00010001-
101111100000000
11-00
00000001-
111011100000000
00000-01100
000001100000000
00000-011-1
001100
00
0000-1
10
011111
0
100000001100000
00-001
00
000001100000000
101-11
00
000010100000000
11-011
00
000001100000000
0011-0
10
001110000000000
001110
001010000000001
00-011
000001000000000
-01000
0-101
001100100000000
000011000000000
010000000000010
010000000000010
0
000001000000000
-10-10
10
000110000000000
01-01
00
000010100000000
-0011
00
000010100000000
01111
010010000000000
-101-1
00
000011100000000
-10110
010100000000001
11-101
000010000000000
10
001011000000000
111
010000100000000
011010
10-
00-101
-11001
100000000000000
001001000000000
011001
00111
100000001100000
001110000000000
001000000000000
0-10-1
1-
001101
001100
100000001100000
100000001100000
-10110
010110100000000
0100
000001000000000
11-0-0
000100000000000
1101
000001000000000
000010000000000
0-0011
-0-111
000001000000000
010000100000000
-10011
001100000000000
OHIO
1100
00
111100100000000
11-10
10
111101000000000
000010100000000
-10101
-11011
100000001100000
100000001100000
-00010
100000001100000
-00010
100000001100000
-00010
00-001
100000001100000
1
1
-00010
-00010
-00010
100000001100000
-00010
100000001100000
100000001100000
100000001100000
B-15
0111-0
011010000000100
1-
-00010
00-101
00-101
100000001100000
00-101
00-101
100000001100000
100000001100000
100000001100000
100000001100000
11-101
010001000000000
00-101
00-101
100000001100000
100000001100000
0-1111
001101000000000
-10010
100000001100000
101-00
101-00
100000001100000
101-00
100000001100000
101-00
100000001100000
100000001100000
-00101
101-00
101-00
100000001100000
100000001100000
101-00
100000001100000
100000001100000
0-1010
001011000000000
1-
101-00
101-11
100000001100000
100000001100000
001001100000000
-01011
Oil
000100000000000
11-111
100000001100000
11-110
100000001100000
001000000000000
-010-0
1-0-01
1011
100011000010000
101100000000000
000010000000000
-100-1
0100
000100000000000
000001000001000
-1000
10101
101110010000000
1-0-0
10101
100001000000000
101110010000000
1010-1
101110010000000
0i
010000000000000
000101000000000
-1010
0111
100000001100000
11-01
111010000000000
-0011
100000001100000
1
11-00
100000001100000
11-00
100000001100000
100000001100000
11-00
100000001100000
11-00
11-00
0-
100000001100000
11-00
100000001100000
100000001100000
11-00
11
100000001100000
11-00
100000001100000
00
100000001100000
11-11
100000001100000
11-11
100000001100000
11-11
100000001100000
11-11
11-11
0-
11-11
11-11
100000001100000
100000001100000
010000000000000
010
100011000010000
1-0-1-1
1-0-1
100000001100000
100011000010000
B-16
1-0-11
1-0
100011000010000
100000001100000
1101
101100000000000
11-0-0
111010000000000
dec_|rame Espresso Input

.i
.o
10
7
fr
type
1111111
.phase
000
000
-1-
000
0000
000
0000
000
0000
000
000
100
1-0-
000
0000
000
100
1-
111
0100
000
100
0-0-
001
0010
001
0-0-
001
0010
001
1-
111
0100
001
1-0-
Oil
0000
Oil
-1-0
Oil
0000
Oil
111
0100
Oil
-0-0
010
0001
010
-0-0
010
0001
010
111
0100
010
-1-0
110
1000
110
110
-1-
110
1000
110
1000
110
110
1000
110
000
000
0000
111
111
0100
111
0100
111
-1-
111
111
0100
111
000
000
0000
end
dec frame Espresso Results

:
.i
.o
10
7
#. phase 1111111
.p
15
1
011
1
-01
0110000
-0-1000-0-
-0-100
0110000
1-
-010-0-
0010010
1110100
0010010
01
0-0
010
1-0
1101000
1-
1110100
-01
1-0
1-0-1
0100001
1101000
1101000
B-17
1-01
1101000
1-11
1110100
1-1-1
1110100
1-11
1110100
0i
.
moioo
FindEOI Espresso
.i
.o
Input
18
16
type
.phase
0000
0000
fr
1111111111111111
0000
0000
00000000
0000
0000
00000000
0000
0000
00000000
0000
0000
00000000
1001
0001
00000111
00-
0001
0010
00000000
00-
0001
0010
00000000
1001
0001
00000111
10-
0011
0000
00000000
1
-0-
0000
0000
110
0000
110
0000
110
10-1-
0001
0001
-1-
0001
0011
11111111
0011
0000
00000000
0011
11111111
0010
0010
00000000
0011
0011
0000
00000000
0011
0001
0010
00000000
0011
0-
0011
0000
00000000
0011
o-
0001
0010
00000000
0011
0000
00000000
00000000
0011
0001
0010
0011
0011
0000
00000000
0011
0001
0010
00000000
0011
0011
0011
0000
00000000
0011
0001
0010
00000000
0011
0000
00000000
0001
0010
00000000
0011
0000
00000000
0001
0010
00000000
0011
0011
--0
0011
-0
0011
-0
0011
0011
0000
00000000
0011
0001
0010
00000000
00-
0010
0010
00000000
1001
0001
00000111
10-
0110
0000
00000000
0010
0010
-1-
0010
0110
11011001
0110
0000
00000000
0110
11011001
1110
0100
00000000
0110
0110
0000
00000000
0110
0001
0010
00000000
0110
1_
0110
0000
00000000
0110
1_
0110
0000
00000000
0001
0010
00000000
0110
0110
0001
0010
00000000
0110
0110
0000
00000000
0110
0001
0010
00000000
0110
0110
0000
00000000
0110
0001
0010
00000000
B-18
0110
0110
OOOO
00000000
0110
0001
0010
00000000
ono
-o
0110
0000
00000000
0110
-0
0001
0010
00000000
0110
0110
0000
00000000
0110
0001
0010
00000000
1110
000
0000
0000
00000000
1110
1110
0100
00000000
1110
0100
00000000
1110
0100
00000000
1110
1110
-1-
1001
1001
0001
00000111
1001
1011
0000
00000000
1011
1011
0000
00000000
1011
1111
1000
00000000
1111
000
0000
0000
00000000
1111
1111
1000
00000000
1111
1000
00000000
1111
1000
00000000
0100
0000
0000
00000000
0101
0000
0000
00000000
0111
0000
0000
00000000
1000
0000
0000
00000000
1010
0000
0000
00000000
1100
0000
0000
00000000
1101
0000
0000
00000000
1111
1111
-1-
end
FindEOI
.i
.o
Espresso
Results
18
16
#. phase 1111111111111111
.p
36
0110
10
0001001000000000
0011
111111110
0010001000000000
1-
1001000100000001
000-110
0
0001001000000000
00-
0001001000000000
0001001000000000
0001001000000000
0001001000000000
0001001000000000
0010
00-
0010001000000000
0011
00
0001001000000000
0001
00-
0001001000000000
0011
0-0
0001001000000000
0011
000-110
0011
0011
0011
0011
0011
0
0
0
0
0001001000000000
00
0110
110110-10
1110010000000000
0110
0110000000000000
0011000000000000
-Oil
00-1
10-
0011000000000000
1001
1001000100000111
10-1
1011000000000000
B-19
0110
0110
00
0001001000000000
0001001000000000
0001001000000000
0110
0110
0110
0110
0001001000000000
0001001000000000
0001001000000000
0-10
10-
11101
0001
0110000000000000
1110010000000000
1-
1001000100000111
1110-1
1110010000000000
11101
1110010000000000
11111
1111-1
11111
1111100000000000
1111100000000000
1111100000000000
1011
1111100000000000
0010
1-
1001000100000111
FindSOS
# find
.i
.o
Espresso
start
of
Input
scan
19
11
fr
.type
11111111111
.phase
0000
0000
0000
0000
0011
0011
0011
0011
0011
0011
0011
0011
0011
0011
0011
0011
0011
0011
0011
0011
0011
0010
0010
0010
0110
0000000
0000
0000000
1001
0001100
00-
0001
0010000
0001
0010000
1001
0001100
-1-
00-1-
10-
0011
0000000
11111111
0011
0000000
11111111
0010
0010000
0011
0000000
0001
0011
0000
0001
0001
10-
0001
0010000
0-
0011
0000000
0-
0001
0010000
0011
0000000
0001
0010000
0011
0000000
0001
0010000
0011
0000000
0001
0010000
0011
0000000
0001
0010000
0011
0000000
0010000
-0
0001
0011
0000000
0001
0010000
00-
0010
0010000
1001
0001100
0110
0000000
0110
0000000
-0
-1-
10-
11011011
B-20
0110
11011011
0111
0000010
0110
0110
0000000
0110
0100
0000000
0110
0-
0110
0000000
0110
0-
0100
0000000
0110
0110
0000000
0110
0100
0000000
0110
0000000
0100
0000000
0110
0000000
0100
0000000
0110
0110
0000000
0110
0100
0000000
0110
0110
0110
0110
0110
-0
0110
0000000
0110
-0
0100
0000000
0110
0110
0000000
0100
0000000
0110
OlOO
11000100
0100
0000000
0100
11000100
1100
0000001
0100
0100
0000000
0100
1010
0000000
0100
1-
0100
0000000
0100
1-
1010
0000000
0100
0100
0000000
0100
1010
0000000
0100
0100
0000000
0100
1010
0000000
0100
0100
0000000
0100
1010
0000000
0100
0100
0000000
0100
1010
0000000
0100
-0
0100
0000000
0100
-0
1010
0000000
0100
0100
0000000
0100
1010
0000000
0111
0-0
0111
0000010
0111
1-0
1111
0000000
0111
1001
0001100
1111
1111
0000000
1111
0001
0010000
1100
00
1100
0000001
1100
10
1110
0000000
1100
1001
0001100
1110
1-
1110
0000000
1110
0-
0001
0010000
1010
11011010
1010
0000000
1010
11011010
1011
1000000
1010
1010
0000000
1010
0001
0010000
1010
0-
1010
0000000
1010
0-
0010000
,-
0001
1010
1010
0000000
1010
0001
0010000
1010
1010
0000000
B-21
1010
1010
1010
1010
1010
1010
1010
1010
1010
0001
0010000
1010
0000000
0001
0010000
1010
0000000
0001
0010000
-0
1010
0000000
-0
0001
0010000
1010
0000000
0001
0010000
1011
0000
0000000
1011
1011
1000000
1001
0001100
1000
0000000
1000
0000000
1101
0100000
1001
1001
1000
1000
1101
0000
0000000
1101
1101
0100000
end
FindSOS
# find
start
of
Results
scan
19
.i
11
.o
#.
Espresso
11111111111
phase
.p
56
0011-111111110
00100010000
010110001000
11000000001
0110-110110110
00110000010
10111000000
1010-110110100
00
1100
00
000-1
00010010000
10
11-0
10
0-10
11000000001
11100000000
01100000000
1010
0-0
00010010000
1010
10
00010010000
00010010000
00010010000
00010010000
00010010000
1010-0
00010010000
0110
00100000000
1010
10
00010010000
1010
0
1010
1
1010
1010
00100010000
00
0010
1001
00010001100
1000
01010100000
0011
00
00010010000
0011
0-0
00010010000
00010010000
00010010000
0011
0
0011
0011
0011-0
010
0011
00010010000
00010010000
01000000000
00010010000
B-22
00010010000
00-1
0011
10
00110000000
1010
10100000000
1111
00010010000
1110
0-
00010010000
01-1
0-0
01110000010
010
010
0100
10100000000
10100000000
10100000000
1110
1-
moooooooo
010
10
10100000000
010
1-0
10100000000
010
00
10100000000
10100000000
Oio
010
10100000000
1100
000-1
0-01
10010001100
00
00010010000
0110
01000000000
0011
00110000000
01-1
1-0
10111
1
10010001100
1
1111
11110000000
11010100000
-1011
100
10000000000
0-01
01-1
10010001100
1
10010001100
loadq
Espresso
# load q
.i
.o
11110000000
10111000000
0010
10010001100
table
Input
controller
24
12
type
fr
111111111111
.phase
00000
00000
0000000
00000
-1-0
00000
0000000
00000
11111
1000000
00000
-0-0
00001
0000010
-0-0
00001
0000010
11111
1000000
-1-0
00011
0000000
-1
00011
0000000
-0
00010
0000000
00000000
00110
0000010
11111
1000000
1-
11111
1000000
11111
1000000
11111
1000000
urn
ioooooo
11111
1000000
-i
urn
ioooooo
11111
IOOOOOO
00001
00001
00001
00011
00011
00010
00010
00010
00010
00010
oooio
00010
oooio
00010
B-23
00110
00110
0000010
11111
IOOOOOO
00100
0000000
00100
00100
0000000
00100
00101
0000000
00111
0000010
-0-0
00110
00110
-1-0
00101
01000011
00101
11111
IOOOOOO
00101
11111
IOOOOOO
00101
11111
IOOOOOO
00101
11111
IOOOOOO
00101
11111
IOOOOOO
00101
11111
IOOOOOO
00101
11111
IOOOOOO
00101
11111
IOOOOOO
00111
0000010
11111
IOOOOOO
01111
0000000
01111
01111
0000000
01111
01101
0000000
00111
-0-0
00111
00111
-1-0
01100
0010000
01101
11111
IOOOOOO
01101
11111
IOOOOOO
01101
11111
IOOOOOO
01101
11111
IOOOOOO
01101
11111
IOOOOOO
01101
11111
IOOOOOO
01101
11111
IOOOOOO
01101
11111
IOOOOOO
01101
00000000
01100
000000
01000
0000010
01100
01100
0010000
01100
1-
01100
0010000
01100
01100
0010000
01100
01100
0010000
01100
01100
0010000
01100
0010000
01100
01000
-0-0
01000
0000010
01000
11111
IOOOOOO
01000
-1-0
01001
0000000
01001
0000000
01011
0000100
01001
01001
-1
-0
01011
0-
01010
0000001
01011
1-
01011
0000000
01010
0-
01010
0000001
01010
1-
OHIO
0000000
OHIO
1-
OHIO
0000000
OHIO
0-
11110
0001000
11110
11110
0001000
11110
11100
0000000
B-24
11100
11100
11000
11000
11000
11000
11000
11000
11000
11100
0000000
11000
0000000
000000
10000
0100000
01000
0000010
1-
01000
0000010
01000
0000010
01000
0000010
-1
01000
0000010
01000
0000010
10000
00000
0000000
10000
10000
0100000
11111
11111
IOOOOOO
inn
ooooo
ooooooo
end
Espresso
loadq
# load q
table
controller
24
.i
12
.o
#.
Results
111111111111
phase
60
.p
-1101
00000000
000000010000
010
00000000
001000000010
-0101
01000011
000100000010
-0
01100-000000
110
010000000010
000000
100000100000
0000-1
0-0
000010000010
01000
0-0
010000000010
-0001
0-0
000010000010
-011
0-0
000100000010
01100
011000010000
01100
01100
011000010000
011000010000
01100
011000010000
01100
011000010000
011000010000
01100-1
010100000000
0-111
010010000000
-10-1
000010000000
-010
000010000000
0-111
010010000000
0100
OHIO
111100001000
01-10
011100000000
-101
010000000001
010000000010
110
010000000010
110
110
-1101
010000000010
110
-1001
010000000010
110
10
010000000010
110
010000000010
100000100000
010110000100
0
1
100111000000
B-25
0000-1
111111000000
-01
000110000000
0-
-0101
011-1
110101000000
011000000000
1-1-0
111000000000
101
110111000000
101
1-
110111000000
01000
110
111111000000
111100001000
1
-0010
-0010
111011000000
111011000000
-0010
111011000000
-0010
111011000000
-0010
111011000000
1
111011000000
1-
111011000000
-0010
-0010
-0010
111011000000
01
000100000000
001000000000
-01
1-10
110000000000
-0001
-Oil
111111000000
110111000000
1
101
101
101
110111000000
101
110111000000
101
1
110111000000
110111000000
11
111111000000
huff_lenloader Espresso
# huffman data length

.i
.o
110111000000
Input
and
type
loader
33
13
type
.phase
fr
1111111111111
00000
00000
00000000
00000
110
00000
00000000
00000
1-1
11111
01000000
00000
100
00001
00000001
00001
-00
00001
00000001
00001
11111
01000000
00001
-10
00011
00000000
00011
00000000
00010
00100000
00010
00110
00001000
00110
00100
00001000
00011
00011
-1-
-0-
00100
0000000000000000
11111
01000000
00100
00101
00010000
00100
00101
00010000
00100
00101
00010000
00100
00101
00010000
B-26
00100
00101
00010000
00100
00101
00010000
00100
00101
00010000
00100
00101
00010000
00100
00101
00010000
ooioo
00101
00010000
00100
00101
00010000
00100
00101
00010000
00100
00101
00010000
00100
00101
00010000
00101
00010000
00101
00010000
00100
_1
00100
00101
00101
00010000
00101
00111
00000000
00111
00111
00000000
00111
0000000000000000
11111
01000000
00111
01111
00010000
00111
1_
01111
00010000
00111
01111
00010000
00111
01111
00010000
00111
01111
00010000
00111
01111
00010000
00111
01111
00010000
00111
01111
00010000
00111
01111
00010000
00111
01111
00010000
00111
01111
00010000
00111
01111
00010000
00111
01111
00010000
00111
01111
00010000
00111
__
01111
00010000
00111
01111
00010000
01111
01111
00010000
01111
01101
00000000
01101
00000000
01101
0000000000000000
11111
01000000
01101
01100
00000001
01101
1_
01100
00000001
01101
01100
00000001
01101
01100
00000001
01101
01100
00000001
01101
01100
00000001
01101
01100
00000001
01101
01100
00000001
01101
01100
00000001
01101
01100
00000001
01101
01100
00000001
01101
01100
00000001
01101
01100
00000001
01101
01100
00000001
01101
01101
_1
01100
00000001
01101
01100
00000001
01100
-00
01100
00000001
01100
11111
01000000
01100
-10
OHIO
00000000
B-27
OHIO
OHIO
OHIO
OHIO
OHIO
OHIO
-1_
-0-
0000
-0-
-0-
-0-
-1
-0-
01010
01011
01001
OHIO
OOOOOOOO
01010
00000100
11111
01000000
11111
01000000
11111
01000000
11111
01000000
01011
00000010
01001
00010010
01001
00010010
01001
0000000000000000
11111
01000000
01001
01000
10000000
01001
1-
01000
10000000
01000
10000000
01000
10000000
01000
10000000
01000
10000000
01000
10000000
01000
10000000
01000
10000000
01000
10000000
01000
10000000
01000
10000000
01000
10000000
01000
10000000
01001
01001
01001
01001
01001
01001
01001
01001
01001
01001
01001
01001
01001
-1
01000
10000000
01001
01000
10000000
01000
10000000
00000
OOOOOOOO
11111
01000000
00000
OOOOOOOO
01000
01000
11111
11111
end
Buff lenloader Espresso Output
# huffman data length

.i
.o
type
loader
13
#. phase
.p
and
33
1111111111111
92
-0111
00000000000000000
1111101000000
0000000000000000-
1111101000000
00000000000000000
1111101000000
-0100
-1-01
-1110-0-0000
0101000000100
-000-100
0000100000001
-0011-0
0000000100000
-0001-00
0000100000001
-1001
10
0100010000000
-1001
1-0
0100010000000
10
0100010000000
0100010000000
0100010000000
0100010000000
-1001
-1001
-1001
-1001
B-28
-1001
-1001
-1001
-1001
-1001
-1001
-1001
-1001
-1001
-1001
0100010000000
0100010000000
0100010000000
0100010000000
0100010000000
0100010000000
0100010000000
0100010000000
0100010000000
0100010000000
-10001
0100010000000
-1100-00
0110000000001
-00-1-1
0001100000000
0001000000000
-001
-1110-0
-1110-0
1111101000000
1111101000000
1111101000000
-1110-01
1111101000000
-1110-0-1
-0100
-0100
-010
0010100010000
0010100010000
0010100010000
0010100010000
-0100
-0100
0010100010000
-0100
0010100010000
0010100010000
-0100
0010100010000
-0100
0010100010000
-0100
-0100
0010100010000
0010100010000
-0100
0010100010000
1
1
-0100
0010100010000
-0100
-0100
0010100010000
-0100
-010
1-
0010100010000
0010100010000
0010000001000
-0-10
-1101
10
0110000000001
-1101
1-0
0110000000001
-1101
10
0110000000001
0110000000001
0110000000001
0110000000001
0110000000001
0110000000001
0110000000001
0110000000001
0110000000001
0110000000001
0110000000001
0110000000001
0110000000001
0110000000001
-1101
-1101
-1101
-1101
-1101
-1101
-1101
-1101
-1101
-1101
-1101
-1101
-1101
1111101000000
-000-1-1
OH-i
0110100000000
0101100000010
-1010
0_ni
10
0111100010000
0_ni
1-0
0111100010000
0111100010000
0111100010000
0111100010000
0111100010000
0_ni
1
0_ni
1
0_ni
0_ni
B-29
0-111
0111100010000
0111100010000
0111100010000
0111100010000
0111100010000
0111100010000
0111100010000
0111100010000
0111100010000
0111100010000
-10-1
0100100010010
-01-1
0011100000000
0-111
0-111
0-111
0-111
0-111
0-111
0-111
0-111
0-111
0111000000000
-11-0-1
0100100010010
-1011
-0101
-0001
0010100010000
1111101000000
01111
0111100010000
-11001
1111101000000
1111101000000
1
e
hread Espresso Input
#
.i
.o
in huffman data
read
8
9
.type
fr
111111111
.phase
0000
0000
00100
0000
11-0
0000
00100
oooo
mi
10100
0000
10-0
0001
00000
0011
00000
0010
00110
0001
--
0011
0010
0010
0110
0110
-0
0010
00110
-1
1111
10100
0110
00100
0110
00100
0111
00101
-0-
0010
-1-
-0
-1-
-0--
0111
00
0111
00101
oin
mi
10100
0111
-10
0101
00100
0101
_-
0101
-1-
-o-
0101
00100
1101
01100
1101
1-
1101
01100
1101
0-
0000
00100
1111
1-
1111
10100
1111
0-
0000
00100
0000
00100
1000
_-
B-30
1001
1010
0000
00100
0000
00100
1011
0000
1100
0000
00100
00100
1110
0000
00100
0100
0000
00100
end
hread Espresso Output
in huffman
read
.o
#.
data
.i
111111111
phase
18
.p
0111
00
000-10
0-
0101
11011
001
0-0
0111
0-10-1
001000001
000100000
100001000
110101000
001000110
101010000
011000000
0110-0
011100001
0001
001100000
inn
liinoooo
00
000000100
0-1
0010
0011
000000100
111110000
001000110
00-01
111110100
01-1
010100000
000000100
000000100
-1
.
hreader Espresso
#
.o
in huffman data
read
.i
Input
9
9
type
fr
111111111
.phase
00000
0000
0000
0000
110
0000
00000
0000
1111
01000
0000
100
0001
00100
0001
-00
0001
00100
0001
1111
01000
0001
-1--0
0011
00000
0011
-1
0011
00000
0011
-0
0010
00010
0010
0-0
0010
00010
0010
1111
01000
0010
1-0
0110
00000
B-31
0110
0110
00000
0110
0100
00001
0100
00
0100
0100
1111
00001
01000
0100
10
0101
00000
0101
1-
0101
00000
0101
0-
0111
10000
0111
0111
10000
0111
0000
00000
1111
1111
01000
1111
0000
00000
end
hreader Espresso Output
in huffman data
read
.i
.o
#. phase
.p
111111111
18
011100
001000001
000-10
000100000
01010-
100001000
11011
110101000
0010-0
001000110
0111
101010000
0-10-1
011000000
0110-0
011100001
0001
001100000
11111
111110000
00
000000100
0-1
000000100
0010
111110000
0011
001000110
00-011
111110100
01-1
010100000
000000100
000000100
_1
.
qaddr
#
.i
.o
Espresso
quant
address
Input
incrementer
3
4
.type
fr
1111
.phase
00
00
00
00
01
00
11
01
01
11
10
10
10
10
10
10
00
00
.end
B-32
qaddr
Espresso Output
quant
address
incrementer
.i
4
#. phase
.o
1111
0-1
0100
1-1
1010
01-
1101
11-
1010
qment
Espresso, Input
# load q table
5
.i
.o
fr
type
1111111
.phase
000
00
000
0000
000
11
000
0000
000
01
001
0001
000
10
100
0010
011
1000
001
011
-1
011
0100
011
-0
000
0000
110
1000
100
110
1-
110
1000
110
0-
000
0000
101
000
0000
111
000
0000
010
000
0000
end
qmem
Espresso. Output
# load q
.i
.o
#.
.p
table
5
7
phase
1111111
00010
1000010
00001
0010001
011-1
0110100
1-01-
1101000
100
1101000
001
0111000
B-33
Appendix C
Support Code
dec.c
**
behavioral
of
model
jpeg
baseline decoder
**********************
#include <stdio.h>
#include <unistd.h>
#include <roath.h>
înclude
<sys/types.h>
#include <fcntl.h>
înclude
<sys/time.h>
#include <values.h>
/*
Local Defintions
Sdefine ON 1
0
#define OFF
/+
#define HDEBUG 0
/*
#define IDEBUG 1
/*
#define DEBUG
debug
general
/*
MCU
#define BDEBUG 0
/*
NextByte
#define ADEBUG 0
/*
AC decoder
#define DDEBUG 1
#define PASS
printf
*/
statements
huffman coding debug printf statements */

IDCT debug printf statements
V
debug
*/
statements
printf
*/
statement
printf
*/
statements
printf
#define FAIL 1
#define RESTART
#define NORESTART
/*
/*
0xD8
#define SOI
Start
Frame,
of
Start
of
SOFO
OxCO
/*
Start
of
^define
S0F1
OxCl
/*
Start
of
ffdefine SOF2
0xC2
/*
Start
of
S0F3
0xC3
/*
Start
of
/+
Start of
Frame,
Huffman coding */
non-differential
#define
#define
image
V
Frame, Baseline DCT
Frame, Extended sequential DCT
S0F5
0xC5
/*
Start
of
Frame,
#define
S0F6
0xC6
/*
Start
of
0xC7
/*
Frame, Differential
Frame, Differential
/+
S0F7
Start of
Frame,
/+
0xC8
Start
of
Reserved for
Differential
JPEG
JPG
#define
S0F9
#define
DHT
0xC4
/+
Define Huffman table (s)
#define
DAC
OxCC
/*
Define
arithmetic
OxDB
/*
Define
quantization
#define
^define
DQT
/*
DRI
Extended
/*
OxDD
sequential
Define
/*
application
segment
OxEl
/*
application
segment
#define APP2
0xE2
/*
application
segment
APP3
0xE3
/*
application
segment
0xE4
/+
application
segment
application
segment
#define
APP5
0xE5
/*
#define
APP6
0xE6
/*
application
segment
#define APP7
0xE7
/*
application
segment
#define APP8
0xE8
/*
APP9
segment
/*
application
segment
OxEA
/*
application
segment
A
B
APPB
OxEB
/*
application
segment
#define APPC
OxEC
/+
application
segment
#define APPD
OxED
/*
application
segment
#define APPE
OxEE
/*
application
segment
Sdefine APPF
OxEF
/*
application
segment
#define
#define
COM
OxFE
/+
#define
TEM
0x01
/*
#define
RESL
0x02
/
/
Temporary
reserved,
*/
lower
reserved,
modulo
count
modulo
count
OxDO
RSTU
OxDT
ftdefine
DNL
OxDC
/*
Define
#define
SOS
OxDA
/*
Start of Scan
0xD9
/*
#def ine
EOI
DHP
EXP
End
/+
OxDE
OxDE
/+
/*
*/
end
Restart
RSTL
#define
#define
*/
end
upper
Restart with
#define
#define
of
with
number
Image
reference
"m"
"m"
lower
end
*/
upper
end
*/
lines
*/
*/
Define hierarchical
Expand
*/
*/
Comment
/+
OxBF
RESU
#define
/*
conditions
application
0xE9
Sdefine APPA
#define
*/
table(s) */
interval */
restart
OxEO
#define APP4
+/
*/
coding
APP1
#define
DCT
spatial
DCT
frdefine APPO
#define
DCT
progressive
extensions
#define
0xC9
sequential
coding */
arithmetic
non-differential
lossless
(sequential)
Spatial
#define
frdefine
*/
Progressive DCT
Frame,
Frame,
differential Huffman coding
progression
component(s)
*/
C-l
#define DC 0
ftdefine AC 1
-local
external
variables
QTables[4] [64);
NumLinelmage;
NumSamplesImage;
NumlmgCompFranie;
NumlmgCompScan;
short
int
int
int
int
int Compldent[256] ;
int HorzSampFactor [256] ;
int VertSampFactor[256] ;
int QuantTableSelector[256)
int ScanCompIdent [256] ;
int ScanDCTableSel[256]
int ScanACIableSel[256]
short
;
;
precision;
int StartSpectral;
int EndSpectral;
SuccAppxBitHigh;
SuccAppxBitLow;
short
short
int Restartlnterval ;
int byte_counter;
int CNT;
int file;
/*
file desc
int outfile;
/*
huffman coding
int BITS [17] ;
int HUFFVALS [256] ;
stuff
*/
huffstruct
struct
[
int lastk;
int
int
int
int
int
int
int
BITS
[17] ;
HUFFCODE[256]
HUFFSIZE[256]
HUFFVALS [256]
VALPTR[17] ;
MINC0DE[17] ;
MAXC0DE[17] ;
/*
/+
first
index */
is table 0, 1 is table 1 */
second index V
is DC table, 1 is AC table */
/*
/*
struct
/*
huffstruct huffman_tables [2] [2]
short
PRED [10] ;
short
DIFF;
T;
short
short
ZZ[64] ;
SS[8] [8]
short
ss[8]
[8]
short
zigzag[64]
short
struct
huffman decoder */
{ 0, 1, 5, 6,14,15,27,28,
2, 4, 7,13,16,26,29,42,
3, 8,12,17,25,30,41,43,
9,11,18,24,31,40,44,53,
10,19,23,32,39,45,52,54,
20,22,33,38,46,51,55,60,
21,34,37,47,50,56,59,61,
35,36,48,49,57,58,62,63);
=
scan_struct
{
short
line[1024] [1024];
I;
struct
scan_struct
scans
[3];
/+
Local
int ReadAByte (short *d_byte)
Global Functions
main()
(
char
filename [80]
void
FindStartOf Image
void
GetFileName (char *filename) ;
void
FindStartOfFrameO
DecodeFrame ( ) ;
void
0;
Restartlnterval
byte_counter
{)
0;
C-2
GetFileName
file
(filename)
("Reading %s
printf
\n", filename)
JPEG file
open(filename,C__RDONLY) ;
printf
("File is open\n") ;
printf
("Reading
the
file, %s\n", filename)
FindStartOf Imaged ;
FindStartOf Frame ( ) ;
DecodeFrame
()
(file) ;
(outfile)
close
close
printf
("File closed\n")
printf
("done\n")
(1)
return
**
FindStartOfImage
void
FindStartOf Image ( )
(
int
res ;
data_byte;
short
int marker;
("Searching for
printf
res
start
of
image\n")
1;
!=
(res
while
0)
{
=
res
if
ReadAByte (_data_byte) ;
(data_byte
==
OxFF)
{
marker
ON;
}
if
else
(marker
==
ON)
(
if
(data_byte
SOI)
(
printf
("Start
image found
of
FF%OX\n",data_byte) ;
return;
}
else
marker
OFF;
marker
OFF;
}
else
{
}
1
(file)
close
printf
("ERROR! !
printf
("Aborting\n\n")
Start
Image NOT found\n") ;
of
exit(l) ;
**
FindStartOfFrame
void
FindSta rtOf Frame
()
{
int
res ;
short
int
data_byte;
marker;
void
InterpretComment
()
void
InterpretAPP (int type);
void
DefineQuantTables
void
Def ineHuf fmanT able s
()
()
()
() ;
void
DefineArithmeticTables
void
DefineRestartlnterval
printf
res
("Searching for
start
of
Frame\n");
=1;
C-3
!=
(res
while
0)
(
res
if
ReadAByte
(data_byte
(_data_byte)
OxFF)
(
marker
ON;
1
if
else
(marker
==
ON)
{
switch
(data__byte)
[
DHT:
case
("Define Huffman tables

DefineHuffmanTables () ;
printf
FFI02X\n",data_byte)
break;
DAC:
case
printf
("Define Arithmetic
Def ineArithmeticTables
Conditioning
() ;
FF%02X\n",data_byte
break;
DQT:
case
("Define Quantization Tables

DefineQuantTables () ;
printf
FF%02X\n",data_byte)
break;
DRI:
case
printf
("Define Restart Interval
DefineRestartlnterval ()
break;
APPO:
case
printf
("Application defined
marker
marker
FF%OX\n",data_byte)
FF%OX\n",data_byte)
marker
FF%OX\n",data_byte)
marker
FF%OX\n",data_byte)
marker
FF%OX\n",data_byte)
InterpretAPP ( 0 ) ;
break;
APP1:
case
printf
InterpretAPP (1) ;
break;
APP2:
case
printf
InterpretAPP (2) ;
break;
APP3:
case
printf
InterpretAPP
(3)
break;
APP4:
case
printf
InterpretAPP ( 4
break;
APP5:
case
printf
InterpretAPP
(5)
marker
FF%OX\n",data_byte)
marker
FF%OX\n",data_byte)
marker
marker
FF%OX\n",data_byte)
marker
FF-OX\n",data_byte) ;
marker
break;
APP6:
case
printf
InterpretAPP
(6)
break;
APP7:
case
printf
InterpretAPP (7) ;
break;
APP8:
case
printf
InterpretAPP
(8)
break;
APP9:
case
printf
InterpretAPP (9) ;
break;
APPA:
case
printf
FF%OX\n",data_byte)
InterpretAPP (10) ;
break;
APPB:
case
printf
("Application defined marker B
InterpretAPP
(11)
break;
case
APPC:
printf
InterpretAPP
(12)
marker
FF%OX\n",data_byte)
marker
FF%OX\n",data_byte)
marker
marker
break;
case
APPD:
printf
InterpretAPP (13);
break;
case
APPE:
printf
InterpretAPP
(14)
break;
case
APPF:
printf
InterpretAPP (15) ;
break;
C-4
COM:
case
("Comment
printf
Interpret Comment ( ) ;
break;
SOFO:
case
printf
("Start
of
data_byte)
Frame,
Baseline DCT
Frame,
Extended
FF%0X\n",
return;
SOF1:
case
printf
("Start
printf
("Extended
printf
("
(file)
(1) ;
close
exit
of
sequential
ABORTINGW)
DCT
sequential
not
DCT\n");
implementedW)
S0F2:
case
printf
("Start
printf
("Progressive
printf
close
Frame, Progressive DCT\n");

DCT not implemented\n")
ABORTING\n") ;
("
(file)
of
exit(l) ;
return;
S0F3:
case
printf
("Start
printf
("Spatial
printf
close
Frame, Spatial (sequential) lossless\n")

(sequential) lossless not implemented\n")
ABORTINGW) ;
("
(file)
of
;
;
exit(l) ;
return;
S0F5:
case
printf
("Start
printf
("Differential
printf
close
("
Frame,
of
Differential
sequential
ABORTINGW)
(file)
DCT
sequential
DCT\n");
implementedW)
not
exit(l) ;
return;
S0F6:
case
printf
printf
printf
close
("Start
of
Frame, Differential
("Differential
("
progressive
ABORTING\n")
(file)
DCT
DCT\n")
implemented\n") ;
progressive
not
exit(l);
return;
S0F7:
case
printf
printf
printf
close
("
Differential
Frame,
of
spatial
ABORTING\n")
(file)
(1)
exit
("Start
("Differential
not
spatialW);
implemented\n")
return;
TEM:
case
printf
("Temp
private
use
in
arithmetic
coding\n");
break;
default
if
( (data_byte
>=
RESL)
&_
(data_byte
<=
RESU) )
{
printf
("Reserved
printf
("Unknown marker\n") ;
marker
used
}
else
(
printf
("
marker
FF%02X\n",data_byte) ;
}
break;
)
marker
OFF;
marker
OFF;
}
else
}
close
(file)
printf
("ERROR! !
printf
("Exiting\n\n")
Start
of
Frame NOT found\n");
exit(l) ;
**
GetFileName
void
GetFileName (char ^filename)
{
int fileptr;
char lastfile[80];
FILE *lastused;
lastused
if
fopen("lastused", "r")
NULL)
(lastused
C-5
(
("Error reading last
fclose (lastused) ;
printf
used
file\n ABORTING! !\n\n") ;
exit(l) ;
)
fscanf
(lastused, "_s", lastfile)
printf
("Enter file
", lastfile);
(filename)
gets
if
name
[Is]:
(filename [0]
0)
==
strcpy (filename, lastfile) ;

printf ("file
%s\n", filename) ;
fileptr = open (filename, 0__RDONLY)
(fileptr
while
==
-1)
[
printf
("fileptr
%d\n", fileptr)
("Invalid fileW) ;
printf ("Enter file name
printf
(filename)
gets
if
(filename [0]
");
;
'e'
(
(fileptr)
(0) ;
close
exit
}
fileptr
open
( filename, 0 RDONLY)
)
fclose
(lastused)
lastused
f printf
("lastused", "w") ;
(lastused, "%s", filename) ;
fclose (lastused)
close
f open
(fileptr)
DecodeFrame
void
DecodeFrame ()
(
int
res;
input [4]
char
data_byte;
short
int marker;
int counter;
DecodeScan () ;
Dec ode Frame Header () ;
DefineHuffmanTables ()
void
void
void
void
DefineArithmeticTables () ;
DefineRestartlnterval () ;
void
DefineQuant Tables () ;
void
Interpret Comment ( ) ;
void
0;
counter
printf
("Decoding FrameW)
DecodeFrameHeader () ;
1;
res
(res
while
0)
if
res
(dataj-yte
OxFF)
==
[
marker
ON;
}
if
else
(marker
ON)
{
switch
(data_byte)
{
case
SOS:
printf
("Start
DecodeScan
()
of
Scan
FF%02XW,data_byte)
break;
case
EOI:
printf
of Image
("Done Decoding Frame\n");
("End
printf
return;
case
DHT:
printf
("Define Huffman tables
DefineHuffmanTables
()
FF_02XW,data_byte)
break;
case
DAC:
printf
("Define Arithmetic
()
Conditioning
break;
C-6
DQT:
case
("Define Quantization Tables
printf
Def ineQuant Tables () ;
break;
DRI:
case
("Define Restart Interval
printf
FF%02X\n"/data_byte)
Def ineRestartlnterval () ;
break;
APPO:
case
printf
marker
FF_02XW,data_byte)
marker
marker
marker
FF%02XW,data_byte)
marker
FF%02XW,data__byte)
marker
marker
marker
marker
marker
marker
FF%02XW,data_byte) ;
marker
marker
marker
FF%02XW,data_byte)
marker
marker
FF-02X\n",data_byte) ;
break;
APP1:
case
printf
break;
APP2:
case
printf
break;
APP3:
case
printf
break;
APP4:
case
printf
break;
APP5:
case
printf
break;
APP6:
case
printf
break;
APP7:
case
printf
break;
APP8:
case
printf
break ;
APP9:
case
printf
break;
APPA:
case
printf
break;
APPB:
case
printf
break ;
APPC:
case
printf
break;
APPD:
case
printf
break;
case
APPE:
printf
break;
case
APPF:
printf
break;
case
TEM:
("Temp
printf
in
use
private
arithmetic
codingW) ;
break;
case
COM:
("Comment\n")
printf
Interpret Comment
()
break;
default
if
((data_byte
printf
if
lse
if
("Reserved
("Restart
((data_byte
counter
/+
RESL)
((data_byte
printf
lse
>=
printf
used
marker
>=
RSTL)
marker
0)
&&
<=
RESU) ]
(data_byte
<=
RSTU) )
I I
(data_byte
OxFF)}
do nothing
printf
(data_byte
__
stuffed
bytes
*/
("Unknown markerW) ;
("
marker
break;
)
marker
OFF;
counter++;
>
else
(
marker
OFF;
)
if
(counter
10)
C-7
("[RET]
(input) ;
to continue
printf
gets
if
( input [ 0 ]
'
:");
{
printf
("ABORTINGW)
return;
\
counter
0;
}
}
("Error! ! No End
printf
of
Image
found! !! !\n\n")
return;
**
DecodeScan
void
DecodeScan ()
[
void
OpenOutputFile {)
void
WriteOutHeader ()
timeval
struct
long tv_sec;
unsigned
long
tv_usec;
In
struct
timeval
struct
timezone
first,
second,
lapsed;
{
int tz_minuteswest;
int tz__dsttime;
In
timezone
struct
tzp;
DecodeMCU (short x,
short
short
void
DecodeScanHeader () ;
DecodeRestartlnterval ( )
void
ConvertRGBO
void
y,
hmax,
short
short
vmax,
int
num_blocks) ;
int wid, height;

int hmax, vmax;
short
i;
short
x,y;
short
int
cnt,
n;
m,
data[80]
char
num_blocks;
short
res;
rst,
DecodeScanHeader
printf
if
("
()
Decoding Scan\n");
(NumlmgCompScan
==
1)
[
if
(DEBUG)
printf
("
Scan in non-interleaved\n") ;
}
else
{
if
(DEBUG)
printf
("
Scan is
interleaved
with
%d scans\n", NumlmgCompScan)
)
if
{
if
(Restartlnterval
(DEBUG)
printf
PRED[0]
PRED[1]
PRED[2]
PRED [3]
0)
Restart NOT EnabledW) ;
0;
0;
0;
0;
OpenOutputFile
WriteOutHeader
if
==
("
()
()
(! DEBUG)
(
printf
("Begining
to decode Scan\n");
}
CNT
0;
hmax
for
vmax
(i
=1;
0;
<
NumlmgCompScan;
i++)
t
if
(HorzSampFactor
[i]
(VertSampFactor [i]
if
hmax)
hmax
HorzSampFactor
> vmax)
vmax
VertSampFactor
>
[i]
[i]
;
;
)
wid
(int) ceil ( ( (double)NumSamplesImage/8.0)/ (double) hmax)

(int) ceil ( ( (double)NumLineImage/8.0)/ (double) vmax)
Number of MCU's to decode
height) ;
%d\n",
height
printf
("
num_blocks
for
{i
0;
;
;;
wid*
=0;
<
NumlmgCompScan;
i++)
{
num_blocks
num_blocks
HorzSampFactor [i]*VertSampFactor
C-8
[i]
if
(DEBUG)
y
(i
for
Number
(fifirst,
fitzp)
0;
0;
(wid*height)
gettimeofday
x
("
printf
<
of
B blocks
is Id
W,num_blocks)
i++)
{
if
(DEBUG)
if (DEBUG)
=
res
("
MCU Id
\n",i+l);
printf ("Corner
(x,y) : (*4d, I4d) \n",x,y)
printf
DecodeMCU(x,y/hmax,vmax,num_blocks)
(8+hmax) ;
if (x >= NumSamplesImage)
1
0;
(8*vmax)
>
}
gettimeofday (ssecond, &tzp) ;
if (first. tv_usec > second. tv usee)
[
second.
tv_usec
+=
second.
tv_sec
1000000;
}
lapsed. tv_usec
second. tv_usec
lapsed. tv_sec
printf
if
second.
("Elapsed time to decode
lapsed. tv__usec)
(! DEBUG)
first. tv_usec;
tv_sec
first. tv_sec;
%u
sec
Id usecW, lapsed. ty_sec,
{
printf
("Done
decodingW)
}
if
(NumlmgCompScan
1)
>
{
if
(JDEBUG) printf ("Converting to RGBW);

ConvertRGB ( ) ;
if (!DEBUG) printf ("Done converting to RGB\n")
)
data to file
write
if
(1DEBUG)
for
printf
("Writing
image to fileW)
0;
cnt
*/
(y
0; y
<
NumLinelmage; y++)
[
for
(x
0;
<
NumSamplesImage; x++)
(i
0;
<
NumlmgCompScan;
{
for
i++]
[
"13d
(data,
",
(outfile, data, 4)
sprintf
write
scans
[i]
.line[x]
[y] )
cnt++;
1
if
(cnt
>=
17)
(
cnt
0;
sprintf
(data, "\n") ;
(outfile, data,
write
strlen(data)
}
J
}
if
(1DEBUG)
printf
("Done writing image to fileW);
}
else
I
("
Restart ENabledW) ;
OpenOutputFileO ;
WriteOutHeader { ) ;
nura_blocks
0;
for (i
0; i < NumlmgCompScan;
{
printf
num_blocks
num_blocks
i++)
HorzSampFactor
[i] ^VertSampFactor [i]
}
if
CNT
for
(DEBUG)
printf
Number
of
8 blocks
is Id \n",num_blocks)
0;
hmax
("
vmax
(i
0;
1;
<
NumlmgCompScan;
i++)
{
if (HorzSampFactor [i]
if (VertSampFactor [i]
hmax)
hmax
HorzSampFactor
> vmax)
vmax
VertSampFactor [i] ;
>
[i]
)
(int) ceil ( ( (double) NumSamplesImage/ 8. 0)/ (double) hmax)
=
(int) ceil ( ( (double) NumLinelmage/ 8. 0)/ (double) vmax)
printf
Number of MCU's to decode = ldW,wid*height) ;
num_blocks
0;
for (i
0; i < NumlmgCompScan; i++)
wid
height
;
; ;
("
[
num__blocks
num_blocks
HorzSampFactor [i]*VertSampFactor
[i]
)
if
i
(DEBUG)
printf
("
Number
of
8 blocks
is Id \n",num_blocks)
0;
rst
0;
0;
C-9
while
((i <
while
(i <
(wid*height))
tr,
(rst
<
Restartlnterval))
'/
(wid*height) ]
[
if
if
(DEBUG) printf (" MCU 8d \n",i+l);

(DEBUG) printf ("Corner (x,y) : (Hd, 4d)\n",x,y)
res
DecodeMCU(x, y, hmax, vmax, num_blocks) ;
if (res
(short) NORESTART)
{
x
x +
(8*hmax) ;
if (x >= NumSamplesImage)
==
[
0;
y +
(B*vmax)
)
i++;
)
else
I
if
(1DEBUG)
PRED[0)
printf
("Restart interval %d\n",rst+l)
0;
PRED[1]
PRED[2]
PRED[3]
0
0
rst++;
1
I
if
(! DEBUG)
[
printf
if
("Done decoding\n")
(NumlmgCompScan
>
1)
[
if
(1DEBUG)
ConvertRGB (
if
printf
(!DEBUG)
("Converting
to RGB\n");
;
printf
("Done converting to RGB\n");
)
data to file */
write
if
(1DEBUG) printf ("Writing image to file\n");

cnt
0;
for (y
0; y < NumLinelmage; y++)
t
for (x
0; x < NumSamplesImage; x++)
[
for (i
0; i < NumlmgCompScan; i++)
(
sprintf (data, "%3d ", scans [i]
[x] [y] )
write (out file, data, 4) ;
=
.line
cnt++;
1
if
>=
(cnt
17)
{
=
cnt
0;
sprintf
(data, "\n") ;
( out file, data, str len (data) )
write
("
printf
Done
Decoding Scan\n")
return;
)
/*********************************-***
**
DecodeScanHeader
void
DecodeScanHeader
()
[
char
data[l]
short
data_byte;
short
data_byte2;
int i ;
short
counter;
int Cs;
short
int
printf
("
ReadAByte
ReadAByte
if
if
Ta;
Td,
sum;
Decode
Scan Header\n") ;
(_data_byte) ;
(&data_byte2)
(DEBUG)
(DEBUG)
printf
printf
("
Scan Header
("Scan Header len
len
=
%02X%02X
",data_byte,data_byte2) ;
IdW, ( (data__byte
8)
C-10
data_byte2))
ReadAByte
(_data_byte) ;
data__byte;
("
Number of Image components in Scan
(DEBUG) printf
%d\n", NumlmgCompScan)
if (NumlmgCompScan > 1)
(
if (DEBUG) printf ("
Checking for Ns greater than 1 here!W);
sum
0;
NumlmgCompScan
if
for
(i
0;
<
NumlmgCompScan;
i++)
{
sum
sum
>
10)
HorzSampFactor [i]
[i]
VertSampFactor
}
if
(sum
t
("
printf
close
ERROR,
("
printf
>
sum
10 in
header
scan
check!
!W);
ABORTING! !\n\n") ;
(file)
exit(l);
\
else
[
if
(DEBUG)
printf
("
Ns > 1
checks
good!
sum
IdW,
sum);
)
1
for
(i
0;
NumlmgCompScan;
<
i++)
[
ReadAByte
Cs
(&data_byte)
data_byte;
ScanCompIdent
Td
=*
Ta
if
if
Cs;
[i]
ReadAByte (Sdata_byte2) ;
(data_byte2
OxOF;
4)
_
data_byte2
(DEBUG)
OxOF;
("
printf
for
(i
0;
<
Scan
("
(DEBUG) printf
ScanDCTableSel[i]
ScanACTableSel [i]
)
DC
Comp
table
Selector
ldW,Cs);
Id AC table
IdW, Td, Ta)
Td;
Ta;
NumlmgCompScan;
i++)
{
if
(DEBUG)
("
printf
ld\n", ScanCompIdent [i]
Scan Id Frame
,CompIdent
)
ReadAByte
(data_byte) ;
=
data_byte;
StartSpectral
if
(DEBUG)
ReadAByte
("
printf
StartSpectral
Start Spectral
/+
0;
FOR DCT
IdW , StartSpectral)
*/
modes
(&data_byte) ;
data_byte;
EndSpectral
if
(DEBUG)
ReadAByte
End Spectral
/*
63;
FOR DCT
(_data_byte)
SuccAppxBitHigh
SuccAppxBitLow
if
("
printf
EndSpectral
(DEBUG)
data_byte
printf
("
&
if
(DEBUG)
printf
4)
OxOF;
Successive Appx Bit High
SuccAppxBitLow
("
*d\n", EndSpectral)
+/
OxOF;
SuccAppxBitHigh, SuccAppxBitLow)
SuccAppxBitHigh
(data_byte
modes
Done
Id Low
ld\n",
0;
/+
DCT
modes
Decoding Scan HeaderW)
of
operation
Interpret Comment
void
Interpret Comment
()
[
data [1] ;
char
short
data_byte;
short
data_byte2;
int
numbytes;
int i;
short
counter;
ReadAByte (_data_byte2) ;
printf
("
COM length
(data_byte
numbytes
printf
printf
("Comment length
("
counter
for
(i
COMMENT
",data_byte,data_byte2) ;
I02XI02X
8)
data_byte2;
IdW, numbytes)
FOLLOWS
\n\t")
=0;
0;
<
numbytes-2;
i++)
{
count er++;
C-ll
*/
[i] )
ReadAByte
if
(*data_byte) ;
>=
'A') 4_ (data_byte <= *Z*))
("lc",data_byte)
if ((data_byte >= 'a')
(data__byte <= 'z'))
((data_byte
printf
else
_s
("_c",data_byte)
printf
if
else
{{data_byte
>=
'0')
(data_byte
__
("%c",data_byte)
printf
<=
'9'))
else
printf
if
(".")
(counter
30)
==
{
counter
printf
=0;
("\n\t")
}
1
("\n")
printf
InterpretAPP
void
InterpretAPP (int type)
data [1]
char
data__byte;
data_byte2;
short
short
int numbytes;
int i ;
short
int
counter;
res;
ReadAByte
ReadAByte
("
printf
numbytes
printf
printf
(fidata_byte) ;
(_data_byte2)
(data_byte
!02XI02X",data_byte,data_byte2)
8)
("
APP
("
Application Id data
(i
length
data_byte2;
IdW, numbytes)
:\n\tVt", type) ;
0;
counter
for
length
APP
0;
<
numbytes-2;
i++)
{
counter++;
if
ReadAByte (&data_byte) ;
( (data_byte >= *A*) & (data_byte
printf ("lc",data_byte) ;
if
>=
<=
'2'))
( (data_byte
'a') &_ (data_byte
("lc",data_byte) ;
if ((data__byte >= '0') && (data_byte
printf ("lc",data_byte) ;
else
<=
*z'))
<=
*9*))
printf
else
else
printf
if
(".")
(counter
30)
(
=
counter
printf
0;
("\n\t\t");
)
)
printf
("\n")
**
DefineQuantTables
void
DefineQuantTables
()
{
data[l] ;
data_byte;
data_byte2;
int i, j;
char
short
short
int
numbytes;
short
P, T;
short
num_tables;
short
x,y;
ReadAByte (sdata_byte) ;
ReadAByte ( fidata_by te2 ) ;
if
(DEBUG)
numbytes
if
(DEBUG)
num_tables
printf
("
(data_byte
printf
("
Quant
length
l02X_02X",data_byte,data_byte2) ;
data_byte2;
Quant length = IdW, numbytes)
8)
(numbytes-2) /65;
C-12
if
(DEBUG)
for
(i
("
printf
0;
<
Number
Tables
of
%d\n",num_tables)
i++)
num_tables;
{
ReadAByte
P
(sdata_byte)
(data_byte
4) i
data_byte 5 OxOF;
if
(DEBUG)
if
(P
printf!"
OxOF;
P
*01X T
lX\n",P,T);
0)
(
if
(DEBUG)
printf
("
Quantization tables
are
bit\n")
)
else
[
printf
("Quantization tables
printf
("NOT supported\n") ;
printf
("ABORTING\n")
close
(file)
16 bit\n");
are
exit(l) ;
if
for
)
("
(DEBUG) printf
Loading Quantization Table #Sd\n
0; j < 64; j++)
(j
",T);
{
ReadAByte (sdata_byte) ;
QTables[T] [j]
data_byte;
if (DEBUG) printf("%2d ",QTables (T) [j] )
if ((((j+l)/8)+8)
(j+1))
if (DEBUG) printf ("\n
");
=
I
if
(DEBUG)
if
(DEBUG)
0; y
(y
for
printf
("\n"),
printf("
Unzigzagged Quantization Table #*d\n
",T)
8; y++)
<
(
for
(x
<
8; x++)
(
if
)
if
1
if
(DEBUG)
(DEBUG)
(DEBUG)
printf
printf
('
printf
("S2d ",QTables [T] [zigzag! (y*8) +x] ]) ;
("\n");
\n")
DecodeFrameHeader
void
DecodeFrameHeader ( )
[
data[l] ;
data_byte;
data_byte2;
short data_byte3;
char
short
short
int i ;
ReadAByte
(&data_byte)
ReadAByte (fidata__byte2) ;
if
if
(DEBUG)
(DEBUG)
printf
printf
("
Frame Header len
("
Frame Header len
%02XI02X",data_byte,data_byte2) ;
8) + data_byte2) )
IdW, ( (data_byte
=
precision
if
(DEBUG)
data_byte;
printf
("
Precision
IdW, precision)
ReadAByte
(_data_byte) ;
ReadAByte (Sdata_byte2)
NumLinelmage
8)
(data_byte
ReadAByte (&data_byte)
data_byte2;
ReadAByte (Sdata_byte2) ;
NumSamplesImage
printf
("
Image
8)
(data_byte
size
(%4d
data_byte2;
I4d) \n", NumSamplesImage, NumLinelmage)
NumlmgCompFrame
if
for
(DEBUG)
(i
printf
0;
<
data_byte;
("
Number
of
Image
components
frame=
IdW, NumlmgCompFrame )
NumlmgCompFrame; i++)
{
ReadAByte
ReadAByte
ReadAByte
(_data_byte) ;
( Sdata_byte2 )
(
)
_data_byte3
;
;
C-13
CompIdent[i]
data_byte;
(data_byte2
HorzSampFactor[i]
4) & OxOF;
data_byte2 5 OxOF;
[i]
=
VertSampFactor
QuantTableSelector [i]
if
data_byte3;
(DEBUG)
printf
if
("
Comp d Quant Table
d\n",CompIdent [i]
,QuantTableSelector
[i] )
(DEBUG)
printf
("
Horz
Factor
VertSampFactor
[i] )
Sd Vert Factor
Sd\n", HorzSampFactor [i]
**
DefineHuffmanTables
void
DefineHuffmanTables ( )
I
LoadAHuffTable (short Htable,
void
short
data_byte;
short
data_byte2;
int
int
short
Htype)
numbytes;
i,j,)c, 1;
Tc, Th;
short
ReadAByte
(data_byte)
ReadAByte ( &data_byte2 ) ;
if
(HDEBUG)
numbytes
if
i
("
printf
Huffman
(data_byte
(HDEBUG)
8)
("
printf
length
S02X802X",data_byte,data_byte2)
data_byte2;
-j
Huffman length
Sd\n",
numbytes) ;
0;
(i <
while
(numbytes-2) )
[
/*
Read in huff table descriptors

ReadAByte
(sdata_byte)
*/
i++;
Tc
(data_byte
Th
(data_byte
if
if
(HDEBUG)
(Tc
0)
4)
6
OxOF;
&
OxOF)
("
printf
Huffman Table
Loading
Sd, type is ",Th);
==
[
if
(HDEBUG)
printf
("DC\n")
("AC\n")
1
if
else
(Tc
1)
==
[
if
(HDEBUG)
printf
1
else
[
printf
("Error
printf!"
close
with
Huffman table type\n");
ABORTING\n\n")
(file)
exit(l) ;
I
/*
for
in
read
(j
BITS
1;
<
array */
17; j++)
I
BITStj]
data_byte;
huf fman_tables [Th] [Tc]
=
.BITStj]
data_byte;
i++;
if
(HDEBUG)
[
("BITS
printf
[Sd]
Sx\n", j
Sd
huffman_tables
[Th] [Tc]
,huffman_tables
[Th] [Tc]
.BITS
[j] )
-BITS
[ j]
)
I
/*
read
1
for
HUFFVAL array */
in
0;
1; j
(j
<-
17;
j++)
(
for
(1c
0;
k < BITStj];
k++)
1
i++;
ReadAByte (5data_byte) ;
HUFFVALS
data_byte;
[1]
[Th] [Tc]
=
huffman_tables
if
.HUFFVALS
[1]
data_byte;
(HDEBUG)
I
printf
("HUFFVALS [Sd]
huffman_tables
S4d 44x\n",
[Th] [Tc]
l,huffman_tables
[1] )
.HUFFVALS
[Th] [Tc]
I
1++;
C-14
.HUFFVALS
[1]
LoadAHuffTable(Th,Tc)
)
if
!=
(i
printf
**
(numbytes-2)]
!=
("i
numbytes-2");
LoadAHuffTable
void
LoadAHuffTable (short
Htable,
Htype)
GenHuffTableSize (short Htable, short Htype, int *HUFFSIZE,int

*lastk) ;
GenHuffCodeTables (short Htable, short Htype, int *HUFFSIZE,int
*HUFFCODE)
HuffGen(int Htable, int Htype);
void
void
void
int lastk;
int HUFFSIZE[256]
int HUFFCODE [256]
/*
short
Generate Table Size */
GenHuffTableSize (Htable, Htype, HUFFSIZE, slastk) ;

/*
Generate Code Table */

GenHuffCodeTables (Htable, Htype, HUFFSIZE, HUFFCODE)
Huf fGen
**
(Htable, Htype)
pg F-25
Huf fGen (int
void
Htable,
int Htype)
I
int i ,
i
j;
0;
(i
while
<=
16)
i++;
if
(huffman_tables [Htable] [Htype]
.BITS
!=
[i]
0)
(
huffman_tables [Htable] [Htype]
huf fman_tables [Htable] [Htype]
j;
.VALPTR[i]
=
.MINCODE[i]
.
HUFFCODE
[j ]
j + huffman_tables [Htable] [Htype]

[i]
huffman_tables [Htable] [Htype] .MAXCODE[i]
.BITS
.HUFFCODE[j]
j++;
.MAXCODEti]
-1;
I
)
for
(i
0;
<
17; i++)
I
if
(HDEBUG)
printf ("MINCODE[83d]
:
84d 84x MAXCODE[83d]
84d $4x VALPTR[83d]
i, huffman_tables [Htable] [Htype]
,
fman_tables
huf
[Htable] [Htype]
[i] ,
i,huffman_tables [Htable] [Htype]
,
[i) ,
i, huffman_tables [Htable] [Htype] .VALPTR[i],
huf fman_tables [Htable] [Htype] VALPTR[i] ) ;
.MINCODE[i]
.MINCODE
.MAXCODEti]
.MAXCODE
1
1
/* + * + + + **
**
+ *
+ * + + + + + * + + + + # + + + + + + + + + i**i* + + * + * + ***# ***** + + *#+ + + ** + + ** + +
GenHuffCodeTables
void
GenHuffCodeTables (short Htable,
short
Htype,
int *HUFFSIZE, int 'HUFFCODE)
[
int k, CODE,
int DONE;
DONE
SI;
0;
C-15
84d
84x\n"
0;
0;
CODE
SI
HUFFSIZEtO]
(DONE
while
==
0)
1
HUFFCODE
[k]
CODE;
huf fman_tables [Htable]
if
[Htype]
.HUFFCODE
[k]
CODE;
(HDEBUG)
printf
("HUFFCODE [8d]
CODE++;
k++;
if (HUFFSIZE [k]
!=
8d\n",k,huffman_tables [Htable] [Htype]
.HUFFCODE[k]
SI)
I
if
(HUFFSIZE[k]
0)
return;
else
(
SI++;
CODE
CODE
1;
[k]
(HUFFSIZE
while
!-
(
SI++;
CODE
**
CODE
1;
GenHuffTableSize
void
GenHuffTableSize (short
Htable, short Htype,
int *HUFFSIZE,int *lastk)
[
int i,
j, k;
0;
1;
j
(i
while
<=
16)
[
<=
(j
while
BITS[i])
t
i;
HUFFSIZE[k]
huffman_tables [Htable) [Htype]
if
.HUFFSIZE
i;
[k]
(HDEBUG)
printf
8d\n"
("HUFFSIZE [Sd]
k, huf fman_tables
[Htable] [Htype]
k++;
j++;
)
1;
i++;
)
HUFFSIZE [k]
0;
*
lastk
lastk
k;
k;
**
void
()
(
printf
printf
("
Arithmetic
"
Tables
ABORTING\n\n"
implemented\n"
not
close(file) ;
exit(l) ;
**
void
1
char
data[l] ;
data_byte;
data_byte2;
short
short
int
numbytes;
C-16
.HUFFSIZE[k]
ReadAByte
ReadAByte
(&data_byte) ;
(_data_byte2)
("
printf
Restart int
len
(data_byte
numbytes
printfl"
8)
Restart int len
%02XI02X",data_byte,data__byte2)
data_byte2;
IdW, numbytes)
ReadAByte
(_data_byte) ;
ReadAByte (_data_byte2)
Restartlnterval
("
printf
(data_byte
8)
Restart Interval
data_byte2;
IdW, Restartlnterval)
ReadAByte
int
ReadAByte (short
*d_byte)
(
data
char
[1]
int res;
res
read(file,data,l) ;
*d_byte
data[0];
*d_byte
if
*d_byte
&
OxOOFF;
(BDEBUG)
("Byte
printf
-2x\n".*d_byte)
byte_counter++ ;
return
res;
/*********************tn
**
DecodeRestartlnterval
void
DecodeRestartlnterval ()
(
I
**
DecodeMCU
*+
For
baseline,
sequential
MCU is
an
8x8 block;
V
short
DecodeMCU (short
startX,
short
startY,
short
hmax,
short
vmax,
int
num_blocks)
{
DecodeDCCoeff (short comp,
DecodeACCoeff (int ACsel);
short
short
int DCSel);
Calclnverse (int QTable) ;
void
short
res ;
y;
short
x,
short
dx, dy;
short
sx,
sy;
short
lx,
ly;
short
wid;
i, j,n,m,k,l;
short
input [3]
char
for
(i
=0;
< NumlmgCompScan;
i++)
{
wid
=
HorzSampFactor
0;
y
for (j
0;
<
[i]
8;
(HorzSampFactor [i]*VertSampFactor [i] ) ;
j++)
{
res
if
(res
DecodeDCCoeff (i,ScanDCTableSel
[i] )
(short) RESTART)
{
if
(DEBUG) printf ("Returning RestartW)

return
(short) RESTART ;
}
res
if
(res
return
DecodeACCoeff (ScanACTableSel
Calclnverse (QuantTableSelector
[i] )
(short) RESTART)
(short) RESTART;
=
[i] )
0;
C-17
sy
for
startY
(k
y;
k <
startY+y;
(startY+y+8)
k++)
[
=
sx
0;
startX
for
(1
x;
startX+x;
<
(startX+x+8)
1++)
[
if
((ss[m][n]
if
(38 [m] [n]
<
0)
I I
(ss[m][n])
>
255]
{
ss
[m] [n]
<
0)
0;
255;
else
ss[m]
[n]
)
if
((hmax
==
HorzSampFactor [i] )
ss
(vmax
VertSampFactor [i] ) )
[
scans[i]
.line[l]
[k]
=ss[m][n];
1
else
(
for
(dy
0; dy
< vmax/VertSampFactor
[i]
dy++)
<
for
(dx
0; dx
<
hmax/HorzSampFactor [i]
dx++)
1
lx
ly
scans
[i]
sx
sy
.line
dx;
dy;
[lx] [ly]
ss[m][n];
I
I
I
n++;
sx
sx
hmax/HorzSampFactor[i)
vmax/HorzSampFactor[i]
)
m++;
=
sy
sy
)
=
if
8;
(x
wid)
I
0;
x
=
8;
)
)
)
(short)NORESTART;
return
**
Calclnverse
void
Calclnverse (int QTable)
[
void
DeQuantize (int QTable);
void
IDCTO
DeQuantize
IDCT
(QTable)
(QTable)
I
/"""
*+
DecodeACCoeff
short
DecodeACCoeff (int ACsel)
[
short
i,k;
short
RS;
short
DECODE (int
short
SSSS;
short
R;
short
for
int Type,
short
*rst);
k, short SSSS, short *rst)
Decode_ZZ (short
void
ACsel,
rst;
1;
(i
ZZ[i]
while
1;
=
64;
<
i++)
0;
(1)
[
if
(k > 63)
1
printf
("ERROR! !
printf
("K
close
==
(file)
>
63\n ABORTINGW ) ;
8d\n",k);
exit(l) ;
C-18
}
RS
DECODE
if
(ADEBUG)
if
(rst
(ACsel, AC, Srst) ;

printf ("DecodeAC RS
(short) RESTART)
S.2X\n",RS);
(
if
(DEBUG) printf ("DecodeAC returning

(short) RESTART;
restart\n") ;
return
)
SSSS
RS
(RS
if
(SSSS
if
(R
OxOF;
s OxFO)
0)
4;
==
[
!=
15)
return;
else
k +
k + R;
16;
1
else
[
k
Decode_ZZ(k, SSSS, srst)

if
(rst
return
if
(short) RESTART)
(short) RESTART;
63)
==
(k
return;
else
k++;
)
)
(short)NORESTART;
return
**
**
Decode_ZZ
F-24,
pg.
fig
F.14
void
Decode_ZZ (short
k, short SSSS, short *rst)
(
short
RECEIVElint SSSS,
short
short
EXTEND(int
int SSSS);
ZZ[k]
if
("rst
DIFF,
*rst)
RECEIVE(SSSS,rst) ;
==
(short) RESTART)
return;
ZZ[k]
EXTEND
(ZZ[k), SSSS)
*+
DecodeDCCoeff
short
int DCsel)
DecodeDCCoeff (short comp,
[
DECODE (int Htable, int type, short *rst) ;
short
short
RECEIVE(int
short
EXTEND(int
short
T;
short
rst;
DECODE
SSSS, short *rst)

DIFF, int T) ;
(DCsel, DC, Srst)
if
(ADEBUG)
if
(rst
printf
("DC decode
return
8.2X\n",T);
(short) RESTART)
(
if
(DEBUG) printf ("DecodeDCCoeff (1) returning

(short) RES TART;
restart\n");
return
)
DIFF
if
RECEIVE
(rst
(T,
Srst) ;
(short) RESTART)
return
rst;
DIFF
EXTEND(DIFF,T)
PRED [comp] + DIFF;

ZZ[0]
ZZ[0];
PREDtcomp]
=
return
rst
f ********* ^
**
**
RECEIVE
C-19
F-27
pg.
***********
short
RECEIVE(int SSSS,
*rst)
short
{
short
NEXTBIT(short *rst)
i , v;
short
tmp;
short
0;
(i
while
SSSS)
tmp
if
NEXTBIT (rst) ;
(*rst
(short) RESTART)
==
[
if
(DEBUG)
printf
("RECEIVE returning
restart\n
return;
j
v
(v
1)
tmp;
i++;
)
return v;
1
/*
**.++.++.+
**
DECODE
**
pg.
""
? WW...
....
....
F-26
short
DECODElint Htable, int Htype,
short
*rst)
(
NEXTBIT (short *rst) ;
short
short
i,
short
VALUE;
CODE;
short
j;
1;
CODE
NEXTBIT
if
(*rst
I
if
(DEBUG)
(rst)
(short) RESTART)
==
printf
("DECODE
(1)
returning RestartW) ;
return;
)
(CODE >
while
.MAXCODE
[i] )
(
if
if
(ADEBUG)
(ADEBUG)
CODE
if
(CODE
(*rst
==
printf
("CODE
printf
("i
2X\n", CODE)
8d\n",i);
1) + NEXTBIT (rst)
(short) RESTART)
[
if
(DEBUG)
printf
("DECODE
(2)
returning restart\n") ;
return;
i++;
if
if
if
j
if
(ADEBUG)
(ADEBUG)
(ADEBUG)
("CODE
printf
("i
.2X\n",
printf
printf
.VALPTR[i]
8d\n",j);
("j
("j
CODE)
8d\n",i);
huffman_tables
huffman_tables
(ADEBUG)
return
printf
CODE
(ADEBUG)
VALUE
if
printf
[Htable] [Htype]
.MINCODE[i]
8d\n",j);
[Htable] [Htype]
("VALUE
.4X\n",
.HUFFVALS
VALUE)
[j];
VALUE;
**
NEXTBIT
'*
pg F-28
short
NEXTBIT (short *rst)
[
static
short
B;
static
short
B2;
short
mask;
short
BIT;
C-20
?rst
if
( short )NORES TART;
(CNT
0)
(
ReadAByte
CNT
if
(SB)
8;
(B
OxFF)
-=
[
ReadAByte ( SB2 )
if (B2 != 0)
[
if
(B2
DNL)
==
[
("DNL
printf
marker
found in scan,
("ABORTINGW)
(file) ;
(1)
printf
not
programmed
to
close
exit
)
else
I
if
((B2
>=
RSTL)
ii
(B2
<=
RSTU) )
(
if
(DEBUG)
*rst
CNT
printf
("RST
marker
found FF802XW,B2) ;
(short) RESTART;
0;
return;
1
else
(
printf
("?Unknown
printf("
close
close
(file) ;
(outfile)
found FF802XW,B2)
marker
ABORTINGW)
exit(l)
(CNT-
mask
BIT
BIT
BIT
1);
mask;
(CNT -1)
CNT;
BIT;
return
/ +.
+ + .-* + + . ....*. ..... ...
..
* *
EXTEND
**
F-22
short
int T)
EXTEND (int V,
1
Vt;
short
Vt
if
(int)pow(2.0, (double) (T-D)
(V
<
Vt)
Vt
V
(-1
V +
T)
1;
Vt;
1
return
V;
1
.+*+*+*++++++.+.+.++++. + *
-
..
"
DeQuantize
+......+
void
DeQuantize (int QTable)
[
short
j;
if (DDEBUG)
for (i = 0;
printf
<
("\n\t Unloaded\n\t") ;
8;
i++)
(
for
(j
0;
<
8;
j++)
[
if
(DDEBUG)
printf
("* 4d ",ZZ [ (i*8) +j] )
C-21
handleW)
if
(DDEBUG)
printf
("\n\t")
(DDEBUG)
printf
("\n")
)
if
if
(DDEBUG) printf ("\n\t Deguantized and unZigZagged\n\t") ;

for (i
0; i < 8; i++)
I
for (j
0; j < 8; j++)
I
SS[i][j]
ZZ[zigzag[(i*8)+j]] * QTables [QTable] [zigzag! (i*8) +j] ]
if (DDEBUG) printf(" 4d ",SS [i] [ j] ) ;
)
if (DDEBUG) printf ("\n\t");
)
if (DDEBUG) printf ("W);
=
**
IDCT
Performs
The
Inverse Discrete Cosine Transform
an
method
using two 1-D transforms is
of
level
Also the
shift
operation
1-D transform.
second
is
It is hard
performed
coded
on
8x8
an
array.
performed.
for
at
the
eight
end
of
the
bit data.
void
IDCTO
[
short
x,y;
short
u,v;
double
a,b,CV,Cu;
double mid;
double sum;
i,
short
int
if
j;
num_blocks;
short
[8] [8]
sss
(I DEBUG)
(
("Begin IDCT\n\t");
printf
)
for
0; y
(y
8;
<
y++)
[
for
0;
*.
<
8; X++)
0.0;
(u = 0;
<-
8;
(X
1
sum
for
u++)
1
a
cos((((2.0*x)+1.0)*(double)u*M_PI)/16.0);
if
(u
0)
==
Cu
M_SQRT1_2;
else
Cu
=
sum
1.0;
[y] [u]*Cu+a;
SS
sum
)
(int)sum;
sss[y][x]
1
for
(x
0;
==
8;
x++)
1
for
(y
0;
==
y <
8;
y++)
<
8;
V++]
j
0. 0;
sum
for
(V
0;
==
(
b
if
Cv
(((2.0'
cos(
(v
=
==
y)+1.0)*
(double
lv*M_ PD/16. 0);
0)
M_SQRT1_2;
else
Cv
1.0;
sum
sum
ss5i[v]
[x]*Cv*b;
1
ss[y]
(int) ((;:um/4. 0))
[x; 1
128;
1
)
if
for
(DDEBUG) printf ("W);

0; y < 8; y++)
(y
=
[
for
(x
0;
<
8;
x++)
(
if
(DDEBUG)
printfC'S
4d ",ss[y][x]);
)
if
(DDEBUG)
printf
if
(DDEBUG)
printf
if
(I DEBUG)
("\n")
("\n")
C-22
("\n")
printf
if
**
(I DEBUG)
("Finished
printf
IDCTW)
OpenOuputFile
i*
**
the output file
open
for
PPM image
void
OpenOutputFile
()
(
=
outfile
if
open
(outfile
( "out. ppm",0__RDWR I
==
0_CREAT)
-1)
[
printf
("Error opening
output
printf
("Aborting\n\n")
(file)
close
file!!W);
exit(l) ;
void
WriteOutHeader
char
if
()
data [80] ;
(NumlmgCompScan
write
1)
(outfile, "P2\n",3)
==
else
write
(outfile, "P3\n", 3)
write
(outfile, "#
Doug's
codeW,14);
(data, "Id ld\n", NumSamplesImage, NumLinelmage)

(out file, data, str len (data) ) ;
sprintf
write
write(outfile,"255W,4) ;
**
**
ConvertRGB
Convert YCrCb to RGB
void
()
ConvertRGB
(
x,y,i;
short
float Y,Cb,Cr;
input [2]
char
for
(y
0; y
< NumLinelmage;
y++)
i
for
(x
0;
< NumSamplesImage;
x++)
{
(float) scans [0]
(float) scans [1]
(float) scans [2]
.line[x]
Cb
Cr
scans[0].line[x]
scans[l].line[x]
scans[2]
-line[x]
if
(scans
if
(scans [1]
(scans [2]
if
[0]
[y]
[y]
[y]
.line[x]
(short) (Y
(short) (Y
(short) (Y
[x] [y]
<
<
[x] [y]
<
0)
0)
0)
[y]
>
[y]
[y]
>
-line
if
(scans
[0]
-line[x]
if
(scans[l]
-line[x]
if
(scans
-line[x]
[2]
.line[x]
line [x] [y]
.line
[y] ;
[y]
[y]
>
(1.402*
(Cr-128.0) ))
0.344148*
1.772*
scans
[0]
[1]
scans
[2]
scans
.line
.line
255)
[0]
255)
255)
scans
[1]
[2]
0
0
[y]
=255
line[x] [y]
=255
line
=255
.line[x]
0)
[x] [y]
[x] [y]
[y]
.linetx]
scans
scans
(Cb-128.
(Cb-128. 0) ) ;
[x] [y]
conv.c
**
conv.c
**
Convert
jpg
file
to
ascii
text
file
C-23
0.71414*
(Cr-128.0) )
**
usage
input_f ile_name
conv
**
************************************************
#define
înclude <stdio.h>
#include <fcntl.h>
ffinclude <sys/types
(f include <unistd.h>
/*
local
global
int
infile;
int
outfile;
main(int
.h>
*argv[])
char
argc,
*/
variables
{
void
OpenlnFile (char
void
GetlnFileName (char *inf ilename) ;

OpenOutFile ( ) ;
void
char
inf ilename [80]
char
data [1]
unsigned
int
d_byte;
short
counter;
char
if
*inf ilename) ;
str
[3]
(argc
==
1)
{
GetlnFileName (inf ilename) ;
}
if
else
(argc
2)
==
{
strcpy ( inf ilename, argv[l] ) ;
}
else
{
( "Usage
(1) ;
printf
exit
[infile]
conv
\n"
OpenlnFile ( inf ilename ) ;
OpenOutFile ( ) ;
0;
(read(infile,data,l)
counter
while
!=
NULL]
{
counter++;
d_byte
data[0]
d_byte
d_byte
OxOOFF;
(str, "%02X",d_byte)
(outfile, str, 2 ) ;
sprintf
write
if
(counter
30)
{
"\n"
( str,
(outfile,
sprintf
write
counter
str,
strlen
(str) )
0;
}
}
printf
close
\n"
( "Done !
(infile)
/*********************
********* ********************************* ******
* *
**
OpenlnFile
**
**
**
Attempt
so,
to
open
the
input
file.
If
unable
to
do
abort.
**
*********************************************************************/
void
C-24
OpenlnFile (char *infilename)
{
infile
if
(inf ilename,
open
(infile
==
0_RDONLY);
-1)
{
printf
("Error opening input
printf
( "Try Again
file
Aborting
%s\n", infilename)
) ;
conversion\n\n"
exit(l) ;
/*******************************************************************+*
* *
**
GetlnFileName
**
**
Get
the
input
file
name,
including
path
**
**********************************************************************,
void
GetlnFileName (char
*f ilename)
(
int
fileptr;
char
lastfile[80]
FILE
*lastused;
lastused
if
f open (
(lastused
"lastused",
"r"
NULL)
==
{
("Error reading
fclose (lastused) ;
printf
last
used
file\n ABORTING! !
\n\n"
exit(l) ;
fscanf (lastused, "%s", lastfile)
( "Enter file name [%s] : ", lastfile);

( filename ) ;
if (filename[0]
0)
strcpy ( filename, lastfile) ;
fileptr
open ( filename, 0_RDONLY ) ;
printf
gets
==
while
(fileptr
==
-1)
(
%d\n", fileptr )
( "Invalid file\n");
:
printf ( "Enter file name
");
gets ( filename ) ;
if (filename[0]
'e')
{
close ( fileptr) ;
printf
("fileptr
printf
==
exit(0) ;
}
fileptr
open
(f ilename, 0_RDONLY ) ;
}
fclose (lastused) ;
fprintf
"w"
f open ( "lastused",
)
(lastused, "%s", filename) ;
lastused
fclose (lastused) ;
close
(fileptr)
)
/***********************************
**********************************
**
**
OpenOutFile
**
**
**
Open
the
open
output
to
file,
write
hard
over
coded
name
existing
file
vhdl.dat
**
*********************************************************************/
void
OpenOutFile
{ ]
C-25
outfile
if
open("vhdl.dat",0_RDWR
(outfile
==
0_CREAT);
-1)
{
("\nError opening
printf
Aborting\n\n"
printf("
(infile)
close
file
output
%d\n",
outfile
exit(l) ;
display, c
**
display.^
**
Convert the
output
**
into
display
**
proper
usage
from the
decoder,
which
format.
I.E line
by
has data
line. Write
as
a
8x8
ppm
blocks,
b/w file.
display
**
**
input file
**
name
file
output
vhdl.ppm
name
display. ppm
înclude <stdio.h>
#include <fcntl.h>
#include <sys/types.h>
#include
/*
<unistd.h>
local
global
variables
FILE *infile;
FILE *outfile;
main()
1
OpenlnFile ();
OpenOutFile () ;
data [80] ;
void
void
char
int line_block[64] [1024]

int xlen
0;
int ylen
0;
int line_cntr
int vert cntr
int
int
pix
cntr
0;
0;
0;
x,y,xx,yy;
int
,k;
int
0;
int
int
lI;
l2;
int
3;
int
l4;
int
5;
int
6;
int
7;
int
8;
int : 9;
int
10;
int : 11;
int : 12;
int
13;
int d 14;
int
15;
int : 16;
int i[17];
char
input [ 9 ]
.
printf
("\nDisplay
program
in
work\n");
OpenlnFile
() ;
OpenOutFile ()
/*
next
two lines
fgets
if
(fgets
for test only to
are
(data, 80, infile)

fprintf (outfile, data)
fgets (data, 80, infile)
fprintf (outfile, data)
read
in
comments
*/
;
;
;
;
(data, 80, infile)
==
NULL)
(
fclose (infile) ;
fclose (outfile) ;
printf
exit
("Error reading X,Y
dimension\n\n")
(1) ;
C-26
else
(
sscanf
(data,"Sd
printf
("X len
fprintf
%d", ixlen, sylen) ;

%d Y len
8d\n",xlen,ylen)
(outfile, data)
)
if
(fgets (data,
80, infile)
==
NULL)
(
fclose (infile) ;
fclose (outfile)
("Error reading
printf
num
colors\n\n") ;
exit(l);
)
else
fprintf
(outfile, data)
0;
y
line_cntr
0;
0;
vert_cntr
pix_cntr
0;
(fgets(data, 80, infile)
while
!=
NULL)
1
(data,"%d %d Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd ",
sscanf
Si0,sil,i2,si3,5i4,si5,si6,i7,si8,si9,sil0,sill,sil2,sil3,sil4,sil5,sil6);
(data) ;
iO;
il;
i2;
i3;
i4;
i5;
i6;
i7;
i8;
i9;
ilO;
printf
i[0]
ill]
1[2]
i[3]
i[4]
i[5]
i[6]
i[7]
i[8]
i[9]
i[10]
i[ll]
i[12]
i[13]
i[14]
i[15]
i[16]
ill
il2
il3
il4
=
il5
il6
0;
< 17)
(
i[j);
line_block[vert_cntr+y] [line_cntr+x]
printf ("Sd Sd
Sd\n", line_cntr+x,vert_cntr+y,i [j ] )
(j
while
x++;
pix_cntr++;
if
(x
8)
==
0;
y++;
if
8)
(y
(
0;
line_cntr+=
if
8;
>=
(line_cntr
xlen)
I
line_cntr =0;
vert_cntr+=
8;
)
)
1
k
for
0;
(y
0; y
<
ylen;
y++)
{
for
(x
0;
x++)
xlen;
[
fprintf (outfile, "83d
k++;
if (k
==
", line_block[y] [x] )
17)
(
k
0;
fprintf
(outfile, "\n")
1
1
)
fclose (infile) ;
fclose (outfile) ;
printf
("Display
program
complete
view
display. ppm\n\n") ;
OpenlnFile
C-27
Attempt to
open
the
input file.
If
unable
to do
abort.
so,
void
OpenlnFile ()
(
infile
if
f open ("vhdl. ppm",
(infile
"r");
NULL)
==
{
printf
("Error opening input file
printf
("Try
(1)
exit
Again
Aborting
vhdl.ppmW) ;
conversion\n\n") ;
\
I
/** + + + * + + + **** + + ** + + ** + ****** + + + **** + * + **mm + + 1t*m*4
**
OpenOutFile
**
Open the output
file, hard
coded
name
to write over existing
open
vhdl.dat
file
void
OpenOutFile ()
if
fopen("display.ppm", "w")
outfile
(outfile
NULL)
==
(
printf
printf
("\nError opening
("
Aborting\nW)
fclose (infile)
exit
(1)
output
file
%dW, outfile)
compare. c
/*******************************************
**
**
**
**
compare.-
Compare
input file to the display. ppm
an
usage
input__file_name
compare
înclude
<stdio.h>
#include
<fcntl.h>
înclude <sys/types.h>
înclude
<unistd.h>
înclude <string.h>
#include
<strings.h>
/*
global
local
variables
*/
/*
FILE *infile;
/*
FILE *disfile;
main(int
compare
display. ppm
*/
*/
*argv[])
char
argc,
file to
(
void
OpenlnFile (char *infilename) ;
void
GetlnFileName (char *infilename) ;
void
OpenOutFile
char
infilename [80]
()
char
indata[80]
char
disdata[80] ;
counter
0;
int
int
;
;
disx, disy, dispix;
char
distype[10];
int
inx, iny, inpix;
cha r
int
intype [10];
in_pix [ 17 ] ;
int
dis_pix[17];
int
X/y;
int
num_pix,
short
hits;
i;
(argc
==
1)
GetlnFileName (inf ilename) ;
lse
if
(argc
==
2)
strcpy (inf ilename, argv[l] )
C-28
else
{
printf
( "Usage
[ infile] W)
compare
exit(l) ;
I
OpenlnFile (inf ilename) ;
OpenOutFile () ;
printf
/*
in headers...");
("\nReading
number
of
be P2 */
must
colors,
fgets
(disdata, 80,disfile)
fgets (indata, 80, infile) ;
printf
(".")
(disdata, "%c",distype) ;
sscanf (indata, "Ic", intype) ;
if (strcmp(distype, intype) != 0)
t
printf ("FAILW) ;
sscanf
printf
("\n\tPPM types did
not
ABORTING! !
match!!
!\n\n")
fclose (infile) ;
fclose (disfile) ;
exit
(1)
}
/*
line */
comment
fgets
(disdata, 80, disfile)

printf
(".")
/*
x,y dimensions, must be the

fgets (disdata, 80, disfile) ;
fgets (indata, 80, infile)

sscanf
sscanf
if
(indata, "%d %d", &inx, siny) ;

(disdata, "%d %d", Sdisx, idisy)
!=
(inx
*/
same
disx)
{
printf
("FAIL\n")
printf
("\n\tX dimensions did
fclose (infile)
;
not
ABORTING! !
match!!
!\nW)
fclose (disfile) ;
exit(l) ;
\
else
!=
if(iny
disy)
t
printf
("FAILW)
printf
("\n\tY dimesions did
fclose (infile)
;
not
ABORTING! !
match!!
!\n\n")
fclose (disfile) ;
exit(l) ;
\
printf
/*
(".")
number
of
possible
colors;
bit
size
*/
fgets (disdata, 80, disfile) ;

sscanf
sscanf
if
;
(indata, "%d",
(disdata, "%d", fidispix)
!=
dispix)
-inpix)
(inpix
{
printf
("FAILW)
printf
("\n\tBits/pixel
;
count
did
not
match!!
ABORTING! ! !\n\n") ;
fclose (infile) ;
fclose (disfile) ;
exit(l) ;
I
printf
(".")
printf
("..DONE\n\n")
printf
("Checking data...W);
0;
0;
num_pix
hits
while! (fgets
0;
(disdata, 80, disfile)
!=
NULL)
ss
(fgets (indata,
80, infile)
1
for
(i
0;
<
(
-1;
in_pix[i]
dis_pix[i]
17;
i++)
-1;
)
sscanf
(indata, "Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd",
C-29
!=NULL))
sin_pix[0)
sin_pix[l]
Sin_pix[6),sin_pix[7]
sscanf
for
&in_pix[2]
sin_pix[3]
,sin_pix[8]
iin_pix[9]
,sin_pix[10] ,sin_pix[ll] ,
&in_pix[4]
sin_pix[5]
sin_pix[12],sin_pix[13] ,sin_pix[14] ,sin_pix[15] , sin_pix[16] )

(disdata, "Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd Sd",
fidis_pix[0]
,&dis_pix[l] ,sdis_pix[2] ,sdis_pix[3] ,sdis_pix[4]

,
&dis_pix[5]
dis_pix[6]
,sdis_pix[ll] ,
sdis_pix[15]
0;
,sdis_pix[7] ,sdis_pix[8] ,sdis_pix[9] ,
dis_pix[10]
(i
sdis_pix[12)
dis_pix[16] )
sdis_pix[13]
sdis_pix[14]
17; i++)
<
(
if
(((in_pix[i)
>
-dis_pix[i])
1)
||
((in_pix[i)
dis_pix[i])
<.
-1))
hits++;
("Diff
printf
>
(83d, 83d)
in:S3d dis:83d
,x,y,in_pix[i] ,dis_pix[i] ,
diff:83d\n"
(in_pix[i]-dis_pix[i) ) )
x++;
num_pix++;
if
(x
inx)
I
x
0;
y++;
)
printf
(".
printf
("Number
fclose
.Done!\n")
of
(infile) ;
(disfile)
fclose
pixels
Sd Number
analyzed
of
hits
8d\n",nun_pix,hits)
**
OpenlnFile
Attempt to
the input
open
file.
If
unable
to do
abort.
so,
void
OpenlnFile (char
*infilename)
{
infile
if
fopen(infilename, "r")
(infile
==
NULL)
[
printf
("Error opening input file
printf
("Try
Again
Aborting
%s\n", infilename)
compare\n\n") ;
exit(l) ;
/*********************************************
* *
**
GetlnFileName
**
Get the input
file name,
including
path
void
GetlnFileName (char *filename)
1
FILE *fileptr;
lastfile[80]
char
strcpy (lastfile,
"out. ppm") ;
("Enter file name [Is] :

(filename) ;
if
[0]
0)
strcpy (filename, lastfile)
fileptr
fopen(filename, "r")
", lastfile]
printf
gets
(filename
==
while
(fileptr
==
;
;
NULL)
%d\n", fileptr)
printf
("fileptr
printf
("Invalid fileW) ;
("Enter file name :
printf
(filename) ;
(filename[0]
")
gets
if
'e')
[
fclose (fileptr)
exit(0) ;
)
fileptr
fopen (filename, "r")
C-30
fclose (fileptr)
**
OpenOutFile
Open the
open
output
to
file, hard
write
coded
name
existing file
over
void
OpenOutFile ()
{
disfile
printf
if
fopen ("out. ppm", "r") ;

change to display. ppm here!!!W);
("Need to
(disfile
NULL)
==
{
printf
printf
fclose
("\nError opening
("
Aborting\n\n")
(infile)
display
file
display. ppmW)
exit(l) ;
C-31

A VHDL Design of A JPEG Still Image Compression Standard Decoder

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A VHDL Design of A JPEG Still Image Compression Standard Decoder

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Rochester Institute of Technology

RIT Scholar Works

A VHDL design of a JPEG still image compression

Follow this and additional works at: http://scholarworks.rit.edu/theses

A VHDL Design of a JPEG Still Image

Partial Fulfillment of the

Committee Member - Dr. Ronald G. Matteson

Department Head - Dr. Roy S. Czemikowski

DEPARTMENT OF COMPUTER ENGINEERING

THESIS RELEASE PERMISSION FORM

Title: A VHDL Design of a JPEG Still Image Compression Standard Decoder

compression standard allows the amount of

ASIC that implements

implements the baseline decoder defined

few exceptions, the

images. The decoder

images is greatly increased. The decoder

to synthesize the ASIC using standard

1.3 DIGITAL IMAGING

1.5 TYPES OF JPEG IMPLEMENTATIONS

1.7 DESIGN BRIEF

1.8 SOFTWARE USED

2. 1.2 HUFFMAN CODING

2. 1.3 DISCRETE COSINE TRANSFORM

2.2 A JPEG ENCODER AND DECODER

2.3 INTERCHANGE FORMAT

2.4.1 BEHAVIORAL MODELING

2.4.2 STRUCTURAL MODELING

3.1 C PROGRAM BEHAVIORAL MODEL

3.2 LIMITATIONS OF STRUCTURAL MODEL

3.3 VHDL STRUCTURAL MODEL

3.3.1 VHDL TEST BENCH

3.3.2 CONTROL SIGNALS

3.3.3 DECODER MODULE

3.3.4 DECODING A SCAN

3.3.5 MISCELLANEOUS MODULES

4.1 DECODED IMAGES

4.2 SYNTHESIS OF A MODULE

5.3 LESSONS LEARNED

VHDL SOURCE CODE

STATE TABLES AND ESPRESSO RESULTS

Example Compressed Images

DPCM Model for

Zig Zag Ordering

Figure 2-10 Typical Compressed Image Data Format

Figure 2-11 A Decoder Circuit

Figure 2-12 Example VHDL Circuit

Figure 2-13 Example VHDL Behavioral Model

Figure 2-14 Example VHDL Structural Model

VHDL Test Bench

VHDL Test Bench Basic Structure

Control Signals Example Schematic

Example Control Signals

NextByte Espresso Input

VHDL Source Code

Figure 3-10 NextByte Espresso Output File

Figure 3-11 VHDL Source Code From Espresso Output

Figure 3-12 ISR Symbol

Figure 3-13 FindSOI Symbol

Figure 3-14 Example Wired Or Schematic

Figure 3-15 FindSOF Symbol

Figure 3-16 Frame Header Syntax

Figure 3-17 FrHeader Symbol